VIS Preliminary VG36128401A VG36128801A VG36128161A CMOS Synchronous Dynamic RAM Description The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank, 4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package. Features * Single 3.3V ( 0.3V) power supply * High speed clock cycle time : 7.5ns/10ns * Fully synchronous with all signals referenced to a positive clock edge * Programmable CAS Iatency (2,3) * Programmable burst length (1,2,4,8,& Full page) * Programmable wrap sequence (Sequential/Interleave) * Automatic precharge and controlled precharge * Auto refresh and self refresh modes * Quad Internal banks controlled by BA0 & BA1 (Bank select) * Each Bank can be operated simultaneously and independently * I/O level : LVTTL compatible * Random column access in every cycle * x4, x8, x16 organization * Input/Output controlled by DQM ( LDQM, UDQM ) * 4,096 refresh cycles/64ms * Burst termination by burst stop and precharge command * Burst read/single write option The information shown is subject to change without notice. Document : 1G5-0154 Rev.1 Page 1 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Pin Configuration VG36128401 (X 4) VG36128801 (X 8) VG36128161 (X 16) VDD VDD VDD 1 54 VSS VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC DQ7 VSSQ NC DQ6 VDDQ NC DQ5 DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC NC DQ0 DQ0 2 53 VDDQ VDDQ VDDQ 3 52 NC NC DQ1 4 51 DQ1 VSSQ DQ1 VSSQ DQ2 5 50 VSSQ 6 49 NC NC DQ3 DQ2 DQ2 7 8 48 DQ4 VDDQ VDDQ VDDQ 9 46 45 47 NC NC DQ5 DQ3 DQ3 DQ6 10 11 44 VSSQ VSSQ VSSQ 12 43 NC VDD NC NC VDD NC DQ7 13 42 VDD 14 41 LDQM 15 40 WE WE WE 16 39 CAS CAS CAS 17 38 RAS RAS RAS 18 37 CS CS CS 19 36 BA0 BA1 A10 A0 A1 A2 A3 VDD BA0 BA1 A10 A0 A1 A2 A3 VDD BA0 20 35 A11 A11 A11 BA1 A10 A0 A1 A2 A3 VDD 21 34 22 33 A9 A8 A7 A6 A5 A4 VSS A9 A8 A7 A6 A5 A4 VSS A9 A8 A7 A6 A5 A4 VSS Pin Description VG36128801/VG36128161 Pin Name 23 32 24 31 25 30 26 29 27 28 Function Pin Name Function A0 - A11 BAO, BA1 Address inputs Bank select DQ0 ~ DQ15 Data - in/data - out CLK Clock input RAS Row address strobe CKE Clock enable CAS Column address strobe WE Write enable VDDQ Supply voltage for DQ VSS Ground VSSQ Ground for DQ VDD Power (+ 3.3V) Document : 1G5-0154 DQM, LDQM, UDQM, CS Rev.1 Upper DQ Mask enable, Lower DQ Mask enable Chip select Page 2 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Block Diagram Clock CKE Generator Address Mode Register (Bank D) (Bank C) Bank B Row Address Buffer & Refresh Counter Row Decoder CLK Bank A WE Document : 1G5-0154 Data Control Circuit Rev.1 Input & Output Buffer CAS DQM Column Decoder & Latch Circuit Column Address Buffer & Burst Counter Latch Circuit RAS Control Logic CS Command Decoder Sense Amplifier Page 3 DQ VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Absolute Maximum D.C. Ratings Parameter Voltage on any pin relative to Vss Symbol Value Unit VIN, VOUT -0.5 to + 4.6 V VDD, VDDQ -0.5 to + 4.6 V IOUT 50 mA PD 1.0 W Operating temperature T OPT 0 to + 70 J Storage temperature T STG -55 to + 125 J Supply voltage relative to Vss Short circuit output current Power dissipation Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Maximum A.C. Operating Requirements for LVTTL Compatible Parameter Symbol Min Input High Voltage VIH 2.0 Input Low Voltage VIL -0.3 < 3ns 2. Undershoot limit: VIL(min)=VSSQ -2.0V with a pulse with < 3ns Max Unit Notes VDD + 0.3 V 1 0.8 V 2 Typ Max Unit 3.3 3.6 V Note: 1. Overshoot limit: VIH(max)=VDDQ +2.0V with a pulse with and -1.5v with a pulse < 5ns Recommended DC Operating Conditions for LVTTL Compatible Parameter Symbol Min Supply Voltage VDD, VDDQ 3.0 Input High Voltage, all inputs VIH 2.0 VDD + 0.3 V Input Low Voltage, all inputs VIL -0.3 0.8 V Capacitance (Ta=25C, f = 1MHZ) Parameter Symbol Min Max Unit Notes Input capacitance (CLK) C11 2.5 4 pF 1 Input capacitance (all input pins except data pins.) C12 2.5 5 pF 1 Data input/output capacitance CI/O 4.0 6.5 pF 1 Notes : 1. Capacitance measured with effective capacitance measuring method. Document : 1G5-0154 Rev.1 Page 4 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM DC Characteristics (Recommended Operating Conditions unless otherwise noted) -75 Parameter Unit Notes 120 125 135 2 100 105 115 2 mA 1 2 2 20 20 7 7 VIL(MAX.) tCK = min. CKE VIL(MAX.) tCK = 7 7 5 5 CKE VIH(MIN.) tCK = min. 30 30 20 20 115 130 160 190 105 120 150 190 1 1 mA Test Conditions Min ICC1 Burst length = 1 One bank active tRC tRC(MIN.), Io = 0mA ICC2P ICC2PS VIL(MAX.) tCK = min. CKE VIL(MAX.) tCK = ICC2N CKE VIH(MIN.) tCK = min. Operating current Precharge standby current in Power down mode Precharge standby current in Nonpower down mode -8H Max Symbol x4 x8 x16 CKE Max Min mA mA CS VIH(MIN.) Input signals are changed one time during 2 CLK cycles. ICC2NS CKE VIH(MIN.) tCK = CLK VIL(MAX.) Input signals are stable. Active standby current ICC3P in Power ICC3PS down mode ICC3N Active standby current in Nonpower down mode ICC3NS CKE mA mA CS VIH(MIN.) Input signals are changed one time during 2CLKs CKE VIH(MIN.) tCK = CLK VIL(MAX.) Input signals are stable. tCK tCK(MIN.) Io = 0mA All banks Active Operating current (Burst mode) ICC4 Refresh current ICC5 tRC = 4 x tRC(MIN) Self refresh Current ICC6 CKE 0.2V x4 x8 x16 Input Ieakage current (Inputs) lLI VIN 0, VIN VDD(MAX.) Pins not under test = 0V Intput leakage current (I/O pins) lLO VOUT 0, VOUT Output Low Voltage VOL IOL = 2mA Output High Voltage VOH IOH = -2mA VDD(MAX.) mA 2 mA 3 -1 1 -1 1 uA -1.5 1.5 -1.5 1.5 uA 0.4 V 4 V 4 DQ# in H - Z., Dout Disabled 0.4 2.4 2.4 Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. I CC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 4. For LVTTL compatible. Document : 1G5-0154 Rev.1 Page 5 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Characteristics : (Ta = 0 to 70C V DD = 3.3V 0.3V ,VSS = 0V) Test Conditions for LVTTL Compatible : AC input Levels (VIH/VIL) 2.0/0.8V Input rise and fall time 1ns Input timing reference level/ Output timing reference level Output load condition 1.4V 50pF AC Test Load Circuits (for LVTTL interface) : VDDQ VDDQ VOUT Z = 50 Device Under Test Document : 1G5-0154 50PF Rev.1 Page 6 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Characteristics : (Ta = 0 to 70C V DD = 3.3V 0.3V, VSS = 0V) symbol A.C. Parameter -75 Min. -8H Max. Min. tRC Row cycle time 60 70 tRCD RAS to CAS delay 20 20 tRP Precharge to refresh/row activate command 15 20 tRRD Row activate to row activate delay 15 20 tRAS Row activate to precharge time tCK2 tCK3 Clock cycle time 37.5 100,000 50 CL2 7.5 10 CL3 7.5 10 tCH Clock high time 2.25 3 tCL Clock low time 2.25 3 tAC2 Access time from CLK (positive edge) tAC3 CL3 5 6 tCCD CAS to CAS Delay time 1 1 tOH Data output hold time 2.5 3 tLZ Data output low impedance 0 0 tHZ3 Data output high impedance ns 6 1 10 1 10 CLK CL2 4 6 CL3 4 6 ns tIS Data/Address/Control Input setup time 1 2 tIH Data/Address/Control Input hold time 0.5 1 tSRX Minimum CKE "High"for Self-Refresh exit 1 1 CLK tPDE Power Down Exit set-up time 2 2 ns tRSC Mode Register Set Cycle 2 2 CLK tDPL Data-in to precharge 2 1 CLK tDAL2 Data-in to ACT (REF) Command CL2 2clk+tRP 1clk+tRP CL3 2clk+tRP 1clk+tRP 1 1 tDAL3 tBDL Last data in to burst stop tREF Refresh time Document : 1G5-0154 64 Rev.1 note 100,000 5 Transition time of CLK (Rise and Fall) unit ns CL2 tT tHZ2 Max. ns CLK 64 ms Page 7 9 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Basic Features and Function Description 1.Simplified State Diagram Self Refresh LF SE Mode Register Set try en LF SE MRS it ex AUTO Refresh REF IDLE CK E ACT CK E Power Down CKE ROW ACTIVE ter min atio n) CKE rge cha WRITEA n) atio min ter POWER ON Precharge ith e d w arg Rea Prech uto (writA e re cove ry) Pre E( PR CKE R Auto ead w Prec ith harg e CKE READ SUSPEND CKE Write Write with Auto Precharge WRITEA SUSPEND READ Read with Auto Precharge CKE READA CKE READA SUSPEND har ge CKE Read (write recovery) WRITE Read Pre c CKE Re ad PR E( WRITE SUSPEND y er ov c re PRE e rit W Au Write to p rec with har ge Write (Write recovery) h wit rge ad cha Re Pre to Au e rit W T BS BS T CKE Active Power Down Precharge Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state. Document : 1G5-0154 Rev.1 Page 8 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 2. Truth Table 2.1 Command Truth Table CKE A11 A9 - A0 WE BA(1) A10 X X X X X H H X X X L L L L V L H H V V V L H L H V L V X L H L H V H V H X L H L L V L V WRITA H X L H L L V H V Precharge select bank PRE H X L L H L V L X Precharge all banks PALL H X L L H L X H X Burst stop BST H X L H H L X X X CBR (Auto) refresh REF H H L L L H X X X Self refresh SELF H L L L L H X X X Symbol n -1 n CS Device deselect DESL H X H X No operation NOP H X L H Mode register set MRS H X L L Bank activate ACT H X L READ H X READA H WRIT FUNCTION Read Read with auto precharge Write Write with auto precharge RAS CAS 2.2 DQM Truth Table CKE FUNCTION DQM Symbol n -1 n -1 U L Data write/output enable ENB H X L Data mask/output disable MASK H X H Upper byte write enable/output enable ENBU H X L X Lower byte write enable/output enable ENBL H X X L Upper byte write inhibit/output disable MASKU H X H X Lower byte write inhibit/output disable MASKL H X X H 2.3 CKE Truth Table CKE Current State Function Symbol n-1 n CS RAS CAS WE Add ress Activating Clock suspend mode entry H L X X X X X Any Clock suspend L L X X X X X Clock suspend Clock suspend mode exit L H X X X X X Idle CBR refresh command REF H H L L L H X Idle Self refresh entry SELF H L L L L H X Self refresh Self refresh exit L H L H H H X L H H X X X X Idle Power down entry H L X X X X X Power down Power down exit L H X X X X X H : High level, L : Low level X : High or Low level (Don't care), V : Valid Data input Document : 1G5-0154 Rev.1 Page 9 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM (1/3) 2.4 Operative Command Table Notes 1 Current state Idle Row active Read Write CS RAS CAS WE Address Command Action Notes H X X X X DESL Nop or Power down 2 L H H X X NOP or BST Nop or Power down 2 L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BR, RA ACT Row active L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Refresh or Self refresh L L L L Op - Code MPS Mode register access H X X X X DESL Nop L H H X X NOP or BST Nop L H L H BA, CA, A10 READ/READA Begin read : Determine AP 5 L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Precharge 6 L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst end L H L H BA, CA, A10 READ/READA Term burst, new read : Determine AP L H L L BA, CA, A10 WRIT/WRITA Term burst, start write : Determine AP L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL Term burst, precharging L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop L H L H BA, CA, A10 READ/READA Term burst, start read : determine AP L H L L BA, CA, A10 WRIT/WRITA Term burst, new write : Determine AP 7 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Term burst, precharging 9 L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL Document : 1G5-0154 Rev.1 4 Row active Row active Row active 7 7,8 3 Write recovering Write recovering Row active Page 10 7,8 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM (2/3) Current state Read with auto precharge Write with auto precharge precharging Row activating Document : 1G5-0154 CS RAS CA WE Address Command Action Notes H X X X X DESL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST L H L H BA, CA, A10 READ/READA Illegal for single bank, but legal for multibanks interleave Illegal for single bank, but legal for multibanks interleave L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL H X X X X DESL Continue burst to end Write recovering with auto precharge L H H H X NOP L H H L X BST Continue burst to end Write recovering with auto precharge ILLEGAL L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA L L H L L L L H L L L H X L Prcharging Prcharging ACT Illegal for single bank, but legal for multibanks interleave Illegal for single bank, but legal for multibanks interleave ILLEGAL 3 BA, A10 PRE/PALL ILLEGAL 3 X PEF/SELF ILLEGAL L Op - Code MRS ILLEGAL X X X DESL Nop Enter idle after tRP H H H X NOP Nop L H H L X BST L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL Nop Enter idle after tRP L L L H X PEF/SELF ILLEGAL Enter idle after tRP Nop Enter idle after tRP L L L L Op - Code MRS ILLEGAL H X X X X DESL Nop Enter row active idle after tRCD L H H H X NOP Nop Enter row active idle after tRCD L H H L X BST Nop Enter row active idle after tRCD L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3,9 L L H L BA, A10 PRE/PALL ILLEGAL 3 L L L H X PEF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL Rev.1 Page 11 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM (3/3) Current state CS RAS CA WE H X X X X DESL Nop L H H H X NOP Nop L H H L X BST Nop L H L H BA, CA, A10 READ/READA Start read, Determine AP L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PALL ILLEGAL 3 Write recovering Write recovering with auto precharge Auto Refreshing Mode register setting Address Command Action Notes Enter row active after tDPL Enter row active after tDPL Enter row active after tDPL 8 L L L H X PEF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL H X X X X DESL Nop L H H H X NOP Nop L H H L X BST Nop Enter precharge after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL 3,8 Enter precharge after tDPL Enter precharge after tDPL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 REF/PALL ILLEGAL 3 L L L H X REF/SELF ILLEGAL L L L L Op - Code MRS ILLEGAL H X X X X DESL Nop Enter idle after t RC L H H X X NOP/BST Nop Enter idle after t RC L H L X X READ/WRIT ILLEGAL L L H X X ACT/PRE/PALL ILLEGAL L L L X X REF/SELF/MRS ILLEGAL H X X X X DESL Nop L H H H X NOP Nop L H H L X BST ILLEGAL L H L X X READ/WRITE ILLEGAL L L X X X ACT/PRE/ PALL/ ILLEGAL Enter idle after 2 Clocks Enter idle after 2 Clocks Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy t DPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but for multibanks interleave Document : 1G5-0154 Rev.1 Page 12 VIS CMOS Synchronous Dynamic RAM 2.5 Command Truth Table for CKE Note 1 CKE RAS CS RAS CAS Current state n-1 Self refresh (S.R.) Self refresh recovery Power down (P.D.) Both banks idle Any state other than listed above VG36128401A VG36128801A VG36128161A Preliminary WE Address Action Notes X X H X X X X X X INVALID, CLK (n-1)would exit S.R. S.R. Recovery S.R. Recovery X X X X X X ILLEGAL ILLEGAL Maintain S.R. n H X X X L H H X L H L H L H L H L H L L L L X X L X X H H H X X X X Idle after tRC H H L H H X X Idle after tRC H H L H H H L L L X X X X X X X X ILLEGAL ILLEGAL Begin clock suspend next cycle H L X X X X X X X Begin clock suspend next cycle ILLEGAL ILLEGAL 5 X X X X X Exit clock suspend next cycle Maintain clock suspend INVALID, CLK(n-1) would exit P.D. 2 EXIT P.D. Idle Maintain power down mode Refer to operations in Operative Command Table 2 H L H X H L L H H L L H H L L L L H X X L L X X H X X X X X X L H X X X X X L L X X H H X X X X H X X H H L H X X H H L L H X H H L L H H L L L L H L H L H X X X H L L H X X H L L L H X H L L L L H H L L L L L L X X X H H X X X X X X X X H L X X X X X L H X X L L X X 5 Refer to operations in Operative Command Table Refer to operations in Operative Command Table X Auto Refresh Op-Code Refer to operations in Operative Command Table X Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh 3 Op-Code Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle X X X Exit clock suspend next cycle X X X Maintain clock suspend Note 1. H : Hight level, L : low level, X : High or low level (Don't care) 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. IIIegal if tSREX is not satisfied. Document : 1G5-0154 2 2 Rev.1 Page 13 3 4 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 5.Mode Register (Address Input for Mode Set) 13 12 11 0 0 0 10 0 9 0 8 0 1 13 12 x x 11 x 10 x 9 1 8 0 7 0 6 13 12 x x 11 x 10 x 9 0 8 0 7 0 6 7 6 5 4 3 2 Reserved 5 4 LTMODE 5 4 LTMODE 3 3 1 0 JEDEC Standard Test Set 2 WT 1 2 WT 1 0 BL Burst Read and Single Write (for Write Through Cache) 0 BL Burst Read and Burst Write X = Don't care Bits2 - 0 WT = 0 WT = 1 1 1 000 Burst length Wrap type 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 R R 111 Full page R 0 1 Sequential Interleave Bits6 - 4 CAS Iatency R 000 001 Latency mode R 010 2 011 3 100 R 101 R 110 R 111 R Remark R : Reserved Document : 1G5-0154 Rev.1 Page 14 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 5.1 Burst Length and Sequence (Burst of Two) Starting Address (column address A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 (Burst of Four) Starting Address (column address A1 - A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 (Burst of Eight) Starting Address (column address A2 - A0, binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1 ,2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6 ,7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 2048 / 1024 / 512 for 32M x 4 / 16M x 8 / 8M X16 devices, respectively. Document : 1G5-0154 Rev.1 Page 15 VIS VG36128401A VG36128801A VG36128161A Preliminary CMOS Synchronous Dynamic RAM 6 Address Bits of Bank-Select and precharge 6.1 Quad banks controlled by A12 & A13 Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A12 A13 0 0 Select Bank A "Activate " command 0 1 Select Bank B "Activate" command 1 0 Select Bank C "Activate" command 1 1 Select Bank D "Activate" command (Activate command) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Row (Precharge command) Rev.1 A12 A13 Result 0 0 0 Precharge Bank A 0 0 1 Precharge Bank B 0 1 0 Precharge Bank C 0 1 1 Precharge Bank D 1 X X Precharge All Banks 0 Disables Auto - Precharge (End of Burst) 1 Enables Auto - Precharge (End of Burst) Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (CAS strobes) Document : 1G5-0154 A10 Result A12 A13 Result 0 0 Enables Read/Write commands for Bank A 0 1 Enables Read/Write commands for Bank B 1 0 Enables Read/Write commands for Bank C 1 1 Enables Read/Write commands for Bank D Page 16 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 7.Precharge The precharge command can be asserted anytime after tRAS(min) is satisfied. Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows. PrechargeE T0 T1 T3 T2 T4 Burst lengh=4 T7 T6 T5 CLK Command Read PRE CAS latency = 2 DQ Q0 Command Q1 Read Q2 Hi - Z Q3 PRE CAS latency = 3 DQ Q1 Q0 Q2 Q3 Hi - Z CAS latency = 2 : One clock earlier than the last output data. 3 : Two clocks earlier than the last output data. (tRAS is satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter "t DPL" must be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing tDPL(min.) by the clock cycle time. In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. Document : 1G5-0154 CAS latency Read Write 2 -1 + tDPL(min.) 3 -2 + tDPL(min.) Rev.1 Page 17 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 8.Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically after the burst access. In the write cycle, t DAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied. A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles. The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write. 8.1 Read with Auto Precharge During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output. READ with AUTO PRECHARGE Burst lengh = 4 T0 T1 T4 T3 T2 T6 T5 T7 CLK No New Command to Bank B Command Auto precharge starts READA B CAS latency = 2 DQ QB0 QB1 QB2 Hi - Z QB3 No New Command to Bank B Auto precharge starts Command READA B CAS latency = 3 DQ QB0 QB1 QB2 QB3 Hi - Z Remark READA means READ with AUTO PRECHARGE Document : 1G5-0154 Rev.1 Page 18 T8 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 8.2 Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data word input to the device. WRITE with AUTO PRECHRGE Burst lengh = 4 T0 T1 T3 T2 T4 T5 T6 T7 CLK No New Command to Bank B Command AUTO PRECHARGE starts WRITA B tDPL CAS latency = 2 DQ DB0 DB1 DB2 Hi - Z_ DB3 No New Command to Bank B AUTO PRECHARGE starts Command WRITA B tDPL CAS latency = 3 DQ DB0 DB2 DB1 Hi - Z DB3 Remark WRITA means WRITE with AUTO Precharge In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. Document : 1G5-0154 CAS latency Read Write 2 -1 + tDPL(min.) 3 -2 + tDPL(min.) Rev.1 Page 19 T8 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 8.3 Multibank Operation- Read with Auto Precharge During a READA cycle interrupted by a Read, Write command of another banks, the auto-precharge scheduled time would not be changed. Multibank Operation Burst lengh=8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CLK Auto precharge bank A starts Command READA A Read B CAS latency=2 Hi-Z DQ QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 Auto precharge bank A starts Command READA A Read B CAS latency=3 DQ Hi-Z QA0 QA1 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 Similiar top.21 Document : 1G5-0154 Rev.1 Page 20 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 8.4 Multibank Operation- Write with Auto Precharge During a WRITEA cycle interrupted by a Read, Write command of another banks, the auto-precharge scheduled time would not be changed. Multibank Operation Burst lengh=8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK Auto precharge bank A starts Command WRITA A Read B CAS latency=2 DQ DB1 DB0 DA1 DA0 DB2 DB3 DB4 Hi-Z DB5 Auto precharge bank A starts Command WRITA A Read B CAS latency=3 DQ DB0 DA1 DA0 DB1 DB2 DB3 Hi-Z DB4 Multibank Operation Burst lengh=8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CLK Auto precharge bank A starts Command WRITA A Write B CAS latency=2 DQ DA0 DA1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Hi-Z Auto precharge bank A starts Command WRITA A Write B CAS latency=3 DQ Document : 1G5-0154 DA0 DA1 DB0 DB1 DB2 Rev.1 DB3 DB4 DB5 DB6 DB7 Hi-Z Page 21 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 9.Read/Write Command Interval 9.1 Read to Read command interval During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction. READ to READ Command Interval Burst lengh=4, CAS latency=2 T0 T1 T3 T2 T4 T6 T5 T7 T8 CLK Read B Read A Command DQ QA0 QB0 QB1 QB2 Hi-Z_ QB3 1 cycle 9.2 Write to Write Command Interval During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction. WRITE to WRITE Command Interval Burst lengh=4, CAS latency=2 T0 T1 T3 T2 T4 T5 T6 T7 CLK Command Write A Write B DQ QA0 QB0 QB1 QB2 QB3 Hi-Z_ 1 cycle Document : 1G5-0154 Rev.1 Page 22 T8 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 9.3 Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. WRITE to READ Command Interval Burst lengh=4 T0 T1 T2 T3 T4 T6 T5 T8 T7 CLK 1 cycle Command WRITE A Read B CAS latency=2 Hi-Z DA0 DQ Command Write A QB0 QB1 QB2 QB3 QB1 QB2 Read B CAS latency=3 DA0 DQ Hi-Z QB0 QB3 9.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write. Document : 1G5-0154 Rev.1 Page 23 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM READ to WRITE Command Interval T0 T1 T3 T2 T4 T6 T5 T7 CAS latency=2 T8 CLK Read Command Write DQM DQ Hi-Z D0 D1 D2 D3 1 cycle T0 T1 T3 T2 T4 T6 T5 T7 Burst length=8, CAS latency=2 T8 T9 CLK Command Write Read DQM Q0 DQ Q2 Q1 D0 D2 D1 Hi-Z is necessary example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T6 T5 T8 T7 CLK Command Read Write DQM DQ Q2 Hi-Z is D0 D1 D2 necessary The minimum command interval = (4+1) cycles Document : 1G5-0154 Rev.1 Page 24 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 10.BURST Termination There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command. 10.1 BURST Stop Command During a read burst. when the burst stop command is asserted, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command. During a write burst, when the burst stop command is asserted, any data provided at that cycle will not be written. The burst write is effectively terminated and no further data can be written until a new write command is asserted. Burst Termination T0 T1 T3 T2 T4 Burst lengh=X, CAS Intency=2,3 T7 T6 T5 CLK BST Read Command Q0 CAS latency=2 DQ CAS latency=3 Q1 Q2 Q0 Q1 Hi-Z Hi-Z Q2 DQ Remark BST: Burst stop command T0 T1 T3 T2 T4 T5 Burst lengh=X, CAS latency=2,3 T7 T6 CLK Command BST Write CAS latency=2,3 Q0 Q0 Q1 Q2 Hi-Z_ DQ Remark BST: Burst command Document : 1G5-0154 Rev.1 Page 25 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 10.2 PRECHARGE TERMINATION 10.2.1 PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is asserted, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2,the read data will remain valid until one clock after the precharge command. When CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Precharge Termination in READ Cycle T0 T1 T3 T2 T4 T6 T5 T7 Burst lengh= X T8 CLK Command PRE Read ACT CAS latency=2 Q0 DQ Q1 Q2 Hi-Z Q3 tRP command Read PRE ACT tRP CAS latency=3 DQ Document : 1G5-0154 Q0 Rev.1 Q1 Q2 Q3 Hi-Z Page 26 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM 10.2.2 Precharge Termination in WRITE Cycle During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is asserted, the burst write operation is terminated and precharge starts. The same bank can be activated again after t RP from the precharge command. The DQM must be high to mask invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. PRECHARGE TERMINATION in WRITE Cycle T0 T1 T3 T2 T4 T6 T5 T7 Burst lengh = X T8 CLK Command Write PRE ACT CAS latency = 2 DQM DQ D0 D1 D2 D3 Hi - Z D4 tRP command Write PRE ACT CAS latency = 3 DQM DQ D0 D1 D2 D3 D4 Hi - Z tRP Document : 1G5-0154 Rev.1 Page 27 VIS VG36128401A VG36128801A VG36128161A Preliminary CMOS Synchronous Dynamic RAM , Timing Diagram Document : 1G5-0154 Rev.1 Page 28 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Mode Register Set T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE t RSC CS RAS CAS WE BS A10 Address Key ADD DQM t RP DQ Hi-Z Precharge Command All Banks Document : 1G5-0154 Mode Register Set Command Command Rev.1 Page 29 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Parameters for Write Timing (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CH CKE t CL t CK2 t CMS t CKS Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D) t CKH t CMH CS RAS CAS WE BS A10 tAS tAH ADD DQM tRCD DQ tDAL t RRD tDS tRC t DH t DPL t RP QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank A Command Bank B (Bank D) Bank B Bank A (Bank D) Document : 1G5-0154 Write without Auto Precharge Command Bank A Rev.1 Precharge Command Bank A Activate Command Bank A Activate Command Bank B (Bank D) Page 30 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Parameters for Write Timing (2 of 2) Burst Length=4, CAS Latency=3,4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK t CL t CH CKE t CK3 t CMS t CKS Begin Auto Precharge Begin Auto Precharge Bank A Bank B (Bank D) t CKH t CMH CS RAS CAS WE BS A10 tAS tAH ADD DQM tRCD DQ t DAL t RRD t tDS RC t DH QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 Activate Command Bank A Document : 1G5-0154 Write with Activate Write with Auto Precharge Command Auto Precharge Command Bank B Command Bank A Bank B (Bank D) (Bank D) Activate Command Bank A Rev.1 t DPL t RP QAb0 QAb1 QAb2 QAb3 Write without Auto Precharge Command Bank A Precharge Command Bank A Activate Command Bank A Page 31 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Parameters for Read Timing (1 of 2) Burst Length=2, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CLK tCH tCL tCK2 Begin Auto Precharge Bank B (Bank D) tCMS t CMH CKE tCKS t CKH CS RAS CAS WE BS A10 tAS tAH ADD tRRD tRAS tRC DQM t AC2 tLZ t RCD DQ Hi-Z QAa0 Activate Command Bank A Document : 1G5-0154 tAC2 tOH Read Command Bank A Activate Command Bank B (Bank D) Rev.1 tHZ tOH QAa1 Read with Auto Precharge Command Bank B (Bank D) tRP tHZ QBa0 Precharge Command Bank A QBa1 Activate Command Bank A Page 32 T13 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM AC Parameters for Read Timing (2 of 2) Burst Length=2, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CLK t CH tCL CKE tCKS t CK3 Begin Auto Precharge Bank B (Bank D) t CMS t CMH t CKH CS RAS CAS WE BS A10 t AH t AS ADD t RRD t RAS t RP t RC DQM tAC3 tLZ t RCD DQ tAC3 tOH tHZ tOH Hi-Z QAa0 Activate Command Bank A Document : 1G5-0154 Read Command Bank A Activate Command Bank B (Bank D) Rev.1 QAa1 t QBa0 Read with Precharge Auto Precharge Command Command Bank A Bank B (Bank D) HZ QBa1 Activate Command Bank A Page 33 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Power on Sequence and Auto Refresh (CBR) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK High level is required CKE t RSC Minimum of 2 Refresh Cycles are required CS RAS CAS WE BS A10 Address Key ADD DQM High Level is Necessary t DQ t RC RP Hi-Z Precharge Inputs Command All Banks must be stable for 100us Document : 1G5-0154 1st Auto Refresh Command 2nd Auto Refresh Command Rev.1 Mode Register Set Command Command Page 34 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Clock Suspension During Burst Read (Using CKE) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM t DQ HZ Hi-Z QAa0 Activate Command Bank A Document : 1G5-0154 Read Command Bank A QAa1 Clock Suspended 1 Cycle QAa2 QAa3 Clock Suspended 2 Cycles Rev.1 Clock Suspended 3 Cycles Page 35 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Clock Suspension During Burst Read (Using CKE) (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM t HZ DQ Hi-Z QAa0 Activate Command Bank A Document : 1G5-0154 Read Command Bank A QAa1 Clock Suspended 1 Cycles QAa2 Clock Suspended 2 Cycles Rev.1 QAa3 Clock Suspended 3 Cycles Page 36 Preliminary VIS VG36128401A VG36128801A VG36128161A CMOS Synchronous Dynamic RAM Clock Suspension During Burst Write (Using CKE) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM DQ Hi-Z DAa0 Activate Command Bank A Document : 1G5-0154 DAa1 Clock Suspended 1 Cycle Write Command Bank A DAa2 Clock Suspended 2 Cycles DAa3 Clock Suspended 3 Cycles Rev.1 Page 37 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Clock Suspension During Burst Write (Using CKE) (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM DQ Hi-Z DAa0 Activate Command Bank A Document : 1G5-0154 DAa1 Clock Suspended 1 Cycle Write Command Bank A DAa2 Clock Suspended 2 Cycles DAa3 Clock Suspended 3 Cycles Rev.1 Page 38 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Power Down Mode and Clock Mask Burst Length=4, CAS Latency=2 CLK can be Stopped* T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 t t t CKS CKH CKS CKE VALID CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM t DQ HZ Hi-Z QAa0 QAa1 Activate Command Bank A ACTIVE STANDBY Power Down Mode Entry Document : 1G5-0154 QAa2 Precharge Command Read Command Bank A Power Down Mode Exit QAa3 Clock Mask Start Rev.1 Clock Mask End Power Down Mode Entry Precharge Standby Power Down Mode Exit Command Page 39 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Auto Refresh (CBR) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa DQM t DQ RP t RC t RC Hi-Z Q0 Precharge CBR Refresh Command Command All Banks Document : 1G5-0154 CBR Refresh Command Rev.1 Q1 Q2 Q3 Activate Read Command Command Page 40 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Self Refresh (Entry and Exit) CLK can be Stopped* T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t SRX t SRX t CKS t CKS CKE CS RAS CAS WE BS A10 ADD t RC DQM DQ t RC Hi-Z All Banks must be idle Self refresh Entry Self Refresh Exit Self Refresh Entry Self Refresh Exit Activate Command * Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High Document : 1G5-0154 Rev.1 Page 41 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Column Read (Page Within same Bank)(1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 RAa ADD RAa RAd RAa CAa CAb CAc RAd CAd DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 Precharge Command Bank A Document : 1G5-0154 Read Command Bank A Read Read Command Command Bank A Bank A QAd0 QAd1 QAd2 QAd3 Precharge Activate Read Command Command Command Bank A Bank A Bank A Rev.1 Page 42 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Column Read (Page Within same Bank)(2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS A10 RAa ADD RAa RAd CAa CAb CAc RAd CAd DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 Activate Command Bank A Document : 1G5-0154 Read Command Bank A Read Read Command Command Bank A Bank A Rev.1 Precharge Command Bank A Activate Command Bank A Read Command Bank A Page 43 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Column Write (Page Within same Bank) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 Ra ADD Ra Rd Cb Ca Cc Rd Cd DQM DQ Hi-Z Da0 Activate Command Bank B (Bank D) Document : 1G5-0154 Da1 Write Command Bank B (Bank D) Da2 Da3 Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Dd2 Dd3 Precharge Activate Write Command Command Command Bank B Bank B Bank B (Bank D) (Bank D) (Bank D) Write Write Command Command Bank B Bank B (Bank D) (Bank D) Rev.1 Page 44 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Column Write (Page Within same Bank) (1 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE CS RAS CAS WE BS A10 Ra ADD Ra Rd Cb Ca Cc Rd Cd DQM DQ Hi-Z Da0 Activate Command Bank B (Bank D) Document : 1G5-0154 Da1 Write Command Bank B (Bank D) Da2 Da3 Db0 Db1 Write Command Bank B (Bank D) Dc0 Dc1 Write Command Bank B (Bank D) Rev.1 Dc2 Dc3 Precharge Command Bank B (Bank D) Dd0 Activate Command Bank B (Bank D) Dd1 Write Command Bank B (Bank D) Page 45 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Row Read (Interleaving Banks)(1 of 2) Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS A10 ADD t DQM DQ RCD Hi-Z Activate Command Bank B (Bank D) t AC2 t RP QBb0 QBb1 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Read Command Bank B (Bank D) Activate Command Bank A Precharge Active Command Command Bank B Bank B (Bank D) (Bank D) Read Command Bank B (Bank D) Read Command Bank A Document : 1G5-0154 Rev.1 Page 46 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Row Read (Interleaving Banks) (2 of 3) Burs tLength=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS A10 ADD t DQM DQ t RCD t AC3 RP Hi-Z QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 Activate Command Bank B (Bank D) Document : 1G5-0154 Read Command Bank B (Bank D) Activate Command Bank A Read Command Bank A Rev.1 Precharge Command Bank B (Bank D) Activate Command Bank B (Bank D) Read Precharge Command Command Bank B Bank A (Bank D) Page 47 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Row Write (Interleaving Banks) (1 of 2) Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS A10 ADD t RCD DQM DQ Hi-Z Activate Command Bank A Document : 1G5-0154 t DPL t RP t DPL QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4 Write Command Bank A Activate Command Bank B (Bank D) Precharge Active Command Command Bank A Bank A Write Command Bank B (Bank D) Rev.1 Write Command Bank A Precharge Command Bank B (Bank D) Page 48 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Random Row Write (Interleaving Banks) (2 of 2) Burst Length=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE High CS RAS CAS WE BS A10 ADD RBa t RCD DQM DQ Hi-Z Activate Command Bank A Document : 1G5-0154 t DPL t DPL t RP QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3 Write Command Bank A Activate Command Bank B (Bank D) Write Command Bank B (Bank D) Rev.1 Precharge Command Bank A Activate Command Bank A Precharge Write Command Command Bank B Bank A (Bank D) Page 49 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Read and Write Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAb CAa CAc DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Document : 1G5-0154 Write Command Bank A DAb0 DAb1 DAb3 The Write Data Write Command is Masked with a Bank A Zero Clock latency Rev.1 QAc0 QAc1 Read Command Bank A QAc3 The Read Data is Masked with Two Clocks Latency Page 50 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Read and Write Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS A10 RAa ADD RAa CAa CAb CAc DQM DQ Hi-Z DAb0 DAb1 QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Read Command Bank A DAb3 Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock Latency Document : 1G5-0154 Rev.1 QAc0 QAc1 QAc3 The Read Data is Masked with a Two Clock Latency Page 51 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Interleaved Column Read Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 Ra ADD Ra Cb t DQM DQ Ra RCD Ra Ca Cb Cc Cb Cd t AC2 Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3 Activate Command Bank A Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B (Bank D) (Bank D) (Bank D) (Bank D) (Bank D) Precharge Command Bank B (Bank D) Precharge Command Bank A Document : 1G5-0154 Rev.1 Page 52 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Interleaved Column Read Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ca Ra Cb Cc Cb DQM t RCD t RRD DQ t AC3 Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Read Command Bank A Activate Command Bank B (Bank D) Document : 1G5-0154 Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A (Bank D) (Bank D) (Bank D) (Bank D) Rev.1 Page 53 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Interleaved Column Write Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ca Cb Cc Cb t RCD DQM t DQ Ra Cb t RP t DPL RRD Hi-Z DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3 Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A (Bank D) (Bank D) (Bank D) (Bank D) Document : 1G5-0154 Rev.1 Precharge Command Bank A Write Command Bank B (Bank D) Precharge Command Bank B (Bank D) Page 54 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Interleaved Column Write Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ca Cb t RCD DQM t DQ Ra Cc Cb Cd t DPL t DPL t RP RRD Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3 Activate Command Bank A Write Command Bank A Activate Command Bank B (Bank D) Document : 1G5-0154 Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B (Bank D) (Bank D) (Bank D) (Bank D) Precharge Command Bank B (Bank D) Precharge Command Bank A Rev.1 Page 55 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Auto Precharge after Read Burst (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKE CK2 High Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D) CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ra Rb Ca Cb Rb Rc Cb Rc Cc DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command (Bank D) Bank B (Bank D) Document : 1G5-0154 Read with Auto Precharge Command Bank A Activate Command Read with Bank A Auto Precharge Command Read with Activate Bank B Auto Precharge Command (Bank D) Command Bank B Bank A (Bank D) Rev.1 Page 56 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Auto Precharge after Write Burst (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKE CK3 High Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D) CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ra Rb Ca Cb Rb RBb Cb DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Activate Command Bank B (Bank D) Read with Auto Precharge Command Bank B (Bank D) Read with Auto Precharge Command Bank A Activate Command Bank B (Bank D) QBb0 QBb1 QBb2 Write with Auto precharge Command Bank B (Bank D) Read Command Bank A Document : 1G5-0154 Rev.1 Page 57 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Auto Precharge after Write Burst (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKE CK2 High Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank A CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ra Rb Ca Cb Rb Rc Cb Rc Cc DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B (Bank D) (Bank D) Document : 1G5-0154 Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A (Bank D) Auto Precharge Write with Bank A Auto Precharge Command Bank B (Bank D) Rev.1 Start Auto Precharge Bank A Page 58 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Auto Precharge after Write Burst (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE High Start Auto Precharge Bank A Start Auto Precharge Bank B (Bank D) Start Auto Precharge Bank B (Bank D) CS RAS CAS WE BS A10 Ra ADD Ra Ra Ca Ra Rb Ca Cb Rb RBb Cb DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Activate Command Bank B (Bank D) Read with Auto Precharge Command Bank B (Bank D) Read with Auto Precharge Command Bank A Activate Command Bank B (Bank D) QBb0 QBb1 QBb2 QBb3 Write with Auto precharge Command Bank B (Bank D) Read Command Bank A Document : 1G5-0154 Rev.1 Page 59 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Read Cycle (1 of 2) Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS A10 Ra ADD Ra Rb Ra Ca Ca Ra Rb t RP DQM DQ Hi-Z QAa Activate Command Bank A Document : 1G5-0154 Read Command Bank A QAa+1 QAa+2 QAa-2 QAa-1 Activate Command Bank B (Bank D) QAa QAa+1 QBa Read Command Bank B (Bank D) QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6 Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address The burst counter wraps from the highest order page address back to zero during this time interval Rev.1 Precharge Command Bank B (Bank D) Burst Stop Command Activate Command Bank B (Bank D) Page 60 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Read Cycle (2 of 2) Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS A10 Ra ADD Ra Rb Ra Ca Ca Ra Rb DQM DQ Hi-Z QAa Activate Command Bank A Document : 1G5-0154 Read Command Bank A Activate Command Bank B (Bank D) QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 Full page burst operation Read does not teminate when Command the burst length is satisfied; Bank B the burst counter increments (Bank D) and continues bursting The burst counter wraps beginning with the starting from the highest order address page address back to zero during this time interval Rev.1 Precharge Command Bank B (Bank D) Burst Stop Command Activate Command Bank B (Bank D) Page 61 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Write Cycle (1 of 2) Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS A10 Ra ADD Ra Rb Ra Ca Rb Ca Ra DQM t DQ BDL Hi-Z QAa Activate Command Bank A Document : 1G5-0154 QAa+1 QAa+2 QAa+3 QAa-1 Write Command Bank A QAa QAa+1 Activate Command Bank B (Bank D) The burst counter wraps from the highest order page address back to zero during this time interval QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6 Write Command Bank B (Bank D) Data is ignored Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Rev.1 Precharge Command Bank B (Bank D) Burst Stop Command Activate Command Bank B (Bank D) Page 62 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Write Cycle (2 of 2) Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK CKE High CS RAS CAS WE BS A10 Ra ADD Ra Rb Ra Ca Rb Ca Ra DQM tBDL DQ Data is ignored. Hi-Z DAa Activate Command Bank A Document : 1G5-0154 DAa+1 DAa+2 DAa+3 DAa-1 Write Command Bank A DAa DAa+1 Activate Command Bank B (Bank D) The burst counter wraps from the highest order page address back to zero during this time interval DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 Write Command Bank B (Bank D) Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Rev.1 Precharge Command Bank B (Bank D) Burst Stop Command Activate Command Bank B (Bank D) Page 63 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Byte Write Operation Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE t T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK2 High CS RAS CAS WE BS A10 RAa ADD RAa CAa CAz CAb LDQM UDQM DQ0~DQ7 Hi-Z DQ8~DQ15 Hi-Z Activate Command Bank A Document : 1G5-0154 Read Command Bank A Upper Byte is masked Lower Byte is masked Write Command Bank A Read Write Upper Command is masked Bank A Rev.1 Lower Byte is masked Lower Byte is masked Page 64 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Burst Read and Single Write Operation Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK CKE T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CK2 High CS RAS CAS WE BS A10 RAa ADD RAa CAa CAb CAc CAd CAe LDQM UDQM DQ0~DQ7 Hi-Z DQ8~DQ15 Hi-Z Activate Command Bank A Document : 1G5-0154 Read Command Bank A Read Single Write Single Write Command Command Command Bank A Bank A Bank A Rev.1 Lower Byte is masked Upper Byte is masked Single Write Command Bank A Page 65 Lower Byte is masked VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Random Column Read Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 Ra Ra ADD Ra Ra Rb Ca Ca Cb Cc Cb Cc Rb t RP DQM DQ Hi-Z QAa0 QBa0 Activate Command Bank A Document : 1G5-0154 QAb0 QAb1 Read Read Command Command Bank B Bank B (Bank D) (Bank D) Read Read Command Command Bank A Bank A Activate Command Bank B (Bank D) QBb0 QBb1 Read Command Bank A QAc0 QAc1 QAc2 Read Command Bank B (Bank D) QBc0 QBc1 QBc2 Precharge Command Bank B (Bank D) (Precharge Termination) Activate Command Bank B (Bank D) Rev.1 Page 66 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Full Page Random Column Write Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS A10 Ra Ra ADD Ra Ra Rb Ca Ca Cb Cc Cb Cc Rb t RP DQM DQ Hi-Z QAa0 Activate Command Bank A Document : 1G5-0154 QBa0 QAb0 QAb1 QBb0 QBb1 Write Write Command Command Bank B Bank B (Bank D) (Bank D) Write Write Command Command Bank A Bank A Activate Command Bank B (Bank D) QAc0 QAc1 Write Command Bank A QAc2 QBc0 QBc1 Write Command Bank B (Bank D) QBc2 Precharge Command Bank B (Bank D) (Precharge Termination) Write Data is masked Rev.1 Activate Command Bank B (Bank D) Page 67 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Precharge Termination of a Burst (1 of 2) Burst Length=4,8 or Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS A10 RAa ADD RAa RAb CAa RAb t DPL t RAc CAb RAc t RP CAc t RP RP DQM DQ Hi-Z QAa0 Activate Command Bank A QAa1 Write Command Bank A QAa2 QAb0 Da3 Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Termination of a Write Burst. Write data is masked. Document : 1G5-0154 QAb1 QAb2 Precharge Command Bank A Activate Command Bank A QAc0 Read Command Bank A QAc1 QAc2 Precharge Command Bank A Precharge Termination of a Read Burst. Rev.1 Page 68 VG36128401A VG36128801A VG36128161A Preliminary VIS CMOS Synchronous Dynamic RAM Precharge Termination of a Burst (2 of 2) Burst Length=4,8 or Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS A10 RAa ADD RAa RAb CAa RAb t DPL t DQM DQ t RAc CAb t RP RAc t RAS RP RCD Hi-Z DAa0 Activate Command Bank A Write Command Bank A Precharge Command Bank A Write Data is masked Document : 1G5-0154 QAb0 DAa1 Activate Command Bank A Read Command Bank A QAb1 QAb2 Activate Command Bank A QAb3 Activate Command Bank A Precharge Termination of a Read Burst. Precharge Termination of a Write Burst. Rev.1 Page 69