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FEATURES
DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
SN65LVDT32B
1
2
3
4
8
7
6
5
VCC
1Y
2Y
GND
1A
1B
2A
2B
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
SN65LVDS32B
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Logic Diagram
(positive logic)
SN65LVDT32B
ONLY (4 Places)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
VCC
4B
4A
4Y
3,4EN
3Y
3A
3B
SN65LVDT3486B
D PACKAGE
(TOP VIEW)
SN65LVDS3486B
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Logic Diagram
(positive logic)
SN65LVDT3486B
ONLY (4 Places)
1,2EN
3,4EN
1A
1B
2A
2B
1Y
2Y
SN65LVDT9637B
ONLY
SN65LVDT9637B
SN65LVDS9637B
Logic Diagram
(positive logic)
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
HIGH-SPEED DIFFERENTIAL RECEIVERS
•Meets or Exceeds the Requirements of ANSIEIA/TIA-644 Standard for Signaling Rates
(1)
upto 400 Mbps•Operates With a Single 3.3-V Supply•–2-V to 4.4-V Common-Mode Input VoltageRange
•Differential Input Thresholds <50 mV With50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range•Integrated 110- ΩLine Termination ResistorsOffered With the LVDT Series•Propagation Delay Times 4 ns (typ)•Active Fail Safe Assures a High-Level OutputWith No Input•Bus-Pin ESD Protection Exceeds 15 kV HBM•Inputs Remain High-Impedance on PowerDown
•Recommended Maximum Parallel Rate of200 M-Transfer/s
•Available in Small-Outline Package With1,27-mm Terminal Pitch•Pin-Compatible With the AM26LS32, MC3486,or µA9637
This family of differential line receivers offersimproved performance and features that implementthe electrical characteristics of low-voltage differentialsignaling (LVDS). LVDS is defined in theTIA/EIA-644 standard. This improved performancerepresents the second generation of receiverproducts for this standard, providing a better overallsolution for the cabled environment. This generationof products is an extension to TI's overall productportfolio and is not necessarily a replacement forolder LVDS receivers.
(1) Signaling rate, 1/t, where t is the minimum unit interval and isexpressed in the units bit/s (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Improved features include an input common-mode voltage range 2 V wider than the minimum required by thestandard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between adriver and receiver. TI has additionally introduced an even wider input common-mode voltage range of –4 to 5 Vin their SN65LVDS/T33 and SN65LVDS/T34.
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltagehysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no morethan ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matchingresistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminatesthis external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also availablefor multidrop or other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostaticdischarges to the receiver input pins with respect to ground without damage. This provides reliability in cabledand other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 nsafter loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, orpowered-down transmitters. This prevents noise from being received as valid data under these fault conditions.This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband datatransmission over controlled impedance media of approximately 100 Ω. The transmission media may beprinted-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependentupon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, andSN65LVDT9637B are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
NUMBER OF TERMINATIONPART NUMBER
(1)
SYMBOLIZATIONRECEIVERS RESISTOR
SN65LVDS32BD 4 No LVDS32BSN65LVDT32BD 4 Yes LVDT32BSN65LVDS3486BD 4 No LVDS3486SN65LVDT3486BD 4 Yes LVDT3486SN65LVDS9637BD 2 No DK637BSN65LVDT9637BD 2 Yes DR637B
(1) Add the suffix R for taped and reeled carrier.
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FUNCTION TABLES
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
SN65LVDS32B and SN65LVDT32B
DIFFERENTIAL INPUT ENABLES
(1)
OUTPUT
(1)
A-B G G YH X HV
ID
≥–32 mV
X L HH X ?–100 mV < V
ID
≤–32 mV
X L ?H X LV
ID
≤–100 mV
X L LX L H ZH X HOpen
X L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
SN65LVDS3486B and SN65LVDT3486B
DIFFERENTIAL INPUT ENABLES
(1)
OUTPUT
(1)
A-B EN YV
ID
≥–32 mV H H–100 mV < V
ID
≤–32 mV H ?V
ID
≤–100 mV H LX L ZOpen H H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
SN65LVDS9637B and SN65LVDT9637B
DIFFERENTIAL INPUT OUTPUT
(1)
A-B YV
ID
≥-32 mV H–100 mV < V
ID
≤-32 mV ?V
ID
≤-100 mV LOpen H
(1) H = high level, L = low level, ? = indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
37 Ω
7 V
Y Output
LVDT Only 110 Ω
7 V
300 kΩ
50 Ω
VCC
Enable
Inputs
300 kΩ
(G Only)
(EN and G Only)
7 V
VCC
Attenuation
Network
A Input
Attenuation
Network
B Input
7 V
VCC
Attenuation
Network
60 kΩ
250 kΩ
200 kΩ
1 pF
3 pF
7 V
7 V
6.5 kΩ6.5 kΩ
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 VEnables or Y –0.5 V to V
CC
+ 3 VVoltage range A or B –4 V to 6 V|V
A
– V
B
| (LVDT) 1 VElectrostatic discharge: A, B, and GND
(3)
Class 3, A: 15 kV, B: 600 VContinuous power dissipation See Dissipation Rating TableStorage temperature range –65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with MIL-STD-883C Method 3015.7.
T
A
≤25°C OPERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
D8 725 mW 5.8 mW/°C 377 mWD16 950 mW 7.6 mW/°C 494 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage Enables 2 VV
IL
Low-level input voltage Enables 0.8 VLVDS 0.1 3 V| V
ID
| Magnitude of differential input voltage
LVDT 0.8 VV
I
or V
IC
Voltage at any bus terminal (separately or common-mode) –2 4.4 VT
A
Operating free-air temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT1
Positive-going differential input voltage threshold 50V
IB
= -2 V or 4.4 V,
mVSee Figure 1 and Figure 2V
IT2
Negative-going differential input voltage threshold –50V
IT3
Differential input fail-safe voltage threshold See Table 1 and Figure 5 –32 –100 mVV
ID(HYS)
Differential input voltage hysteresis, V
IT1
– V
IT2
50 mVV
OH
High-level output voltage I
OH
= –4 mA 2.4 VV
OL
Low-level output voltage I
OL
= 4 mA 0.4 VG or EN at V
CC
, No load, Steady-state 16 23'32B or '3486BI
CC
Supply current G or EN at GND 1.1 5 mA'9637B No load, Steady-state 8 12V
I
= 0 V, Other input open ±20V
I
= 2.4 V, Other input open ±20SN65LVDS µAV
I
= –2 V, Other input open ±40V
I
= 4.4 V, Other input open ±40I
I
Input current (A or B inputs)
V
I
= 0 V, Other input open ±40V
I
= 2.4 V, Other input open ±40SN65LVDT µAV
I
= –2 V, Other input open ±80V
I
= 4.4 V, Other input open ±80V
ID
= 100 mV, V
IC
= –2 V or 4.4 V,SN65LVDS ±3 µADifferential input current
See Figure 1I
ID
(I
IA
- I
IB
)
SN65LVDT V
ID
= 0.2 V, V
IC
= –2 V or 4.4 V 1.55 2.22 mAV
A
or V
B
= 0 V or 2.4 V, V
CC
= 0 V ±20SN65LVDS
V
A
or V
B
= –2 V or 4.4 V, V
CC
= 0 V ±35Power-off input currentI
I(OFF)
µA(A or B inputs)
V
A
or V
B
= 0 V or 2.4 V, V
CC
= 0 V ±30SN65LVDT
V
A
or V
B
= –2 V or 4.4 V, V
CC
= 0 V ±50I
IH
High-level input current (enables) V
IH
= 2 V 10 µAI
IL
Low-level input current (enables) V
IL
= 0.8 V 10 µAI
OZ
High-impedance output current ±10 µAC
I
Input capacitance, A or B input to GND V
I
= 0.4 sin (4E6 πt) + 0.5 V 5 pF
(1) All typical values are at 25°C and with a 3.3 V supply.
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SWITCHING CHARACTERISTICS
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 2.5 4 6 nsSee Figure 3t
PHL
Propagation delay time, high-to-low-level output 2.5 4 6 nst
d1
Delay time, fail-safe deactivate time 9 nsSee Figure 3 andFigure 6t
d2
Delay time, fail-safe activate time 0.3 1.5 µst
sk(p)
Pulse skew (|t
PHL1
- t
PLH1
|) 200 pst
sk(o)
Output skew
(2)
150 pst
sk(pp)
Part-to-part skew
(3)
C
L
= 10 pF, See Figure 3 1 nst
r
Output signal rise time 0.8 nst
f
Output signal fall time 0.8 nst
PHZ
Propagation delay time, high-level-to-high-impedance output 5.5 9 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 4.4 9 nsSee Figure 4t
PZH
Propagation delay time, high-impedance -to-high-level output 3.8 9 nst
PZL
Propagation delay time, high-impedance-to-low-level output 7 9 ns
(1) All typical values are at 25°C and with a 3.3-V supply.(2) t
sk(o)
is the magnitude of the time difference between the t
PLH
or t
PHL
of all receivers of a single device with all of their inputs driventogether.
(3) t
sk(pp)
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when bothdevices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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PARAMETER MEASUREMENT INFORMATION
VID
A
B
Y
VO
VIB
VIA
VIC
(VIA + VIB)/2 IIB
IIA VO
VID
VO
10 pF,
2 Places 10 pF
100 Ω†
1000 Ω
1000 Ω
100 Ω
VIC
VID
VO
VID
VO
VIT1
0 V
–100 mV
100 mV
0 V
VIT2
†Removed for testing the LVDT device
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
+
–
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
Figure 1. Voltage and Current Definitions
Figure 2. V
IT1
and V
IT2
Input Voltage Threshold Test Circuit and Definitions
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VID
VO
VIB
VIA CL = 10 pF
tPHL tPLH
tftr
80%
20%
80%
20%
VIA
VIB
VID
VO
1.4 V
1 V
0.4 V
0 V
–0.4 V
VOH
1.4 V
VOL
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A. All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 50 Mpps, Pulsewidth = 10 ±0.2 ns . C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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B
A
G
G
VO±
500 Ω
VTEST
10 pF
1.2 V
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH
VOH –0.5 V
1.4 V
0
VTEST
A
G, 1,2EN,or 3,4EN
G
Y
VTEST
A
G
Y
Inputs
G, 1,2EN,or 3,4EN
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
1,2,EN, or 3,4, EN
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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VIA
VIB
VO
–100 mV @ 250 KHz
–32 mV @ 250 KHz
Failsafe Asserted
VIA
VIB
VO
a) No Failsafe
b) Failsafe Asserted
td1 td2
1.4 V
1 V
0.4 V
0 V
–0.4 V
VOH
1.4 V
VOL
–0.2 V
>1.5 µs
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
Table 1. Receiver Minimum and Maximum V
IT3
Input Threshold Test Voltages
APPLIED VOLTAGES
(1)
RESULTANT INPUTS
V
IA
(mV) V
IB
(mV) V
ID
(mV) V
IC
(mV) Output
–2000 –1900 –100 –1950 L–2000 –1968 –32 –1984 H4300 4400 –100 4350 L4368 4400 –32 4384 H
(1) These voltages are applied for a minimum of 1.5 µs.
Figure 5. V
IT3
Failsafe Threshold Test
Figure 6. Waveforms for Failsafe Activate and Deactivate
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TYPICAL CHARACTERISTICS
0IOL − Low-Level Output Current − mA
4
3
020 30
2
10
VCC = 3.3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
5
40
IOH − High-Level Output Current − mA
VOH− High-Level Output Voltage − V
4
3
0
2
1
−30 −20−40 0−10
VCC = 3.3 V
TA = 25°C
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
− Low-To-High Propagation Delay Time − ns
tPLH
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
− High-To-Low Propagation Delay Time − ns
tPHL
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGEvs vsLOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT CURRENT
Figure 7. Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME HIGH-TO-LOW PROPAGATION DELAY TIMEvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 9. Figure 10.
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80
60
20
00 100
100
120
150 200
40
− Supply Current − mAICC
f − Switching Frequency − MHz
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
140
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vsFREQUENCY
Figure 11.
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APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100 Ω
100 Ω
100 Ω
(see Note B)
100 Ω
VCC
See Note C
≈3.6 V
0.1 µF
(see Note A) 1N645
(2 places)
0.01 µF
5 V
RELATED INFORMATION
TERMINATED FAILSAFE
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
CC
and the groundplane. The capacitor should be located as close as possible to the device terminals.B. The termination resistance value should match the nominal characteristic impedance of the transmission media with±10%.
C. Unused enable inputs should be tied to V
CC
or GND as appropriate.
Figure 12. Operation with 5-V Supply
IBIS modeling is available for this device. contact the local TI sales office or the TI Web site at www.ti.com formore information.
For more application guidelines, see the following documents:•Low-Voltage Differential Signaling Design Notes (SLLA014 )•Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038 )•Reducing EMI With LVDS (SLLA030 )•Slew Rate Control of LVDS Circuits (SLLA034 )•Using an LVDS Receiver With RS-422 Data (SLLA031 )•Evaluating the LVDS EVM (SLLA033 )
A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. CurrentLVDS fail-safe solutions require either external components with subsequent reduction in signal quality orintegrated solutions with limited application. This family of receivers has a new integrated fail-safe that solvesthe limitations seen in present solutions. A detailed theory of operation is presented in application note TheActive Fail-Safe Feature of the SN65LVDS32A (SLLA082 ).
Figure 13 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to ahigh-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form awindow comparator. The window comparator has a much slower response than the main receiver and detectswhen the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs.When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.
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_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
BR
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
R3 R3
VCCICC
5 Meters
of CAT-5
R1 R1
VEE R2
VCCICC
R3 = 240 Ω
R1 = 50 Ω
R2 = 50 Ω
VBVBLVDSLV/PECL
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 13. Receiver With Terminated Failsafe
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer ofchoice for system designers. Designers know of the established technology and that it is capable of high-speeddata transmission. In the past, system requirements often forced the selection of ECL. Now technologies likeLVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be adesign option, designers have been able to take advantage of LVDS by implementing a small resistor dividernetwork at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-modeLVDS receiver (no divider network required) which can be connected directly to an ECL driver with only thetermination bias voltage required for ECL termination (V
CC
– 2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being receivedby TI's wide common-mode receiver and the resulting eye pattern. The values for R3 are required in order toprovide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match thecharacteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possiblecommon-mode current reflections.
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
15Submit Documentation Feedback
www.ti.com
TEST CONDITIONS
EQUIPMENT
Tektronix PS25216
Programmable
Power Supply
Bench Test Board
Tektronix HFS 9003
Stimulus System
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
– DPO
Trigger
SN65LVDS32B , , SN65LVDT32BSN65LVDS3486B , SN65LVDT3486BSN65LVDS9637B , SN65LVDT9637B
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 15. LV/PECL to Remote SN65LVDS32B at 500 Mbps Receiver Output (CH1)
•V
CC
= 3.3 V•T
A
= 25°C (ambient temperature)•All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZdata.
•Tektronix PS25216 programmable power supply•Tektronix HFS 9003 stimulus system•Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Figure 16. Equipment Setup
16
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LVDS32BD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS32BDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS32BDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS32BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3486BD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3486BDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3486BDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3486BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9637BD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9637BDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9637BDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9637BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT32BD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT32BDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT32BDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT32BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT3486BD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT3486BDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT3486BDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT9637BD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT9637BDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT9637BDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDT9637BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNLVDT3486BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jan-2009
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jan-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS32BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS3486BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDS9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDT32BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDT3486BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDT9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS32BDR SOIC D 16 2500 333.2 345.9 28.6
SN65LVDS3486BDR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS9637BDR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDS9637BDR SOIC D 8 2500 367.0 367.0 35.0
SN65LVDT32BDR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDT3486BDR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDT9637BDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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