Kingmax - Memory Module MSPA83S - 68KX MSPA83S-68KX (PC-100 128MB 144Pin SDRAM SO-DIMM) DESCRIPTION The MSPA83S-68KX is 16M bit x 64 Synchronous Dynamic RAM high density memory module. The MSPA83S-68KX consists of eight CMOS 16M x 8 bit with 4 banks Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin TSSOP package on a 144-Pin glass-epoxy substrate. One 0.1uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The MSPA83S-68KX is a Small Outline Dual in-line Memory Module and is intended for mounting into 144-Pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies , programmable latencies allows the same device to be useful for a variety of high bandwidth , high performance memory system application. FEATURES Performance range - 100MHz Max Freq.( CL=3&2 ) Burst mode operation Auto & self refresh capability (4096 Cycles / 64ms ) LVTTL compatible inputs and outputs Single 3.3V + 0.3V power supply MRS cycle with address key programs Latency ( Access from column address ) Burst length ( 1 , 2 , 4 , 8 & Full page ) Data scramble ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Signal 3.3V +/- 0.3V power supply Serial presence detect with EEPROM PCB : Height ( 1181 mil ), singal sided component Kingmax - Memory Module MSPA83S - 68KX PIN CONFIGURATIONS (Front side/back side) Pin Front Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 Vss DQM0 DQM1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Front Pin Front Pin Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQM4 DQM5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc RAS WE CS0 CS1 DU Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Back DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 *A12 *A13 CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 Pin 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Back DQ22 DQ23 Vcc A6 A8 Vss A9 A10/AP Vcc DQM2 DQM3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss **SDA Vcc PIN NAMES Pin Back 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS **SCL Vcc Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM Vcc VSS Power supply (3.3V) SDA Serial data I/O SCL DU Serial clock Don t use NC No connection Ground * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM. CKE Clock enable Masks system clock to freeze operation from the next clock c ycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time . RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. Kingmax - Memory Module MSPA83S - 68KX FUNCTIONAL BLOCK DIAGRAM CS0 PCLK3 PCLK1 PCLK0 CLK CLK CS DQM DQM0 DQ0~7 DQ0~7 CLK DQM4 D1 DQ7~15 DQ0~7 CLK DQ16~23 DQ0~7 CLK DQM3 CLK DQM5 D2 DQ0~7 CLK DQM6 DQ48~55 SDRAM U1 ~ U8 RAS SDRAM U1 ~ U8 CAS SDRAM U1 ~ U8 WE SDRAM U1 ~ U8 CKE0 SDRAM U1 ~ U8 CS DQ0~7 CLK D7 CS DQM DQM7 D4 D6 DQM CS A0 ~ An, BA0 & 1 CS DQ0~7 CS D3 D5 DQM DQ40~47 DQM DQ24~31 DQ0~7 CS DQM DQM2 DQM DQ32~39 DQM DQM1 CS DQ0~7 DQ56~63 D8 10 CLK0 PCLK0 10 PCLK1 10 DQn Every DQpin of SDRAMs Serial PD SCL WP VDD One 0.1uF Capacitors per each SDRAM Vss To all SDRAMs A0 A1 A2 SDA Kingmax - Memory Module MSPA83S - 68KX ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +125 C Power dissipation PD 32 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced toV SS = 0V, TA = 0 to 70C) Parameter Symbol Min Typ Max Unit Supply voltage VDD 3.0 3.3 3.6 V Note Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1 Input low voltage VIL -0.5 0 0.8 V 2 Output high voltage VOH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA Input leakage current (Inputs) IIL -5 - 5 uA 3 Input leakage current (I/O pins) IIL -3 - 3 uA 3,4 Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for a ll bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ. CAPACITANCE (VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Parameter Symbol Min Max Unit Input capacitance (A0 ~ A11, BA0 ~ BA1) CIN1 22 35 pF Input capacitance (RAS, CAS, WE) CIN2 22 35 pF Input capacitance (CKE0) CIN3 25 45 pF Input capacitance (CLK0) CIN4 25 40 pF Input capacitance (CS0 ) CIN5 25 40 pF Input capacitance (DQM0 ~ DQM7) CIN6 10 18 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 6 10 pF Kingmax - Memory Module MSPA83S - 68KX DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70C) PARAMETER/CONDITION SYMBOL MAX UNITS OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3; tCK = 10ns IDD1 1,020 mA STANDBY CURRENT: Power-Down Mode; = 10ns; CKE = LOW; All banks idle IDD2 16 mA STANDBY CURRENT: Active Mode; S0#, S2# = HIGH; tCK = 10ns; CKE = HIGH; All banks active after tRCD met; No accesses in progress IDD3 300 mA OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; tCK = 10ns; All banks active; CAS latency = 3 IDD4 1,020 mA tRC = tRC (MIN); CL = 3 IDD5 1,920 mA tRC IDD6 340 mA IDD7 12 mA tCK AUTO REFRESH CURRENT: CKE = HIGH; S0#, S2# = HIGH; tCK = 10ns = 15.625s; CL = 3 SELF REFRESH CURRENT: CKE 0.2V Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Kingmax - Memory Module MSPA83S - 68KX AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value Unit 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V See Fig. 2 3.3V Vtt = 1.4V 1200 50 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0 = 50 50pF 870 50pF (Fig. 1) DC output load circuit OPERATING AC PARAMETER Parameter (Fig. 2) AC output load circuit (AC operating conditions unless otherwise noted) Symbol Version Unit Note -08A Row active to row active delay tRRD (min) 20 ns 1 RAS to CAS delay tRCD (min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 tRAS(min) 50 ns 1 tRAS(max) 120 us Row cycle time tRC(min) 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD (min) 1 CLK 3 ea 4 Row active time Number of valid output data CAS latency=3 2 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time, and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and re ad burst stop. Kingmax - Memory Module MSPA83S - 68KX AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE. Parameter -08A Symbol Min CLK cycle time CAS latency=3 tCC CAS latency=2 CLK to valid output delay CAS latency=3 8 CAS latency=3 Note 1000 ns 1 ns 1,2 ns 2 10 6 tSAC CAS latency=2 Output data hold time Unit Max 6 tOH CAS latency=2 3 3 CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tSS 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low-Z tSLZ 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns sho uld be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensat ion should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter . 6 7 ns Kingmax - Memory Module MSPA83S - 68KX A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 Address Bus A0 BURST DEFINITION 11 10 9 Reserved* WB 8 6 7 Op Mode 5 4 CAS Latency 3 1 2 BT 0 Mode Register (Mx) Burst Length *Should program M11, M10 = 0, 0 to ensure compatibility with future devices. M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access All other states reserved MODE REGISTER DEFINITION Starting Column Order of Accesses Within a Burst Address: Type = Sequential Type = Interleaved 2 Burst Length M2 M1 M0 Burst Length 4 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 8 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Full n = A0-A9 Cn+3, Cn+4... Page (location 0-1,023) ...Cn-1, (1,024) Cn... NOTE: 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 1. For a burst length of two, A1-A9 select the block of two burst; A0 selects the starting column within the block. 2. For a burst length of four, A2-A9 select the block of four burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3-A9 select the block of eight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0-A9 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0-A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. Kingmax - Memory Module MSPA83S - 68KX SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP code L L L H X X H Entry Self refresh Exit H H Bank active & row addr. H X Read & column address Auto precharge disable H X Write & column address Auto precharge disable L H H H H X X X L L H H X V L H L H X V X X L H L L H X X L L H H L H L L X H L Exit L H Entry H L Precharge power down mode Exit L V Column address (A0 ~ A9) L X X All banks Entry L DQM H No operation command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 Column address (A0 ~ A9) H H Clock suspend or active power down 3 Row address H H Note 1,2 X Auto precharge enable Bank selection A11, A9 ~ A0 3 Auto precharge enable Burst stop A10/AP L L Precharge BA0,1 X V L X H 4 4,5 4 4,5 6 X X X X X X X V X X X 7 (V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM . The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precha rge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A i s selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B i s selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/ write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Kingmax - Memory Module MSPA83S - 68KX PACKAGE DIMENSIONS Units : Inches (Millimeters) 2.66 (67.60) 2.50 (63.60) 0.91 (23.20) 0.13 (3.30) 2-f 0.07 (1.80) 1.29 (32.80) 0.18 0.10 (2.50) 1.181 (30.00) 0.24 (6.0) 0.16 0.039 (4.00 0.10) 0.79 .(20 00) 2-R 0.078 Min (2.00 Min) (4.60) 0.083 (2.10) Z Y 0.10 Min 0.200 Min (5.08 Min) 0.157 Min (4.00 Min) 0.140 Max (3.55 Max) 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1) 45o 8 5mil 0.04 0.0039 (1.00 0.10) Detail Z Tolerances : .006(.15) unless otherwise specified The used device is 16Mx8 SDRAM, Tiny BGA (2.55 Min) 0.15 (3.70) 0.024 0.001 (0.60 0.05) 0.015 Max (0.38 Max) 0.03 TYP (0.80 TYP ) Detail Y