MSPA83S-68KX (PC-100 128MB 144Pin SDRAM SO-DIMM)
Kingmax - Memory Module
DESCRIPTION
The MSPA83S-68KX is 16M bit x 64 Synchronous Dynamic RAM high density
memory module. The MSPA83S-68KX consists of eight CMOS 16M x 8 bit with
4 banks Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin
TSSOP package on a 144-Pin glass-epoxy substrate. One 0.1uF decoupling capacitor
is mounted on the printed circuit board in parallel for each SDRAM.
The MSPA83S-68KX is a Small Outline Dual in-line Memory Module and is intended
for mounting into 144-Pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies ,
programmable latencies allows the same device to be useful for a variety of high
bandwidth , high performance memory system application.
MSPA83S - 68KX
FEATURES
Performance range - 100MHz Max Freq.( CL=3&2 )
Burst mode operation
Auto & self refresh capability (4096 Cycles / 64ms )
LVTTL compatible inputs and outputs
Single 3.3V + 0.3V power supply
MRS cycle with address key programs
Latency ( Access from column address )
Burst length ( 1 , 2 , 4 , 8 & Full page )
Data scramble ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the system clock
Serial presence detect with EEPROM
PCB : Height ( 1181 mil ), singal sided component
Signal 3.3V +/- 0.3V power supply
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
CKE Clock enable
Masks system clock to freeze operation from the next clock c ycle.
CKE should be enabled at least one cycle prior to new comman d.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the C LK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
PIN NAMES
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
Pin Name Function
A0 ~ A11 Address input (Multiplexed)
BA0 ~ BA1 Select bank
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK1 Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS1 Chip select input
RAS Row address strobe
CAS Column address strobe
WE Write enable
DQM0 ~ 7 DQM
Power supply (3.3V)
VSS Ground
SDA Serial data I/O
SCL Serial clock
DU Don¢t use
NC No connection
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
13
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
Front
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Vss
DQ12
DQ13
DQ14
DQ15
WE
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
Front
CS0
A0
A6
A8
A10/AP BA1
CLK0
DQM2
DQM3
NC
Vcc
Pin
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Front
DQ18
DQ19
NC
CKE1
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VSS **SDA **SCL
Pin
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Back
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
NC
NC
CAS
DQM4
Pin
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Back
DQM5 CS1
RAS
A1
A2
Vss
A3
A4
A7
A9
BA0
A11
CLK1
*A12 DQM6
DQM7
*A13
NC
NC
DQ48
DQ49
Pin
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
Kingmax - Memory Module
MSPA83S - 68KX
11
15
Vss
DQM0
DQM1
Vcc Vcc
DQ8
DQ9
DQ10
DQ11
Vcc
Vss
Vcc
DQ38
DQ39
Vss
Vcc
A5
Vss
Vss
DU
Vcc
Vss
NC
NC
Vcc
DQ17
DQ16
DQ20
Vss
CKE0
Vcc
Vss
Vcc
Vss
Vcc
Vss
Vcc
Vss
Vcc
Vss
Vcc
Vcc
Vss
Vcc
Vcc
Vcc
DQ24~31
DQ16~23
FUNCTIONAL BLOCK DIAGRAM
CLK CS
DQM
DQ0~7 D1
CS0
CLK CS
DQM
DQ0~7 D2
DQ0~7
DQ7~15
CLK CS
DQM
DQ0~7 D5
DQ32~39
CLK CS
DQM
DQ0~7 D6
DQ40~47
CLK CS
DQM
DQ0~7 D3
CLK CS
DQM
DQ0~7 D4
CLK CS
DQM
DQ0~7 D7
DQ48~55
DQM6
CLK CS
DQM
DQ0~7 D8
DQ56~63
PCLK1
DQM4
Serial PD
SDASCL A1 A2A0
WP
PCLK0
PCLK1 PCLK3
PCLK0
DQM0
10Ω
CLK0
VDD
Vss
One 0.1uF Capacitors
per each SDRAM To all SDRAMs
A0 ~ An, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U1 ~ U8
SDRAM U1 ~ U8
SDRAM U1 ~ U8
SDRAM U1 ~ U8
SDRAM U1 ~ U8
Kingmax - Memory Module
MSPA83S - 68KX
DQM2
DQM1
DQM3
DQM5
DQM7
10Ω
10Ω
DQn Every DQpin of SDRAMs
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +125 °C
Power dissipation PD32 W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATIN GS" are exceeded.
Functional operation should be restricted to recommended ope rating condition.
Exposure to higher than recommended voltage for extended per iods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced toVSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 3.0 3.3 3.6 V
Input high voltage VIH 2.0 3.0 VDDQ+0.3 V1
Input low voltage VIL -0.5 00.8 V2
Output high voltage VOH 2.4 - - VIOH = -2mA
Output low voltage VOL - - 0.4 VIOL = 2mA
Input leakage current (Inputs) IIL -5 -5uA 3
Input leakage current (I/O pins) IIL -3 -3uA 3,4
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter Symbol Min Max Unit
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
Input capacitance (CLK0)
Input capacitance (CS0 )
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
22
22
25
25
25
10
6
35
35
45
40
40
18
10
pF
pF
pF
pF
pF
pF
pF
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for a ll bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
Notes :
Kingmax - Memory Module
MSPA83S - 68KX
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
1. Measured with outputs open.
2. Refresh period is 64ms.
Notes :
PARAMETER/CONDITION SYMBOL MAX UNITS
OPERATING CURRENT: Active Mode; IDD11,020 mA
Burst = 2; READ or WRITE; tRC = tRC (MIN);
CAS latency = 3; tCK = 10ns
STANDBY CURRENT: Power-Down Mode; IDD216 mA
tCK = 10ns; CKE = LOW; All banks idle
STANDBY CURRENT: Active Mode; S0#, S2# = HIGH; IDD3300 mA
tCK = 10ns; CKE = HIGH; All banks active after tRCD met;
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst; IDD41,020 mA
READ or WRITE; tCK = 10ns; All banks active; CAS latency = 3
AUTO REFRESH CURRENT: CKE = HIGH; tRC = tRC (MIN); IDD51,920 mA
S0#, S2# = HIGH; tCK = 10ns CL = 3
tRC = 15.625µs; IDD6 340 mA
CL = 3
SELF REFRESH CURRENT: CKE ≤ 0.2V IDD712 mA
Kingmax - Memory Module
MSPA83S - 68KX
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
-08A
Row active to row active delay tRRD(min) 20 ns 1
RAS to CAS delay tRCD(min) 20 ns 1
Row precharge time tRP(min) 20 ns 1
Row active time tRAS(min) 50 ns 1
tRAS(max) 120 us
Row cycle time tRC(min) 70 ns 1
Last data in to row precharge tRDL(min) 2
Last data in to new col. address delay tCDL(min) 1CLK 2
Last data in to burst stop tBDL(min) 1CLK 2
Col. address to col. address delay tCCD(min) 1CLK 3
Number of valid output data CAS latency=3 2ea 4
CAS latency=2 1
1. The minimum number of clock cycles is determined by divid ing the minimum time required with clock cycle time,
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and re ad burst stop.
Notes :
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
Kingmax - Memory Module
MSPA83S - 68KX
CLK
2
REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
Parameter Symbol -08A Unit Note
Min Max
CLK cycle time CAS latency=3 tCC 8 ns 1
CAS latency=2 10
CLK to valid output delay CAS latency=3 tSAC 6ns 1,2
CAS latency=2 6
Output data hold time CAS latency=3 tOH 3ns 2
CAS latency=2 3
CLK high pulse width tCH 3 ns 3
CLK low pulse width tCL 3ns 3
Input setup time tSS 2 ns 3
Input hold time tSH 1ns 3
CLK to output in Low-Z tSLZ 1ns 2
CLK to output in Hi-Z CAS latency=3 tSHZ 6ns
CAS latency=2 7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns sho uld be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensat ion should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Kingmax - Memory Module
MSPA83S - 68KX
1000
Kingmax - Memory Module
NOTE: 1. For a burst length of two, A1-A9 select the block of
two burst; A0 selects the starting column within the
block.
2. For a burst length of four, A2-A9 select the block of
four burst; A0-A1 select the starting column within
the block.
3. For a burst length of eight, A3-A9 select the block of
eight burst; A0-A2 select the starting column within
the block.
4. For a full-page burst, the full row is selected and
A0-A9 select the starting column.
5. Whenever a boundary of the block is reached within
a given sequence above, the following access wraps
within the block.
6. For a burst length of one, A0-A9 select the unique
column to be accessed, and Mode Register bit M3 is
ignored.
BURST DEFINITION
Burst Starting Column Order of Accesses Within a Burst
Length Address: Type = Sequential Type = Interleaved
A0
2 0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n = A0-A9 Cn, Cn+1, Cn+2
Page (location 0-1,023) Cn+3, Cn+4... Not supported
(1,024) …Cn-1,
Cn…
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M6
0
0
0
1
1
1
1
M4
0
0
1
0
1
0
1
M5
0
1
1
0
0
1
1
Burst Length
Burst LengthCAS Latency BT Mode Register (Mx)
Address Bus
976543
8210
M3
M6-M0
M8 M7
Op Mode
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
MODE REGISTER DEFINITION
MSPA83S - 68KX
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,
A9 ~ A0Note
Register Mode register set HXL L L L XOP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit LHLH H H X X 3
HX X X 3
Bank active & row addr. HXL L H H X V Row address
Read &
column address Auto precharge disable HXLHLHX V LColumn
address
(A0 ~ A9)
4
Auto precharge enable H4,5
Write &
column address Auto precharge disable HXLHLLX V LColumn
address
(A0 ~ A9)
4
Auto precharge enable H4,5
Burst stop HXLH H LX X 6
Precharge Bank selection HXL L HLXVLX
All banks XH
Clock suspend or
active power down Entry HLHX X X XX
LV V V
Exit LHX X X X X
Precharge power down mode
Entry HLHX X X X
X
LH H H
Exit LHHX X X X
LV V V
DQM HV X 7
No operation command HXHX X X X X
LH H H
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precha rge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A i s selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B i s selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/ write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks th e data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
Kingmax - Memory Module
MSPA83S - 68KX
PACKAGE DIMENSIONS
2.66
2.50
Units : Inches (Millimeters)
0.03 TYP
0.024 ± 0.001
0.015 Max
(0.38 Max)
2-R 0.078 Min
(2.00 Min)
0.18
(4.60)
0.91
(23.20) 1.29
(32.80)
0.24
(6.0)
0.13
0.79
(20. 00)
(0.60 ± 0.05)
(0.80 TYP)
0.10 Min
(2.55 Min)
Detail Y
(3.30)
(63.60)
(67.60)
Detail Z
0.16 ± 0.0039
(4.00 ± 0.10)
0.06 ± 0.0039
(1.50 ± 0.1)
Tolerances : ±.006(.15) unless otherwise specified
The used device is 16Mx8 SDRAM, Tiny BGA
2-f 0.07
(1.80)
1.181
(30.00)
0.16 ± 0.039
(4.00 ± 0.10)
0.083
(2.10)
0.10
(2.50) ZY
0.15
(3.70)
0.140 Max
0.04 ± 0.0039
(1.00 ± 0.10)
0.157 Min
(4.00 Min)
(3.55 Max)
0.200 Min
(5.08 Min)
Kingmax - Memory Module
MSPA83S - 68KX
8 ± 5mil
45o
