2004 Microchip Technology Inc. DS21812C-page 1
MCP6291/2/3/4/5
Features
• Gain Bandwidth Product: 10 MHz (typ.)
• Supply Current: IQ = 1.0 mA
• Supply Voltage: 2.4V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6293)
• Dual with Chip Select (CS) (MCP6295)
Applications
• Automotive
• Port ab le Equi pm ent
• Photo Diode Pre-amps
• Analog Filters
• Notebooks and PDAs
• Battery-Pow e red Sys tem s
Available Tools
• SPICE Macro Model (at www.microchip.com)
•FilterLab
® Software (at www.microchip.com)
Typical Application
Description
The Microchip Technology Inc. MCP6291/2/3/4/5 family
of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 10 MHz
gain bandwidth product (GBWP) and a 65° phase
margin. This f amily also operates f rom a singl e supply
voltage as low as 2.4V, while drawing 1 mA (typ.)
quiescent current. In addition, the MCP6291/2/3/4/5
supports rail-to-rail input and output swing, with a
common mode input voltage range of VDD +300mV to
VSS – 300 mV. This family of operational amplifiers is
designed with Microchip’s advanced CMOS process.
The MCP62 95 has a chip sele ct input (CS) f or dual o p
amps in an 8-pin package. This device is manufactured
by cascading the two op amps, with the output of op
amp A being connected to the non-inverting input of op
amp B. The chip select input puts the device in a Low
Power mode.
The MCP6291/2/3/4/5 family operate s in the Exte nded
Temperature Range of -40°C to +125°C. It also has a
power supply range of 2.4V to 5.5V.
Package Types
AB
CS
R2
C1
R1
VIN
VOU
T
R4R3
C2
C3
R5
MCP6295
Second-Order Sallen-Key Low-Pass Filter with
an Extra Pole-Zero Pair and a Chip Select.
1
2
3
5
6
7
8
7
6
5
VIN_
MCP6291
VDD
1
2
3
4
-
+
NC
NC
NC
VIN+
VSS
MCP6292
PDIP, SOIC, MSOP
MCP6294
1
2
3
4
14
13
12
11
-+-
+
10
9
8
5
6
7
+
--
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
-
+-
+
VOUT
MCP6293
1
2
3
4
8
7
6
5
-
+
VINA_
VINA+
VSS
VOUTA
VOUTB
VDD
VINB_
VINB+
VSS
VIN+
VIN_
NC CS
VDD
VOUT
NC
VOUTA
VINA_
VINA+
VDD VSS
VOUTB
VINB_
VINB+
VOUTC
VINC_
VINC+
VOUTD
VIND_
VIND+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6295
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
+-
VINA_
VINA+
VSS
VOUTA / VINB+
VOUTB
VDD
VINB_
CS
-+
1.0 mA, 10 MHz Rail-to-Rail Op Amp
MCP6291/2/3/4/5
DS21812C-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All Inputs and Outputs ......................VSS -0.3 V to VDD +0.3V
Difference Input Voltage ......................................|VDD – VSS|
Output Short Circuit Current ................. ......... .. .... ..continuous
Current at Input Pins ..... .... ......... .. .... .... ......... .. .... .... .... .±2 mA
Current at Output and Supply Pins ............................ ±30 mA
Storage Temperature......................... .. .. .. ..... .-65°C to +150°C
Junction Temperature (TJ) ..........................................+150°C
ESD Protection On All Pins (HBM/MM)................≥ 4 kV/400V
† Notice: St resses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
PIN FUNCTION TABLE
Name Function
VIN+, V INA+, VINB+, VINC+, VIND+ Non-inverting Inputs
VIN_, VINA_, VINB_, VINC_, VIND_Inverting Inputs
VDD Positive Power Supply
VSS Negative Power Supply
VOUT, VOUTA, VOUTB, VOUTC,
VOUTD
Outputs
NC No Internal Connection
CS Chip Select
VOUTA / V INB+ Output of op amp A and
non-inverting input of op
amp B (MCP6295)
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
RL = 10 kΩ to VDD/2 and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Of fset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature) VOS -5.0 — +5.0 mV TA = -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift ∆VOS/∆TA—±1.7—µV/°CT
A = -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection PSRR 70 90 — dB VCM = VSS (Note 1)
Input Bias , Input Offset Current and Im pe da nce
Input Bias Current IB— ±1.0 — pA Note 2
At Temperature IB— 50 200 pA TA = +85°C (Note 2)
At Temperature IB—25nAT
A = +125°C (Note 2)
Input Offset Current I OS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Range VCMR VSS−0.3 — VDD+0.3 V
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 90 110 — dB VOUT = 0.2V to VDD - 0.2V,
VCM =V
SS (Note 1)
Note 1: The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6295’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
4: The MCP6295’s VINB– pin (op amp B) has a c om m on m ode rang e ( VCMR) of VSS + 100 mV to
VDD – 100 m V. Th e M C P 62 95’s VOUTA/VINB+ pin ( op amp B) has a voltage range specif ie d by VOH an d V OL.
2004 Microchip Technology Inc. DS21812C-page 3
MCP6291/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
TEMPERATURE SPECIFICATIONS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 15 mV
Output Short-Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.4 — 5.5 V TA = -40°C to +125°C
Quiescent Current per Amplifier IQ0.7 1.0 1.3 mA IO = 0
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
RL = 10 kΩ to VDD/2 and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Note 1: The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6295’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
4: The MCP6295’s VINB– pin (op amp B) has a c om m on m ode rang e ( VCMR) of VSS + 100 mV to
VDD – 100 m V. Th e M C P 62 95’s VOUTA/VINB+ pin ( op amp B) has a voltage range specif ie d by VOH an d V OL.
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 k Ω to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 10.0 — MHz
Phase Margin at Unity-Gain PM — 65 — °
Slew Rate SR — 7 — V/µs
Noise
Input Noise Voltage Eni — 3.5 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —8.7—nV/√Hz f = 10 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Tem perat ure Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
MCP6291/2/3/4/5
DS21812C-page 4 2004 Microchip Technology Inc.
MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logi c Thr eshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01— µACS = VSS
CS High Specifications
CS Logi c Thr eshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.7 2 µACS = VDD
GND Current IQ—-0.7— µACS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Tu rn-on Time tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6— VV
DD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic
specification is tested at the output of op amp B (VOUTB).
2004 Microchip Technology Inc. DS21812C-page 5
MCP6291/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Current with
TA = +85 °C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.4V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current with
TA = +125 °C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
Note: The g r ap hs and t ables prov id ed fol low i ng thi s n ote are a statistical s umm ar y based on a l im ite d n um ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Input Offset Voltage (mV)
Percentage of Occurrences
840 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
30%
35%
40%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = 85 °C
0
50
100
150
200
250
300
350
400
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.4 V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0%
5%
10%
15%
20%
25%
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
840 Samples
VCM = VSS
TA = -40°C to +125°C
0%
5%
10%
15%
20%
25%
30%
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = +125 °C
200
250
300
350
400
450
500
550
600
650
700
750
800
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5 V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6291/2/3/4/5
DS21812C-page 6 2004 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: CMRR, PSRR vs.
Frequency.
FIGURE 2-9: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
FIGURE 2-10: Input Bias, Input Offset
Currents vs. Ambient Temperature VDD = 5.5V.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
100
150
200
250
300
350
400
450
500
550
600
650
700
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Volta ge (V)
Input Offset Voltage (µV)
VCM = VSS
Representati ve Part
VDD = 5.5V
VDD = 2.4V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+ 01 1.E+02 1.E+03 1.E +04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
VDD = 5.0V
1 10k 100k 1M10010 1k
PSRR+
PSRR-
CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
Input Bias Current
Input Offset Current
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temper ature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = VDD
VDD = 5.5V
60
70
80
90
100
110
120
-50-250 25507510012
5
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
VCM = VSS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125 °C
VDD = 5.5V
Input Bias Current
Input Offset C urrent
2004 Microchip Technology Inc. DS21812C-page 7
MCP6291/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-13: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-16: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-17: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-18: Slew Rate vs. Ambi en t
Temperature.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current
(mA/Amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1 1 10 100 1k 10k 100k 1M 10M 100M
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequenc y (Hz)
Maximum Output Voltage
Swing (VP-P)
1k 10k 100k 1M 10M
VDD = 5.5V
VDD = 2.4V
1
10
100
1000
0.01 0.1 1 10
Output Current Ma gni tude (mA)
Ouput Voltage Headroom (mV)
VOL - VSS
VDD - VOH
0
2
4
6
8
10
12
14
16
-50-250 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
50
55
60
65
70
75
80
85
90
Phase Margin (°)
GBWP, VDD = 5.5V
GBWP, VDD
= 2.4V
PM, VDD = 5.5V
PM, VDD = 2.4V
0
2
4
6
8
10
12
-50-250 255075100125
Ambient Tem per a tur e (°C)
Slew Rate (V/µs)
Rising Edge, VDD
= 5.5V
VDD
= 2.4V
Falling Edge, VDD = 5.5V
VDD = 2.4V
MCP6291/2/3/4/5
DS21812C-page 8 2004 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-19: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-20: Output Short-Circuit Current
vs. Power Supply Voltage.
FIGURE 2-21: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 2.4V (MCP6293
and MCP6295 only).
FIGURE 2-22: Input Noise Volt age Density
vs. Common Mode Input Volt age at 10 kHz.
FIGURE 2-23: Channel-to-Channel
Separation vs. Frequency (MCP6292, MCP6294
and MCP6295 only).
FIGURE 2-24: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 5.5V (MCP6293
and MCP6295 only).
1
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Ouptut Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.00.20.40.60.81.01.21.41.61.82.0
Chip Select Voltage (V)
Quiescent Current (mA)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.4V
CS swept
high to low CS swept
low to high
0
1
2
3
4
5
6
7
8
9
10
11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/¥Hz)
f = 10 kHz
100
110
120
130
140
1 10 100
Frequency (kHz)
Channel-to-Channel Separation
(dB)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current (mA)
Hysteresis
VDD = 5.5V
CS swept
low to high
CS swept
high to low
Op Amp shuts off
Op Amp turns on
2004 Microchip Technology Inc. DS21812C-page 9
MCP6291/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
FIGURE 2-25: Large Signal Non-inverting
Pulse Response.
FIGURE 2-26: Small Signal Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) to
Amplifier Output Response Time with VDD = 2.4V
(MCP6293 and MCP6295 only).
FIGURE 2-28: Large Signal Inverting Pulse
Response.
FIGURE 2-29: Small Signal Inverting Pulse
Response.
FIGURE 2-30: Chip Select (CS) to
Amplifier Output Response Time with VDD = 5.5V
(MCP6293 and MCP6295 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E-06 2. E-06 3.E-06 4. E-06 5.E- 06 6.E-06 7.E -06 8.E-06 9. E-06 1.E-05
Time (1 µs/div)
Output Voltage (V)
G = +1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.E+00 5.E-06 1.E-05 2. E-05 2.E-05 3.E- 05 3.E-05 4.E-05 4.E- 05 5.E-05 5.E-05
Time (5 µs/div)
Chip Select, Output Voltage (V)
VOUT Output On
Output High-Z
VDD = 2.4V
G = +1V/V
VIN = VSS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E-06 2.E- 06 3.E-06 4.E -06 5.E-06 6.E -06 7.E-06 8.E -06 9.E-06 1.E-05
Time (1 µ s/d iv)
Output Voltage (V)
G = -1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = -1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.E+00 5.E-06 1. E-05 2.E- 05 2.E-05 3 .E-05 3.E -05 4.E-05 4.E-05 5. E-05 5.E-0 5
Time (5 µs/div)
Chip Select, Output Voltage (V)
VOUT
Output High-Z
VDD = 5.5V
G = +1V/V
VIN = VSS
CS Voltage
Output On
MCP6291/2/3/4/5
DS21812C-page 10 2004 Microchip Technology Inc.
3.0 APPLICATION INFORMATION
The MCP6291/2/3/4/5 family of op amps is manufac-
tured using Microchip’s state-of-the-art CMOS
process, specifically designed for low-cost, low-power
and general-purpose applications. The low supply
voltage, low quiescent current and wide bandwidth
makes the MCP6291/2/3/4/5 ideal for battery-powered
applications.
3.1 Rail-to-Rail Input
The MCP6291/2/3/4/5 op amps are designed to
prevent pha se rev ersal wh en t he inpu t pins exceed th e
supply voltages. Figure 3-1 shows the input voltage
exceeding the supply voltage without any phase
reversal.
FIGURE 3-1: The MCP6291/2/3/4/5 Show
No Phase Reversal.
The input stage of the MCP6291/2/3/4/5 op amp uses
two di ffer ential in put sta ges in p arallel . One op erates at
low c ommon m ode inp ut vol tag e (VCM), while the other
operates at high VCM. With this topology, the device
operates with VCM up to 300 mV above VDD and
300 mV below VSS. The Input Offset Voltage is
measured at VCM =V
SS – 300 mV and VDD +300mV
to ensure proper operation.
Input voltages that exceed the input voltage range
(VSS – 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 3-2.
FIGURE 3-2: Input Current Limiting
Resistor (R IN).
3.2 Rail-to-Rail Output
The output voltage range of the MCP6291/2/3/4/5 op
amp is VDD –15mV (min.) and V
SS +15mV (max.)
when RL=10kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to F igu r e 2-16 for m o re in fo r m at i on.
3.3 MCP6293/5 Chip Select (CS)
The MCP6293 and MCP6295 are single and dual op
amps with chip select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typ.)
and flows through the CS pin to VSS. When this
happens, the amplifier output is put into a high-imped-
ance state. By pulling CS low, the amplifier is enabled.
If the CS pin is left floating, the amplifier may not
operate properly. Figure 3-3 shows the output voltage
and supply current response to a CS pulse.
FIGURE 3-3: Timing Diagram for the Chip
Select (CS) pin on the MCP6293 and MCP6295.
-1
0
1
2
3
4
5
6
-15 -14 -13 -1 2 -11 -10 -9 -8 - 7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2V/V
VIN VOUT
RIN VSS Minimum expected VIN
()–2 mA
-----------------------------------------------------------------------------------
≥
RIN Maximum expected VIN
()VDD
–
2 mA
-------------------------------------------------------------------------------------
≥
VIN
RIN VOUT
–
+
MCP6291
VIL
Hi-Z
ton
VIH
CS
toff
VOUT
-0.7 µA, typ.
Hi-Z
IVSS
ICS 0.7 µA, typ. 0.7 µA, typ
.
-0.7 µA, typ
.
-1.0 mA, typ.
10 nA, typ
2004 Microchip Technology Inc. DS21812C-page 11
MCP6291/2/3/4/5
3.4 Cascaded Dual Op Amps
(MCP6295)
The MCP6295 is a dual op amp with chip select (CS).
The chip sel ec t inp ut is av ai lab le o n w hat would be the
non-inverting input of a standard dual op amp (pin 5).
This feature is provided by connecting the output of op
amp A to the non-inve rting input of op amp B, as shown
in Figure 3-4. The chip select input, which can be con-
nected to a microcontroller I/O line, puts the device in
Low Power mode. Refer to Section 3.3 “MCP6283/5
Chip Se lect (CS)”.
FIGURE 3-4: Cascaded Gain Amplifier.
The key issue to note from this configuration is that the
output of op amp A is loaded by the input impedance.
The input impedance of the op amp is typically
1013Ω||6 pF, as specified in t he DC specification table
(Refer to Secti on 3.5 “Capacitive Loads” for furth er
details regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the n on-i nv erti ng i npu t range of op am p B
is limited to the common mode input range of
VSS + 20 mV and VDD –20mV.
3.5 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensit ive to c apa citiv e load s, thoug h all g ain s show th e
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-5) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The band-
wid th will be g enerally low er than the bandwidth with no
capacitive load.
FIGURE 3-5: Output Resistor, RISO
stabilizes large capacitive loads.
Figure 3-6 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit 's noise gain. For non-inverti ng gains, GN an d the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 3-6: Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6291/2/3/4/5 SPICE macro
model are very helpful.
AB
CS
2
3
5
6
7
VINA+
VOUTB
MCP6295
1
VINA–
VOUTA/VINB+VINB–
VIN
RISO VOUT
CL
–
+
MCP6291
10
100
10 100 1,000 10,00
0
Normalized Load Capacitance; CL/GN (pF)
Recommend ed RISO ()
GN = 1 V/ V
GN ≥ 2 V/V
MCP6291/2/3/4/5
DS21812C-page 12 2004 Microchip Technology Inc.
3.6 Supply Bypass
With this family of operational amplifiers, the power
suppl y pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
prov ide large, slow curr ents. This b ulk cap acitor can be
shared with other parts.
3.7 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces is 1012Ω. A 5V dif ference would
cause 5 pA, if current-to -flo w, which is great er than the
MCP6291/2/3/4/5 family’s bias current at 25°C (1 pA,
typ).
The easiest way to reduce surface leakage is to use a
guard ring around se ns itiv e p ins (or t rac es). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 3-7.
FIGURE 3-7: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting (Figure 3-7) and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the inp ut
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This b iases th e g uard ring t o th e
common mode input voltage.
3.8 Application Circuits
3.8.1 MULTIPLE FEEDBACK LOW-PASS
FILTER
The MCP6291/2/3/4/5 op amp can be used in active-
filter applications. Figure 3-8 shows an inverting, third-
order, multiple feedback low-pass filter that can be
used as an anti-aliasing filter.
FIGURE 3-8: Multiple Feedback Low-
Pass Filter.
This filter, and others, can be designed using
Microchip’s FilterLab® software, which is available on
our web site (www.microchip.com).
3.8.2 PHOTO DIODE AMPLIFIER
Figure 3-9 shows a photo diode biased in the photo-
voltaic mode for high precision. The resistor R
converts the diode current ID to the voltage VOUT. The
capacitor is used to limit the bandwidth or to stabilize
the circuit against the diode’s capacitance (it is not
always needed).
FIGURE 3-9: Photo Diode Amplifier.
Guard Ring
VSS
VIN–V
IN+
MCP6291
VOUT
VIN
VDD/2
R3C3
C1
R1R2
C4
R4
MCP6291
VOUT
ID
VDD/2
R
C
light
2004 Microchip Technology Inc. DS21812C-page 13
MCP6291/2/3/4/5
3.8.3 CASCADED OP AMPS
APPLICATIONS
The MCP6295 provides the flexibility of Low Power
mode for dual op amps in an 8-pin package. The
MCP6295 eliminates the added cost and space in
battery-powered applications by using two single op
amp s with chip sel ect line s or a 10-p in devi ce wit h chip
select line for each op amp. The only inh erent limit ation
to this dev ice is that the tw o op amps ar e internally ca s-
caded. T herefore, thi s device cannot be used in circuit s
that require active or passive elements between the
two op amps. However, there are several applications
where this op amp configuration with chip select line
becomes suitable. The circuits below show possible
applications for this device.
3.8.3.1 Load Isolation
With the cas caded op amp configuration, op amp B can
be used to isolate the load from op amp A. In applica-
tions w here op amp A is drivi ng cap aci tive o r low re sis-
ta nce load s in t he feedback loop (s uch a s an integra tor
circuit or filter circuit) the op amp may not have
suffici e nt s ou rce cu r re nt t o dri ve t he loa d . In t h is ca se,
op amp B can be used as a buffer.
FIGURE 3-10: Isolating the Load with a
Buffer.
3.8.3.2 Cascaded Gain
Figure 3-11 shows a cascaded gain circuit configura-
tion with chip select. Op amps A and B are configured
in a no n-inve rtin g amplif ier config uration . In th is co nfig-
uration, it is important to note that the input offset volt-
age of op amp A is amplified by the gain of op amp A
and B, as shown below:
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain, or as a unity-gain buffer.
FIGURE 3-11: Cascaded Gain Circuit
Configuration.
3.8.3.3 Dif ference Amplifier
Figure 3-12 shows op amp A as a difference amplifier
with chip select. In this configuration, it is recom-
mended to use well matched resistors (0.1%) to
increase the common mode rejection ratio (CMRR). Op
amp B can be used for additional gain or as a unity-g ain
buffer to isolate the load from the difference amplifier.
FIGURE 3-12: Differenc e Am pli fie r Circ uit .
AB
MCP6295
CS
VOUTB
VOUT VINGAGBVOSAGAGBVOSBGB
++=
Where:
GA= op amp A gain
GB= op amp B gain
VOSA = op amp A offset voltage
VOSB = op amp B offset voltage
AB
CS
R4R3R2R1
VIN
VOU
T
MCP6295
AB
CS
R2R1
VIN2
VIN1 R2
R1
VOU
T
R4R3
MCP6295
MCP6291/2/3/4/5
DS21812C-page 14 2004 Microchip Technology Inc.
3.8.3.4 Buffered Non-inverting Integrator
Figure 3-13 shows a buffered non-inverting integrator
with chip select. Op amp A is configured as a non-
inverting integrator. In this configuration, matching the
impedance at each input is recommended. Rf is used
to provid e a feedba ck loop a t frequenci es << 1/(2πRC).
Op amp B is used to isolate the load from the integrator.
FIGURE 3-13: Buffered Non-inverting
Integrator with Chip Select Circuit.
3.8.3.5 Integrator with Active Compensation
and a Chip Select
Figure 3-14 uses an a cti ve c ompensator (op a mp B) to
compensate for the non-ideal characteristics intro-
duced at higher frequency integration. The alternative
is to us e a pass ive element, such as a resistor, for com-
pensati on. However , the quality of compensa tion would
not be constant since the AC characteristics of an
amplifier varies over temperatu re and process. This c ir-
cuit uses op amp B as a unity-gain buffer to isolate the
inte gra tion ca pacit or C1 from op amp A and drives the
capacitor with low impedance source. Since both
amplifiers are matched very well, it provides a higher
quality of integration.
FIGURE 3-14: Integrator Circuit with Active
Compensation.
3.8.3.6 Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
Figure 3-15 is a second-order multiple feedback low-
pass filter with chip select. Use the Filterlab® software
from Mic rochi p to det ermine the R and C va lues for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3 and R6.
FIGURE 3-15: Second-Order Multiple
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair and Chip Sele ct.
3.8.3.7 Second-Order Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
Figure 3-16 is a second-order Sallen-Key low-pass
filter with chip select. Use the Filterlab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3 and R5.
FIGURE 3-16: Second-Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
A1 A2
CS
Rf
C1
R1C1
R1
VIN
VOU
T
MCP6295
A
CS
B
VIN VOUT
R1C1
MCP6295
AB
CS
R1C1
R5
VIN VOU
T
C2R4
R3R2
R6C3
MCP6295
AB
CS
R2
C1
R1
VIN
VOU
T
R4R3
C2
C3
R5
MCP6295
2004 Microchip Technology Inc. DS21812C-page 15
MCP6291/2/3/4/5
3.8.3.8 Capacitorless Second-Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 3-17 does not
require external capacitors. It uses only three external
resistors. The op amp’s GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the
amplifier bandwidth varies greatly over temperature
and process. However, this configuration provides a
low cost solution for applications with high bandwidth.
FIGURE 3-17: Capacitorless Second-Order
Low-Pass Filter with Chip Select Circuit.
4.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6291/2/3/4/5 family of op amps.
4.1 SPICE Macro Model
The latest version of SPICE Macro Model for the
MCP6291/2/3/4/5 op amp s is availabl e o n our web site
at www.microchi p.com. T his model is int ended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macr o model need to be v ali dat ed b y
comparing them to the data sheet specifications and
characteristic curves.
4.2 FilterLab® Software
Microc hip’ s Fi lterLab sof tware is an in novat ive too l that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microc hip.com, the FilterLa b activ e-filte r softwa re
design tool provides full schematic diagrams of the filter
circuit with component values. It also outputs the filter
circuit in SPICE format, which can be used with the
macro model to simulate actual filter performance.
AB
CS
VREF
VIN
VOUT
R2R1
R3
MCP6295
MCP6291/2/3/4/5
DS21812C-page 16 2004 Microchip Technology Inc.
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOI C (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Micro chip p art num ber can not be ma rked on on e line, it will
be carried ov er to the ne xt li ne thus lim iti ng th e nu mb er of av ai lab le c hara ct ers
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
MCP6291
E/P256
0407
MCP6291
E/SN0407
256
8-Lead MSOP Example:
XXXXXX
YWWNNN
6291
407256
2004 Microchip Technology Inc. DS21812C-page 17
MCP6291/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6294) Example:
14-Lead TSSOP (MCP6294) Example:
14-Lead SOIC (150 mil) (MCP6294) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6294-E/P
0407256
6294ST
0407
256
XXXXXXXXXX MCP6294ESL
0407256
MCP6291/2/3/4/5
DS21812C-page 18 2004 Microchip Technology Inc.
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
5°
5° -
-
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REFFFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0°
0.23
0.40
8°
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15°5° -
15°5° -
JEDEC Equivalent: MO-187
0° - 8°
5°
5° -
-
15°
15°
--
--
2004 Microchip Technology Inc. DS21812C-page 19
MCP6291/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
MCP6291/2/3/4/5
DS21812C-page 20 2004 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2M old ed Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equiva lent : MS- 012
Drawing No. C04-057
§ Significant Characteristic
2004 Microchip Technology Inc. DS21812C-page 21
MCP6291/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimen sion Li mits MIN NOM MAX MIN NOM MAX
Number of Pins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Widt h E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overal l Length D .740 .75 0 .7 60 1 8.8 0 19.05 19.30
T ip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .37 0 .4 30 7.87 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
MCP6291/2/3/4/5
DS21812C-page 22 2004 Microchip Technology Inc.
14-Lead Plasti c Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Wid th 0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150E1Molded Packag e Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Pa ckag e Thick ness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significant Characteristic
2004 Microchip Technology Inc. DS21812C-page 23
MCP6291/2/3/4/5
14-Lead Plasti c Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot A ngle
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007B1Lead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1Molded Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Molded Packag e Thickness 1.10.043AOverall Height 0.65.026
p
Pitch 1414
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
MCP6291/2/3/4/5
DS21812C-page 24 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21812C-page 25
MCP6291/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or ob tain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Device: MCP6291: Single Operational Amplifier
MCP6291T: Single Operational Amplifier
(Tape and Reel) (SOIC, MSOP)
MCP6292: Dual Operational Amplifier
MCP6292T: Dual Operational Amplifier
(Tape and Reel) (SOIC, MSOP)
MCP6293: Single Operational Amplifier with
Chip Select
MCP6293T: Single Operational Amplifier with
Chip Select (Tape and Reel) (SOIC, MSOP)
MCP6294: Quad Operational Amplifier
MCP6294T: Quad Operational Amplifier
(Tape and Reel) (SOIC, TSSOP)
MCP6295: Dual Operational Amplifier with Chip Select
MCP6295T: Dual Operational Amplifier with Chip Select
(Tape and Reel) (SOIC, MSOP)
Temperature Range: E = -40°C to +125°C
Package: MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
PA RT NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6291-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6291-E/MS: Extended Temperature,
8LD MSOP package .
c) MCP6291-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6291T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6292-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6292-E/MS: Extended Temperature,
8LD MSOP package .
c) MCP6292-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6292T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6293-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6293-E/MS: Extended Temperature,
8LD MSOP package .
c) MCP6293-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6293T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6294-E/P: Extended Temperature,
14LD PDIP package.
b) MCP6294T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
c) MCP6294-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6294-E/ST: Extended Temperature,
14LD TSSOP package.
a) MCP6295-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6295-E/MS: Extended Temperature,
8LD MSOP package .
c) MCP6295-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6295T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www. micro chip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
MCP6291/2/3/4/5
DS21812C-page 26 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21812C-page 27
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Te chnology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MAT E, PowerSm art , rfPIC, and
SmartShunt are registered trademark s of Microchip
Tec hnolo gy Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXD EV, MXLAB, PICMASTER, SEEV AL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzy LAB, In-Circ uit Serial
Programm ing, ICSP, ICEPIC, Migratable Memory, MPASM ,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Tec hnolo gy Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We a t Microc hip are committed to continuously improving the c ode protect ion f eatures of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonv olatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21812C-page 28 2004 Microchip Technology Inc.
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05/28/04
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