MCP6291/2/3/4/5 1.0 mA, 10 MHz Rail-to-Rail Op Amp Features Description * * * * * * * * The Microchip Technology Inc. MCP6291/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 10 MHz gain bandwidth product (GBWP) and a 65 phase margin. This family also operates from a single supply voltage as low as 2.4V, while drawing 1 mA (typ.) quiescent current. In addition, the MCP6291/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of operational amplifiers is designed with Microchip's advanced CMOS process. Gain Bandwidth Product: 10 MHz (typ.) Supply Current: IQ = 1.0 mA Supply Voltage: 2.4V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP6293) Dual with Chip Select (CS) (MCP6295) Applications * * * * * * The MCP6295 has a chip select input (CS) for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp A being connected to the non-inverting input of op amp B. The chip select input puts the device in a Low Power mode. Automotive Portable Equipment Photo Diode Pre-amps Analog Filters Notebooks and PDAs Battery-Powered Systems The MCP6291/2/3/4/5 family operates in the Extended Temperature Range of -40C to +125C. It also has a power supply range of 2.4V to 5.5V. Available Tools * SPICE Macro Model (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) Package Types MCP6291 PDIP, SOIC, MSOP Typical Application R2 C3 R5 VIN_ 2 VIN+ 3 1 6 VIN R3 3 B A 7 VOUT MCP6295 C1 C2 + VSS 4 2 R4 8 NC NC 1 R1 5 CS MCP6292 PDIP, SOIC, MSOP VOUTA 1 7 VDD VINA_ 2 6 VOUT VINA+ 3 5 NC VIN _ 2 VIN+ 3 VSS 4 + + - 6 VINB_ 5 VINB+ MCP6294 PDIP, SOIC, TSSOP 8 CS VOUTA 1 7 VDD VINA_ 2 6 VOUT VINA+ 3 VDD 4 5 NC VINB+ 5 VINB_ 6 Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and a Chip Select. 7 VOUTB - + VSS 4 MCP6293 PDIP, SOIC, MSOP NC 1 8 VDD VOUTB 7 14 VOUTD - + + - 13 VIND_ 12 VIND+ 11 VSS 10 VINC+ -+ +- 9 V _ INC 8 VOUTC MCP6295 PDIP, SOIC, MSOP VOUTA / VINB+ 1 VINA _ 2 VINA+ 3 VSS 4 2004 Microchip Technology Inc. 8 VDD 7 VOUTB - + + - _ 6 VINB 5 CS DS21812C-page 1 MCP6291/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Function VIN+, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs VIN_, VINA_, VINB_, VINC_, VIND_ Inverting Inputs VDD Positive Power Supply VSS Negative Power Supply Output Short Circuit Current ..................................continuous VOUT, VOUTA, VOUTB, VOUTC, VOUTD Outputs Current at Input Pins ....................................................2 mA NC No Internal Connection Current at Output and Supply Pins ............................30 mA CS Chip Select Storage Temperature.....................................-65C to +150C VOUTA / VINB+ Output of op amp A and non-inverting input of op amp B (MCP6295) Absolute Maximum Ratings VDD - VSS .........................................................................7.0V All Inputs and Outputs ...................... VSS -0.3V to VDD +0.3V Difference Input Voltage ...................................... |VDD - VSS| Junction Temperature (TJ) . .........................................+150C ESD Protection On All Pins (HBM/MM) ................ 4 kV/400V Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 k to VDD/2 and VOUT VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -3.0 -- +3.0 mV VCM = VSS (Note 1) Input Offset Voltage (Extended Temperature) VOS -5.0 -- +5.0 mV TA = -40C to +125C, VCM = VSS (Note 1) VOS/TA -- 1.7 -- V/C TA = -40C to +125C, VCM = VSS (Note 1) PSRR 70 90 -- dB VCM = VSS (Note 1) IB -- 1.0 -- pA Note 2 At Temperature IB -- 50 200 pA TA = +85C (Note 2) At Temperature IB -- 2 5 nA TA = +125C (Note 2) Input Offset Current IOS -- 1.0 -- pA Note 3 Common Mode Input Impedance ZCM -- 1013||6 -- ||pF Note 3 Differential Input Impedance ZDIFF -- 1013||3 -- ||pF Note 3 Common Mode Input Range VCMR VSS-0.3 -- VDD+0.3 V Common Mode Rejection Ratio CMRR 70 85 -- dB VCM = -0.3V to 2.5V, VDD = 5V Common Mode Rejection Ratio CMRR 65 80 -- dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 -- dB VOUT = 0.2V to VDD - 0.2V, VCM = VSS (Note 1) Input Offset Input Offset Temperature Drift Power Supply Rejection Input Bias, Input Offset Current and Impedance Input Bias Current Common Mode (Note 4) Open-Loop Gain DC Open-Loop Gain (large signal) Note 1: 2: 3: 4: The MCP6295's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6295's VINB- pin is specified by IB only. This specification does not apply to the MCP6295's VOUTA/VINB+ pin. The MCP6295's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6295's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. DS21812C-page 2 2004 Microchip Technology Inc. MCP6291/2/3/4/5 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, RL = 10 k to VDD/2 and VOUT VDD/2. Parameters Sym Min Typ Max Units VOL, VOH VSS + 15 -- VDD - 15 mV ISC -- 25 -- mA VDD 2.4 -- 5.5 V IQ 0.7 1.0 1.3 mA Conditions Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: TA = -40C to +125C IO = 0 The MCP6295's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6295's VINB- pin is specified by IB only. This specification does not apply to the MCP6295's VOUTA/VINB+ pin. The MCP6295's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6295's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units GBWP -- 10.0 -- MHz Conditions AC Response Gain Bandwidth Product Phase Margin at Unity-Gain PM -- 65 -- Slew Rate SR -- 7 -- V/s Input Noise Voltage Eni -- 3.5 -- Vp-p Input Noise Voltage Density eni -- 8.7 -- nV/Hz f = 10 kHz Input Noise Current Density ini -- 3 -- fA/Hz f = 1 kHz Noise f = 0.1 Hz to 10 Hz TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Conditions Temperature Ranges Note Thermal Package Resistances Thermal Resistance, 8L-PDIP JA -- 85 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 120 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. 2004 Microchip Technology Inc. DS21812C-page 3 MCP6291/2/3/4/5 MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS -- 0.2 VDD V CS Input Current, Low ICSL -- 0.01 -- A CS Logic Threshold, High VIH 0.8 VDD -- VDD V CS Input Current, High ICSH -- 0.7 2 A CS = VDD GND Current IQ -- -0.7 -- A CS = VDD Amplifier Output Leakage -- -- 0.01 -- A CS = VDD CS Low to Valid Amplifier Output, Turn-on Time tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High to Amplifier Output High-Z tOFF -- 0.01 -- s CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VHYST -- 0.6 -- V VDD = 5V CS Low Specifications CS = VSS CS High Specifications Dynamic Specifications (Note 1) Hysteresis Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested at the output of op amp B (VOUTB). DS21812C-page 4 2004 Microchip Technology Inc. MCP6291/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 25% Percentage of Occurrences 20% 840 Samples VCM = VSS TA = -40C to +125C 15% 10% 5% Input Offset Voltage (mV) FIGURE 2-4: 30% 60 70 80 90 100 FIGURE 2-5: TA = +125 C. Input Bias Current with 400 Input Offset Voltage (V) Input Offset Voltage (V) VDD = 2.4 V 350 300 250 200 TA = -40C TA = +25C TA = +85C TA = +125C 150 100 50 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.4V. 2004 Microchip Technology Inc. 10 8 6 4 2 0 -2 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2: TA = +85 C. 3000 50 2800 40 2600 30 2400 20 2200 10 2000 0 0% 1800 0% 5% 1600 5% 1400 10% 10% 1200 15% 15% 1000 20% 20% 800 25% 210 Samples TA = +125 C 600 30% 25% 0 Percentage of Occurrences Percentage of Occurrences 210 Samples TA = 85 C Input Offset Voltage Drift. 400 Input Offset Voltage. 40% 35% -4 Input Offset Voltage Drift (V/C) 200 FIGURE 2-1: -6 -10 -8 0% 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -1.6 -2.0 840 Samples VCM = VSS -2.4 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% -2.8 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Input Bias Current with 800 VDD = 5.5 V 750 700 650 600 550 500 450 400 350 300 250 200 -0.5 0.0 0.5 1.0 1.5 2.0 TA = +125C TA = +85C TA = +25C TA = -40C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. DS21812C-page 5 MCP6291/2/3/4/5 700 650 600 550 500 450 400 350 300 250 200 150 100 10,000 VCM = VSS Representative Part Input Bias, Offset Currents (pA) Input Offset Voltage (V) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. VDD = 5.5V VDD = 2.4V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCM = VDD VDD = 5.5V 1,000 Input Bias Current 100 Input Offset Current 10 1 5.5 25 35 45 Output Voltage (V) FIGURE 2-7: Output Voltage. Input Offset Voltage vs. 65 75 85 95 105 115 125 FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature VDD = 5.5V. 120 110 VDD = 5.0V 100 110 90 PSRR, CMRR (dB) CMRR, PSRR (dB) 55 Ambient Temperature (C) CMRR 80 PSRR- 70 PSRR+ 60 50 40 100 CMRR 90 PSRR VCM = VSS 80 70 30 20 60 1.E+00 1.E+01 1 1.E+02 10 1.E+03 100 1.E+04 1k 1.E+05 10k 1.E+06 100k -50 1M -25 Frequency (Hz) FIGURE 2-8: Frequency. CMRR, PSRR vs. FIGURE 2-11: Temperature. 2.5 Input Bias, Offset Currents (nA) Input Bias, Offset Currents (pA) 55 45 Input Bias Current 35 25 15 5 Input Offset Current -5 TA = +85C VDD = 5.5V -15 0 25 50 75 100 125 Ambient Temperature (C) 2.0 CMRR, PSRR vs. Ambient TA = +125 C VDD = 5.5V 1.5 Input Bias Current 1.0 0.5 0.0 Input Offset Current -0.5 -1.0 -25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +85C. DS21812C-page 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +125C. 2004 Microchip Technology Inc. MCP6291/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. Ouput Voltage Headroom (mV) 1.6 1.2 1.0 0.8 TA = +125C TA = +85C TA = +25C TA = -40C 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1000 100 10 VOL - VSS VDD - VOH 1 0.01 5.5 0.1 Power Supply Voltage (V) FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. Phase -90 60 -150 0 -180 1.E+08 1.E+07 90 14 85 GBWP, VDD = 5.5V GBWP, VDD = 2.4V 12 10 75 8 70 6 65 4 60 PM, VDD = 5.5V PM, VDD = 2.4V 2 -50 -25 Frequency (Hz) FIGURE 2-14: Frequency. 0 25 50 75 100 50 125 Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 12 Slew Rate (V/s) 10 VDD = 5.5V VDD = 2.4V 1 Falling Edge, VDD = 5.5V VDD = 2.4V 8 6 4 2 Rising Edge, VDD = 5.5V VDD = 2.4V 1M 1.E+07 100k 1.E+06 10k 1.E+05 1k 1.E+04 0 1.E+03 Maximum Output Voltage Swing (VP-P) 55 Ambient Temperature (C) 10 0.1 80 0 -210 10k 100k 1M 10M 100M 1.E+06 1k 1.E+05 100 1.E+04 1.E-01 10 1.E+03 20 1.E+02 -120 1.E+01 40 Gain Bandwidth Product (MHz) -60 80 Open-Loop Phase () Gain 1.E+00 Open-Loop Gain (dB) 16 -30 100 1 10 FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. 0 120 -20 0.1 1 Output Current Magnitude (mA) Phase Margin () Quiescent Current (mA/Amplifier) 1.4 10M -50 -25 Frequency (Hz) FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. 2004 Microchip Technology Inc. 0 25 50 75 100 125 Ambient Temperature (C) FIGURE 2-18: Temperature. Slew Rate vs. Ambient DS21812C-page 7 MCP6291/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 11 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density (nV/Hz) 1,000 100 10 1 1.E-01 1.E+00 0.1 1 1.E+01 1.E+02 10 100 1.E+03 1.E+04 1k 10k 1.E+05 9 8 f = 10 kHz 7 6 5 4 3 2 1 0 1.E+06 100k 10 1M 0.0 Frequency (Hz) FIGURE 2-19: vs. Frequency. 30 25 20 15 TA = +125C TA = +85C TA = +25C TA = -40C 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 4.0 4.5 5.0 1.2 4.5 5.0 110 100 10 100 FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). 1.6 Quiescent Current (mA) Quiescent Current (mA) 0.8 Hysteresis 0.2 4.0 Frequency (kHz) Op-Amp turns on here CS swept high to low 3.5 120 1 VDD = 2.4V Op-Amp shuts off here 0.4 3.0 130 5.5 FIGURE 2-20: Output Short-Circuit Current vs. Power Supply Voltage. 0.6 2.5 140 Power Supply Voltage (V) 1.0 2.0 FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. Channel-to-Channel Separation (dB) Ouptut Short Circuit Current (mA) 35 5 1.0 Common Mode Input Voltage (V) Input Noise Voltage Density 10 0.5 CS swept low to high 0.0 VDD = 5.5V Op Amp shuts off Op Amp turns on 1.4 Hysteresis 1.2 1.0 0.8 CS swept high to low 0.6 CS swept low to high 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 2.4V (MCP6293 and MCP6295 only). DS21812C-page 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 5.5V (MCP6293 and MCP6295 only). 2004 Microchip Technology Inc. MCP6291/2/3/4/5 Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2 and CL = 60 pF. 5.0 4.0 3.5 3.0 2.5 2.0 1.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.0 0.5 0.5 0.0 G = -1V/V VDD = 5.0V 4.5 Output Voltage (V) Output Voltage (V) 5.0 G = +1V/V VDD = 5.0V 4.5 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 0.0 1.E-05 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 FIGURE 2-25: Pulse Response. 5.E-06 6.E-06 7.E-06 Large Signal Non-inverting FIGURE 2-28: Response. 9.E-06 1.E-05 Large Signal Inverting Pulse G = -1V/V Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = +1V/V Time (200 ns/div) Time (200 ns/div) Small Signal Non-inverting 3.0 VDD = 2.4V G = +1V/V VIN = VSS CS Voltage 2.5 2.0 1.5 Output On VOUT 1.0 0.5 Output High-Z 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 Time (5 s/div) FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time with VDD = 2.4V (MCP6293 and MCP6295 only). 2004 Microchip Technology Inc. FIGURE 2-29: Response. Chip Select, Output Voltage (V) FIGURE 2-26: Pulse Response. Chip Select, Output Voltage (V) 8.E-06 Time (1 s/div) Time (1 s/div) Small Signal Inverting Pulse 6.0 VDD = 5.5V G = +1V/V VIN = VSS 5.5 CS Voltage 5.0 4.5 4.0 3.5 VOUT 3.0 Output On 2.5 2.0 1.5 1.0 Output High-Z 0.5 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 Time (5 s/div) FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time with VDD = 5.5V (MCP6293 and MCP6295 only). DS21812C-page 9 MCP6291/2/3/4/5 3.0 APPLICATION INFORMATION - The MCP6291/2/3/4/5 family of op amps is manufactured using Microchip's state-of-the-art CMOS process, specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6291/2/3/4/5 ideal for battery-powered applications. 3.1 RIN VIN ( Maximum expected V IN ) - V DD R IN ------------------------------------------------------------------------------------2 mA Rail-to-Rail Input The MCP6291/2/3/4/5 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 3-1 shows the input voltage exceeding the supply voltage without any phase reversal. V SS - ( Minimum expected V IN ) R IN ----------------------------------------------------------------------------------2 mA FIGURE 3-2: Resistor (RIN). 3.2 Input, Output Voltage (V) 6 4 VOUT VIN Input Current Limiting Rail-to-Rail Output The output voltage range of the MCP6291/2/3/4/5 op amp is VDD - 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-16 for more information. VDD = 5.0V G = +2V/V 5 VOUT MCP6291 + 3 3.3 2 1 0 -1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 Time (1 ms/div) FIGURE 3-1: The MCP6291/2/3/4/5 Show No Phase Reversal. The input stage of the MCP6291/2/3/4/5 op amp uses two differential input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The Input Offset Voltage is measured at VCM = VSS - 300 mV and VDD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS - 0.3V to VDD + 0.3V at 25C) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 3-2. MCP6293/5 Chip Select (CS) The MCP6293 and MCP6295 are single and dual op amps with chip select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 A (typ.) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 3-3 shows the output voltage and supply current response to a CS pulse. CS VIL VIH toff ton VOUT Hi-Z Hi-Z -1.0 mA, typ. IVSS ICS -0.7 A, typ. 0.7 A, typ. -0.7 A, typ. 10 nA, typ 0.7 A, typ. FIGURE 3-3: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. DS21812C-page 10 2004 Microchip Technology Inc. MCP6291/2/3/4/5 3.4 Cascaded Dual Op Amps (MCP6295) 3.5 The MCP6295 is a dual op amp with chip select (CS). The chip select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This feature is provided by connecting the output of op amp A to the non-inverting input of op amp B, as shown in Figure 3-4. The chip select input, which can be connected to a microcontroller I/O line, puts the device in Low Power mode. Refer to Section 3.3 "MCP6283/5 Chip Select (CS)". VOUTA/VINB+ VINB- 1 VINA- VINA+ 6 2 3 B A 7 VOUTB Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 3-5) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. MCP6295 - 5 CS MCP6291 VIN + VOUT CL Cascaded Gain Amplifier. The key issue to note from this configuration is that the output of op amp A is loaded by the input impedance. The input impedance of the op amp is typically 1013||6 pF, as specified in the DC specification table (Refer to Section 3.5 "Capacitive Loads" for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as VSS - 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD - 20 mV. FIGURE 3-5: Output Resistor, RISO stabilizes large capacitive loads. Figure 3-6 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 100 Recommended RISO ( ) FIGURE 3-4: RISO GN = 1 V/V GN 2 V/V 10 10 100 1,000 10,000 Normalized Load Capacitance; CL/GN (pF) FIGURE 3-6: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6291/2/3/4/5 SPICE macro model are very helpful. 2004 Microchip Technology Inc. DS21812C-page 11 MCP6291/2/3/4/5 3.6 Supply Bypass 3.8 With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other parts. 3.7 Application Circuits 3.8.1 The MCP6291/2/3/4/5 op amp can be used in activefilter applications. Figure 3-8 shows an inverting, thirdorder, multiple feedback low-pass filter that can be used as an anti-aliasing filter. PCB Surface Leakage R1 In applications where low input bias current is critical, printed circuit board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA, if current-to-flow, which is greater than the MCP6291/2/3/4/5 family's bias current at 25C (1 pA, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-7. VIN- VIN+ MULTIPLE FEEDBACK LOW-PASS FILTER VSS R2 R4 VOUT VIN C1 R3 C4 C3 MCP6291 VDD/2 FIGURE 3-8: Pass Filter. Multiple Feedback Low- This filter, and others, can be designed using Microchip's FilterLab(R) software, which is available on our web site (www.microchip.com). 3.8.2 PHOTO DIODE AMPLIFIER Figure 3-9 shows a photo diode biased in the photovoltaic mode for high precision. The resistor R converts the diode current ID to the voltage VOUT. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode's capacitance (it is not always needed). Guard Ring FIGURE 3-7: for Inverting Gain. 1. 2. For Inverting (Figure 3-7) and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. DS21812C-page 12 C Example Guard Ring Layout ID R VOUT light MCP6291 VDD/2 FIGURE 3-9: Photo Diode Amplifier. 2004 Microchip Technology Inc. MCP6291/2/3/4/5 3.8.3 CASCADED OP AMPS APPLICATIONS R4 R3 The MCP6295 provides the flexibility of Low Power mode for dual op amps in an 8-pin package. The MCP6295 eliminates the added cost and space in battery-powered applications by using two single op amps with chip select lines or a 10-pin device with chip select line for each op amp. The only inherent limitation to this device is that the two op amps are internally cascaded. Therefore, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with chip select line becomes suitable. The circuits below show possible applications for this device. FIGURE 3-11: Configuration. 3.8.3.1 3.8.3.3 Load Isolation With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit) the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. R2 B A VIN VOUTB CS Cascaded Gain Circuit Difference Amplifier Figure 3-12 shows op amp A as a difference amplifier with chip select. In this configuration, it is recommended to use well matched resistors (0.1%) to increase the common mode rejection ratio (CMRR). Op amp B can be used for additional gain or as a unity-gain buffer to isolate the load from the difference amplifier. VIN2 A MCP6295 VOUT MCP6295 R4 B R1 VIN1 R2 R1 R2 A R1 R3 B VOUT MCP6295 CS FIGURE 3-10: Buffer. 3.8.3.2 CS Isolating the Load with a FIGURE 3-12: Difference Amplifier Circuit. Cascaded Gain Figure 3-11 shows a cascaded gain circuit configuration with chip select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B Where: GA = op amp A gain GB = op amp B gain VOSA = op amp A offset voltage VOSB = op amp B offset voltage Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain, or as a unity-gain buffer. 2004 Microchip Technology Inc. DS21812C-page 13 MCP6291/2/3/4/5 3.8.3.4 Buffered Non-inverting Integrator Figure 3-13 shows a buffered non-inverting integrator with chip select. Op amp A is configured as a noninverting integrator. In this configuration, matching the impedance at each input is recommended. Rf is used to provide a feedback loop at frequencies << 1/(2RC). Op amp B is used to isolate the load from the integrator. R1 Second-Order MFB Low-Pass Filter with an Extra Pole-Zero Pair Figure 3-15 is a second-order multiple feedback lowpass filter with chip select. Use the Filterlab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3 and R6. C1 R1 R6 R1 C3 C1 Rf VIN 3.8.3.6 VOUT A2 A1 VIN MCP6295 R3 C2 C1 R2 R5 R4 B A VOUT MCP6295 CS CS FIGURE 3-13: Buffered Non-inverting Integrator with Chip Select Circuit. 3.8.3.5 Integrator with Active Compensation and a Chip Select Figure 3-14 uses an active compensator (op amp B) to compensate for the non-ideal characteristics introduced at higher frequency integration. The alternative is to use a passive element, such as a resistor, for compensation. However, the quality of compensation would not be constant since the AC characteristics of an amplifier varies over temperature and process. This circuit uses op amp B as a unity-gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with low impedance source. Since both amplifiers are matched very well, it provides a higher quality of integration. R1 FIGURE 3-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair and Chip Select. 3.8.3.7 Figure 3-16 is a second-order Sallen-Key low-pass filter with chip select. Use the Filterlab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3 and R5. R2 VIN C1 Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair R4 R3 R1 MCP6295 VOUT MCP6295 C2 VOUT A VIN C3 B A C1 B R5 CS FIGURE 3-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. CS FIGURE 3-14: Compensation. DS21812C-page 14 Integrator Circuit with Active 2004 Microchip Technology Inc. MCP6291/2/3/4/5 3.8.3.8 Capacitorless Second-Order Low-Pass filter with Chip Select The low-pass filter shown in Figure 3-17 does not require external capacitors. It uses only three external resistors. The op amp's GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain and R3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. However, this configuration provides a low cost solution for applications with high bandwidth. VIN R3 A B VREF VOUT MCP6295 CS FIGURE 3-17: Capacitorless Second-Order Low-Pass Filter with Chip Select Circuit. 2004 Microchip Technology Inc. DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6291/2/3/4/5 family of op amps. 4.1 SPICE Macro Model The latest version of SPICE Macro Model for the MCP6291/2/3/4/5 op amps is available on our web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. R1 R2 4.0 4.2 FilterLab(R) Software Microchip's FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site at www.microchip.com, the FilterLab active-filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21812C-page 15 MCP6291/2/3/4/5 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Example: 8-Lead MSOP XXXXXX 6291 YWWNNN 407256 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP6291 E/P256 0407 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: Note: * Example: MCP6291 E/SN0407 256 XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. DS21812C-page 16 2004 Microchip Technology Inc. MCP6291/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6294) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6294) Example: MCP6294-E/P 0407256 Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6294) MCP6294ESL 0407256 Example: XXXXXX YYWW 6294ST 0407 NNN 256 2004 Microchip Technology Inc. DS21812C-page 17 MCP6291/2/3/4/5 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 A2 A c A1 (F) L Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .000 .006 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF 0 8 Foot Angle c Lead Thickness .003 .006 .009 Lead Width B .009 .012 .016 55 15 Mold Draft Angle Top 55 -15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21812C-page 18 2004 Microchip Technology Inc. MCP6291/2/3/4/5 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2004 Microchip Technology Inc. DS21812C-page 19 MCP6291/2/3/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21812C-page 20 2004 Microchip Technology Inc. MCP6291/2/3/4/5 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 2004 Microchip Technology Inc. MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21812C-page 21 MCP6291/2/3/4/5 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21812C-page 22 2004 Microchip Technology Inc. MCP6291/2/3/4/5 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 2004 Microchip Technology Inc. DS21812C-page 23 MCP6291/2/3/4/5 NOTES: DS21812C-page 24 2004 Microchip Technology Inc. MCP6291/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP6291: Single Operational Amplifier MCP6291T: Single Operational Amplifier (Tape and Reel) (SOIC, MSOP) MCP6292: Dual Operational Amplifier MCP6292T: Dual Operational Amplifier (Tape and Reel) (SOIC, MSOP) MCP6293: Single Operational Amplifier with Chip Select MCP6293T: Single Operational Amplifier with Chip Select (Tape and Reel) (SOIC, MSOP) MCP6294: Quad Operational Amplifier MCP6294T: Quad Operational Amplifier (Tape and Reel) (SOIC, TSSOP) MCP6295: Dual Operational Amplifier with Chip Select MCP6295T: Dual Operational Amplifier with Chip Select (Tape and Reel) (SOIC, MSOP) Temperature Range: E = -40C to +125C Package: MS P SN SL ST = = = = = Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead Examples: a) MCP6291-E/SN: b) MCP6291-E/MS: c) MCP6291-E/P: d) MCP6291T-E/SN: a) MCP6292-E/SN: b) MCP6292-E/MS: c) MCP6292-E/P: d) MCP6292T-E/SN: a) MCP6293-E/SN: b) MCP6293-E/MS: c) MCP6293-E/P: d) MCP6293T-E/SN: a) MCP6294-E/P: b) MCP6294T-E/SL: c) MCP6294-E/SL: d) MCP6294-E/ST: a) MCP6295-E/SN: b) MCP6295-E/MS: c) MCP6295-E/P: d) MCP6295T-E/SN: Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. Extended Temperature, 14LD PDIP package. Tape and Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. Extended Temperature, 8LD SOIC package. Extended Temperature, 8LD MSOP package. Extended Temperature, 8LD PDIP package. Tape and Reel, Extended Temperature, 8LD SOIC package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2004 Microchip Technology Inc. DS21812C-page 25 MCP6291/2/3/4/5 NOTES: DS21812C-page 26 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. 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The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS21812C-page 27 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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