1999 Microchip Technology Inc. Preliminary DS35008B-page 1
Microcontrolle r Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches, which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Pr ogrammable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming (ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temper ature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Di agram
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via ex ternal
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit mul ti-c ha nnel Analog-to -D igi tal converter
• Synchronous Serial Port (SSP) with Enhanced
SPI and I2C
PIC16C72A
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
PIC16C62B/72A
28-Pin 8-Bit CMOS Microcontrollers
PIC16C62B/72A
DS35008B-page 2 Preliminary 1999 Microchip Technology Inc.
Pin Diagrams
PIC16C62B
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
Key Features
PICmicro™ Mid-Range Reference Manual
(DS33023) PIC16C62B PIC16C72A
Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)
Program Memory (14-bit words) 2K 2K
Data Memory (bytes) 128 128
Interrupts 7 8
I/O Ports Ports A,B,C Ports A,B,C
Timers 3 3
Capture/Compare/PWM modules 1 1
Serial Communications SSP SSP
8-bit Analog-to-Digital Module — 5 input channels
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 3
Table of Contents
1.0 Device Overv iew ....................................... ...... ...... ..... ...... ............................ ...... ..... ...... .........................................5
2.0 Memory Organization.............................................................................................................................................7
3.0 I/O Ports...............................................................................................................................................................19
4.0 Timer0 Modu le .....................................................................................................................................................25
5.0 Timer1 Modu le .....................................................................................................................................................27
6.0 Timer2 Modu le .....................................................................................................................................................31
7.0 Capture/Compare/PWM (CCP) Module...............................................................................................................33
8.0 Synchronous Serial Port (SSP) Module ...............................................................................................................39
9.0 Analog-to-Digital Converter (A/D) Module............................................................................................................49
10.0 Special Features of the CPU................................................................................................................................55
11.0 Instruction Set Summary......................................................................................................................................67
12.0 Development Support...........................................................................................................................................75
13.0 Electric al Chara cteris tic s........... ..... ...... ..... ...... ...... ............................ ..... ...... ...... ..................................................81
14.0 DC and AC Characteristics Graphs and Tables................................................................................................. 103
15.0 Packaging Information........................................................................................................................................105
Appendix A: Revision History ...................................................................................................................................111
Appendix B: Conversion Considerations ..................................................................................................................111
Appendix C: Migration from Base-line to Mi d-Range Devices ..................................................................................112
Index...........................................................................................................................................................................113
On-Line Support..........................................................................................................................................................117
Reader Response.......................................................................................................................................................118
PIC16C62B/72A Product Iden tification System..........................................................................................................119
To Our Valued Customers
Most Current Data Sheet
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To deter mine if an errata sheet exists for a part icular device, please check with one of the following:
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Corrections to this Data Sheet
We constantly strive to improv e the quality of all our products and documentation. W e hav e spent a great deal of time to ensure that
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We appreciate your assistance in making this a better document.
PIC16C62B/72A
DS35008B-page 4 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 5
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary docu ment to this dat a sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are two devices (PIC16C62B, PIC16C72A) cov-
ered b y this data sheet . The PIC16C6 2B does not have
the A/D module implemented.
Figure 1-1 is the block diagram for both devices. The
pinouts are listed in Table 1-1.
FIGURE 1-1: PIC16C62B/PIC16 C72 A BLOCK D IAGRAM
EPROM
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr 7
RAM Addr(1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register .
2: The A/D module is not available on the PIC16C62B.
CCP1 Synchronous A/D(2)
Timer0 Timer1 Timer2
Serial Port
RA4/T0CKI
RA5/SS/AN4(2)
RA3/AN3/VREF(2)
RA2/AN2(2)
RA1/AN1(2)
RA0/AN0(2)
8
3
2K x 14
128 x 8
PIC16C62B/72A
DS35008B-page 6 Preliminary 1999 Microchip Technology Inc.
TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION
Pin Name DIP
Pin# SOIC
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0(4) 2 2 I/O TTL RA0 can also be analog input 0
RA1/AN1(4) 3 3 I/O TTL RA1 can also be analog input 1
RA2/AN2(4) 4 4 I/O TTL RA2 can also be analog input 2
RA3/AN3/VREF(4) 5 5 I/O TTL RA3 can also be analog input 3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input 4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O por t . PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi- directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes .
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 I/O ST
RC7 18 18 I/O ST
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power or program
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buff er is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Tr igger input when used in serial programming mode.
3: This buffer is a Schmitt Tr igger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not avai lable on the PIC16C62B.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 7
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these micro-
controllers. Each block (Program Memory and Data
Memory) has its own bus, so that concurrent access
can occur.
Addit ional inf ormation on de vic e memory ma y be f oun d
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16C62B/72A devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space . Each device has 2K x 14 w ords of pro-
gram memory. Accessing a location above 07FFh will
cause a wr ap arou nd.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
User Memory
Space
PIC16C62B/72A
DS35008B-page 8 Preliminary 1999 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Functio n Regis ters . Abo v e the Sp ecial Functi on Regi s-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly , or indi-
rectly through the File Select Register FSR
(Section 2.5).
FIGURE 2-2: REGISTER FILE MAP
RP1(1) RP0 (STATUS<6:5>)
Note 1: Maintain this bit clear to ensure upward compati-
bility with future products.
Unimplemented data memory locations,
read as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C62B, read as ’0’.
File
Address File
Address
00h INDF(1) INDF(1) 80h
01h TMR0 OPTION_REG 81h
02h PCL PCL 82h
03h STATUS STATUS 83h
04h FSR FSR 84h
05h PORTA TRISA 85h
06h PORTB TRISB 86h
07h PORTC TRISC 87h
08h — — 88h
09h — — 89h
0Ah PCLATH PCLATH 8Ah
0Bh INTCON INTCON 8Bh
0Ch PIR1 PIE1 8Ch
0Dh — — 8Dh
0Eh TMR1L PCON 8Eh
0Fh TMR1H —8Fh
10h T1CON —90h
11h TMR2 —91h
12h T2CON PR2 92h
13h SSPBUF SSPADD 93h
14h SSPCON SSPSTAT 94h
15h CCPR1L —95h
16h CCPR1H —96h
17h CCP1CON —97h
18h — — 98h
19h — — 99h
1Ah — — 9Ah
1Bh — — 9Bh
1Ch — — 9Ch
1Dh — — 9Dh
1Eh ADRES(2) —9Eh
1Fh ADCON0(2) ADCON1(2) 9Fh
20h
General
Purpose
Registers
General
Purpose
Registers
A0h
BFh
—C0h
—
7Fh —FFh
Bank 0 Bank 1
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 9
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on :
POR,
BOR
Value on all
other resets
(4)
Bank 0
00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS(1) IRP(5) RP1(5) RP0 TO PD ZDCC0001 1xxx 000q quuu
04h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA(6,7) —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB(6,7) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC(6,7) PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h-09h —Unimplemented — —
0Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF
(3) —— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh —Unimplemented — —
0Eh TMR1L Hol ding register for t he Least Significant Byte of the 16- bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial P ort Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh —Unimplemented — —
1Eh ADRES(3) A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0(3) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’ ,
Shaded locations are unimplemented, read as ’0’ .
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
PIC16C62B/72A
DS35008B-page 10 Preliminary 1999 Microchip Technology Inc.
Bank 1
80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS(1) IRP(5) RP1(5) RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h-89h —Unimplemented — —
8Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 —ADIE
(3) —— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh —Unimplemented — —
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh-91h —Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address R egist er 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h-9Eh —Unimplemented — —
9Fh ADCON1(3) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’ ,
Shaded locations are unimplemented, read as ’0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: A/D not implemented on the PIC16C62B, maintain as ’0’.
4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
5: The IRP and RP1 bits are reserved. Always maintain these bits clear.
6: On any device reset, these pins are configured as inputs.
7: This is the value that will be in the port output latch.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on :
POR,
BOR
Value on all
other resets
(4)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 11
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Regi ster 2-1, contains
the arithmeti c status of th e ALU , the RESET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, the wr ite to these three bits is dis-
abled. These bits are set or cleared according to the
device log ic . Th e TO and PD bits are not writable. The
result of an instruction with the STATUS register as
destination may be different than intended.
For example, CLRF STATUS will cl ear t h e up p er -t h ree
bits an d set the Z bit. This lea v e s the STATUS register
as 000u u1uu (where u = unchang ed).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
aff ect the Z, C or DC bits from the STATUS regist er . F or
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: The IRP a nd RP1 bits are res erv ed. Mai n-
tain these bits clear to ensure upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indi rect addressing)
(reserved, maintain clear)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
Note: RP1 is reserved, maintain clear
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instru ction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (f or borro w, the pol arity is reversed )
1 = A carry-out from the 4th low o rder bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is reversed)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: F or borro w, the polarity is re v ers ed. A subt racti on is exe cuted by add ing the tw o’s complemen t of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
PIC16C62B/72A
DS35008B-page 12 Preliminary 1999 Microchip Technology Inc.
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register , which contains various control bits to conf igure
the TMR0 prescaler/WDT postscaler (single assign-
able register known as the prescaler), the External INT
Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h)
Note: To achi eve a 1:1 pr escaler as signmen t for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readab le bit
W = Writab le bit
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PO RTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled for all PORTB inputs
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on R A4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT )
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increm ent on high- to-low transition on RA4/T0CKI pin
0 = Increm ent on low-to- high transition on RA 4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate W DT Rate
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 13
2.2.2.3 INTCON REGISTER
The I NTCON Regi ster i s a rea dab le a nd w ritabl e regi s-
ter, which contains various interrupt enable and flag
bits for the TMR0 register overflow, RB Port change
and External RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interrupt flag b its a re set when an in terru pt
conditi on occ urs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writab le bit
- n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT exter nal interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (software must clear bit)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT exter nal interrupt occurred (software must clear bit)
0 = The RB0/INT exter nal interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 input pins have changed state (clear by reading PORTB)
0 = None of the RB7:RB4 input pins have changed state
PIC16C62B/72A
DS35008B-page 14 Preliminary 1999 Microchip Technology Inc.
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIE(1) — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIE(1): A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4: Unimplemented: R ead as ‘0’
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this
bit clear.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 15
2.2.2.5 PIR 1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag b its a re set when an in terru pt
conditi on occ urs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—ADIF(1) — — SSPIF CCP1IF TMR2IF TMR1IF R = Readab le bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as ‘0’
bit 6: ADIF(1): A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversi on is no t complete
bit 5-4: Unimplemented: R ead as ‘0’
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capt ure occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to P R2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: The PIC16C62B does not have an A/D module. This bit location is reserv ed on these devices. Alwa ys maintain this
bit clear.
PIC16C62B/72A
DS35008B-page 16 Preliminary 1999 Microchip Technology Inc.
2.2.2.6 PCON REGISTER
The P ower Control register (PCON) conta ins flag bits to
allo w differentiatio n betwe en a Pow er-on Res et (POR),
Brown-Out Reset (BOR) and resets from other
sources. .
REGISTER 2-6: PCON REGISTER (ADDRESS 8Eh)
Note: On Power-on Reset, the state of the BOR
bit is unknown and is not predictable.
If the BODEN bit in the configuration word
is set, the user must first set the BOR bit on
a POR, and chec k it on subs equent res ets.
If BOR is cleared whi le POR remains set,
a Brown-out reset has occurred.
If the BODEN bit is clear, the BOR bit may
be ignored.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
————— —PORBOR R = Readable bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as ’0’
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (mus t be se t in software after a Brown-out Reset occu rs)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 17
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register and is
readable and writable. The high byte is called the PCH
register. This register contains the PC<12:8> bits and
is not di rec tly a cc es si ble. All upd ates to the PCH regis-
ter go through the PCLATH register.
2.3.1 STACK
The stack allows any combination of up to 8 program
calls and interrupts to occur. The stack contains the
return address from this branch in program execution.
Mid-range devices have an 8 level deep hardware
stack. The stack space is not part of either program or
data sp ace a nd the st ac k po inter i s not acce ssib le . Th e
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the e vent of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not modified
when the stack is PUSHed or POPed.
After t he stac k has been PUSHe d eight t imes , the nin th
push overwrites th e value that w as s tored fro m the firs t
push. The tenth push o verwrites the second pus h (an d
so on).
2.4 Pr ogram Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page . When d oing a CALL or GOTO instruction,
the upper bit of the address is provided by
PCLATH<3>. The user must ensure that the page
select bit is programmed to address the proper pro-
gr am m em ory page . If a re turn from a CALL instruction
(or inte rrupt) i s ex ecuted, the entire 13-bit PC i s popped
from the stack. Therefore, manipulation of the
PCLATH<3> bit is not required for the return instruc-
tions.
PIC16C62B/72A
DS35008B-page 18 Preliminary 1999 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and FSR
Registers
The IN DF r egist er is not a physical r e gis ter. Addre ss-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
).
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effectiv e 9-bit address is o btai ne d by concatena ting
the 8-bit F SR regist er and the IRP b it (STATUS<7>), as
shown in Figure 2-3. However, IRP is not used in the
PIC16C62B/72A.
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING
Note 1: Maintain clear for upward compatibility with future products.
2: Not implemented.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(1) (1)
(2) (2)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 19
3.0 I/O PORTS
Some I/O port pins are multiplexed with an alternate
function for the peripheral features on the device. In
genera l, when a peripher al is en ab led, t hat pin ma y not
be used as a general purpose I/O pin.
Addit ion al information on I/O po rts ma y be foun d i n th e
PICmicro™ Mid-Range Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (=1 ) wi ll m ake the corres po ndi ng PO RTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
mak e the corresp onding POR TA pin an ou tput, (i.e. , put
the contents of the output latch on the selected pin).
The PORTA register reads the state of the pins,
wherea s writin g t o i t wil l w rite to the port latch . Al l w rite
operations are read-modify-write operations. There-
f ore, a write to a po rt implies that th e port pins are rea d,
this value is modified , and then written to the port data
latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Pin RA5 is multiplexed with the SSP to become the
RA5/SS pin.
On the PIC16C 7 2A device, ot he r PORTA pins are m u l-
tiplexed w ith a nal og inputs and analog VREF input. The
oper ation of e ach pin is selected by c learing/setti ng the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user m ust ensure the bits in the TRISA regi ster are
maintained set when using them as analo g inputs.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On a Power-on Reset, pins with analog
functions are configured as analog inputs
with di gi tal i np ut buffers di sa b l ed . A di gita l
read of these pins will return ’0’.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (72A only)
(72A
only)
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pi n (1)
TMR0 clock input
QD
Q
CK
QD
Q
CK
EN
QD
EN
Note 1: I/O pin has protection diodes to VSS only.
PIC16C62B/72A
DS35008B-page 20 Preliminary 1999 Microchip Technology Inc.
TABLE 3-1 PORTA FUNCTIONS
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/ AN0 bit0 TTL Input /output or analog input(1)
RA1/ AN1 bit1 TTL Input /output or analog input(1)
RA2/ AN2 bit2 TTL Input /output or analog input(1)
RA3/AN3/VREF bit3 TTL Input/output or analog input(1) or VREF(1)
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS/AN4 bit5 TTL Input/outpu t or slave select input for synchronous serial port or analog input(1)
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C62B does not implement the A/D module.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other resets
05h PORTA
(for PIC16C72A only) —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
05h PORTA
(for PIC16C62B only) —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1(1) — — — — —PCFG2PCFG1PCFG0---- -000 ---- -000
Legend: x = un kn own, u = un change d, - = unimp lemen ted loc ations read as ’0’ . Shaded c ells are not used b y POR TA.
Note 1: The PIC16C62B does not implement the A/D module. Maintain this register clear.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 21
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will mak e the corres ponding POR TB pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, (i.e.,
put the contents of the output latch on the selected pin).
Each o f the POR TB pi ns h as a weak internal pull -up. A
single control bit can turn on all the pull-ups . This is per-
formed by c learing bi t R BPU (OPTION_REG<7 >). The
weak pu ll-up i s automa tically tur ned of f when the por t
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compare d with the old v a lue latc hed on the la st read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in th e interrupt service routine , can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on c h ange
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
RB0/INT is an external interupt pin and is configured
using the INTEDG bit (OPTION_REG<6>). RB0/INT is
discussed in detail in Section 10.10.1.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pi ns
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
Note 1: I/O pins have d i ode prote ction to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
PIC16C62B/72A
DS35008B-page 22 Preliminary 1999 Microchip Technology Inc.
TABLE 3-3 PORTB FUNCTIONS
TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input.
Internal so ftware programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change).
Internal so ftware programmable weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change).
Internal so ftware programmable weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change).
Internal software programmable weak pull-up. Serial programming cl ock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Tr igger input when configured as the external interrupt.
2: This buffer is a Schmitt Tr igger input when used in serial programming mode.
Address Name Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 23
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional por t. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) w ill make th e correspondin g PORTC pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, (i.e.,
put the contents of the output latch on the selected pin).
POR TC is m ultiple x ed with se ver al periphera l function s
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
mak e a pin an input. Since the T RIS bit o v erride ma ybe
in effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) wi th TRISC as
destina tion sh ould be a v oided. Th e user should ref er to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Data Bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Per ipheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
PORT
Peripheral
OE(3)
Peripheral input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: P ort/P eripheral select signal selects between port
data and peripheral output.
3: Per ipheral OE (output enable) is only activa ted if
peripheral select is active.
PIC16C62B/72A
DS35008B-page 24 Preliminary 1999 Microchip Technology Inc.
TABLE 3-5 PORTC FUNCTIONS
TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer
Type Function TRISC
Override
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input Yes
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input Yes
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output No
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes. No
RC4/SDI/SDA bit4 ST RC4 can also be th e SPI Da ta In (SPI mo de) or da ta I/O (I2C mo de). No
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output No
RC6 bit6 ST Input/out put port pin No
RC7 bit7 ST Input/out put port pin No
Legend: ST = Schmitt Trigger input
Addr e s s Name Bit 7 Bi t 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unc hanged.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 25
4.0 T IMER0 MODULE
The Timer0 module ti mer/counter h as the f ollow ing f ea-
tures:
• 8-bit timer/counter
- Read and write
- INT on overflow
• 8-bit soft ware programm able pres caler
• INT or EXT clock select
- EXT clock edge select
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
4.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule wi ll i nc rem ent every instruction cycle (withou t pre s-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
use r can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG <4 >). Cl eari ng b it T0SE sel ec ts the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an e xternal clock inp ut is used f or Timer0 , it must
meet certain requirements. The requirements ensure
the e xternal cloc k can b e synchron ized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the Electrical Specifications section of
this manual, and in the PICmicro™ Mid-Range Refer-
ence Manual, (DS33023).
4.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. There is only one prescaler available
which is shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 modul e means th at there is no pres caler f o r the
Watchdog Timer, and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler a ssignment an d prescale ratio .
Clearing bit PSA wil l assign t he presc aler to the Ti mer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TM R0 register (e .g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment or ratio.
Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(TCY delay)
PSout
Data Bus
8
PSA
PS2, PS1, PS0 Se t interrupt
flag bit T0IF
on ov erfl ow
3
PIC16C62B/72A
DS35008B-page 26 Preliminary 1999 Microchip Technology Inc.
4.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, (i.e ., it can be chang ed “on-the -fly” du ring progr a m
executio n).
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister ove rflows from FFh to 00 h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unc hanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (= Fosc/4)
SYNC
2
TCY TMR0 r e g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
Prescaler
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 27
5.0 T IMER1 MODULE
The Tim er1 module timer/count er has the f ollo wing f ea-
tures:
• 16-bit timer/counter
• Readable and writable
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP mo dule trigger
Timer1 has a control register, shown in Register 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1O N (T1CO N<0 >).
Figure 5-1 is a simplified block diagram of the Timer1
module.
Additional infor mation on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
5.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is deter mined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In coun ter mo de, it in creme nts on every ri sing
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 a lso has an in ternal “reset input ”. This reset can
be generated by the CCP module as a special event
trigger (Section 7.0).
REGISTER 5-1:T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled (TRISC<1:0> ignored)
0 = Oscillator is shut off
(The oscillator is turned off to reduce power drain
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bi t
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 us es the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC16C62B/72A
DS35008B-page 28 Preliminary 1999 Microchip Technology Inc.
FIGURE 5-1: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP input
T1OSCEN
Enable
Oscillator(1) FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inver ter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow TMR1
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 29
5.2 Timer1 Oscillator
A crystal oscillator circuit is built-in betw een pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). When the
Timer1 oscillator is enabled, RC0 and RC1 pins
become T1OSO and T1OSI inputs, overriding
TRISC<1:0>.
The oscillator is a low power oscillator rated up to 200
kHz. It will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 5-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1 CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
5.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit TMR1IF (PIR1<0>).
This int errupt can be enab led b y setting TM R1 interrupt
enable bit TMR1IE (PIE1<0>).
5.4 Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this si gnal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchro-
niz ed counter m ode to tak e adv antage of th is f eature . If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coi ncides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of oper ation, the CCPR1H:CC PR1L regis -
ters pair effectively becomes the period register for
Timer1.
TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
Thes e values are for design guidance only.
Cr ysta ls Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonato r /c rystal man ufacturer for appropri-
ate values of external components.
Note: The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Eh T MR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register f or the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
PIC16C62B/72A
DS35008B-page 30 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 31
6.0 T IMER2 MODULE
The Time r2 module timer has the following features:
• 8-bit timer (TMR2 register)
- Readable and writable
• 8-bit period register (PR2)
- Readable and writable
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on match (TMR2 = PR2)
• Timer2 can be used by SSP and CCP
Timer2 has a control register, shown in Register 6-1.
Timer2 can be shut off by clearing co ntrol bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 6-1 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
FIGURE 6-1: TIMER2 BLOCK DIAGRAM
REGISTER 6-1:T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
to
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writable bi t
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2: TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC16C62B/72A
DS35008B-page 32 Preliminary 1999 Microchip Technology Inc.
6.1 Timer2 Operation
The Time r2 output is also used by the CCP module to
generate the PWM "On-Time", and the PWM period
with a match with PR2.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The i nput clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1: 0>).
The match output of TMR2 goes through a 4-bit
post sc al er (whi ch gives a 1:1 to 1:16 scaling ) to gen er-
ate a TMR2 interrupt (latched in flag bit TMR2IF,
(PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TM R2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
6.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readab le and writable register. The PR2 register is ini-
tialized to FFh upon reset.
6.3 Output of TMR2
The outpu t of TMR2 (bef ore th e postscaler) i s fed to the
Synchron ous Serial P ort module, w hich option ally uses
it to generate shift clock.
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -00- 0000 0000 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 33
7.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (C ap ture /Com pare /PWM ) m od ule c on tain s a
16-bit register, which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave duty cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
TABLE 7-1 CCP MODE - TIMER
RESOURCE
TABLE 7-2 INTERACTION OF TWO CCP MODULES
REGISTER 7-1:CCP1CON REGISTER (ADDRESS 17h)
CCP Mode Timer Re source
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base.
Capture Compare The compare should be configured for the special ev ent trigger , which clears TMR1.
Compare Compare The compare(s) should be configured for the special ev ent trigger , which clears TMR1.
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM Capture None.
PWM Compare None.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit
W =Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of t he PWM duty cyc le. The eight M Sbs are found in CC PR1L.
bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mo de , clear output on match (CCP 1IF bit is set)
1010 = Com pare mode , generate so ftware in terrupt on match (C CP1IF bit is set, CC P1 pin is unaff ected )
1011 = Compare mode, tr igger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D
conversion (if A/D module is enabled))
11xx = PWM mode
PIC16C62B/72A
DS35008B-page 34 Preliminary 1999 Microchip Technology Inc.
7.1 Captu re Mod e
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register, when an event
occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit ,CCP1IF (PIR1<2>), is set. It must
be clea red in softw are. If anot her capture occu rs befo re
the value in register CCPR1 is read, the old captured
value will be lost.
FIGURE 7-1: CAPTURE MODE OPERATION
BLOC K DIAGRAM
7.1.1 CCP PIN CONFIGURATION
In Captu re m ode, the RC2/CCP1 p in s hou ld b e config-
ured as an input by setting the TRISC<2> bit.
7.1.2 TIMER1 MODE SELECTION
Timer1 m ust be runni ng in timer m ode or s ynchr oniz ed
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work consistently.
7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should clear
CCP1 IE ( PI E 1< 2> ) before c han gi n g t he ca pt u re mo de
to avoid false interrupts. Clear the interrupt flag bit,
CCP1IE before setting CCP1IE.
7.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
Note: If the RC2/CCP1 is configured as an out-
put, a write to th e port can cause a ca pture
conditi on.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 35
7.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. Wh en a match occurs, the RC2/CCP1 pin is:
•driven High
• driven Low
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). The inter-
rupt flag bit, CCP1IF, is set on all compare matches.
FIGURE 7-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
7.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation ma y not work.
7.2.3 SOFTWARE INTERRUPT MODE
When a generated software interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
7.2.4 SPECIAL EVENT TRIGGER
In this mod e, an in ternal hardw a re trigger is g ener ated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
eff ec tiv el y be a 16-b it prog ram mab le period register f or
Timer1.
The special trigger output of CCP1 resets the TMR1
register pair and starts an A/D conversion (if the A/D
module is enabled).
TABLE 7-3 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Ev ent Trigger
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>), which starts an A/D
conversion
Note: Clear ing the CCP1C ON register will force
the RC2/ CCP1 comp are output latc h to the
default low level. This is not the data latch.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all othe r
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
PIC16C62B/72A
DS35008B-page 36 Preliminary 1999 Microchip Technology Inc.
7.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is m ultiplex ed with the PORTC data latch,
the TRISC<2> bit mu st be cleared to make the CCP1
pin an out put.
Figure 7-3 shows a simplified block diagram of the CCP
module in PWM mode.
F or a step by step pro cedure on h ow t o set up the CCP
module for PWM operation, see Section 7.3.3.
FIGURE 7-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 7-4) has a time base (period)
and a tim e that the output sta ys high (on-time). T he fre-
quency of the PWM is the inverse of the period
(1/period).
FIGURE 7-4: PWM OUTPUT
7.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR 2 is equal to PR2, the f ollo wing three e v ents
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
7.3.2 PWM ON-TIME
The PWM on-time is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolutio n is a v ailab le. C CPR1L c ontains e ight
MSbs and CCP1CON<5:4> contains two LSbs. This
10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM on-time = (CCPR1L:CCP1CON<5:4>) •
To sc • (TMR2 prescale value)
CCPR1L and CC P1CON <5:4> c an be writ ten to at an y
time , but the on-ti me value is not latc he d i nto CCPR1H
until after a match between PR2 and TMR2 occurs (i.e .,
the period is complete). In PWM mode, CCPR1H is a
read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM on-time. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
For an example PWM period and on-time calculation,
see the PICmicro™ Mid-Range Reference Manual,
(DS33023).
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
Period
On-Time
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Tim er2 p ost sc ale r (s ee Se ction 6.0) is
not us ed in t he det erm inati on of t he PWM
frequenc y. The pos tscaler cou ld be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note: If the PWM o n-time v alu e is l arger than th e
PWM period, the CCP1 pin will not be
cleared.
log ( Fpwm
log(2)
Fosc )bits=
Resolution
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 37
7.3.3 SET-UP FOR PWM OPERATION
The followi ng steps sh ould be ta ken wh en configu ring
the CCP module for PWM operation:
1. Se t the PWM p eriod b y writing to t he PR2 regi s-
ter.
2. Set the P WM on-time by wr iting to the CCPR1L
register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC< 2> bit.
4. Set the TMR2 prescale value and enab le Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 7-4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 7-5 REGISTERS ASSOCIATED WITH PWM AND TIMER2
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
Add res s Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/ PWM r egister1 ( LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compar e/ PWM regis ter1 ( MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
PIC16C62B/72A
DS35008B-page 38 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 39
8.0 SYNCHR ONOUS SERIAL P O RT
(SSP) MODULE
8.1 SSP Module Overview
The Synchronous Serial Por t (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play driv ers, A/D conv e rters, etc. Th e SSP modul e ca n
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
For more information on SSP operation (including an
I2C Overview), ref er to the PICmicro™ Mid-Range Ref-
erence Manual, (DS33023). Also, refer to Application
Note AN578,
“Use of the SSP Module in th e I
2
C Multi-
Master En viro nm ent .”
8.2 SPI Mode
This section contains register definitions and opera-
tional ch aracteristics of the SPI module.
Additional information on SPI operation may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
8.2.1 OPERATION OF SSP MODULE IN SPI
MODE
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-1.
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, three pins are used:
• Serial Data Out (SDO)RC5/SDO
• Serial Data In (SDI)RC4/SDI/SDA
• Serial Clock (SCK)RC3/SCK/SCL
Additionally, a fourth pin may be used when in a slave
mode of operation:
•Slave Select (SS
)RA5/SS/AN4
When initializing the SPI, several options need to be
specif ied. This is don e by prog ramming the ap propriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
• Master Operation (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock Edge (Output data on rising/falling edge of
SCK)
• Clock Rate (master operation only)
• Slave Sel ect Mo de (Slave mode only )
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) m ust be set. To reset or recon figure SPI
mode, clear bit SSPEN , re-initialize the SSPCON reg-
ister, and then se t bi t SSPEN. Th is con fig ures the SDI,
SDO , S CK and S S pins as serial port pins. F o r the p ins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (master operation) must have TRISC<3>
cleared
• SCK (Sla ve mode) must ha ve TRISC<3> set
•SS
must have TRISA<5> set (if used)
FIGURE 8-1: SSP BLOCK DIAGRAM
(SPI MODE)
Note: When t he SPI is in Sla ve Mode wi th SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note: If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
Read Write
Internal
Data Bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
PIC16C62B/72A
DS35008B-page 40 Preliminary 1999 Microchip Technology Inc.
TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V alue on
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF ——SSPIFCCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE ——SSPIECCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 41
8.3 SSP I2C Operation
The SSP mod ule in I2C mode fully imple ments all sl av e
functions, except general call support, and provides
interrupts on start and stop bits in hardware to support
firmware implementations of the master functions. The
SSP module im pl em ents the s tand ard mod e speci fic a-
tions, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits.
The SSP modul e functions are enab le d b y setti ng SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 8-2: SSP BLOCK DI AGRAM
(I2C MODE)
The SSP module has five registers for I2C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit addres s)
•I
2C Slave mode (7-bit address), with start and
stop bit interrupts enabled for firmware master
mode support
•I
2C Slave mode (10-bit address), with start and
stop bit interrupts enabled for firmware master
mode support
•I
2C start and stop bi t interrupts enabled for firm-
ware master mode support, slave mode idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be operated as open
drain outputs, provided these pins are programmed to
inputs by setting the appropriate TRISC bits.
Additional information on SSP I2C operation may be
f ound in the PICmicro™ Mid-Range Ref erence Manual,
(DS33023).
8.3.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as i nputs (TRISC<4:3> s et). Th e SSP module will
override the input state with the output data when
required (sl a ve-transmit ter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
load th e SSPBUF re gister with the receiv ed v alue in the
SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. This happens if
either of the following conditions occur:
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was completed.
b) The o v erflo w bit SSPOV (SSPCON<6>) was s et
before the transfer was completed.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-2 shows what happens when a data transfer
byte is receiv ed, given the status of bits BF and SSPOV.
The shaded cells show the condition where user soft-
ware did not properly clear the ov erflow condition. Flag
bit BF i s cleare d by re ading th e SSPBUF register, while
bit SSPOV is cleared through s oftware.
The SCL clock input must have a minimum high and
low for proper opera tio n. Th e high and low time s of th e
I2C specification, as well as the requirement of the SSP
module , is sho wn in timing par ameter #100 , THIGH, an d
parameter #101, TLOW.
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBU F reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
shift
clock
MSb
SDI/ LSb
SDA
PIC16C62B/72A
DS35008B-page 42 Preliminary 1999 Microchip Technology Inc.
8.3.1.1 ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR <7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) o f the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the tw o MSbs
of the address. The sequence of events for 10-bit
address is as f ollo ws, with steps 7- 9 f or s lav e-tr ansmit-
ter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Upd ate the SSPADD register with the first (hig h)
by te of Addres s, if match releas es SCL line , thi s
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 8-2 DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR → SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 Yes No Yes
Note:Shaded cells show the conditions where the user software did not properly clear the overflow condition.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 43
8.3.1.2 RECEPTION
When the R/W bit of the address by te is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister i s cleare d. The re ceive d addr ess is lo aded into the
SSPBUF register.
When t he add ress byte overflow conditi on exists, th en
no ac knowledg e (ACK) pu lse is giv en. An ov erflo w con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
by te. Fla g bit SSPIF (PI R1<3>) m ust be cleared in soft-
ware. The SSPSTAT register is used to deter mine the
status of the byte.
FIGURE 8-3: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
PIC16C62B/72A
DS35008B-page 44 Preliminary 1999 Microchip Technology Inc.
8.3.1.3 TRANSMISSION
When the R/W bi t of the i ncoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and the CKP will be cleared by
hardware, holding SCL low. Slave devices cause the
master t o wait b y holding th e SCL line lo w . The tr ansmit
data is loaded into the SSPBUF register, which in turn
loads the SSPSR register. When bit CKP (SSP-
CON<4>) is set, pin RC3/SCK/SCL releases SCL.
When the SCL line goes high, the master may resume
operating the SCL line and receiving data. The master
must monitor the SCL pin prior to asserting another
clock pulse. The slave devices may be holding off the
master by stretching the clock. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 8-4).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register used to determine the status of
the b yte . Flag bit SSPIF i s set on the falling ed ge of th e
ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SD A line was high (not A CK), then the
data transfer is complete. When the ACK is latched by
the sla v e , th e sla v e lo gic i s rese t (reset s SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the tr ansmit d ata must be load ed into t he SSPBUF re g-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 8-4: I2C WAVEF ORMS F OR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR 1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/W = 1Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in software From SSP interrupt
service routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 45
8.3.2 MASTER OPERATION
Master operation is suppor ted in firmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared by a reset or when the SSP module is dis-
abled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I2C bus may be taken when the P bit is set, or the
bus is idle and both the S and P bits are clear.
In mas ter opera tion, the SCL and SD A lines are manip-
ulated in software by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
transmitting data, a ’1’ data bit must have the
TRISC<4> bit set (input) and a ’0’ data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Byte tr ans fer complet ed
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see
AN554
- Software Implementation of I
2
C Bus Master
.
8.3.3 MULTI-MASTER OPER ATI ON
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bu s may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
le vel is outp ut. If a high le vel is e xpect ed and a low le v el
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues to
receiv e . I f a rbitr atio n w as lo st du ring th e add ress tr ans -
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time .
For more information on master operation, see
AN578
- Use of the SSP Module in the of I
2
C Multi-Master
Environment
.
TABLE 8-3 REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
resets
0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP(1) CKE(1) D/A PSR/WUA BF 0000 0000 0000 0000
87h TRISC PORTC Data Direction register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: Maintain these bits clear in I2C mode.
PIC16C62B/72A
DS35008B-page 46 Preliminary 1999 Microchip Technology Inc.
REGISTER 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF R = Readable bi t
W = Writable bit
U = Unimplemented bit, read
as ‘0 ’
- n =Value at POR reset
bit7 bit0
bit 7: SMP: SPI data input sample phase
SPI Master Operation
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
I2C Mode
This bit must be maintained clear
bit 6: CKE: SPI Clock Edge Select
SPI Mode
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
I2C Mode
This bit must be maintained clear
bit 5: D/A: Data/Address bit (I2C mode only)
1 = Indicate s that the last byte received or tran smitted was data
0 = Indicate s that the last byte received or tran smitted was address
bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Star t bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3: S: Star t bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2: R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1: UA: Update Address (10-bit I2C mode only)
1 = Indicate s that the user ne eds to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 47
REGISTER 8-2: SSPCON: SYNC SERIAL PORT CONTROL RE GISTER (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W = Writable bi t
U = Unimplemented bit, read
as ‘0 ’
- n =Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6: SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A ne w byte is received while the SSPBUF register is still holding th e previous data. In case of o verflo w ,
the data in SSPSR is lost. Ov erflo w can o nly occur in s lav e mode . The u ser must r ead the SSPB UF, ev en
if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since
each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in so ftware in either mode.
0 = No overflow
bit 5: SSPEN: Synchronous Serial Por t Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables seri al port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4: CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stret ch)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master operation, clock = FOSC/4
0001 = SPI master operation, clock = FOSC/16
0010 = SPI master operation, clock = FOSC/64
0011 = SPI master operation, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be us ed as I /O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master operation (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
PIC16C62B/72A
DS35008B-page 48 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 49
9.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has five
input channels.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
abl e to eithe r the de vice’s positiv e supply v oltag e (VDD)
or the voltage level on the RA3/AN3/VREF pin.
The A/D converter has the feature of being able to
oper ate while the devic e is in SLEEP mode. To operat e
in sleep, the A/D conversion clock must be derived from
the A/D’s internal RC oscillator.
Addition al inf ormation on the A/D module is a vai labl e in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
The A/D module has three registers. These registers
are: • A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversi on is abo rted.
The ADCON0 register, shown in Figure 9-1, controls
the operation of the A/D module. The ADCON1 regis-
ter , shown i n Figure 9-2, configur es the func tions of th e
port pins. The port pins can be configured as analog
inputs (R A3 c an als o be a voltage reference ) or as di g-
ital I/O.
REGISTER 9-1:ADCON0 REGISTER (ADDRESS 1Fh)
Note: This section applies to the PIC16C72A
only.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000 = channel 0, (RA0/AN0)
001 = channel 1, (RA1/AN1)
010 = channel 2, (RA2/AN2)
011 = channel 3, (RA3/AN3)
100 = channel 4, (RA5/AN4)
bit 2: GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is comp lete)
bit 1: Unimplemented: Read as '0'
bit 0: ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
PIC16C62B/72A
DS35008B-page 50 Preliminary 1999 Microchip Technology Inc.
REGISTER 9-2:ADCON1 REGISTER (ADDRESS 9Fh)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit
W =Writable bit
U =Unimplemented bit,
read as ‘0 ’
- n = Value at POR
reset
bit7 bit0
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
A = Analog input
D = Digital I/O
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF
000 AAAAA VDD
001 AAAAVREF RA3
010 AAAAA VDD
011 AAAAVREF RA3
100 AADDA VDD
101 AADDVREF RA3
11x DDDDD V
DD
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 51
When the A/D conversion is complete, the result is
loaded into the ADRES register, the GO/DONE bit,
ADCON0<2>, is cleared, and the A/D interrupt flag bit,
ADIF, is set. The block diagram of the A/D module is
shown in Figure 9-1.
The v a lue t hat is in the ADRES regist er is not modifie d
for a P ower-on Rese t. Th e ADR ES re gis ter will co ntai n
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 9.1.
After this acqui sitio n time has e lapse d, the A/D c on v er-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversio n:
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acqu is itio n tim e .
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversi on to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 9-1: A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG2:PCFG0
CHS2:CHS0
000 or
010 or
100 or
001 or
011 or
101
RA5/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
100
011
010
001
000
A/D
Converter
11x
PIC16C62B/72A
DS35008B-page 52 Preliminary 1999 Microchip Technology Inc.
9.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-2. The source
impeda nce (RS) and the internal sampli ng s witch (R SS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
sour ce impe dan ce a ff ects the of fset voltage a t the an a-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
kΩ. After the analog input channel is selected
(changed), this acquisition must pass before the con-
version can be star ted.
To calculate the minimum acquisition time, TACQ, see
Equation 9-1. This equation calculates the acquisition
time to wi thin 1/2 LSb error (512 steps f or the A/D). Th e
1/2 LS b er ror i s th e max imum error allow ed for the A/D
to meet its specified accuracy.
In general;
Assuming RS= 10kΩ
Vdd = 3.0V (RSS = 10kΩ)
Temp. = 50°C (122°F)
TACQ ≈ 13.0 µSec
By increasing VDD and reducing RS and Temp., TACQ
can be substantially reduced.
FIGURE 9-2: ANALOG INPUT MODEL
EQUATION 9-1: ACQUISITION TIME
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
TACQ =
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
TAMP = 5µS
TC = - (51.2pF)(1kΩ + RSS + RS) In(1/511)
TCOFF = (Te mp - 25°C)(0.05µS/°C)
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
RSS
5V
4V
3V
2V
567891011
(kΩ)
VDD
= 51.2 pF
± 500 nA
Legend CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= lea kage current at the pin d ue to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 53
9.2 Selecting the A/D Conver sion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•2T
OSC
•8TOSC
•32TOSC
• Internal RC oscillator
For cor rect A /D co nve rsio ns, the A/ D conversion clock
(TAD) must be sel ect ed to ens ure a minimu m TAD time
of 1.6 µs.
The A/D module can operate during sleep mode, but
the RC oscillator must be selected as the A/D clock
source prior to the SLEEP instruction.
Table 9-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
sour ce se lec ted .
9.3 Configuring Analog Port Pins
The ADCON1 and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desire d
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 9-1 TAD vs. DEVICE OPERATING FREQUENCIES
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note 2: Analo g le vels on an y pin that is d efined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
AD Clock Source (TAD) Dev ice Frequency
Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz
2TOSC 00 100 ns(2) 400 ns(2) 1.6 µs6 µs
8TOSC 01 400 ns(2) 1.6 µs6.4 µs24 µs(3)
32TOSC 10 1.6 µs6.4 µs25.6 µs(3) 96 µs(3)
RC(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)
Legend: Shaded cells are outside of recommended range.
Note1: The RC so urce has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
PIC16C62B/72A
DS35008B-page 54 Preliminary 1999 Microchip Technology Inc.
9.4 A/D Conversions
9.5 Use of the CCP Trigger
An A/D c on ve rsi on can be sta rted b y the “s pecia l e v e nt
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
gr ammed as 1011 and t hat the A/D mod ule be enable d
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, star ting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to au tomat icall y repe at the A/D acquisi tion p eriod
with minimal software overhead. The appropriate ana-
log input channel must be selected and the minimum
acquisition time must pass before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 9-2 SUMMARY OF A/D REGISTERS
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other Resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 —ADIF — —SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 —ADIE — —SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used for A/D con version.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 55
10.0 SPECIAL FEATURES OF THE
CPU
The PIC16C62B/72A devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. These are:
• Oscillator Mode Selection
• Reset
- Power-on Reset (POR)
- P o wer-up Timer (PWR T)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming™ (ICSP)
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that off er n ec es sary delays on power-up. One is
the Oscillator Star t-up Timer (OST), intended to keep
the chi p in rese t until th e crystal osci llator is stab le. Th e
other is th e Power-up Tim er (PWRT), which provides a
fixed delay on power-up only and is designed to keep
the part in reset w hile t he po wer sup ply stab iliz es . Wi th
these two timers on-chip, most applications need no
ex ternal reset circuitry.
SLEEP mode is designed to offer a very low current
pow er-down m ode. The user can w ake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Se veral osc illato r option s are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Addition al information on special features is availab le in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
10.1 Configuration Bits
The con figur ati on bits c an be progr a mmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFF h), whic h can be ac cessed on ly dur ing progra m-
ming.
FIGURE 10-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address: 2007h
bit13 bit0
bit 13-8 CP1:CP0: Code Protect ion bits (2)
5-4: 11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7: Unimplemented: Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: E nabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the va lue of bit PWRTE.
All of the CP1:CP0 pairs must be given the same value to enable the code protection scheme listed.
PIC16C62B/72A
DS35008B-page 56 Preliminary 1999 Microchip Technology Inc.
10.2 Oscillator Configurations
10.2.1 OSCILLATOR TYPES
The PIC16CXXX can be operated in four dif ferent osci l-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
• LP Low Power Crystal
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
10.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 10-2). The
PIC16CXXX oscillator de sign requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can use
an exter nal clock source to drive the OSC1/CLKIN pin
(Figure 10-3).
FIGURE 10-2: CRYS TAL/CERAMI C
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 10-3: EXTERNAL CLOCK I NPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
TABLE 10-1 CERAMIC RESONATORS
TABLE 10-2 CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Note1: See Table 1 0-1 and Table 10-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF va ries with the crystal chosen.
C1(1)
C2(1)
XTALOSC2
OSC1
RF(3)
SLEEP
To
logic
PIC16CXXX
RS(2)
internal
OSC1
OSC2
Open
Clock from
ext. system PIC16CXXX
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
Resonators did not have b uilt -in capacitors.
Osc Type Crystal
Freq Cap. Range
C1 Cap. Range
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15 -33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design g uidance onl y. See
notes at bottom of page.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Higher capacitance increases the stability of the
oscillator, but also increases the star t-up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resona-
tor/crystal manuf acturer for appropriate values of
ex ternal components.
3: Rs may be required in HS mode, as well as XT
mode, to a void overdriving crystals with low drive
level specification.
4: Oscillator performance should be verified when
migrating between de vices (including
PIC16C62A to PIC16C62B and PIC16C72 to
PIC16C72A)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 57
10.2.3 RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) v alu es , and the oper at-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
var iation due to tolerance of exter nal R and C compo-
nents used. Figure 10-4 shows how the R/C combina-
tion is connected to the PIC16CXXX.
FIGURE 10-4: RC OSCILLATOR MODE
10.3 Reset
The PIC16CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
•MCLR
reset during normal operation
•MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
Some registers are not affected in any reset condition;
their stat us is unkn own o n POR and unch anged b y an y
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and on
Brown-out Reset (BOR). They are not affected by a
WDT Wake-up from SLEEP, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared depending on the reset situation, as
indica ted in Table 10-4. These bits are u sed in softwa re
to determine the nature of the reset. See Table 10-6 for
a full description of reset states of all registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown in Figu re 10-5.
The PICmicro devices have a MCLR noise filter in the
MCLR reset path. The filter will ignore small pulses.
However, a valid MCLR pulse must meet the minimum
pulse width (TmcL, Specification #30).
No internal reset source (WDT, BOR, POR) willdrive
the MCLR pin low.
OSC2/CLKOUT
Cext
Rext
PIC16CXX
OSC1
Fosc/4
Internal
clock
VDD
VSS
Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
PIC16C62B/72A
DS35008B-page 58 Preliminary 1999 Microchip Technology Inc.
FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 59
10.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate e xternal RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified (SVDD, parameter D004). For a slow rise
time, see Figure 10-6.
When the device starts normal operation (exits the
reset co ndi tion), devic e op er ating parameters (voltage ,
frequency, temperature,...) mu st be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset ma y be used to meet the sta rt-up con-
ditions.
FIGURE 10-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
10.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time -out
(TPWRT, parameter #33) from the POR. The Power-up
Timer ope rates on an internal RC o scillator. The chip is
kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
The po wer-up ti me dela y will v ary from ch ip-to-chip du e
to VDD, temperature and process variation. See DC
parameters for details.
10.6 Oscillator Start-up Timer (OST)
The Os cillator Sta rt-up Timer ( OST) pro vides a del ay of
1024 oscillator cycles (from OSC1 input) after the
PWRT delay is over (TOST, parameter #32). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
10.7 Brown-Out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-Out Reset circuit. If VPP falls below Vbor
(parameter #35, about 100µS), the brow n-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a reset may not occur.
Once the brown-out occurs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (par ameter #3 3, about 72 mS). If VDD shou ld f all
below VBOR during TPWRT, the brown-out reset pro-
cess will restar t when VDD rises above VBOR with the
power-up timer reset. The power-up timer is always
enabled when the brown-out reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
Note1: External P ower-on Reset cir cuit is required
only if V DD power-up s lope is too slo w . The
diode D helps discharge the capacitor
quickl y when V DD powers down.
2: R < 40 kΩ is recommended to make sure
that voltag e drop across R does not vi olate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break -
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16CXX
Note: The OST delay may not occur when the
device wakes from SLEEP.
PIC16C62B/72A
DS35008B-page 60 Preliminary 1999 Microchip Technology Inc.
10.8 Time-out Sequence
When a POR reset occurs, the PWRT delay starts (if
enabled). When PWRT ends, the OST counts 1024
oscillator cycles (LP, XT, HS modes only). When OST
completes, the device comes out of reset. The total
time-out will vary based on oscillator configuration and
the st atu s of th e PWRT. For example , in RC mo de with
the PWRT disabled, there will be no time-out at all.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MC LR high will begin ex ecution imme-
diately. This is useful f or testing purposes or to synchro-
nize more than one PIC16CXXX device operating in
parallel.
Table 10-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 10-6 shows the
reset conditions for all the registers.
10.9 Power Control/Status Register
(PCON)
The BOR bit is unknown on Power-on Reset. If the
Brown-out Reset circuit is used, the BOR bit must be
set by the user and checked on subsequent resets to
see if it was cleared, indicating a Brown-out has
occurred.
POR (Power-on Reset Status bit) is cleared on a
Power-on Reset and unaffected otherwise. The user
Status Register
PCON Register
TABLE 10-3 TIME-OUT IN VARIOUS SITUATIONS
TABLE 10-4 STATUS BITS AND THEIR SIGNIFICANCE
TABLE 10-5 RESET CONDITION FOR SPECIAL REGISTERS
IRP RP1 RP0 TO PD ZDC C
POR BOR
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms —72 ms —
POR BOR TO PD
0x11Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 61
TABLE 10-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable
Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
W62B72Axxxx xxxx uuuu uuuu uuuu uuuu
INDF 62B 72A N/A N/A N/A
TMR0 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
PCL 62B 72A 0000h 0000h PC + 1(2)
STATUS 62B 72A 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(4) 62B 72A --0x 0000 --0u 0000 --uu uuuu
PORTB(5) 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
PORTC(5) 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 62B 72A ---0 0000 ---0 0000 ---u uuuu
INTCON 62B 72A 0000 000x 0000 000u uuuu uuuu(1)
PIR1 62B 72A ---- 0000 ---- 0000 ---- uuuu(1)
62B 72A -0-- 0000 -0-- 0000 -u-- uuuu(1)
TMR1L 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 62B 72A --00 0000 --uu uuuu --uu uuuu
TMR2 62B 72A 0000 0000 0000 0000 uuuu uuuu
T2CON 62B 72A -000 0000 -000 0000 -uuu uuuu
SSPBUF 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 62B 72A 0000 0000 0000 0000 uuuu uuuu
CCPR1L 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 62B 72A --00 0000 --00 0000 --uu uuuu
ADRES 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 62B 72A 0000 00-0 0000 00-0 uuuu uu-u
OPTION_REG 62B 72A 1111 1111 1111 1111 uuuu uuuu
TRISA 62B 72A --11 1111 --11 1111 --uu uuuu
TRISB 62B 72A 1111 1111 1111 1111 uuuu uuuu
TRISC 62B 72A 1111 1111 1111 1111 uuuu uuuu
PIE1 62B 72A ---- 0000 ---- 0000 ---- uuuu
62B 72A -0-- 0000 -0-- 0000 -u-- uuuu
PCON 62B 72A ---- --0q ---- --uq ---- --uq
PR2 62B 72A 1111 1111 1111 1111 1111 1111
SSPADD 62B 72A 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 62B 72A 0000 0000 0000 0000 uuuu uuuu
ADCON1 62B 72A ---- -000 ---- -000 ---- -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 10-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
PIC16C62B/72A
DS35008B-page 62 Preliminary 1999 Microchip Technology Inc.
10.10 Interrupts
The interrupt control register (INTCON) reco rds individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables or disables all interrupts. When bit GIE is
enab led, and an interrupt’ s fla g bit and ma sk bit are se t,
the interrupt will vector immediately. Individual inter-
rupts can be disabled through their corresponding
enable bits in v ari ous registers. Indi vi dua l in terrupt flag
bits are set regardless of the status of the GIE bit. The
GIE bit is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit, which re-
enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial fu nction regist ers PIR1 and PI R2. The co rrespond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bi t i s co nta ine d i n sp eci al function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pu sh ed onto the stack and the PC is lo ade d
with 0004h. Once in the interrupt service routine, the
source of the interrupt can be de termined by pol ling the
interrupt flag b its . The in terrupt flag bi t must be cleare d
in softw are bef ore re-enab ling int errupts to av oid rec ur-
sive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycl es , depe nding on whe n th e
interrupt event occurs. The latency is the same for one
or two cycle instructions. Individual interrupt flag bits
are set regardless of the status of their corresponding
mask bit or the GIE bit
FIGURE 10-7: INTERRUPT LOGIC
Note: Indiv id ual int errupt fla g bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
ADIF(1)
ADIE(1)
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
Note 1: The A/D module is not implemented on the PIC16C62B.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 63
10.10.1 INT INTERRUPT
The external interrupt on RB0/INT pin is edge trig-
gered: either risi ng, i f bi t INTEDG (OPT ION_REG<6>)
is set, or f all ing, if the IN TEDG bit is cle ar . Wh en a v alid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interr upt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be clea red in s oftware i n the in terrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEE P, if bit INTE was
set prior to goin g into SLEEP. The sta tus of global inter-
rupt enable bit GIE decides whether or not the proc es-
sor b ra nc h es to t h e in te rrup t vect or follow in g wake-u p.
See Section 10.13 for details on SLEEP mode.
10.10.2 TMR0 INTERRUPT
An overf l ow (F F h → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
10.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
10.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on th e stack. Typically, users may wi sh to sa v e key reg-
isters during an interrupt, (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 10-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each ba nk and m ust be defined at the same offs et from
the bank base address (i.e., if W_TEMP is defined at
0x20 i n bank 0, it must also be de fin ed at 0xA0 in bank
1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the interrupt service routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR)
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
PIC16C62B/72A
DS35008B-page 64 Preliminary 1999 Microchip Technology Inc.
10.12 Watchdog Timer (WDT)
The W atchdog Timer is a free running on-chip RC oscil-
lato r w h ic h do es no t re qu i re any exte rna l com po n en ts.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. The WDT will run, even if the
clock on the OSC1/CLKIN and OSC2/CLKOUT pins of
the de vice has been stopped, f or example , by e xecution
of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Wat chdog Timer Reset). If the de vice is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer W ake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Tim er time-out .
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 10.1).
The WDT time-out period (TWDT, parameter #31) is
multiplied by the prescaler ratio, when the prescaler is
assigned to the WDT. The prescaler assignment
(assigned to either the WDT or Timer0) and pres caler
ratio are set in the OPTION_REG register.
.
FIGURE 10-8: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The CLRWDT and SLEEP instr uctions clear
the WDT an d th e postscaler, if assigned to
the WDT, and prev ent it from timing out and
generating a device RESET condition.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
From TMR0 Clock Source
(Figure 4-2)
To TMR0 (Figure 4-2)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
8
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 65
10.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
ke eps running , the PD bit (STATUS<3>) is clea red, th e
TO (STATUS<4>) bit is set, and the oscillator driver is
tur ned off. The I/O por ts ma intai n the sta tus th ey had,
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low exter nally, to
avoid switching curre nts ca us ed by floating inp uts. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC,
parameter D042).
10.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt fro m INT pin, RB port change , or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP capture mode interrupt.
3. Special event trigger (Timer1 in asynchronous
mode u sing an ex ter nal cl ock. CCP1 i s in co m-
pare mode).
4. SSP (Start/Stop) bit detect interrupt.
5. SSP transmit or receiv e in slav e mode (SPI/I2C).
6. USART RX or TX (synchronous slave mode).
Other pe ripherals can not gener ate interrupts s ince dur-
ing SLEEP, no on-chip clocks are present.
When th e SLEEP inst ruction is being ex ecuted, the ne xt
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device resumes execution at the
instruction after the SLEEP instr uct ion . If t he GIE bi t is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
ru pt ad dress (00 04h ). In ca ses wh ere the execution of
the instru cti on follow i ng SLEEP is not d esi rable , a NOP
should follow the SLEEP inst ruction.
10.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt flag bit se t, one o f the f o llo wing w ill o ccur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction wi ll com -
plete as a NOP. There fore, the WD T and WDT
pos tscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleare d.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, the device will imme-
diately wake up from slee p. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP ins truc tion exec uted, t est
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT i nstr uc-
tion should be executed before a SLEEP instruction.
PIC16C62B/72A
DS35008B-page 66 Preliminary 1999 Microchip Technology Inc.
FIGURE 10-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
10.14 Program Verification/Code Protection
If the code protection bits have not been programmed,
the on-chi p prog ram m emory can be read out f o r v erifi-
cation purposes .
10.15 ID Locations
F our memory locations (2000h - 2003h) are designate d
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
10.16 In-Circuit Serial Programming™
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done wit h two lines f or c lock a nd dat a, and thre e
more lines for power , ground and th e programming volt-
age. This al lows customers to manufacture boards wi th
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom fir mware
to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, DS30277.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’ 0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but sho wn here for tim ing reference.
Note: Microchip does not recommend code pro-
tecting windowed devices.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 67
11.0 INSTR UCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
oper at ion of the instructio n. The PIC 16CXX ins tructio n
set summary in Table 11-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 11-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W regi ster . If ’ d’ is one, the resu lt is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
design ator which selec ts t he number of the bit affe cte d
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eigh t or eleven bit constant or literal value.
TABLE 11-1 OPCODE FIELD
DESCRIPTIONS
The ins truc ti o n se t is hig hl y orthogon al an d is grou p ed
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont r ol operations
All instructions are executed within one single instr uc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In thi s case, t he exe cut ion t akes two ins tr ucti on cy cles
with the second cycle ex ecuted as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osci llator frequ ency of 4 MHz, the normal instructio n
e xecution tim e is 1 µs . If a condit ional te st is true or th e
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 11-2 lists the instructions recognized by the
MPASM assembler .
Figur e 11-1 sho ws the gene ral f ormats that the ins truc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 11-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file r egister
kLiteral field, constant data or label
xDon’t care location (= 0 or 1)
The assembler will generat e code with x = 0. I t is t he
recommended form of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Time-out bit
PD Power-down bit
ZZero bit
DC Digit Carry bit
CCarry bit
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instru ctions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C62B/72A
DS35008B-page 68 Preliminary 1999 Microchip Technology Inc.
TABLE 11-2 PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Cl ear
Bit Test f, Skip if Se t
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move lit eral to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an e xternal
devi ce , the data will be written back with a ’0’.
2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 69
11.1 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [
label
] ADDLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register are
added to the eight bit literal ’ k’ and the
result is placed in the W register.
ADDWF Add W and f
Syntax: [
label
] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ’f ’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
ANDLW AND Literal with W
Syntax: [
label
] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register .
ANDWF AND W with f
Syntax: [
label
] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
BCF Bit Clear f
Syntax: [
label
] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is cleared.
BSF Bit Set f
Syntax: [
label
] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Description: Bit 'b' in register 'f' is set.
PIC16C62B/72A
DS35008B-page 70 Preliminary 1999 Microchip Technology Inc.
BTFSS Bit Test f, Skip if Set
Syntax: [
label
] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ’ b’ in register ’ f’ is ’0’, then the next
instruction is executed.
If bit ’b’ is ’1’, then the next instruction
is discarded and a NOP is executed
instead, making this a 2TCY instruc-
tion.
BTFSC Bit Test, Skip if Clear
Syntax: [
label
] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ’ b’ in register ’ f’ i s ’1’ , then the ne xt
instruction is executed.
If bit ’ b’ in register ’f’ is ’0’, then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
CALL Call Subroutine
Syntax: [
label
] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
elev en bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two cycle inst ruction.
CLRF Clear f
Syntax: [
label
] CLRF f
Operands: 0 ≤ f ≤ 127
Operat ion: 00h → (f)
1 → Z
Status Affected: Z
Description: The contents of register ’ f’ are cleared
and the Z bit is set.
CLRW Clear W
Syntax: [
label
] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.
CLRWDT Clear Watchdog Timer
Syntax: [
label
] CLRW DT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the Watch-
dog Timer . It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 71
COMF Complement f
Syntax: [
label
] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register ’f’ are comple-
mented. If ’d’ is 0, the result is stored
in W. If ’d’ is 1, the result is stored
back in register ’f’.
DECF Decrement f
Syntax: [
label
] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affected: Z
Description: Decrement register ’f’. If ’d’ is 0, the
result is stored in the W register. If ’d’
is 1, the result is stored back in regis-
ter ’f’.
DECFSZ Decrement f, Skip if 0
Syntax: [
label
] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Description: The contents of regist er ’f’ are decre-
mented. If ’d’ is 0, the result is plac ed in
the W register. If ’d’ is 1, the result is
placed back in register ’f ’.
If the result is 1, the next instruction, is
e xecuted. If the result is 0, then a NOP is
executed ins tead making it a 2TCY
instruction.
GOTO Unconditional Branch
Syntax: [
label
] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. T he upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruct ion.
INCF Increment f
Syntax: [
label
] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register . If ’ d’ is 1, the result is
placed back in register ’f’.
INCFSZ Increment f, Skip if 0
Syntax: [
label
] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operat ion: (f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed
in the W register . If ’d’ is 1, the result is
placed back in register ’f’.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead making it a 2TCY
instruction.
PIC16C62B/72A
DS35008B-page 72 Preliminary 1999 Microchip Technology Inc.
IORLW Inclusive OR Literal with W
Syntax: [
label
] IORLW k
Operands: 0 ≤ k ≤ 255
Operat ion: (W) .OR. k → (W)
Status Affected: Z
Description: The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [
label
] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (dest inati on)
Status Affected: Z
Description: Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0, the result is placed in
the W register. If 'd' is 1, the result is
placed back in register 'f'.
MOVF Move f
Syntax: [
label
] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register f is move d to
a destination dependant upon the sta-
tus of d. If d = 0, destination is W reg-
ister. If d = 1, the destination is file
register f itself. d = 1 is useful t o test a
file register since status flag Z is
affected.
MOVLW Move Literal to W
Syntax: [
label
] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Description: The eight bit l iter al 'k' is loaded int o W
register. The don’t cares will assem-
ble as 0’s.
MOVWF Move W to f
Syntax: [
label
] MOVWF f
Operands: 0 ≤ f ≤ 127
Operat ion: (W) → (f)
Status Affected: None
Description: Move data from W register to register
'f'.
NOP No Operation
Syntax: [
label
] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 73
RETFIE Return from Interrupt
Syntax: [
label
] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
RETLW Return with Literal in W
Syntax: [
label
] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Description: The W register is loaded with t he eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
RETURN Return from Subroutine
Syntax: [
label
] RETURN
Operands: None
Operation: T OS → PC
Status Affected: None
Description: Return from subroutine. The stack is
POPed and the t op of the stack (T OS)
is loaded into the program counter.
This is a two cycle instruction.
RLF Rotate Left f through Carry
Syntax: [
label
] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See des c ription below
Status Affected: C
Description: The contents of register ’f ’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
RRF Rotate Right f through Carry
Syntax: [
label
] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description bel ow
Status Affected: C
Description: The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
SLEEP
Syntax: [
label
] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Description: The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Wat chdog Timer and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 10.13 for more details.
Register fC
Register fC
PIC16C62B/72A
DS35008B-page 74 Preliminary 1999 Microchip Technology Inc.
SUBLW Subtract W from Literal
Syntax: [
label
]SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s com-
plement method) from the eight bit lit-
eral 'k'. The result is placed in the W
register.
SUBWF Subtract W from f
Syntax: [
label
]SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status
Affected: C, DC, Z
Description: Subtract (2’s complement method) W
register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is
1, the result is stored back in register 'f'.
SWAPF Swap Nibbles in f
Syntax: [
label
] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of regis-
ter 'f' are exchanged. If 'd' is 0, the
result is placed in W register . If 'd' is 1,
the result is placed in register 'f'.
XORLW Exclusive OR Lite ral with W
Syntax: [
label
]XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the eight bit literal 'k '.
The result is placed in the W regis-
ter.
XORWF Exclusive OR W with f
Syntax: [
label
] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd'
is 1, the result is stored back in regis-
ter 'f'.
1999 Microchip Technology Inc. Preliminary DS35008B-page 75
PIC16C62B/72A
12.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment tools:
• Integrated Development Environment
- MPLAB™ IDE Software
• Assemblers/Compilers/Linkers
- MPASM Assembler
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
- MPLAB-SIM Software Simulator
•Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circui t
Emulator
-ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F 877
• Device Programmers
-PRO MATE
II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- SEEVAL
-KEELOQ
12.1 MPLAB Integrated Development
Environment Software
- The MPLAB IDE sof tware brin gs an ease of
software development previously unseen in
the 8-bit microcontroller market. MPLAB is a
Windows-based application which contains:
• Multiple functionality
-editor
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
• On-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct informati on)
• Debug using:
- source files
- abs olute listing file
- object co de
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consi ste nt pl atform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
12.2 MPASM Assembler
MPASM is a full f eat ured unive rsal macr o assembl er for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
MPASM has a command line interface and a Windows
shell and c an be u sed a s a stand alone appli catio n o n a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file whi ch con tai ns so urce lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
MPASM feature s includ e:
• MPASM and MPLINK are integrated into MPLAB
projects.
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directiv es a llow c omplete c ontrol o ve r the
assem b l y proces s .
12.3 MP LAB- C17 and MPLAB- C18
C Compilers
The MPLAB-C 17 and MPLAB -C18 Code De v elop ment
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC16C62B/72A
DS35008B-page 76 Preliminary 1999 Microchip Technology Inc.
12.4 MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that cont ains
that routine will be linked in with the application. This
allows l arg e li brarie s t o b e u se d eff i ci ent l y i n ma ny di f -
ferent applications. MPLIB manages the creation and
modification of library files.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
MPLIB features include:
• MPLIB makes linkin g ea sie r bec au se sin gle librar-
ies can be included instead of many smaller files.
• MPLIB hel ps k ee p code main tainab l e b y g roupin g
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
12.5 MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
leve l. On a ny given inst ructi on, the data are as can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
e xecution can be perf ormed in singl e step, e xecute until
break, or trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
deb ug code outside of the laboratory enviro nment mak-
ing it an excellent multi-project software development
tool.
12.6 MPLAB-ICE High P erfor mance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platf orm and M icrosoft® Windows
3.x/95/98 en vironment w ere chosen to best mak e these
features available to you, the end user.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
12.7 PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technolog y is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
12.8 ICEPIC
ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the
Microchip Technology PIC16 C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-
progr amma b le (OTP) microcontrollers . The modula r
system can suppo rt different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeab le persona lity modules or daughter
boards. The em ulator is capable of emulating without
target application circuitry being present.
12.9 MPLAB-ICD In-Circuit Debugger
Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a po w-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Developmen t Environment. This enables a designer to
de velop and deb u g sourc e code by watc hing variables ,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
1999 Microchip Technology Inc. Preliminary DS35008B-page 77
PIC16C62B/72A
12.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
ture d programme r capable of operati ng in stand -alo ne
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memor y
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to suppor t various package types. In
stand-al on e m ode the PRO MATE II can read , verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
12.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Pl us supp o rts a ll PI Cmicr o devices wi th up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
12.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchi p’s PIC12C5XX, PIC12C E5 XX, an d
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE wor ks in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SI MICE enables
a developer to run simulator code for driving the target
system . In addition, the target system can provi de input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu -
able debugging tool for entry-level system develop-
ment.
12.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and downl o a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
12.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, an d easil y test firmware .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ket (s). Some of the f eatures include a RS-232 int er-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of th e I2C bu s and separ ate hea ders f or connec -
tion to an LCD module and a keypad.
12.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers wi th a LCD Mo dul e . All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PIC DEM -3 boa rd, on a PRO MATE II pro gram-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Addit ional protot ype a rea has been provided to
the us er for adding ha rdware and con necti ng it to the
microcontroller socket(s). Some of the f eatures i nclude
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the we ek . Th e PICDEM-3 pro vi de s a n add i-
tional RS-232 interface and Windows 3.1 software for
showing the demulti plex ed LCD signals on a PC . A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PIC16C62B/72A
DS35008B-page 78 Preliminary 1999 Microchip Technology Inc.
12.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers, including PIC17C752, PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is incl uded to run bas ic demo prog rams, which are su p-
plied on a 3.5-inch disk. A programmed sample is
includ ed, and the us er ma y eras e it an d prog ram it wi th
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code . In additio n, PICDEM-17 su p-
ports down-loa ding of progr ams to and e xec uting out of
e xt ernal FLASH memory on board. The PICD EM -17 i s
also usab le with th e MPL AB-ICE or PI CMASTER em u-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
12.17 SEEV AL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Ser ial EEPROMs. The kit
includes everything necessar y to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized syst em.
12.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transm issions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. Preliminary DS35008B-page 79
PIC16C62B/72A
TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft w ar e To ol s
MPLAB Integrated
Develo pm en t Envi ro nm e nt
á
á
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á
á
MPLAB C18 Compiler
á
MPASM/MPLINK
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Emulators
MPLAB™-ICE
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PICMASTER/PICMASTER-CE
á
á
á
á
á
á
á
á
á
á
á
ICEPIC Low-Cost
In-Circuit Emulator
á
á
á
á
á
á
á
á
Debugger
MPLAB-ICD In-Circuit Debugger
á
*
á
*
á
Programmers
PICSTARTPlus
Low-Cost Universal Dev. Kit
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer
á
á
á
á
á
á
**
á
á
á
á
á
á
á
á
á
á
Demo Boards and Eval Kits
SIMICE
á
á
PICDEM-1
á
á
á
†
á
á
PICDEM-2
á
†
á
†
á
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
KEELOQ® Evaluation Kit
á
KEELOQ Transponder Kit
á
microID™ Progr ammer’s Kit
á
125 kHz microID Developer’s Kit
á
125 kHz Anticollision microID
Developer’s Kit
á
13.56 MHz Anticollision microID
Developer’s Kit
á
MCP2510 CAN Developer’s Kit
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC16C62B/72A
DS35008B-page 80 Preliminary 1999 Microchip Technology Inc.
NOTES:
1998 Microchip Technology Inc. Preliminary DS35008B-page 81
PIC16C62B/72A
13.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2)..........................................................................................0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin...........................................................................................................................300 mA
Maximum current in to VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA
Output clamp curr ent, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA
Maximu m out put current sunk by any I/O pin................. ..... ............................ ...... ...... ............................................25 mA
Maximu m out put current sourced by an y I/O pin ................ ...... ............................ ...... ..... .......................................25 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA
Maximum current sunk by PORTC........................................................................................................................200 mA
Maximum current sourced by PORTC ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage s pi kes below V SS at the MCLR/VPP pin, inducin g c urren ts greater than 8 0 m A, may cause latch- up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at thos e or an y other c onditi ons abo v e those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC16C62B/72A
DS35008B-page 82 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-1: PIC16C62B/72A-20 VOLTAGE-FREQUENCY GRAPH
FIGURE 13-2: PIC16LC62B/72A AND PIC16C62B/72A/JW VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
20 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC16CXXX
PIC16CXXX-20
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
10 MHz
5.0 V
3.5 V
3.0 V
2.5 V
FMAX = (12.0 MH z/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
4 MHz
PIC16LCXXX-04
Fmax is no greater than 10 MHz.
1998 Microchip Technology Inc. Preliminary DS35008B-page 83
PIC16C62B/72A
FIGURE 13-3: PIC16C62B/72A-04 VOLTAGE-FREQUENCY GRAPH
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
5.0 V
3.5 V
3.0 V
2.5 V
PIC16CXXX-04
4 MHz
PIC16C62B/72A
DS35008B-page 84 Preliminary 1998 Microchip Technology Inc.
13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended)
PIC16C62B/72A-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤+70°C for commercial
-40°C ≤ TA ≤+85°C for industr ial
-40°C ≤ TA ≤+125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001
D001A VDD Supply Voltage 4.0
4.5
VBOR*
-
-
-
5.5
5.5
5.5
V
V
V
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
D002* VDR RAM Data Retention
Voltage (Note 1) -1.5-V
D003 VPOR VDD Start Voltage to
ens ure internal
Power-on Reset signal
-VSS - V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to
ens ure internal
Power-on Reset signal
0.05
TBD -
--
-V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Brown-out Reset
voltage trip point 3.65 - 4.35 V BODEN bit se t
D010
D013
IDD Supply Current
(Not e 2, 5) -
-
2.7
10
5
20
mA
mA
XT, RC osc modes
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc mode
FOSC = 20 MHz, VDD = 5.5V
D020
D021
D021B
IPD Power-down Current
(Not e 3, 5) -
-
-
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled, 0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
D022*
D022A* ∆IWDT
∆IBOR
Module Differential
Current (Note 6)
Watchdog Timer
Brown-out Reset -
-6.0
TBD 20
200 µA
µAWDTE BIT SET, VDD = 4. 0V
BODEN bit set, VDD = 5.0V
* These parameters are characterized but not te sted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly curre nt is ma inly a fu nction of the ope ratin g v olta ge and freq uency. Other f acto rs suc h as I/O p in
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: F or RC osc mode , current thr ough Re xt i s not inc luded. Th e current throug h the re sistor ca n be esti mated b y
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 os cillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will
perform a brown-out reset when VDD falls below VBOR.
1998 Microchip Technology Inc. Preliminary DS35008B-page 85
PIC16C62B/72A
13.2 DC Characteristics: PIC16LC62B/72A-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤+70°C for commercial
-40°C ≤ TA ≤+85°C for industr ial
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001 VDD Supply Voltage 2.5
VBOR*-
-5.5
5.5 V
VLP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
D002* VDR RAM Data Retention
Voltage (Note 1) -1.5-V
D003 VPOR VDD Start Voltage to
ens ure internal
Power-on Reset signal
-VSS - V See section on Power-on Reset for details
D004*
D004A* SVDD VDD Rise Rate to
ens ure internal
Power-on Reset signal
0.05
TBD -
--
-V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
D005 VBOR Brown-out Reset
voltage trip point 3.65 - 4.35 V BODEN bit se t
D010
D010A
IDD Supply Current
(Not e 2, 5) -
-
2.0
22.5
3.8
48
mA
µA
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP OSC MODE
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
IPD Power-down Current
(Not e 3, 5) -
-
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D022*
D022A* ∆IWDT
∆IBOR
Module Differential
Current (Note 6)
Watchdog Timer
Brown-out Reset -
-6.0
TBD 20
200 µA
µAWDTE BIT SET, VDD = 4. 0V
BODEN bit set, VDD = 5.0V
* These parameters are characterized but not te sted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supp ly curre nt is ma inly a fu nction of the ope ratin g v olta ge and freq uency. Other f acto rs suc h as I/O p in
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: F or RC osc mode , current thr ough Re xt i s not inc luded. Th e current throug h the re sistor ca n be esti mated b y
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 os cillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will
perform a brown-out reset when VDD falls below VBOR.
PIC16C62B/72A
DS35008B-page 86 Preliminary 1998 Microchip Technology Inc.
13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended)
PIC16C62B/72A-20 (Commercial, Industrial, Extended)
PIC16LC62B/72A-04 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Oper ati ng tem per a t ure 0°C ≤ TA ≤+70°C for commercial
-40°C ≤ TA ≤+85°C for industrial
-40°C ≤ TA ≤+125°C for extended
Oper ati ng voltage VDD range as described in DC spec Sectio n 13.1
and Sectio n 13.2
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Input Low Voltage
VIL I/O ports
D030
D030A with TTL buffer VSS
Vss -
-0.15VDD
0.8V V
VFor entire VDD range
4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS -0.2VDD V
D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V
D033 OSC1 (in XT, HS and LP
modes) Vss - 0.3VDD V Note1
Input High Voltage
VIH I/O ports -
D040 with TTL buffer 2.0 - VDD V4.5V ≤ VDD ≤ 5.5V
D040A 0.25VD
D + 0.8V - Vdd V For entire VDD range
D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range
D042 MCLR 0.8VDD -VDD V
D042A OSC1 (XT, HS and LP modes) 0.7VDD -VDD V Note1
D043 OSC1 (in RC mo de) 0.9VDD -VddV
Input Leakage Current
(Notes 2, 3)
D060 IIL I/O ports - - ±1µAVss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061 MCLR, RA4/T0CKI - - ±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 - - ±5µAVss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
D070 IPURB PORTB weak pull-up current 50 250 400 µAVDD = 5V, VPIN = VSS
Output Low Voltage
D080 VOL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
* These parameters are characterized but not te sted.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
device be driven w ith external clo ck in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
1998 Microchip Technology Inc. Preliminary DS35008B-page 87
PIC16C62B/72A
--0.6VIOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKOUT
(RC osc mode) --0.6VI
OL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
--0.6VI
OL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
Output High Voltage
D090 VOH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/C LKOUT (RC osc
mode) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150* VOD Op en-Drain High Voltage - - 8.5 V RA4 pin
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101 CIO All I/O pins and OSC2 (in RC
mode) --50pF
D102 Cb SCL, SDA in I2C mode - - 400 pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Oper ati ng tem per a t ure 0°C ≤ TA ≤+70°C for commercial
-40°C ≤ TA ≤+85°C for industrial
-40°C ≤ TA ≤+125°C for extended
Oper ati ng voltage VDD range as described in DC spec Sectio n 13.1
and Sectio n 13.2
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These parameters are characterized but not te sted.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
device be driven w ith external clo ck in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
PIC16C62B/72A
DS35008B-page 88 Preliminary 1998 Microchip Technology Inc.
13.4 AC (Timing) Characteristics
13.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TFFrequency TTime
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Da ta in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and t heir meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output acce ss High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
1998 Microchip Technology Inc. Preliminary DS35008B-page 89
PIC16C62B/72A
13.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 13-1
apply to all timing specifications unless otherwise
noted. Figure 13-4 specifies the load conditions for the
timing specification s .
TABLE 13-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
FIGURE 13-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS Standard Operating Conditions (unl ess otherwise stated)
Operating temperature 0°C ≤ TA ≤+70°C for commercial
-40°C ≤ TA ≤+85°C for industr ial
-40°C ≤ TA ≤+125°C for extended
Opera ting v oltag e VDD range as described in DC sp ec Se ction 13.1 and Sectio n 13.2.
LC parts operate for commercial/industrial temp’s only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464Ω
CL= 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
Load condition 1 Load condition 2
PIC16C62B/72A
DS35008B-page 90 Preliminary 1998 Microchip Technology Inc.
13.4.3 TIMING DIAGRAMS AND SP ECIFICATIONS
FIGURE 13-5: EXTERNAL CLOCK TIMING
TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
1A Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz RC and XT osc modes
DC — 4 MHz HS osc mode (-04)
DC — 20 MHz HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscilla tor Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4 — 20 MHz HS osc mode
5 — 200 kHz LP osc mode
1Tosc External CLKIN Period
(Note 1) 250 — — ns RC and XT osc modes
250 — — ns HS osc mode (-04)
50 — — ns HS osc mode (-20)
5— —µsLP osc mode
Oscilla tor Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
50 — 250 ns HS osc mode (-20)
5— —µsLP osc mode
2TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC
3* TosL,
TosH Extern al Cl ock in (OSC1) High
or Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4* TosR,
TosF External Clock in (OSC1) Rise
or Fall Time — — 25 ns XT oscil la tor
— — 50 ns LP oscillator
— — 15 ns HS oscill ator
* These parameters are characterized but not te sted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruct ion cycl e period ( TCY) equal s f our ti mes t he inpu t osci llator ti me-ba se period. Al l spec ified v alues are
based o n charac terization da ta f or that particular osc illator type u nder st andard ope rating cond itions w ith the
de vic e e xecutin g code . Ex ceeding the se sp ecified l imits ma y resul t in an unsta b le osc illat or oper at ion an d/or
higher th an e xpected c urrent consum ption. All dev ices are t ested to ope rate at "m in." v alues with an e xternal
clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
3
344
1
2
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKOUT
1998 Microchip Technology Inc. Preliminary DS35008B-page 91
PIC16C62B/72A
FIGURE 13-6: CLKOUT AND I/O TIMING
TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT r ise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* Tc kL 2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in val id before CLKOUT ↑ Tosc + 200 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0——nsNote 1
17* TosH2ioV OSC1↑ (Q1 cycle) to Port out va lid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to Por t
input invalid (I/O in hold
time)
PIC16CXX 100 — — ns
18A* PIC16LCXX 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in set up tim e) 0 — — ns
20* TioR Po rt output rise time PIC16CXX —1040 ns
20A* PIC16LCXX — — 80 ns
21* TioF Port output fall time PIC16CXX —1040 ns
21A* PIC16LCXX — — 80 ns
22††* Tinp INT pin high or low ti me TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* T hese parameters are characte rized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 13-4 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
old value new value
PIC16C62B/72A
DS35008B-page 92 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 13-8: BROWN-OUT RESET TIMING
TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, P OWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TmcL MCLR Pulse Width (lo w ) 2 ——µsVDD = 5V, -40°C to +125°C
31* Twdt Watc hdog Time r Time -out Period
(No Prescaler) 71833msVDD = 5V, -40°C to +125°C
32 Tost Oscillator Start-up Timer Period — 1024
TOSC ——TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C
34 TIOZ I/O Hi-impedance from MCLR
Low or WDT reset ——2.1µs
35 TBOR Brown-out Reset Pulse Width 100 — — µsVDD ≤ BVDD (D005)
* T hese parameters are characte rized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 13-4 for load conditions.
VDD BVDD
35
1998 Microchip Technology Inc. Preliminary DS35008B-page 93
PIC16C62B/72A
FIGURE 13-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 13-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4,..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16CXX 15 — — ns
PIC16LCXX 25 — — ns
Asynchronous PIC16CXX 30 — — ns
PIC16LCXX 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16CXX 15 — — ns
PIC16LCXX 25 — — ns
Asynchronous PIC16CXX 30 — — ns
PIC16LCXX 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16CXX GREATER OF:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LCXX GREATER OF:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16CXX 60 — — ns
PIC16LCXX 100 — — ns
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz
48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note: Refer to Figure 13-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 or
TMR1
PIC16C62B/72A
DS35008B-page 94 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-10: CAPTURE/COMPARE/PWM TIMINGS
TABLE 13-6: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 input low
time No Prescaler 0.5TCY + 20 ——ns
With Prescaler PIC16CXX 10 — — ns
PIC16LCXX 20 — — ns
51* TccH CCP1 input high
time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16CXX 10 — — ns
PIC16LCXX 20 — — ns
52* TccP CCP1 input period 3TCY + 40
N— — ns N = prescale
v alue (1,4, or 16)
53* TccR CCP1 output rise time PIC16CXX —1025ns
PIC16LCXX —2545ns
54* TccF CCP1 output fall time PIC16CXX —1025ns
PIC16LCXX —2545ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 13-4 for load conditions.
CCP1
(Capture Mode)
50 51
52
CCP1
53 54
(Compare or PWM Mode)
1998 Microchip Technology Inc. Preliminary DS35008B-page 95
PIC16C62B/72A
FIGURE 13-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 13-7: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 — — ns
71A Single Byte 40 — — ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 — — ns
72A Single Byte 40 — — ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 — — ns Note 1
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75 TdoR SDO data output rise time PIC16CXX —1025ns
PIC16LCXX —2045ns
76 TdoF SDO data output fall time — 10 25 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX —1025ns
PIC16LCXX —2045ns
79 TscF SCK output fall time (maste r mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data ou tput valid
after SCK edge PIC16CXX ——50ns
PIC16LCXX — — 100 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 13-4 for load conditions.
PIC16C62B/72A
DS35008B-page 96 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 13-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 ——ns
71A Single Byte 40 — — ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 — — ns
72A Single Byte 40 — — ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK
edge 100 — — ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 40 — — ns Note 1
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75 TdoR SDO data output rise
time PIC16CXX —1025ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fall time — 10 25 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX —1025ns
PIC16LCXX 20 45 ns
79 TscF SCK output fall time (master mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid
after SCK edge PIC16CXX — — 50 ns
PIC16LCXX — 100 ns
81 TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY ——ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 13-4 for load conditions.
1998 Microchip Technology Inc. Preliminary DS35008B-page 97
PIC16C62B/72A
FIGURE 13-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 13-9: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 — — ns
71A Single Byte 40 — — ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 — — ns
72A Single Byte 40 — — ns Note 1
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns
73A TB2BLast clock edge of Byte1 to the 1st clock
edge of Byte2 1.5TCY + 4 0 — — ns Note 1
74 TscH 2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — — ns
75 TdoR SDO data output rise time PIC16CXX —1025ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fall time — 10 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX —1025ns
PIC16LCXX 20 45 ns
79 TscF SCK output fall time (maste r mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data ou tput valid
after SCK edge PIC16CXX ——50ns
PIC16LCXX — 100 ns
83 TscH2ssH,
TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT6 - - - -1 LSb IN
83
Note: Refer to Figure 13-4 for load conditions.
PIC16C62B/72A
DS35008B-page 98 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
No. Symbol Characteristic Min Typ† Max Units Conditions
70 TssL2scH,
TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns
71 TscH SCK input high time
(slave mode) Continuous 1.25TCY + 30 — — ns
71A Single Byte 40 — — ns Note 1
72 TscL SCK input low time
(slave mode) Continuous 1.25TCY + 30 — — ns
72A Single Byte 40 — — ns Note 1
73A TB2BLast cloc k edge of Byte 1 to the 1st cl oc k
edge of Byte2 1.5TCY + 40 — — ns Note 1
74 TscH 2diL,
TscL2diL Hold time of SD I dat a inp ut to SCK edge 100 — — ns
75 TdoR SDO data output rise
time PIC16CXX —1025ns
PIC16LCXX 20 45 ns
76 TdoF SDO data output fall time — 10 25 ns
77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns
78 TscR SCK output rise time
(master mo de) PIC16CXX —1025ns
PIC16LCXX —2045ns
79 TscF SCK output fall time (master mode) — 10 25 ns
80 TscH2doV,
TscL2doV SDO data output valid
after SCK edge PIC16CXX ——50ns
PIC16LCXX ——100ns
82 TssL2doV SDO data output valid
after SS↓ edge PIC16CXX ——50ns
PIC16LCXX ——100ns
83 TscH2ssH,
TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BIT6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
NOTE: Refer to Figure 13-4 for load conditions.
1998 Microchip Technology Inc. Preliminary DS35008B-page 99
PIC16C62B/72A
FIGURE 13-15 : I2C BUS START/STOP BITS TIMING
TABLE 13-11: I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No. Sym Characteristic Min Ty
pMax Unit
sConditions
90* TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for repeated
START condition
Setup time 400 kHz mode 600 — —
91* THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92* TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are characterized but not tested.
Note: Refer to Figure 13-4 for load conditions.
91
92
93
SCL
SDA
START
Condition STOP
Condition
90
PIC16C62B/72A
DS35008B-page 100 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-16 : I2C BUS DATA TIMING
TABLE 13-12: I2C BUS DATA REQUIREMENTS
Param.
No. Sym Characteristic Min Max Units Conditions
100* THIGH Clock high time 100 kHz mode 4.0 —µs Device must operate at a min-
imum of 1.5 MHz
400 kHz mode 0.6 — µs Device must operate at a min-
imum of 10 MHz
SSP Module 1.5TCY —
101* TLOW Clock low time 100 kHz mode 4.7 — µs Device must operate at a min-
imum of 1.5 MHz
400 kHz mode 1.3 — µs Device must operate at a min-
imum of 10 MHz
SSP Module 1.5TCY —
102* TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10-400 pF
103* TFSDA and SCL fall
time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from
10-400 pF
90* TSU:STA START condition
setup time 100 kHz mode 4.7 — µs Only rele vant for repeated
STA RT condition
400 kHz mode 0.6 — µs
91* THD:STA START condition hold
time 100 kHz mode 4. 0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92* TSU:STO ST OP condition setup
time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109* TAA Output valid from
clock 100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110* TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — µs
Cb Bus capacitive loading — 400 pF
* These parameters are characterized bu t not tested.
Note 1: As a transmitter, the devi ce must provide this internal minimum delay time to bridge the undefined reg i on (min. 300 ns) of the fall-
ing edge of SCL to avoid unintende d generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode ( 100 kHz) I2C-b us syst em, b ut the require ment Tsu: DAT ≥
250 ns must then be met . This will aut omatically be the case if the device does not stretch the LO W period of the SCL signal. If
such a device does stret ch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR
max.+t su;DAT = 1000 + 250 = 1250 ns (according to the standard - mode I2C bus specification) before the SCL line is released.
Note: Refer to Figure 13-4 for load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
1998 Microchip Technology Inc. Preliminary DS35008B-page 101
PIC16C62B/72A
TABLE 13-13: A/D CONVERTER CHARACTERISTICS:
PIC16C72A-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C72A-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC72A-04 (COMMERCIAL, INDUSTRIAL)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error — — < ± 1 LSB VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03 EIL Integral linearity error — — < ± 1 LSB VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04 EDL Differential linearity error — — < ± 1 LSB VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05 EFS Full scale error — — < ± 1 LSB VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error — — < ± 1 LSB VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10 — Monotonicity — guaranteed
(Note 3) ——VSS ≤ VAIN ≤ VREF
A20 VREF Reference vol tag e 2.5V — VDD + 0.3 V
A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V
A30 ZAIN Recommended impedance of
analog voltage source ——10.0kΩ
A40 IAD A/D conversion
current (VDD)PIC16CXX —180 —µA Average current con-
sumption when A/D is
on. (Note 1)
PIC16LCXX —90 —µA
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
µA
µA
During VAIN acquisi-
tion. Based on differ-
ential of VHOLD to
VAIN to charge
CHOLD, see
Section 9.1.
During A/D conver-
sion cycle
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: When A/D is off, it will not cons ume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the Input Voltage and has no missing codes.
PIC16C62B/72A
DS35008B-page 102 Preliminary 1998 Microchip Technology Inc.
FIGURE 13-17: A/D CONVERSION TIMING
TABLE 13-14: A/D CONVERSION REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Unit
sConditions
130 TAD A/D clock period PIC16CXX 1.6 ——µsTOSC based, VREF ≥ 3.0V
PIC16LCXX 2.0 — — µsTOSC based, VREF full range
PIC16CXX 2.0 4.0 6.0 µsA/D RC Mode
PIC16LCXX 3.0 6.0 9.0 µsA/D RC Mode
131 TCNV Conversion time (not including S/H
time) (Note 1) 11 — 11 TAD
132 TACQ Acquisition time Note 2
5*
20
—
—
—
µs
µs The minimum time is th e
amplifier settling time. Th is
ma y be used if the " ne w" i nput
voltage has not changed by
more than 1 LSb (i.e., 20.0 mV
@ 5.12V) from the last sam-
pled voltage (as stated on
CHOLD).
134 TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 Tswc Switching from convert → sample
time 1.5 — — TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 for min conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLIN G STOPPED
DONE
NEW_DATA
(Tosc/ 2) (1)
7 6543210
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
1 TCY
134
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 103
14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a st atistical summary of data collected on units from different lots over a period
of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’ represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
Data is not av a ilab le at thi s time bu t yo u ma y ref e rence the
PIC16C72 Series Data Sh eet
(DS39016,) DC and AC char-
acteristic section, which contains data similar to what is expected.
PIC16C62B/72A
DS35008B-page 104 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 105
15.0 P ACKAGING INF ORMATIO N
15.1 Package Marking Information
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
AABBCDE
MMMMMMMMMMMMMMMM
Example
PIC16C62B-20/SO
XXXXXXXXXXXXXXX
AABBCDE
28-Lead PDIP (Skinny DIP)
MMMMMMMMMMMM
Example
PIC16C72A-04/SP
Example28-Lead CERD IP Wi ndowed
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C72A/JW
AABBCDE
XXXXXXXXXXXX
XXXXXXXXXXXX
28-Lead SSOP
20I/SS025
PIC16C62B
Example
9917HAT
9917CAT
9910/SAA
9917SBP
XXXXXXXXXXX
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA Year code (last 2 digits of cale ndar year)
BB Week code (week of January 1 is week ‘01’)
C Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D Mask revision number
E Assembly code of the plant or country of origin in which
part was assembled
Note: In the e v ent the ful l Micro chip pa rt num ber canno t be mark ed on one li ne , it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, cer tain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
PIC16C62B/72A
DS35008B-page 106 Preliminary 1999 Microchip Technology Inc.
15.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thi ckness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 8.517.807.09.335.307.279E1Molded Package Width 8.267.947.62.325.313.300EShoulder to S houlder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded P a ckage Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 107
15.3 28-Lea d Ceramic Dual In-line wi th Window (JW) – 300 mil (CERDIP)
3.30 3.56 3.81
7.877.627.37.310.300.290W2Win dow Length .150.140.130W1Window Width 10.809.788.76.425.385.345
eB
Overall Row Spacing 0.530.470.41.021.019.016BLower Lead Width 1.651.461.27.065.058.050B1Upper Lead Width 0.300.250.20.012.010.008
c
Lead Thickness 3.683.563.43.145.140.135LTip to Seating Plane 37.7237.0236.321.4851.4581.430DOvera ll Len gth 7.497.377.24.295.290.285E1Ceramic Pkg. Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.760.570.38.030.023.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 4.954.644.32.195.183.170ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERSINCHES*Units
2
1
D
n
W2
W1
E1
E
eB p
A2
L
B1
B
A1
A
*Controlling Para meter
c
JEDEC Equivalent: MO-058
Drawing No. C04-080
PIC16C62B/72A
DS35008B-page 108 Preliminary 1999 Microchip Technology Inc.
15.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
F oot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Wi dth 10.6710.3410.01.420.407.394EOvera ll Width 0.300.200.10.012.008.004A1Standoff 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
*Controlling Parameter
Notes:
Dimensions D and E1 do not i nclude mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 109
15.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
10501050Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840
φ
F oot Angle 0.250.180.10.010.007.004
c
Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOverall Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.66.026
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
β
c
φ
α
A2
A1
A
β
PIC16C62B/72A
DS35008B-page 110 Preliminary 1999 Microchip Technology Inc.
NOTES:
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 111
APPENDIX A: REVISION HISTORY
APPENDIX B: CONVERSION
CONSIDERATIONS
Consi derations for co nv erting from pre viou s versio ns of
de vices to the ones li sted in thi s data shee t are listed in
Table B-1.
Version Date Revision Description
A 7/98 This is a new data sheet. However, the devices described in this data sheet are the upgrades to
the device s found in the
PIC16C6X Data Sheet
, DS30234, and the
PIC16C7X Data Shee t
,
DS30390.
TABLE B-1: CONVERSION CONSIDERATIONS
Difference PIC16C62A/72 PIC16C62B/72A
Voltage Range 2.5V - 6.0V 2.5V - 5.5V
SSP module Basic SSP (2 mode SPI) SSP (4 mode SPI)
CCP module CCP does not reset TMR1 when in special
event trigger mode. N/A
Timer1 module Writing to TMR1L register can cause over-
flow in TMR1H register. N/A
PIC16C62B/72A
DS35008B-page 112 Preliminary 1999 Microchip Technology Inc.
APPENDIX C: MIGRATION FROM
BASE-LINE TO
MID-RANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a mid-range device (i.e.,
PIC16CXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K no w as opposed t o 512 bef ore) and
register file (128 bytes now versus 32 bytes
before).
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5 X.
5. OPTION_REG and TRIS registers are made
addressable.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (a nd wake-up) types are recogni z e d. Re g-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers a re inv oke d selectiv ely to a v oid unneces sary
delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change feature .
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In- circuit serial prog rammi ng” is m ade poss ible .
The user ca n progr am PIC16CXX devices using
only five pins: VDD, VSS, M CLR/VPP, RB6 (clock)
and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
18. Brown-out protection circuitr y has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed set-
point.
To convert code written for PIC16C5X to PIC16CXXX,
the user should take the following steps:
1. Remove any program memory page select
operat ion s (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them .
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 113
INDEX
A
A/D .....................................................................................49
A/D Converter Enable (ADIE Bit) ...............................14
A/D Converter Flag (ADIF Bit) ............................ 15, 51
A/D Converter Interrupt, Configuring .........................51
ADCON0 Register ................................................ 9, 49
ADCON1 Register ........................................10, 49, 50
ADRES Register .............................................9, 49, 51
Analog Port Pins ..........................................................6
Analog Port Pins, Configuring ...................................53
Block Diagram ...........................................................51
Block Diagram, Analog Input Model ..........................52
Channel Select (CHS2:CHS0 Bits) ............................49
Clock Select (ADCS1:ADCS0 Bits) ...........................49
Configuring the Module .............................................51
Conversion Clock (TAD) .............................................53
Conversion Status (GO/DONE Bit) ..................... 49, 51
Conversions ...............................................................54
Converter Characteristics ........................................101
Module On/Off (ADON Bit) ........................................49
Port Configuration Control (PCFG2:PCFG0 Bits) ......50
Sampling Requirements ............................................52
Special Event Trigger (CCP) .............................. 35, 54
Timing Diagram .......................................................102
Absolute Maximum Ratings ...............................................81
ADCON0 Register ........................................................ 9, 49
ADCS1:ADCS0 Bits ...................................................49
ADON Bit ...................................................................49
CHS2:CHS0 Bits .......................................................49
GO/DONE Bit ..................................................... 49, 51
ADCON1 Register ................................................10, 49, 50
PCFG2:PCFG0 Bi ts ...................................................50
ADRES Register .....................................................9, 49, 51
Architecture
PIC16C62B/PIC16C72A Block Diagram .....................5
Assembler
MPASM Ass e mbler ...................................................75
B
Banking, Data Memory ................................................. 8, 11
Brown-out Reset (BOR) .......................... 55, 57, 59, 60, 61
BOR Enable (BODEN Bit) .........................................55
BOR Status (BO R Bit) ...............................................16
Timing Diagram .........................................................92
C
Capture (CCP Module) ......................................................34
Block Diagram ...........................................................34
CCP Pin Configuration ..............................................34
CCPR1H:CCPR1L Registers ....................................34
Changing Between Capture Prescalers ....................34
Software Interrupt ......................................................34
Timer1 Mode Selection ..............................................34
Capture/Compare/PWM
Interaction of Two CCP Modules ...............................33
Capture/Compare/PWM (CCP) .........................................33
CCP1CON Register .............................................. 9, 33
CCPR1H Register ................................................ 9, 33
CCPR1L Register ................................................. 9, 33
Enable (CCP1IE Bit) ..................................................14
Flag (CCP1IF Bit) ......................................................15
RC2/CCP1 Pin .............................................................6
Timer Resources .......................................................33
Timing Diagram .........................................................94
CCP1CON Register .......................................................... 33
CCP1M3:CCP1M0 Bits ............................................. 33
CCP1X:CCP1Y Bits .................................................. 33
Code Protection ...........................................................55, 66
CP1:CP0 Bits ............................................................ 55
Compare (CCP Module) .................................................... 35
Block Diagram ........................................................... 35
CCP Pin Configuration .............................................. 35
CCPR1H:CCPR1L Registers .................................... 35
Softwar e In terrupt ...................................................... 35
Special Event Trigger ...................................29, 35, 54
Timer1 Mode Selection ............................................. 35
Configuration Bits .............................................................. 55
Conversion Considerations ............................................. 111
D
Data Memory ....................................................................... 8
Ban k Select (R P1:R P0 Bit s) ..................................8, 11
General Purpose Registers ......................................... 8
Register File Map ........................................................ 8
Special Function Registers ......................................... 9
DC Characteristics ......................................................84, 86
Development Support ........................................................ 75
Direct Addressing .............................................................. 18
E
Electrical Characteristics ................................................... 81
Errata ................................................................................... 3
External Power-on Reset Circuit ....................................... 59
F
Firmware Instructions ........................................................ 67
I
I/O Por ts ............................................................................ 19
I2C (SSP Module) .............................................................. 41
ACK Pulse .......................................41, 42, 43, 44, 45
Addressing ................................................................ 42
Block Diagram ........................................................... 41
Buffer Full Status (BF Bit) ......................................... 46
Clock Polarity Select (CKP Bit) ................................. 47
Data/Address (D/A Bit) .............................................. 46
Master Mode ............................................................. 45
Mode Selec t (SS PM 3 :S SPM0 Bits) .......................... 47
Multi-Master Mode .................................................... 45
Read/Write Bit Information (R/W Bit) .... 42, 43, 44, 46
Receive Overflow Indicator (SSPOV Bit) .................. 47
Reception .................................................................. 43
Reception Timing Diagram ........................................ 43
Slave Mode ............................................................... 41
Start (S Bit) ..........................................................45, 46
Stop (P Bit) ..........................................................45, 46
Synchronous Serial Port Enable (SSPEN Bit) .......... 47
Timing Diagram, Data ............................................. 100
Timing Diagram, Start/Stop Bits ................................ 99
Transmission ............................................................. 44
Update Address (UA Bit) ........................................... 46
ID Locations ................................................................55, 66
In-Circuit Serial Programming (ICSP) .........................55, 66
Indirect Addressing ............................................................ 18
FSR Register ....................................................8, 9, 18
INDF Register ............................................................. 9
Instruction Format ............................................................. 67
PIC16C62B/72A
DS35008B-page 114 Preliminary 1999 Microchip Technology Inc.
Instruction Set ....................................................................67
ADDLW ......................................................................69
ADDWF ......................................................................69
ANDLW ......................................................................69
ANDWF ......................................................................69
BCF ............................................................................69
BSF ............................................................................69
BTFSC .......................................................................70
BTFSS .......................................................................70
CALL ..........................................................................70
CLRF .........................................................................70
CLRW .........................................................................70
CLRWDT ...................................................................70
COMF ........................................................................71
DECF .........................................................................71
DECFSZ ....................................................................71
GOTO ........................................................................71
INCF ..........................................................................71
INCFSZ ......................................................................71
IORLW .......................................................................72
IORWF .......................................................................72
MOVF ........................................................................72
MOVLW .....................................................................72
MOVWF .....................................................................72
NOP ...........................................................................72
RETFIE ......................................................................73
RETLW ......................................................................73
RETURN ....................................................................73
RLF ............................................................................73
RRF ...........................................................................73
SLEEP .......................................................................73
SUBLW ......................................................................74
SUBWF ......................................................................74
SWAPF ......................................................................74
XORLW ......................................................................74
XORWF .....................................................................74
Summary Table .........................................................68
INTCON Register .......................................................... 9, 13
GIE Bit .......................................................................13
INTE Bit .....................................................................13
INTF Bit ......................................................................13
PEIE Bit .....................................................................13
RBIE Bit .....................................................................13
RBIF Bit .............................................................. 13, 21
T0IE Bit ......................................................................13
T0IF Bit ......................................................................13
Interrupt Sources ........................................................ 55, 62
A/D Conversion Complete .........................................51
Block Diagram ...........................................................62
Capture Complete (CCP) ...........................................34
Compare Complete (CCP) .........................................35
Interrupt on Change (RB7:RB4 ) ...............................21
RB0/INT Pin, External ........................................... 6, 63
SSP Receive/Transmit Complete ..............................39
TMR0 Overflow ................................................... 26, 63
TMR1 Overflow ................................................... 27, 29
TMR2 to PR2 Match ..................................................32
TMR2 to PR2 Match (PWM) ............................... 31, 36
Interrupts, Context Saving During ......................................63
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit) ...............................14
CCP1 Enable (CCP1IE Bit) .......................................14
Global Interrupt Enable (GIE Bit) ........................ 13, 62
Interrupt on Change (RB7:RB4)
Enable (RBIE Bit) ................................................ 13, 63
Peripheral Interrupt Enable (PEIE Bit) .......................13
RB0/INT Enable (INTE Bit) ........................................ 13
SSP Enable (SSPIE Bit) ............................................ 14
TMR0 Overflow Enable (T0IE Bit) ............................. 13
TMR1 Overflow Enable (TMR1IE Bit) ....................... 14
TMR2 to PR2 Match Enable (TMR2IE Bit ) ................ 14
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) .............................15, 51
CCP1 Flag (CCP1IF Bit) ..............................15, 34, 35
Interrupt on Change (RB7:RB4)
Flag (RBIF Bit) ..............................................13, 21, 63
RB0/INT Flag (INTF Bit) ............................................ 13
SSP Flag (SS PI F Bit) ................................................ 15
TMR0 Overflow Flag (T0IF Bit) ...........................13, 63
TMR1 Overflow Flag (TMR1IF Bit) ............................ 15
TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 15
K
KeeLoq Evaluation and Programmi ng Tools .................. 78
M
Master Clear (MCLR) .......................................................... 6
MCLR Reset, Normal Operation ..................57, 60, 61
MCLR Reset, SLEEP ...................................57, 60, 61
Memory Organization
Data Memory ............................................................... 8
Program Mem ory ......................................................... 7
MPLAB Integrated Development Environment Software .. 75
O
OPCODE Field Descriptions ............................................. 67
OPTION_REG Register ..............................................10, 12
INTEDG Bit ................................................................ 12
PS2:PS0 Bits .......................................................12, 25
PSA Bit ................................................................12, 25
RBPU Bit ................................................................... 12
T0CS Bit ..............................................................12, 25
T0SE Bit ..............................................................12, 25
OSC1/CLKIN Pin ................................................................. 6
OSC2/CLKOUT Pin.............................................................. 6
Oscillator Configuration ...............................................55, 56
HS .......................................................................56, 60
LP ........................................................................56, 60
RC ..................................................................6, 57, 60
Selection (FOSC1:FOSC0 Bits).................................. 55
XT ........................................................................56, 60
Oscillator, Timer1 ........................................................27, 29
Oscillator, WDT ................................................................. 64
P
Packaging ........................................................................ 105
Paging, Program Memory .............................................7, 17
PCON Register ............................................................16, 60
BOR Bit ..................................................................... 16
POR Bit ..................................................................... 16
PICDEM-1 Low-Cost PICmicro Demo Board .................... 77
PICDEM-2 Low-Cost PIC16CXX Demo Board ................. 77
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 77
PICSTART Plus Entry Level Development System ........ 77
PIE1 Register ..............................................................10, 14
ADIE Bit ..................................................................... 14
CCP1IE Bit ................................................................ 14
SSPIE Bit ................................................................... 14
TMR1IE Bit ................................................................ 14
TMR2IE Bit ................................................................ 14
Pinout Descriptions
PIC16C62B/PIC16C72A ............................................. 6
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 115
PIR1 Register ............................................................... 9, 15
ADIF Bit .....................................................................15
CCP1IF Bit .................................................................15
SSPIF Bi t ...................................................................15
TMR1IF Bit ................................................................15
TMR2IF Bit ................................................................15
Pointer, FSR ......................................................................18
PORTA ................................................................................6
Analog Port Pins ..........................................................6
PORTA Register ................................................... 9, 19
RA3:RA0 and RA5 Port Pins .....................................19
RA4/T0CKI Pin ..................................................... 6, 19
RA5/SS/AN4 Pin ................................................... 6, 39
TRISA Register ................................................... 10, 19
PORTB ................................................................................6
PORTB Register ................................................... 9, 21
Pull-up Enable (RBPU Bit) .........................................12
RB0/INT Edge Select (INTEDG Bit) ..........................12
RB0/INT Pin, External .......................................... 6, 63
RB3:RB0 Port Pins ....................................................21
RB7:RB4 Interrupt on Change ...................................63
RB7:RB4 Interrupt on Change
Enable (RBIE Bit) ............................................... 13, 63
RB7:RB4 Interrupt on Change
Fla g (RBIF Bit) ..............................................13, 21, 63
RB7:RB4 Port Pins ....................................................21
TRISB Register ................................................... 10, 21
PORTC ................................................................................6
Block Diagram ...........................................................23
PORTC Register ................................................... 9, 23
RC0/T1OSO/T1CKI Pin ...............................................6
RC1/T1OSI Pin ............................................................6
RC2/CCP1 Pin .............................................................6
RC3/SCK/SCL Pin ................................................ 6, 39
RC4/SDI/SDA Pin ................................................. 6, 39
RC5/SDO Pin ....................................................... 6, 39
RC6 Pin .......................................................................6
RC7 Pin .......................................................................6
TRISC Register .................................................. 10, 23
Postscaler, Timer2
Select (T OUTPS3:TOUTPS0 Bits) ............................31
Postscaler, WDT ................................................................25
Assignment (PSA Bit) ......................................... 12, 25
Block Diagram ...........................................................26
Rate Select (PS2:PS0 Bits) ................................ 12, 25
Switching Between Timer0 and WDT ........................26
Power-on Reset (POR) ........................... 55, 57, 59, 60, 61
Oscillator Start-up Timer (OST) .......................... 55, 59
POR Status (PO R Bit) ...............................................16
Power Control (PCON) Register ................................60
Power-down (PD Bit) .......................................... 11, 57
Power-on Reset Circuit, External ..............................59
Pow e r-up Timer (PWRT) .................................... 55, 59
PWRT Enable (PWRTE Bit) ......................................55
Time-out (TO Bit) ................................................ 11, 57
Time-out Sequence ...................................................60
Timing Diagram .........................................................92
Prescaler, Capture .............................................................34
Prescaler, Timer0 ..............................................................25
Assignment (PSA Bit) ......................................... 12, 25
Block Diagram ...........................................................26
Rate Select (PS2:PS0 Bits) ................................ 12, 25
Switching Between Timer0 and WDT ........................26
Prescaler, Timer1 ..............................................................28
Select (T1CKPS1:T1CKPS0 Bits)......................... ......27
Prescaler, Timer2 .............................................................. 36
Select (T2 C KP S1: T2CKPS0 Bits) ............................. 31
PRO MA TE II Universal Programmer ............................. 77
Program Counter
PCL Register .........................................................9, 17
PCLATH Register ...........................................9, 17, 63
Reset Conditions ....................................................... 60
Program Mem ory ................................................................. 7
Interrupt Vector ........................................................... 7
Paging ...................................................................7, 17
Program Memory Map ................................................ 7
Reset Vector ............................................................... 7
Program Ver ification .......................................................... 66
Programming Pin (Vpp) ....................................................... 6
Programm ing, Device Ins tr uctions .................................... 67
PWM (CCP Module) .......................................................... 36
Block Diagram ........................................................... 36
CCPR1H:CCPR1L Registers .................................... 36
Duty Cycle ................................................................. 36
Example Frequencies/Resolution s ............................ 37
Output Diagram ......................................................... 36
Period ........................................................................ 36
Set-Up for PWM Operation ....................................... 37
TMR2 to PR 2 M atch ............................................31, 36
TMR2 to PR2 Match Enable (TMR2IE Bit ) ................ 14
TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 15
Q
Q-Clock ............................................................................. 36
R
Register File ........................................................................ 8
Register File Map ................................................................ 8
Reset ...........................................................................55, 57
Block Diagram ........................................................... 58
Reset Conditions for All Registers ............................ 61
Reset Conditions for PCON Register ........................ 60
Reset Conditions for Program Counter ..................... 60
Reset Conditions for STATUS Register .................... 60
Timing Diagram ......................................................... 92
Revision History .............................................................. 111
S
SEEVAL Evaluation and Programming System ............. 78
SLEEP ..................................................................55, 57, 65
Software Simulator (MPLAB-SIM) ..................................... 76
Special Features of the CPU ............................................. 55
Special Function Registers .................................................. 9
Speed, Operating ................................................................ 1
SPI (SSP Module)
Block Diagram ........................................................... 39
Buffer Full Status (BF Bit) ......................................... 46
Clock Edge Select (CKE Bit) ..................................... 46
Clock Polarity Select (CKP Bit) ................................. 47
Data Input Sample Phase (SMP Bit) ......................... 46
Mode Selec t (SS PM 3 :S SPM0 Bits) .......................... 47
Receive Overflow Indicator (SSPOV Bit) .................. 47
Serial Clock (RC3/SCK/SCL) .................................... 39
Serial Data In (RC4/SDI/SDA) .................................. 39
Serial Data Out (RC5/SDO) ...................................... 39
Slave Select (RA5/SS/AN4) ...................................... 39
Synchronous Serial Port Enable (SSPEN Bit) .......... 47
PIC16C62B/72A
DS35008B-page 116 Preliminary 1999 Microchip Technology Inc.
SSP ....................................................................................39
Enable (SSPIE Bit) ....................................................14
Flag (SSPIF Bit) .........................................................15
RA5/SS/AN4 Pin ..........................................................6
RC3/SCK/SCL Pin .......................................................6
RC4/SDI/SDA Pin ........................................................6
RC5/SDO Pin ...............................................................6
SSPADD Register ......................................................10
SSPBUF Register ........................................................9
SSPCON Register ................................................ 9, 47
SSPSTAT Register ............................................. 10, 46
TMR2 Output for Cloc k Shift ......................................32
Write Collision Detect (WCOL Bit) .............................47
SSPCON Register .............................................................47
CKP Bi t ......................................................................47
SSPEN Bit .................................................................47
SSPM3:SSPM0 Bits ..................................................47
SSPOV Bit .................................................................47
WCOL Bi t ...................................................................47
SSPSTAT Register ............................................................46
BF Bit .........................................................................46
CKE Bi t ......................................................................46
D/A Bit ........................................................................46
P bit ..................................................................... 45, 46
R/W Bit ...................................................42, 43, 44, 46
S Bit .................................................................... 45, 46
SMP Bit ......................................................................46
UA Bit .........................................................................46
Stack ..................................................................................17
STATUS Register ...................................................9, 11, 63
C Bit ...........................................................................11
DC Bit ........................................................................11
IRP Bit ........................................................................11
PD Bit .................................................................. 11, 57
RP1:RP0 Bits .............................................................11
TO Bit .................................................................. 11, 57
Z Bit ...........................................................................11
T
T1CON Register ........................................................... 9, 27
T1CKPS1:T1CKPS0 Bits ...........................................27
T1OSCEN Bit .............................................................27
T1SYNC Bit ...............................................................27
TMR1CS Bit ...............................................................27
TMR1ON Bit ..............................................................27
T2CON Register ........................................................... 9, 31
T2CKPS1:T2CKPS0 Bits ...........................................31
TMR2ON Bit ..............................................................31
TOUTPS3:TOUTPS0 Bits ..........................................31
Timer0 ................................................................................25
Block Diagram ...........................................................25
Clock Source Edge Select (T0SE Bit) ................ 12, 25
Clock Source Select (T0CS Bit) .......................... 12, 25
Overflow Enable (T0IE Bit) ........................................13
Overflow Flag (T0IF Bit) ...................................... 13, 63
Overflow Inte rrupt ............................................... 26, 63
RA4/T0CKI Pin, External Clock ...................................6
Timing Diagram .........................................................93
TMR0 Register .............................................................9
Timer1 ............................................................................... 27
Block Diagram ........................................................... 28
Capacitor Selection ................................................... 29
Clock Sou rce Select (TM R 1CS Bi t) ........................... 27
External Clock Input Sync (T1SYNC Bit) .................. 27
Module On/Off (TMR1ON Bit) ................................... 27
Oscillator .............................................................27, 29
Oscillator Enable (T1OSCEN Bit) .............................. 27
Overflow Enable (TMR1IE Bit) .................................. 14
Overflow Flag (TMR1IF Bit) ....................................... 15
Overflow Interrupt ................................................27, 29
RC0/T1OSO/T1CKI Pin ............................................... 6
RC1/T1OSI .................................................................. 6
Special Event Trigger (CCP) ...............................29, 35
T1CON Register ....................................................9, 27
Timing Diagram ......................................................... 93
TMR1H Register .......................................................... 9
TMR1L Register .......................................................... 9
Timer2
Block Diagram ........................................................... 32
PR2 Register ................................................10, 31, 36
SSP Clock Shi f t ......................................................... 32
T2CON Register ....................................................9, 31
TMR2 Register ......................................................9, 31
TMR2 to PR2 Match Enable (TMR2IE Bit ) ................ 14
TMR2 to PR2 Match Flag (TMR2IF Bit) .................... 15
TMR2 to PR 2 Match Interrupt ......................31, 32, 36
Timing Diagrams
I2C Reception (7-bit Address) ................................... 43
Wake-up from SLEEP via Interrupt ........................... 66
Timing Diagrams and Specifications ................................. 90
A/D Conversion ....................................................... 102
Brown-out Reset (BOR) ............................................ 92
Capture/Compare/PWM (CCP) ................................. 94
CLKOUT and I/O ....................................................... 91
External Clock ........................................................... 90
I2C Bus Data ........................................................... 100
I2C Bus Start/Stop Bits .............................................. 99
Oscillator Start-up Timer (OST) ................................. 92
Power-up Timer (PW RT ) ........................................... 92
Reset ........................................................................... 2
Timer0 and Timer1 .................................................... 93
Watchdog Timer (WDT) ............................................ 92
W
W Register ......................................................................... 63
Wake-up from SLEEP .................................................55, 65
Interrupts .............................................................60, 61
MCLR Reset .............................................................. 61
Timing Diagram ......................................................... 66
WDT Reset ................................................................ 61
Watchdog Timer (WDT) ..............................................55, 64
Block Diagram ........................................................... 64
Enable (WDTE Bit) ..............................................55, 64
Programming Considerations .................................... 64
RC Oscillator ............................................................. 64
Timing Diagram ......................................................... 92
WDT Reset, Normal Operation ....................57, 60, 61
WDT Reset, SLEEP .....................................57, 60, 61
WWW, On-Line Support ...................................................... 3
PIC16C62B/72A
1999 Microchip Technology Inc. Preliminary DS35008B-page 117
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) sit e.
The we b site is used b y Mic rochi p as a mean s to mak e
files and information easily available to customers. To
vie w the site , the user must ha v e access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Samp le Programs. A vari-
ety of Microchip specific business information is also
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distributors and factory representatives. Other data
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• Latest Microchip Press Releases
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Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
Trademarks: The Microchip name, logo , PIC, PICmicro,
PICSTA RT, PICMASTER and PRO MATE are regist ered
trademarks of Microchip Technology Incor porated in the
U.S.A. and other countries.
Flex
ROM, MPLAB and
fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
981103
PIC16C62B/72A
DS35008B-page 118 Preliminary 1998 Microchip Technology Inc.
READER RESPONSE
It is our i ntention to pro vide you with the bes t d ocu me nta tion possible to ensure succe ssful use of your M ic roc hi p pro d-
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Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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DS35008B
PIC16C62B/72A
1998 Microchip Technology Inc. Preliminary DS35008B-page 119
PIC16C62B/72A
PIC16C62B/72A PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differ ences and recom -
mended workarounds. To determine if an errata sheet exists f or a particular device , please contact one of the following:
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Please specify which de vice , revision of silicon and Data Sheet (include Literature #) you are using.
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PART NO. -XX X /XX XXX Pattern: QTP, SQTP, Code or Special Requirements
Package: JW = Windowed CERDIP
SO = SOIC
SP = Skinny plastic dip
P=PDIP
SS = SSOP
Temperature
Range: -=0
°C to +70°C
I=-40
°C to +85°C
E=-40
°C to +125°C
Frequency
Range: 04 = 4 MHz
10 = 10 MHz
20 = 20 MHz
Device PIC16C62B: VDD range 4.0V to 5.5V
PIC16C62BT: VDD range 4.0V to 5.5V (Tape/Reel)
PIC16LC62B: VDD range 2.5V to 5.5V
PIC16LC62BT: VDD r ange 2.5V to 5.5V (Tape/Reel)
Examples
a) PIC16C72A-04/P 301
Commercial Temp.,
PDIP P ackage, 4 MHz,
normal VDD limits, QTP
pattern #30 1
b)
Information cont ai ned in this publication reg ardi ng device applications and the like is intended for suggestion only and m ay be superseded by updates. No representa tion or war ran ty is given and no liability is assumed
by Microchip Technology Incor porated with res pect to the accurac y or use of such informa tion, or inf ringement of pat ents or other int ellectual property rights aris ing from such use or otherwise. Use of Microchip’ s products
as critical c om ponents in life support systems is not au thorized except with ex pres s written approval by Microchip. No lic ens es are conveyed, impli cit l y or otherwise, under any inte lle ct ual property rights. The Microchip
logo and name are registered trademarks of Micr ochip Technology Inc. in the U.S.A. and ot her countries . Al l rig hts res erved. All other tradem arks mentioned herein are the property of their res pective comp ani es.
1999 Microchip Technology Inc.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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