Data Sheet Comlinear CLC1009, CLC1019, CLC2009 (R) FEATURES n 208A supply current n 35MHz bandwidth n Power down to 35A (CLC1019) n Input voltage range with 5V supply: -0.3V to 3.8V n Output voltage range with 5V supply: 0.08V to 4.88V n 27V/s slew rate n 21nV/Hz input voltage noise n 13mA linear output current n Fully specified at 2.7V and 5V supplies n Replaces MAX4281 n CLC1009: Pb-free SOT23-5, SOIC-8 n CLC1019: Pb-free SOT23-6, SOIC--8 n CLC2009: Pb-free MSOP-8, SOIC-8 General Description APPLICATIONS n Portable/battery-powered applications n Mobile communications, cell phones, pagers n ADC buffer n Active filters n Portable test instruments n Signal conditioning n Medical Equipment n Portable medical instrumentation Typical Performance Examples The COMLINEAR CLC1009 (single), CLC1019 (single with disable), and CLC2009 (dual) are ultra-low power, low cost, voltage feedback amplifiers. These amplifiers use only 208A of supply current and are designed to operate from a supply range of 2.5V to 5.5V (1.25 to 2.75). The input voltage range extends 300mV below the negative rail and 1.2V below the positive rail. The CLC1009, CLC1019, and CLC2009 offer high bipolar performance at a low CMOS price. They offer superior dynamic performance with a 35MHz small signal bandwidth and 27V/s slew rate. The combination of lowpower, high bandwidth, and rail-to-rail performance make the CLC1009, CLC1019, and CLC2009 well suited for battery-powered communication/ computing systems. Output Swing vs. RL 4.85 G=2 4.80 Output Swing (Vpp) Normalized Magnitude (2dB/div) Frequency Response 4.75 4.70 4.65 4.60 4.55 0.1 1 10 100 1 Frequency (MHz) 10 100 RL (k) Ordering Information Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CLC1009IST5X* SOT23-5 Yes Yes -40C to +85C Reel CLC1009ISO8X SOIC-8 Yes Yes -40C to +85C Reel CLC1019IST6X* SOT23-6 Yes Yes -40C to +85C Reel CLC1019ISO8X SOIC-8 Yes Yes -40C to +85C Reel CLC2009IMP8X* MSOP-8 Yes Yes -40C to +85C Reel CLC2009ISO8X SOIC-8 Yes Yes -40C to +85C Reel Rev 1C Part Number Moisture sensitivity level for all parts is MSL-1. *Advance Information, contact CADEKA for availability. (c)2009-2010 CADEKA Microcircuits LLC Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers 0.2mA, Low Cost, 2.5 to 5.5V, 35MHz Rail-to-Rail Amplifiers www.cadeka.com Data Sheet CLC1009 Pin Assignments CLC1009 Pin Configuration 1 -V S 2 +IN 3 +VS 5 + -IN 4 CLC1019 Pin Configuration OUT 1 -V S 2 +IN 3 + - Pin Name Description 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 +VS Positive supply CLC1019 Pin Configuration 6 +VS 5 DIS 4 -IN CLC2009 Pin Configuration +VS OUT1 1 8 -IN1 2 7 OUT2 +IN1 3 6 -IN2 -V S 4 5 +IN2 Pin No. Pin Name 1 OUT Description Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 DIS Disable pin. Enabled if pin is left floating or tied to +VS, disabled if pin is tied to -VS (which is GND in a single supply application). 6 +VS Positive supply CLC2009 Pin Configuration Pin No. Pin Name Description 1 OUT1 Output, channel 1 2 -IN1 Negative input, channel 1 3 +IN1 Positive input, channel 1 4 -VS 5 +IN2 Positive input, channel 2 6 -IN2 Negative input, channel 2 7 OUT2 Output, channel 2 8 +VS Negative supply Positive supply Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers OUT Pin No. Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltage Input Voltage Range Continuous Output Current Min Max Unit 0 -Vs -0.5V -30 6 +Vs +0.5V 30 V V mA Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers Parameter Reliability Information Parameter Min Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 5-Lead SOT23 6-Lead SOT23 8-Lead SOIC 8-Lead MSOP Typ -65 Max Unit 175 150 260 C C C 221 177 100 139 C/W C/W C/W C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) SOT23-5 SOT23-6 SOIC-8 MSOP-8 TBD TBD TBD TBD TBD TBD TBD TBD Recommended Operating Conditions Parameter Min Operating Temperature Range Supply Voltage Range -40 2.5 Typ Max Unit +85 5.5 C V Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Electrical Characteristics at +2.7V TA = 25C, Vs = +2.7V, Rf = Rg =2.5k, RL = 2k to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response Unity Gain -3dB Bandwidth G = +1, VOUT = 0.05Vpp , Rf = 0 28 MHz BWSS -3dB Bandwidth G = +2, VOUT < 0.2Vpp 15 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 7 MHz GBWP Gain Bandwdith Product G = +11, VOUT = 0.2Vpp 16 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 0.2V step; (10% to 90%) 16 ns tS Settling Time to 0.1% VOUT = 1V step 140 ns OS Overshoot VOUT = 1V step 1 % SR Slew Rate 2V step, G = -1 20 V/s Distortion/Noise Response HD2 2nd Harmonic Distortion VOUT = 1Vpp, 100kHz -85 dBc HD3 3rd Harmonic Distortion VOUT = 1Vpp, 100kHz -63 dBc THD Total Harmonic Distortion VOUT = 1Vpp, 100kHz 62 dB en Input Voltage Noise > 10kHz 23 nV/Hz XTALK Crosstalk VOUT = 0.2Vpp, 100kHz 98 dB 0.8 mV DC Performance VIO dVIO Input Offset Voltage Average Drift 11 V/C Ib Input Bias Current 0.37 A dIb Average Drift 1 nA/C IOS Input Offset Current 8 nA PSRR Power Supply Rejection Ratio (1) DC 60 dB AOL Open-Loop Gain VOUT = VS / 2 65 dB IS Supply Current per channel 185 A 1 s 56 Disable Characteristics TON Turn On Time TOFF Turn Off Time 3.5 s OFFISO Off Isolation 1MHz 74 dB ISD Disable Supply Current per channel, DIS tied to GND 13 A >10 M 1.4 pF -0.3 to 1.5 V 92 dB RL = 2k to VS / 2 0.08 to 2.6 V RL = 10k to VS / 2 0.06 to 2.62 V 8 mA 12.5 mA Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio Non-inverting DC, VCM = 0V to VS - 1.5 Output Characteristics VOUT Output Voltage Swing IOUT Output Current ISC Short Circuit Output Current Rev 1C Notes: 1. 100% tested at 25C (c)2009-2010 CADEKA Microcircuits LLC Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers UGBWSS www.cadeka.com 4 Data Sheet Electrical Characteristics at +5V TA = 25C, Vs = +5V, Rf = Rg =2.5k, RL = 2k to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response Unity Gain -3dB Bandwidth G = +1, VOUT = 0.05Vpp , Rf = 0 35 MHz BWSS -3dB Bandwidth G = +2, VOUT < 0.2Vpp 18 MHz BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 8 MHz GBWP Gain Bandwdith Product G = +11, VOUT = 0.2Vpp 20 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 0.2V step; (10% to 90%) 13 ns tS Settling Time to 0.1% VOUT = 1V step 140 ns OS Overshoot VOUT = 1V step 1 % SR Slew Rate 2V step, G = -1 27 V/s Distortion/Noise Response HD2 2nd Harmonic Distortion VOUT = 2Vpp, 100kHz -78 dBc HD3 3rd Harmonic Distortion VOUT = 2Vpp, 100kHz -66 dBc THD Total Harmonic Distortion VOUT = 2Vpp, 100kHz 65 dB en Input Voltage Noise > 10kHz 21 nV/Hz XTALK Crosstalk VOUT = 0.2Vpp, 100kHz 98 dB DC Performance VIO dVIO Ib dIb Input Offset Voltage (1) -5 -1.5 -1.3 0.37 Average Drift 5 20 Input Bias Current (1) Average Drift V/C 1.3 1 A nA/C IOS Input Offset Current (1) PSRR Power Supply Rejection Ratio (1) DC 56 60 dB AOL Open-Loop Gain VOUT = VS / 2 56 62 dB IS Supply Current per channel (1) 7 mV 208 130 260 nA A Disable Characteristics TON Turn On Time 0.7 s TOFF Turn Off Time 4.5 s OFFISO Off Isolation 1MHz 72 dB ISD Disable Supply Current (1) per channel, DIS tied to GND 35 A >10 M 1.2 pF -0.3 to 3.8 V 65 95 dB 0.2 to 4.7 0.1 to 4.8 V 0.08 to 4.88 V Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio (1) Non-inverting DC, VCM = 0V to VS - 1.5 Output Characteristics RL = 2k to VS / 2 (1) VOUT Output Voltage Swing RL = 10k to VS / 2 IOUT Output Current 8.5 mA ISC Short Circuit Output Current 13 mA Rev 1C Notes: 1. 100% tested at 25C (c)2009-2010 CADEKA Microcircuits LLC Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers UGBWSS www.cadeka.com 5 Data Sheet Typical Performance Characteristics TA = 25C, Vs = +5V, Rf = Rg =2.5k, RL = 2k to VS/2, G = 2; unless otherwise noted. 0.1 Normalized Magnitude (1dB/div) G=2 Inverting Frequency Response G=1 Rf = 0 G = 10 G=5 1 10 G = -1 G = -2 G = -10 G = -5 0.1 100 1 Frequency (MHz) 0.1 G=1 Rf = 0 G = 10 G=5 1 10 100 Inverting Frequency Response at VS = 2.7V Normalized Magnitude (1dB/div) Normalized Magnitude (2dB/div) Non-Inverting Frequency Response at VS = 2.7V G=2 10 Frequency (MHz) G = -1 G = -2 G = -10 G = -5 0.1 100 1 Frequency (MHz) 10 100 Frequency (MHz) Frequency Response vs. VOUT Open Loop Gain & Phase vs. Frequency 40 100 Open Loop Gain (dB) Vo = 1Vpp Vo = 2Vpp 80 0 60 -40 40 -80 20 -120 -160 0 Phase -20 0.1 1 10 (c)2009-2010 CADEKA Microcircuits LLC 10 100 1k 10k 100k 1M -200 10M Frequency (Hz) Rev 1C Frequency (MHz) 100 Open Loop Phase (deg) Magnitude (1dB/div) Gain Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers Normalized Magnitude (2dB/div) Non-Inverting Frequency Response www.cadeka.com 6 Data Sheet Typical Performance Characteristics TA = 25C, Vs = +5V, Rf = Rg =2.5k, RL = 2k to VS/2, G = 2; unless otherwise noted. 2nd & 3rd Harmonic Distortion -40 Vo = 2Vpp -50 -50 3rd -60 Distortion (dBc) Distortion (dBc) Vo = 1Vpp -70 -80 2nd 3rd -60 -70 -80 2nd -90 -90 -100 -100 10 100 10 1000 100 Frequency (kHz) 1000 Frequency (kHz) CMRR PSRR -20 10 -30 0 -40 -10 -50 -20 PSRR (dB) CMRR (dB) Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers -40 2nd & 3rd Harmonic Distortion at VS = 2.7V -60 -70 -30 -40 -80 -50 -90 -60 -100 -70 10 100 1k 10k 100k 1M 100 10M Frequency (Hz) 10k 100k 1M 10M Frequency (Hz) Large Signal Pulse Response Output Voltage (0.5V/div) Output Voltage (0.05V/div) Small Signal Pulse Response 1k (c)2009-2010 CADEKA Microcircuits LLC Time (1s/div) Rev 1C Time (1ms/div) www.cadeka.com 7 Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = +5V, Rf = Rg =2.5k, RL = 2k to VS/2, G = 2; unless otherwise noted. Output Swing vs. RL Enable / Disable Response Output Voltage (0.1V/div) Output Swing (Vpp) 4.80 4.75 4.70 4.65 4.60 5V Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers 4.85 Disable Pulse 0V 4.55 1 10 100 Time (1s/div) RL (k) Input Voltage Noise Voltage Noise (nV/Hz) 100 80 60 40 20 0 100 1k 10k 100k 1M Frequency (Hz) Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 8 Data Sheet Application Information +Vs General Description R1 Input Figures 1, 2, and 3 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. Figure 4 shows the typical non-inverting gain circuit for single supply applicaitons. +Vs Output - RL 0.1F The design utilizes a patent pending topology that provides increased slew rate performance. The common mode input range extends to 300mV below ground and to 1.2V below Vs. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. The design uses a Darlington output stage. The output stage is short circuit protected and offers "soft" saturation protection that improves recovery time. Rg 0.1F + Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers The CLC1009 family are a single supply, general purpose, voltage-feedback amplifiers fabricated on a complementary bipolar process. The CLC1009 offers 35MHz unity gain bandwidth, 27V/s slew rate, and only 208A supply current. It features a rail-to-rail output stage and is unity gain stable. 6.8F Rf 6.8F G = - (Rf/Rg) -Vs For optimum input offset voltage set R1 = Rf || Rg Figure 2. Typical Inverting Gain Circuit +Vs Input 6.8F 0.1F + Output - RL 0.1F 6.8F -Vs G=1 Figure 3. Unity Gain Circuit 6.8F +Vs 6.8F + Input 0.1F + Output 0.1F Rg 6.8F -Vs In + RL - Rf G = 1 + (Rf/Rg) 0.01F Out Rf Rg Figure 1. Typical Non-Inverting Gain Circuit Figure 4. Single Supply Non-Inverting Gain Circuit Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Enable/Disable Function (CLC1019) PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff Power dissipation should not be a factor when operating under the stated 2k load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply x IRMS supply Vsupply = VS+ - VS- The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. The CLC1009 is short circuit protected. However, this may not guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. 2 SOIC-8 Maximum Power Dissipation (W) Power Dissipation MSOP-8 1.5 1 0.5 SOT23-6 SOT23-5 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) Figure 5. Maximum Power Derating Power delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in Figure 3 would be calculated as: These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load (c)2009-2010 CADEKA Microcircuits LLC Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 6. www.cadeka.com 10 Rev 1C RL || (Rf + Rg) Driving Capacitive Loads Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers The CLC1019 offers an active-low disable pin that can be used to lower its supply current. Leave the pin floating to enable the part. Pull the disable pin to the negative supply (which is ground in a single supply application) to disable the output. During the disable condition, the nominal supply current will drop to below 40A and the output will be at high impedance with about 2pF capacitance. impedance is needed to determine the dissipated power. Here, PD can be found from Data Sheet Input + Rs - Output CL Rf RL Figure 6. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in approximately <1dB peaking in the frequency response. CL (pF) RS () -3dB BW (kHz) 10pF TBD 20pF TBD 50pF TBD Layout Considerations 100pF TBD General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC1009, CLC1019, and CLC2009 will typically recover in less than 20ns from an overdrive condition. Figure 7 shows the CLC1009 in an overdriven condition. Figure 7. Overdrive Recovery Include 6.8F and 0.1F ceramic capacitors for power supply decoupling Place the 6.8F capacitor within 0.75 inches of the power pin Place the 0.1F capacitor within 0.1 inches of the power pin Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # (c)2009-2010 CADEKA Microcircuits LLC CLC1009, CLC1019 in SOT23 CLC1009 in SOIC CLC2009 in SOIC CLC2009 in MSOP www.cadeka.com Rev 1C CEB002 CEB003 CEB006 CEB010 Products Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers Rg 11 Data Sheet Evaluation Board Schematics Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers Evaluation board schematics and layouts are shown in Figures 8-14. These evaluation boards are built for dualsupply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 10. CEB002 Bottom View Figure 8. CEB002 & CEB003 Schematic Figure 11. CEB003 Top View Rev 1C Figure 9. CEB002 Top View (c)2009-2010 CADEKA Microcircuits LLC Figure 12. CEB003 Bottom View www.cadeka.com 12 Data Sheet Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers Figure 13. CEB006 Bottom View Figure 11. CEB006 & CEB010 Schematic Figure 15. CEB010 Top View Figure 12. CEB006 Top View Rev 1C Figure 16. CEB010 Bottom View (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 13 Data Sheet Mechanical Dimensions SOT23-5 Package Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers SOT23-6 Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet Mechanical Dimensions continued SOIC-8 Package Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers MSOP-8 Package e 02 S Symbol Min H E1 3 7 B E3 E4 1 6 4 2 C D2 A2 b D 4 A1 01 L 03 L1 b c b1 Section A - A A Scale 40:1 c1 E2 A A bbb M A B C 0.25mm 5 A aaa A R Plane 2 ccc A B C 2 R1 t2 E/2 2X Max t1 E1 E Detail A 3.0 3.0 3.0 3 2 3 4 5 6 7 Dimension "E1" and "E2" does not include interlead flash or protrusion. Rev 1C (c)2009-2010 CADEKA Microcircuits LLC www.cadeka.com 15 Data Sheet CADEKA, the CADEKA logo design, COMLINEAR, and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2009-2010 by CADEKA Microcircuits LLC. All rights reserved. Rev 1C CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Amplifiers For additional information regarding our products, please visit CADEKA at: cadeka.com