Data Sheet
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
Comlinear® CLC1009, CLC1019, CLC2009
0.2mA, Low Cost, 2.5 to 5.5V, 35MHz
Rail-to-Rail Ampliers
FEATURES
n 208μA supply current
n 35MHz bandwidth
n Power down to 35μA (CLC1019)
n Input voltage range with 5V supply:
-0.3V to 3.8V
n Output voltage range with 5V supply:
0.08V to 4.88V
n 27V/μs slew rate
n 21nV/√Hz input voltage noise
n 13mA linear output current
n Fully specied at 2.7V and 5V supplies
n Replaces MAX4281
n CLC1009: Pb-free SOT23-5, SOIC-8
n CLC1019: Pb-free SOT23-6, SOIC--8
n CLC2009: Pb-free MSOP-8, SOIC-8
APPLICATIONS
n Portable/battery-powered applications
n Mobile communications, cell phones,
pagers
n ADC buffer
n Active lters
n Portable test instruments
n Signal conditioning
n Medical Equipment
n Portable medical instrumentation
General Description
The COMLINEAR CLC1009 (single), CLC1019 (single with disable), and
CLC2009 (dual) are ultra-low power, low cost, voltage feedback ampliers.
These ampliers use only 208μA of supply current and are designed to
operate from a supply range of 2.5V to 5.5V (±1.25 to ±2.75). The input
voltage range extends 300mV below the negative rail and 1.2V below the
positive rail.
The CLC1009, CLC1019, and CLC2009 offer high bipolar performance at a
low CMOS price. They offer superior dynamic performance with a 35MHz
small signal bandwidth and 27V/μs slew rate. The combination of lowpower,
high bandwidth, and rail-to-rail performance make the CLC1009, CLC1019,
and CLC2009 well suited for battery-powered communication/ computing
systems.
Typical Performance Examples
Ordering Information
Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CLC1009IST5X* SOT23-5 Yes Yes -40°C to +85°C Reel
CLC1009ISO8X SOIC-8 Yes Yes -40°C to +85°C Reel
CLC1019IST6X* SOT23-6 Yes Yes -40°C to +85°C Reel
CLC1019ISO8X SOIC-8 Yes Yes -40°C to +85°C Reel
CLC2009IMP8X* MSOP-8 Yes Yes -40°C to +85°C Reel
CLC2009ISO8X SOIC-8 Yes Yes -40°C to +85°C Reel
Moisture sensitivity level for all parts is MSL-1. *Advance Information, contact CADEKA for availability.
Normalized Magnitude (2dB/div)
Frequency (MHz)
0.1 110 100
G = 2
Output Swing (Vpp)
RL (kΩ)
110 100
4.55
4.60
4.70
4.85
4.75
4.80
4.65
Frequency Response Output Swing vs. RL
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 2
CLC1009 Pin Assignments
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 +VSPositive supply
CLC1019 Pin Conguration
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 DIS
Disable pin. Enabled if pin is left oating or tied
to +VS, disabled if pin is tied to -VS (which is GND
in a single supply application).
6 +VSPositive supply
CLC2009 Pin Conguration
Pin No. Pin Name Description
1 OUT1 Output, channel 1
2 -IN1 Negative input, channel 1
3 +IN1 Positive input, channel 1
4 -VSNegative supply
5 +IN2 Positive input, channel 2
6 -IN2 Negative input, channel 2
7 OUT2 Output, channel 2
8 +VSPositive supply
CLC1009 Pin Conguration
CLC1019 Pin Conguration
2
3
5
4
+IN
+V
S
-IN
1
-V
S
OUT
-
+
2
3
6
4
+IN
+V
S
-IN
1
-V
S
OUT
-
+5
DIS
CLC2009 Pin Conguration
2
3
45
6
7
8
OUT2
+IN1 -IN2
+IN2
1
-IN1
OUT1
-V
S
+V
S
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 3
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reect the
operating conditions noted on the tables and plots.
Parameter Min Max Unit
Supply Voltage 0 6 V
Input Voltage Range -Vs -0.5V +Vs +0.5V V
Continuous Output Current -30 30 mA
Reliability Information
Parameter Min Typ Max Unit
Junction Temperature 175 °C
Storage Temperature Range -65 150 °C
Lead Temperature (Soldering, 10s) 260 °C
Package Thermal Resistance
5-Lead SOT23 221 °C/W
6-Lead SOT23 177 °C/W
8-Lead SOIC 100 °C/W
8-Lead MSOP 139 °C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
ESD Protection
Product SOT23-5 SOT23-6 SOIC-8 MSOP-8
Human Body Model (HBM) TBD TBD TBD TBD
Charged Device Model (CDM) TBD TBD TBD TBD
Recommended Operating Conditions
Parameter Min Typ Max Unit
Operating Temperature Range -40 +85 °C
Supply Voltage Range 2.5 5.5 V
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 4
Electrical Characteristics at +2.7V
TA = 25°C, Vs = +2.7V, Rf = Rg =2.5kΩ, RL = 2kΩ to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
UGBWSS Unity Gain -3dB Bandwidth G = +1, VOUT = 0.05Vpp , Rf = 0 28 MHz
BWSS -3dB Bandwidth G = +2, VOUT < 0.2Vpp 15 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 7 MHz
GBWP Gain Bandwdith Product G = +11, VOUT = 0.2Vpp 16 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 0.2V step; (10% to 90%) 16 ns
tSSettling Time to 0.1% VOUT = 1V step 140 ns
OS Overshoot VOUT = 1V step 1 %
SR Slew Rate 2V step, G = -1 20 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion VOUT = 1Vpp, 100kHz -85 dBc
HD3 3rd Harmonic Distortion VOUT = 1Vpp, 100kHz -63 dBc
THD Total Harmonic Distortion VOUT = 1Vpp, 100kHz 62 dB
enInput Voltage Noise > 10kHz 23 nV/√Hz
XTALK Crosstalk VOUT = 0.2Vpp, 100kHz 98 dB
DC Performance
VIO Input Offset Voltage 0.8 mV
dVIO Average Drift 11 µV/°C
IbInput Bias Current 0.37 μA
dIb Average Drift 1 nA/°C
IOS Input Offset Current 8 nA
PSRR Power Supply Rejection Ratio (1) DC 56 60 dB
AOL Open-Loop Gain VOUT = VS / 2 65 dB
ISSupply Current per channel 185 μA
Disable Characteristics
TON Turn On Time 1 μs
TOFF Turn Off Time 3.5 μs
OFFISO Off Isolation 1MHz 74 dB
ISD Disable Supply Current per channel, DIS tied to GND 13 μA
Input Characteristics
RIN Input Resistance Non-inverting >10 MΩ
CIN Input Capacitance 1.4 pF
CMIR Common Mode Input Range -0.3 to
1.5 V
CMRR Common Mode Rejection Ratio DC, VCM = 0V to VS - 1.5 92 dB
Output Characteristics
VOUT Output Voltage Swing
RL = 2kΩ to VS / 2 0.08 to
2.6 V
RL = 10kΩ to VS / 2 0.06 to
2.62 V
IOUT Output Current ±8 mA
ISC Short Circuit Output Current ±12.5 mA
Notes:
1. 100% tested at 25°C
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 5
Electrical Characteristics at +5V
TA = 25°C, Vs = +5V, Rf = Rg =2.5kΩ, RL = 2kΩ to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
UGBWSS Unity Gain -3dB Bandwidth G = +1, VOUT = 0.05Vpp , Rf = 0 35 MHz
BWSS -3dB Bandwidth G = +2, VOUT < 0.2Vpp 18 MHz
BWLS Large Signal Bandwidth G = +2, VOUT = 2Vpp 8 MHz
GBWP Gain Bandwdith Product G = +11, VOUT = 0.2Vpp 20 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 0.2V step; (10% to 90%) 13 ns
tSSettling Time to 0.1% VOUT = 1V step 140 ns
OS Overshoot VOUT = 1V step 1 %
SR Slew Rate 2V step, G = -1 27 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion VOUT = 2Vpp, 100kHz -78 dBc
HD3 3rd Harmonic Distortion VOUT = 2Vpp, 100kHz -66 dBc
THD Total Harmonic Distortion VOUT = 2Vpp, 100kHz 65 dB
enInput Voltage Noise > 10kHz 21 nV/√Hz
XTALK Crosstalk VOUT = 0.2Vpp, 100kHz 98 dB
DC Performance
VIO Input Offset Voltage (1) -5 -1.5 5 mV
dVIO Average Drift 20 µV/°C
IbInput Bias Current (1) -1.3 0.37 1.3 μA
dIb Average Drift 1 nA/°C
IOS Input Offset Current (1) 7 130 nA
PSRR Power Supply Rejection Ratio (1) DC 56 60 dB
AOL Open-Loop Gain VOUT = VS / 2 56 62 dB
ISSupply Current (1) per channel 208 260 μA
Disable Characteristics
TON Turn On Time 0.7 μs
TOFF Turn Off Time 4.5 μs
OFFISO Off Isolation 1MHz 72 dB
ISD Disable Supply Current (1) per channel, DIS tied to GND 35 μA
Input Characteristics
RIN Input Resistance Non-inverting >10 MΩ
CIN Input Capacitance 1.2 pF
CMIR Common Mode Input Range -0.3 to
3.8 V
CMRR Common Mode Rejection Ratio (1) DC, VCM = 0V to VS - 1.5 65 95 dB
Output Characteristics
VOUT Output Voltage Swing
RL = 2kΩ to VS / 2 (1) 0.2 to
4.7
0.1 to
4.8 V
RL = 10kΩ to VS / 2 0.08 to
4.88 V
IOUT Output Current ±8.5 mA
ISC Short Circuit Output Current ±13 mA
Notes:
1. 100% tested at 25°C
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 6
Typical Performance Characteristics
TA = 25°C, Vs = +5V, Rf = Rg =2.5kΩ, RL = 2kΩ to VS/2, G = 2; unless otherwise noted.
Frequency Response vs. VOUT Open Loop Gain & Phase vs. Frequency
Non-Inverting Frequency Response at VS = 2.7V Inverting Frequency Response at VS = 2.7V
Non-Inverting Frequency Response Inverting Frequency Response
Normalized Magnitude (2dB/div)
Frequency (MHz)
0.1 1
G = 10
10 100
G = 5
G = 1
Rf = 0
G = 2
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.1 1
G = -10
10 100
G = -5
G = -2
G = -1
Normalized Magnitude (2dB/div)
Frequency (MHz)
0.1 1
G = 10
10 100
G = 5
G = 2
G = 1
Rf = 0
Normalized Magnitude (1dB/div)
Frequency (MHz)
0.1 1
G = -10
10 100
G = -5
G = -1
G = -2
Magnitude (1dB/div)
Frequency (MHz)
0.1 110 100
Vo = 1Vpp
Vo = 2Vpp
Open Loop Gain (dB)
Frequency (Hz)
10 100 1k 1M100k10k 10M
-20
0
20
100
40
80
60
Open Loop Phase (deg)
-200
-160
-120
40
-80
0
-40
Gain
Phase
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 7
Typical Performance Characteristics
TA = 25°C, Vs = +5V, Rf = Rg =2.5kΩ, RL = 2kΩ to VS/2, G = 2; unless otherwise noted.
Small Signal Pulse Response Large Signal Pulse Response
CMRR PSRR
2nd & 3rd Harmonic Distortion 2nd & 3rd Harmonic Distortion at VS = 2.7V
Distortion (dBc)
Frequency (kHz)
10 100
3rd
1000
2nd
-100
-90
-80
-70
-60
-50
-40 Vo = 2Vpp
Distortion (dBc)
Frequency (kHz)
10 100
3rd
1000
2nd
-100
-90
-80
-70
-60
-50
-40 Vo = 1Vpp
CMRR (dB)
Frequency (Hz)
10 100 1k 1M100k10k 10M
-100
-90
-80
-70
-20
-60
-50
-30
-40
PSRR (dB)
Frequency (Hz)
100 1k 10k 1M100k 10M
-70
-60
-50
-40
-30
10
-20
-10
0
Output Voltage (0.05V/div)
Time (1ms/div)
Output Voltage (0.5V/div)
Time (1μs/div)
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 8
Typical Performance Characteristics - Continued
TA = 25°C, Vs = +5V, Rf = Rg =2.5kΩ, RL = 2kΩ to VS/2, G = 2; unless otherwise noted.
Input Voltage Noise
Output Swing vs. RL Enable / Disable Response
Output Swing (Vpp)
RL (kΩ)
110 100
4.55
4.60
4.70
4.85
4.75
4.80
4.65
Output Voltage (0.1V/div)
Time (1μs/div)
Disable Pulse
5V
0V
Voltage Noise (nV/√Hz)
Frequency (Hz)
100 1k 10k 1M
0
20
40
60
80
100
100k
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 9
Application Information
General Description
The CLC1009 family are a single supply, general purpose,
voltage-feedback ampliers fabricated on a complementary
bipolar process. The CLC1009 offers 35MHz unity gain
bandwidth, 27V/μs slew rate, and only 208μA supply current.
It features a rail-to-rail output stage and is unity gain stable.
The design utilizes a patent pending topology that provides
increased slew rate performance. The common mode input
range extends to 300mV below ground and to 1.2V below
Vs. Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition.
The design uses a Darlington output stage. The output
stage is short circuit protected and offers “soft” saturation
protection that improves recovery time.
Figures 1, 2, and 3 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Figure 4 shows the typical non-inverting gain circuit for
single supply applicaitons.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1. Typical Non-Inverting Gain Circuit
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Figure 2. Typical Inverting Gain Circuit
+
-
0.1μF
6.8μF
Output
G = 1
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Figure 3. Unity Gain Circuit
+
-Rf
0.01µF
6.8μF
Out
In
+Vs
+
Rg
Figure 4. Single Supply Non-Inverting Gain Circuit
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 10
Enable/Disable Function (CLC1019)
The CLC1019 offers an active-low disable pin that can be
used to lower its supply current. Leave the pin oating to
enable the part. Pull the disable pin to the negative supply
(which is ground in a single supply application) to disable
the output. During the disable condition, the nominal
supply current will drop to below 40μA and the output will
be at high impedance with about 2pF capacitance.
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 2kΩ load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature
is not exceeded. Guidelines listed below can be used to
verify that the particular application will not cause the
device to operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value
ThetaJA (ӨJA) is used along with the total die power
dissipation.
TJunction = TAmbient + (ӨJA × PD)
Where TAmbient is the temperature of the working environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power
equation.
Psupply = Vsupply × IRMS supply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((VLOAD)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include
the effect of the feedback network. For instance,
Rloadeff in Figure 3 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - PLoad
Quiescent power can be derived from the specied IS
values along with known supply voltage, VSupply. Load
power can be calculated as above with the desired signal
amplitudes using:
(VLOAD)RMS = VPEAK / √2
( ILOAD)RMS = ( VLOAD)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS
Assuming the load is referenced in the middle of the
power rails or Vsupply/2.
The CLC1009 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 5
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
0
0.5
1
1.5
2
-40 -20 0 20 40 60 80
Maximum Power Dissipation (W)
Ambient Temperature (°C)
SOT23-5
SOIC-8
MSOP-8
SOT23-6
Figure 5. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive
loading can cause ringing, peaking in the frequency
response, and possible unstable behavior. Use a series
resistance, RS, between the amplier and the load to
help improve stability and settling performance. Refer to
Figure 6.
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 11
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 6. Addition of RS for Driving Capacitive Loads
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response.
CL (pF) RS (Ω) -3dB BW (kHz)
10pF TBD
20pF TBD
50pF TBD
100pF TBD
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is dened as the point when either
one of the inputs or the output exceed their specied
voltage range. Overdrive recovery is the time needed for
the amplier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1009, CLC1019, and CLC2009 will
typically recover in less than 20ns from an overdrive
condition. Figure 7 shows the CLC1009 in an overdriven
condition.
Figure 7. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪ Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
▪ Place the 6.8µF capacitor within 0.75 inches of the power pin
▪ Place the 0.1µF capacitor within 0.1 inches of the power pin
▪ Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
▪ Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB002 CLC1009, CLC1019 in SOT23
CEB003 CLC1009 in SOIC
CEB006 CLC2009 in SOIC
CEB010 CLC2009 in MSOP
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 12
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-14. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
Figure 8. CEB002 & CEB003 Schematic
Figure 9. CEB002 Top View
Figure 10. CEB002 Bottom View
Figure 11. CEB003 Top View
Figure 12. CEB003 Bottom View
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 13
Figure 11. CEB006 & CEB010 Schematic
Figure 12. CEB006 Top View
Figure 13. CEB006 Bottom View
Figure 15. CEB010 Top View
Figure 16. CEB010 Bottom View
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 14
Mechanical Dimensions
SOT23-5 Package
SOT23-6
Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C
©2009-2010 CADEKA Microcircuits LLC www.cadeka.com 15
Mechanical Dimensions continued
SOIC-8 Package
MSOP-8 Package
±
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±
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±
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±
±
±
±
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For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA, the CADEKA logo design, COMLINEAR, and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2009-2010 by CADEKA Microcircuits LLC. All rights reserved.
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
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Data Sheet
Comlinear CLC1009, CLC1019, CLC2009 0.2mA, Low Cost, 35MHz Rail-to-Rail Ampliers Rev 1C