© 2009 Microchip Technology Inc. DS21685D-page 1
MCP6021/1R/2/3/4
Features
• Rail-to-Rail Input/Output
• Wide Bandwidth: 10 MHz (typical)
• Low Noise: 8.7 nV/√Hz, at 10 kHz (typical)
• Low Offset Voltage:
- Industrial Temperature: ±500 µV (maximum)
- Extended Temperature: ±250 µV (maximum)
• Mid-Supply VREF: MCP6021 and MCP6023
• Low Supply Current: 1 mA (typical)
• Total Harmonic Distortion:
- 0.00053% (typical, G = 1 V/V)
• Unity Gain Stable
• Power Supply Range: 2.5V to 5.5V
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended : -40°C to +125°C
Applications
• Automotive
• Multi-Pole Active Filters
• Audio Processing
• DAC Buffer
• Test Equipment
• Medical Instrumentation
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Typical Application
Description
The MCP6021, MCP6021R, MCP6022, MCP6023 and
MCP6024 from Microchip Technology Inc. are rail-to-
rail input and output op amps with high performance.
Key specifications include: wide bandwidth (10 MHz),
low noise (8.7 nV/√Hz), low input offset voltage and low
distortion (0.00053% THD+N). The MCP6023 also
offers a Chip Select pin (CS) that gives power savings
when the part is not in use.
The single MCP6021 and MCP6021R are availa ble in
SOT-23-5. The single MCP6021, single MCP6023 and
dual MCP6022 are available in 8-lead PDIP, SOIC and
TSSOP. The Extended Temperature single MCP6021
is available in 8-lead MSOP. The quad MCP6024 is
offered in 14-lead PDIP, SOIC and TSSOP packages.
The MCP6021/1R/2/3/4 family is available in Industrial
and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
Package Types
Photo
Detector
100 pF
5.6 pF
100 kΩ
VDD/2
MCP6021
Transimpedance Amp lifier
MCP6021
SOT-23-5
1
2
3
5
4
VDD
VIN–
VOUT
VSS
VIN+
MCP6022
PDIP SOIC, TSSOP
1
2
3
4
8
7
6
5
CS
VDD
VOUT
VREF
NC
VIN–
VIN+
VSS
MCP6023
PDIP SOIC, TSSOP
1
2
3
4
8
7
6
5
VDD
VOUTB
VINB–
VINB+
VOUTA
VINA–
VINA+
VSS
MCP6024
PDIP SOIC, TSSOP
1
2
3
4
VOUTD
VIND–
VIND+
VSS
VOUTA
VINA–
VINA+
VDD VINC+
VINC–
VOUTC
5
6
7
VINB+
VINB–
VOUTB
14
13
12
11
10
9
8
MCP6021
PDIP SOIC,
MSOP, TSSOP
1
2
3
4
8
7
6
5
NC
VDD
VOUT
VREF
NC
VIN–
VIN+
VSS
MCP6021R
SOT-23-5
1
2
3
5
4
VSS
VIN–
VOUT
VDD
VIN+
Rail-to-Rail Input/Output, 10 MHz Op Amps
MCP6021/1R/2/3/4
DS21685D-page 2 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 3
MCP6021/1R/2/3/4
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Analog Input Pins (VIN+, VIN–).....................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature .................................–65° C to +150° C
Maximum Junction Temperature (TJ).........................+150° C
ESD Protection On All Pins (HBM; MM).............. ≥ 2 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “ Input V oltage and Current Limits”.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈VDD/2 and RL =10kΩ to VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage:
Industrial Temperature Parts VOS -500 — +500 µV VCM = 0V
Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V
Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V
TA = -40°C to +125°C
Input Offset Voltage Temperature Drift ΔVOS/ΔTA—±3.5—µV/°CT
A = -40°C to +125°C
Power Supply Rejection Ratio PSRR 74 90 — dB VCM = 0V
Input Current and Impedance
Input Bias Current IB—1—pA
Industrial Temperature Parts IB—30150pAT
A = +85°C
Extended Temperature Parts IB— 640 5,000 pA TA = +125°C
Input Offset Current IOS —±1—pA
Common-Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF
Common-Mode
Common-Mode Input Range VCMR VSS-0.3 — VDD+0.3 V
Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V
CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V
Voltage Reference (MCP6021 and MCP6023 only)
VREF Accuracy (VREF –V
DD/2) VREF_ACC -50 — +50 mV
VREF Temperature Drift ΔVREF/ΔT
A
— ±100 — µV/°C TA = -40°C to +125°C
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VCM = 0V,
VOUT = VSS+0.3V to VDD-0.3V
Output
Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD-20 mV 0.5V input overdrive
Output Short Circuit Current ISC —±30—mAV
DD = 2.5V
ISC —±22—mAV
DD = 5.5V
MCP6021/1R/2/3/4
DS21685D-page 4 © 2009 Microchip Technology Inc.
AC ELECTRICAL CHARACTERISTICS
MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈VDD/2, RL =10kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 2.5 — 5.5 V
Quiescent Current per Amplifier IQ0.5 1.0 1.35 mA IO = 0
AC Response
Gain Bandwidth Product GBWP — 10 — MHz
Phase Margin PM — 6 5 — ° G = +1 V/V
Settling Time, 0.2% tSETTLE — 250 — ns G = +1 V/V, VOUT = 100 mVp-p
Slew Rate SR — 7.0 — V/µs
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = +1 V/V THD+N — 0.00053 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V, RL = 600ΩTHD+N — 0.00064 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V THD+N — 0.0014 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +10 V/V THD+N — 0.0009 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +100 V/V THD+N — 0.005 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
Noise
Input Noise Voltage Eni — 2.9 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —8.7—nV/√Hz f = 10 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈VDD/2, RL =10kΩ to VDD/2 and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL -1.0 0.01 — µA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH — 0.01 2.0 µA CS = VDD
GND Current ISS -2 -0.05 — µA CS = VDD
Amplifier Output Leakage IO(LEAK) —0.01— µACS = VDD
CS Dynamic Specifications
CS Low to Amplifier Output Turn-on Time tON — 2 10 µs G = +1, VIN = VSS,
CS = 0.2VDD to VOUT = 0.45VDD time
CS High to Amplifier Output High-Z Time tOFF — 0.01 — µs G = +1, VIN = VSS,
CS = 0.8VDD to VOUT = 0.05VDD time
Hysteresis VHYST —0.6— VV
DD = 5.0V, Internal Switch
© 2009 Microchip Technology Inc. DS21685D-page 5
MCP6021/1R/2/3/4
TEMPERATURE CHARACTERISTICS
FIGURE 1-1: Timing diagram for the CS
pin on the MCP6023.
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Industrial Temperature Range TA-40 — +85 °C
Extended Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 8L-TSSOP θJA — 124 — °C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA — 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any
case, the internal junction temperature (TJ) must not exceed the absolute maximum specification of 150°C.
High-Z
tON
CS
tOFF
VOUT
-50 nA
High-Z
ISS
ICS 10 nA 10 nA 10 nA
-50 nA
-1 mA
Amplifier On
(typical) (typical) (typical)
(typical) (typical)
(typical)
VDD
MCP6021
2kΩ2kΩ
1kΩVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
CB1
RN
RGRF60 pF 10 kΩ
CB2
VDD
MCP6021
2kΩ
1kΩVOUT
VDD/2
VIN
1µF
VL
0.1 µF
2kΩ
CLRL
CB1
RN
RGRF60 pF 10 kΩ
CB2
MCP6021/1R/2/3/4
DS21685D-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 7
MCP6021/1R/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-1: Input Offset Voltage,
(Industrial Temperature Parts).
FIGURE 2-2: Input Offset Voltage,
(Extended Temperature Parts).
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.5V.
FIGURE 2-4: Input Offset Voltage Drift,
(Industrial Temperature Parts).
FIGURE 2-5: Input Offset Voltage Drift,
(Extended Temperature Parts).
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
16%
-500
-400
-300
-200
-100
0
100
200
300
400
500
Input Offset Voltage (µV)
Percentage of Occurances
1192 Samples
VCM = 0V
TA = +25°C
I-Temp
Parts
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-240
-200
-160
-120
-80
-40
0
40
80
120
160
200
240
Input Offset Volt ag e (µ V)
Percentage of Occurances
438 Samples
VDD = 5.0V
VCM = 0V
TA = +25°C
E-Temp
Parts
-500
-400
-300
-200
-100
0
100
200
300
400
500
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.5V -40°C
+25°C
+85°C
+125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-20
-16
-12
-8
-4
0
4
8
12
16
20
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
1192 Samples
VCM = 0V
TA = -40°C to +8 5°C
I-Temp
Parts
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
24%
-20
-16
-12
-8
-4
0
4
8
12
16
20
Input Offset Voltage Drift (µV/°C)
Percentage of Occurances
438 Samples
VCM = 0V
TA = -40°C to +125°C
E-Temp
Parts
-500
-400
-300
-200
-100
0
100
200
300
400
500
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V -40°C
+25°C
+85°C
+125°C
MCP6021/1R/2/3/4
DS21685D-page 8 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Temperature.
FIGURE 2-8: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-9: CMRR, PSRR vs.
Frequency.
FIGURE 2-10: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-11 : Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-12: CMRR, PSRR vs.
Temperature.
-300
-250
-200
-150
-100
-50
0
50
100
-50-250 255075100125
Ambient Temp erat u re (°C)
Input Offset Voltage (µV)
VDD = 5.0V
VCM = 0V
1
10
100
1,000
1.E-01 1.E +00 1.E+ 01 1.E+02 1 .E+03 1. E+04 1.E +05 1.E+0 6
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
0.1 1 10 100 1k 10k 1M100k
20
30
40
50
60
70
80
90
100
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
PSRR+
PSRR-
CMRR
100 1k 10k 100k 1M
-200
-150
-100
-50
0
50
100
150
200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
VCM = VDD/2
VDD = 2.5V
0
2
4
6
8
10
12
14
16
18
20
22
24
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/√Hz)
VDD = 5.0V
f = 1 kHz
f = 10 kHz
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VCM = 0V)
CMRR
© 2009 Microchip Technology Inc. DS21685D-page 9
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-13: Input Bias, Offset Currents
vs. Common Mode Input Voltage.
FIGURE 2-14: Quiescent Current vs.
Supply Voltage.
FIGURE 2-15: Output Short-Circuit Current
vs. Supply Voltage.
FIGURE 2-16: Input Bias, Offset Currents
vs. Temperature.
FIGURE 2-17: Quiescent Current vs.
Temperature.
FIGURE 2-18: Open-Loop Gain, Phase vs.
Frequency.
1
10
100
1,000
10,000
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB, TA = +125°C
VDD = 5.5V
IOS, TA = +85°C
IOS, TA = +125°C
IB, TA = +85°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Volt age (V )
Quiescent Current
(mA/amplifier)
+125°C
+85°C
+25°C
-40°C
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Output Short Circuit Current
(mA)
+125°C
+85°C
+25°C
-40°C
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
IB
VCM = VDD
VDD = 5.5V
IOS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
-50-250 255075100125
Ambient Temperature (°C)
Quiescent Current
(mA/amplifier)
VDD = 5.5V
VDD = 2.5V
VCM = VDD - 0.5V
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
1.E+00 1.E+ 01 1.E+02 1 .E+03 1.E+ 04 1.E+05 1.E +06 1.E+0 7 1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-195
-180
-165
-150
-135
-120
-105
-90
-75
-60
-45
-30
-15
0
Open-Loop Phase (°)
Gain
Phase
1 10010 1k 100k10k 1M 100M10M
MCP6021/1R/2/3/4
DS21685D-page 10 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-19: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-20: Small Signal DC Open-Loop
Gain vs. Output Voltage Headroom.
FIGURE 2-21: Gain Bandwidth Product,
Phase Margin vs. Temperature.
FIGURE 2-22: DC Open-Loop Gain vs.
Temperature.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-24: Gain Bandwidth Product,
Phase Margin vs. Output Voltage.
80
90
100
110
120
130
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
100 1k 10k 100k
70
80
90
100
110
120
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Output Voltag e Headroom (V);
VDD - VOH or VOL - VSS
DC Open-Loop Gain (dB)
VCM = VDD/2
VDD = 2.5V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
9
10
-50-250 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
10
20
30
40
50
60
70
80
90
100
Phase Margin, G = +1 (°)
GBWP, VDD = 5.5V
GBWP, VDD = 2.5V
PM, VDD = 2.5V
PM, VDD = 5.5V
90
95
100
105
110
115
120
-50-250 255075100125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.5V
0
2
4
6
8
10
12
14
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mo d e I n pu t Voltage (V)
Gain Bandwidth Product
(MHz)
0
15
30
45
60
75
90
105
Phase Margin, G = +1 (°)
Gain Bandwidth Product
Phase Margin, G = +1
VDD = 5.0V
0
2
4
6
8
10
12
14
0.00.51.01.52.02.53.03.54.04.55.0
Output Voltage (V)
Gain Bandwidth Product
(MHz)
0
15
30
45
60
75
90
105
Phase Margin, G = +1 (°)
Gain Bandwidth Product
Phase Margin, G = +1
VDD = 5.0V
VCM = VDD/2
© 2009 Microchip Technology Inc. DS21685D-page 11
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-25: Slew Rate vs. Temperature.
FIGURE 2-26: Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz.
FIGURE 2-27: The MCP6021/1R/2/3/4
family shows no phase reversal under overdrive.
FIGURE 2-28: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-29: Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 20 kHz.
FIGURE 2-30: Channel-to-Channel
Separation vs. Frequency (MCP6022 and
MCP6024 only).
0
1
2
3
4
5
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling, VDD = 2.5V
Rising, VDD = 2.5V
Falling, VDD = 5.5V
Rising, VDD = 5.5V
0.0001%
0.0010%
0.0100%
0.1000%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Vol t ag e ( VP-P)
THD+N (%)
f = 1 kHz
BWMeas = 22 kH z
VDD = 5.0V
G = +1 V/V
G = +10 V/V
G = +100 V/V
-1
0
1
2
3
4
5
6
0 102030405060708090100
Time (10 µs/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2 V/V
VIN
VOUT
0.1
1
10
1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Maximum Output Vol tage
Swing (VP-P)
VDD = 5.5V
10k 100k 1M 10M
VDD = 2.5V
0.0001%
0.0010%
0.0100%
0.1000%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
THD+N (%)
G = +10 V/V
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
G = +100 V/V
105
110
115
120
125
130
135
1.E+03 1.E +04 1.E+05 1.E+06
Frequency (Hz)
Channel to Channel Separation
(dB)
1k 1M100k10k
G = +1 V/V
MCP6021/1R/2/3/4
DS21685D-page 12 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-31: Output Voltage Headroom
vs. Output Current.
FIGURE 2-32: Small-Signal Non-inverting
Pulse Response.
FIGURE 2-33: Large-Signal Non-inverting
Pulse Response.
FIGURE 2-34: Output Voltage Headroom
vs. Temperature.
FIGURE 2-35: Small-Signal Inverting Pulse
Response.
FIGURE 2-36: Large-Signal Inverting Pulse
Response.
1
10
100
1,000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom;
VDD-VOH or VOL-VSS (mV)
VDD - VOH
VOL - VSS
-6.E-02
-5.E-02
-4.E-02
-3.E-02
-2.E-02
-1.E-02
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
6.E-02
0.E+00 2.E-07 4. E-07 6.E -07 8.E-0 7 1.E-06 1.E -06 1.E- 06 2.E-06 2 .E-06 2.E- 06
Time (200 ns/div)
Output Voltage (10 mV/ d iv)
G = +1 V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 5.E-07 1.E -06 2.E-06 2.E -06 3.E-0 6 3.E-06 4.E- 06 4.E-06 5.E -06 5.E-06
Time (500 ns/d iv)
Output Voltage (V)
G = +1 V/V
0
1
2
3
4
5
6
7
8
9
10
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom
VDD-VOH or VOL-VSS (mV)
VDD - VOH
VOL - VSS
-6.E-02
-5.E-02
-4.E-02
-3.E-02
-2.E-02
-1.E-02
0.E+00
1.E-02
2.E-02
3.E-02
4.E-02
5.E-02
6.E-02
0.E+00 2.E-07 4.E -07 6.E-07 8.E-0 7 1.E-06 1.E- 06 1.E-06 2.E- 06 2.E-06 2.E- 06
Time (200 ns/d iv)
Output Voltage (10 mV/ d iv)
G = -1 V/V
RF = 1 kΩ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 5.E-07 1.E-0 6 2.E-06 2.E-06 3. E-06 3.E- 06 4.E-06 4.E-0 6 5.E-06 5.E- 06
Time (500 ns/div)
Output Voltage (V)
G = -1 V/V
RF = 1 kΩ
© 2009 Microchip Technology Inc. DS21685D-page 13
MCP6021/1R/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.5V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
RL=10kΩto VDD/2 and CL= 60 pF.
FIGURE 2-37: VREF Accuracy vs. Supp ly
Voltage (MCP6021 and MCP6023 only).
FIGURE 2-38: Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V.
FIGURE 2-39: Chip Select (CS) to
Amplifier Output Response Time (MCP6023
only).
FIGURE 2-40: VREF Accuracy vs.
Temperature (MCP6021 and MCP6023 only).
FIGURE 2-41: Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 5.5V.
FIGURE 2-42: Measured Input Current vs.
Input Voltage (below VSS).
-50
-40
-30
-20
-10
0
10
20
30
40
50
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
VREF Accuracy; VREF – VDD/2
(mV)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5
Chip Select Voltage (V)
Quiescent Current
(mA/amplifier)
Op Amp
shuts off here
Op Amp
turns on here
Hysteresis
VDD = 2.5V
G = +1 V/V
VIN = 1.25V
CS swept
low to high
CS swept
high to l o w
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05
Time (5 µs/div)
Chip Select Voltage,
Output Voltage (V)
Output High-Z
VDD = 5.0V
G = +1 V/V
VIN = VSS
Output
on
Output
on
VOUT
CS Voltage
-50
-40
-30
-20
-10
0
10
20
30
40
50
-50-250 255075100125
Ambient Temperature (°C)
VREF Accuracy; VREF – VDD/2
(mV)
VDD = 5.5V
VDD = 2.5V
Represen t at i v e Part
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current
(mA/amplifier)
Op Amp
shuts off here
Op Amp
turns on here
Hysteresis
CS swept
high to l o w CS swept
low to high
VDD = 5.5V
G = +1 V/V
VIN = 2.75V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
MCP6021/1R/2/3/4
DS21685D-page 14 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 15
MCP6021/1R/2/3/4
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The op amp output pins are low-impedance voltage
sources.
3.2 Analog Inputs
The op amp non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Reference Voltage (VREF, )
MCP6021 and MCP6023
Mid-supply reference voltage provided by the single op
amps (except in SOT-23-5 package). This is an
unbuffered, resistor voltage divider internal to the part.
3.4 Chip Select Digital Input (CS)
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.5 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 2.5V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a bypass capacitor.
MCP6021 MCP6021R MCP6022 MCP6023 MCP6024 Symbol Description
PDIP,
SOIC,
MSOP,
TSSOP
(Note 1)
SOT-23-5 SOT-23-5
(Note 2) PDIP,
SOIC,
TSSOP
PDIP,
SOIC,
TSSOP
PDIP,
SOIC,
TSSOP
6 1 1 161V
OUT,V
OUTA Analog Output (op amp A)
2 4 4 222V
IN–, VINA– Inverting Input (op amp A)
3 3 3 333V
IN+, VINA+ Non-inverting Input (op amp A)
7 5 2 874V
DD Positive Power Supply
—— — 5—5V
INB+ Non-inverting Input (op amp B)
—— — 6—6V
INB– Inverting Input (op amp B)
—— — 7—7V
OUTB Analog Output (op amp B)
—— ———8V
OUTC Analog Output (op amp C)
—— ———9V
INC– Inverting Input (op amp C)
—— ———10V
INC+ Non-inverting Input (op amp C)
42 54411V
SS Negative Power Supply
—— ———12V
IND+ Non-inverting Input (op amp D)
—— ———13V
IND– Inverting Input (op amp D)
—— ———14V
OUTD Analog Output (op amp D)
5— ——5—V
REF Reference Voltage
—— ——8—CSChip Select
1, 8 — — — 1 — NC No Internal Connection
Note 1: The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.
2: The MCP6021R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts.
MCP6021/1R/2/3/4
DS21685D-page 16 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 17
MCP6021/1R/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6021/1R/2/3/4 family of operational amplifiers
are fabricated on Microchip’s state-of-the-art CMOS
process. They are unity-gain stable and suitable for a
wide range of general-purpose applica tio ns.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERSAL
The MCP6021/1R/2/3/4 op amp is designed to prevent
phase reversal when the inpu t pins exceed the sup ply
voltages. Figure 2-42 shows the in put voltage exceed-
ing the supply voltage without any phase reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damag e and/or improper operation
of these op amps, the circuit they are in must li mit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electr ical Characteristics” ). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resi stors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-42. Applications that are
high impedance may need to limit th e useable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6021/1R/2/3/4 op amps use
two differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this topol-
ogy, the device operates with Vcm up to 0.3V above
VDD and 0.3V below VSS.
4.2 Rail-to-Rail Output
The Maximum Output Voltage Swing is the maximum
swing possible under a particular output load.
According to the specification table, the output can
reach within 20 mV of either supply rail when
RL=10kΩ. See Figure 2-31 and Figure 2-34 for more
information concerning typ ical performance.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed loop bandwidth is
reduced. This produce s gain-peaking in th e frequency
response, with overshoot and ringing in the step
response.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1
MCP602X
R1
VDD
D1
R1>VSS – (minimum expe cted V1)
2mA
R2>VSS – (minimum expe cted V2)
2mA
V2R2
D2
R3
MCP6021/1R/2/3/4
DS21685D-page 18 © 2009 Microchip Technology Inc.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
FIGURE 4-3: Output Resistor RISO
Stabilizes Large Cap acitive Loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-4: Recommended RISO values
for capacitive loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Evaluation on the bench and
simulations with the MCP6021/1R/2/3/4 Spice macro
model are helpful.
4.4 Gain Peaking
Figure 2-35 and Figure 2-36 use RF=1kΩ to avoid
(frequency response) gain peaking and (step
response) overshoot. The capacitance to ground at the
inverting input (CG) is the op amp’s common mode
input capacitance plus board pa rasitic capacit ance. CG
is in parallel with RG, which causes an increase in gain
at high frequencies for non-inverting gains greater than
1 V/V (unity gain). CG also reduces the phase margin
of the feedback loop for both non-inverting and
inverting gains.
FIGURE 4-5: Non-inverting Gain Circuit
with Parasitic Capacitance.
The largest value of RF in Figure 4-5 that should be
used is a function of noise gain (see GN in Section 4.3
“Capacitive Loads”) and CG. Figure 4-6 shows results
for various conditions. Other compensation techniques
may be used, but they tend to be more complicated to
the design.
FIGURE 4-6: Non-inverting gain circuit
with parasitic capacitance.
4.5 MCP6023 Chip Select (CS)
The MCP6023 is a single amplifier with chip select
(CS). When CS is pulled high, the supply current drops
to 10 nA (typical) an d flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pulldown resisto r connected to VSS, so it will go lo w if
the CS pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS pulse.
VIN
MCP602X RISO VOUT
CL
10
100
1,000
10 100 1,000 10,000
Normalized Capaci tance; CL/GN (pF)
Recommended RISO (Ω)
GN ≥ +1
VIN
RGRF
VOUT
CG
1.E+02
1.E+03
1.E+04
1.E+05
110
Noise Gain; GN (V/V)
Maximum RF (Ω)
GN > +1 V/V
100
1k
10k
100k
CG
= 7 pF
CG = 20 pF
CG = 50 pF
CG = 100 pF
© 2009 Microchip Technology Inc. DS21685D-page 19
MCP6021/1R/2/3/4
4.6 MCP6021 and MCP6023 Reference
Voltage
The single op a mps (MCP6021 and MCP6023), not in
the SOT-23-5 package, have an internal mid-supply
reference voltage connected to the VREF pin (see
Figure 4-7). The MCP6021 has CS internally tied to
VSS, which always keeps the op amp on and always
provides a mid-supply reference. With the MCP6023,
taking the CS pin high conserves power by shutting
down both the op amp and the VREF circuitry. Taking
the CS pin low turns on the op amp and VREF circuitry.
FIGURE 4-7: Simplified internal VREF
circuit (MCP6021 and MCP6023 only).
See Figure 4-8 for a non-inverting gain circuit using the
internal mid-supply reference. The DC-blocking
capacitor (CB) also reduces noise by coupling the op
amp input to the source.
FIGURE 4-8: Non-inverting gain circuit
using VREF (MCP602 1 and M C P6 02 3 on ly) .
To use the internal mid-supply reference for an
inverting gain circuit, connect the VREF pin to the
non-inverting input, as shown in Figure 4-9. The
capacitor CB helps reduce power supply noise on the
output.
FIGURE 4-9: Inverting gain circuit using
VREF (MCP6021 and MCP6023 only).
If you don’t need the mid-supply reference, leave the
VREF pin open.
4.7 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single sup ply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.8 Unused Op Amps
An unused op amp in a quad package (MCP6024)
should be configured as shown in Figure 4-10. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-10: Unused Op Amps.
VDD
VSS
VREF
CS
50 kΩ
50 kΩ
(CS tied internally to VSS for MCP6021)
5MΩ
VIN
RGRF
VOUT
CBVREF
VIN
RGRFVOUT
VREF
CB
VDD
VDD
¼ MCP6024 (A) ¼ MCP6024 (B)
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
-------------------
×=
MCP6021/1R/2/3/4
DS21685D-page 20 © 2009 Microchip Technology Inc.
4.9 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6021/1R/2/3/4 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
Figure 4-11 shows an examp l e of thi s typ e of layout.
FIGURE 4-11: Example Guard Ring
Layout.
1. Non-inverting Gain and Unity-Gain Buffer.
a) Connect the guard ring to the inverting input
pin (VIN–); this biases the guard ring to the
common mode input voltage.
b) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
2. Inverting (Figure 4-11) and Transimpedance
Gain Amplifiers (convert current to voltage, such
as photo detectors).
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp’s input (e.g., VDD/2 or ground).
b) Conne ct the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.10 High Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a
significant difference in the performance of these op
amps. Good PC board layout techniques w ill help you
achieve the performance shown in Section 1.0 “Elec-
trical Characteristics” and Section 2.0 “T ypical Per-
formance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low speed from high
speed and low power from high power . This will reduce
interference.
Keep sensitive traces short and straight. Separating
them from interfering components and traces. This is
especially important for high-frequency (low rise-time)
signals.
Sometimes it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect the guard
trace to ground plane at both ends, and in the middle
for long traces.
Use coax cables (or low inductance wiring) to route
signal and power to and from the PCB.
4.11 Typical Applications
4.11.1 A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
Figure 4-12 shows a third-order Butterworth filter that
can be used as an A/D converter driver. It has a ba nd-
width of 20 kHz and a reasonable step response. It will
work well for conversion rates of 80 ksps and greater (it
has 29 d B attenuation at 60 kHz).
FIGURE 4-12: A/D Converter Driver and
Anti-aliasing Filter with a 20 kHz Cutoff
Frequency.
This filter can easil y be adjusted to another bandwidth
by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
Guard Ring VIN–V
IN+
14.7 kΩ33.2 kΩ
1.0 nF
100 pF
MCP602X
8.45 kΩ
1.2 nF
© 2009 Microchip Technology Inc. DS21685D-page 21
MCP6021/1R/2/3/4
4.11.2 OPTICAL DETECTOR AMPLIFIER
Figure 4-13 shows the MCP6021 op amp used as a
transimpedance amplifier in a photo detector circuit.
The photo detector looks like a capacitive current
source, so the 100 kΩ resistor gains the input signal to
a reasonable level. The 5.6 pF capacitor stabilizes this
circuit and produces a flat frequency response with a
bandwidth of 370 kHz.
FIGURE 4-13: Transimpedance Amplifier
for an Optical Detector.
Photo
Detector
100 pF
5.6 pF
100 kΩ
VDD/2
MCP6021
MCP6021/1R/2/3/4
DS21685D-page 22 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 23
MCP6021/1R/2/3/4
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6021/1R/2/3/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model available for the
MCP6021/1R/2/3/4 op amps is on Microchip’s web site
at www.microchip.com. This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. Within the
macro model file is information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.micro chip.com/filterl ab, the
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, whic h can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4 Microchip Advanced Pa rt Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards and their corresponding user ’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
Some boards that are especially useful are:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
•8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N: SOIC8EV
•14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N: SOIC14EV
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended a s supplemental ref-
erence resources.
•ADN003: “Select the Right Operational Amp lifier
for your Filtering Circuits”, DS21821
•AN722: “Operational Amplifier T opologies and DC
Specifications”, DS00722
•AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
•AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
•AN990: “Analog Se nsor Conditioning Circuits –
An Overview”, DS00990
•AN1177: “Op Amp Prec ision Design: DC Errors”,
DS01177
•AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP6021/1R/2/3/4
DS21685D-page 24 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 25
MCP6021/1R/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SOT-23 ( MCP6021/MCP6021R)Example: (E-temp)
XXNN EY25
Device E-Temp Code
MCP6021 EYNN
MCP6021R EZNN
Note: Applies to 5-Lead SOT-23
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
MCP6021
I/P256
0903
MCP6021
E/P^^256
0903
OR
3
e
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6021
I/SN0903
256
MCP6021E
SN^^0903
256
OR
3
e
8-Lead MSOP Example:
XXXXXX
YWWNNN
6021E
903256
8-Lead TSSOP Example:
XXXX
YYWW
NNN
6021
E903
256
MCP6021/1R/2/3/4
DS21685D-page 26 © 2009 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6024) Example:
14-Lead TSSOP (MCP6024) Example:
14-Lead SOIC (150 mil) (MCP6024) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6024-I/P
XXXXXXXXXXXXXX
0903256
6024E
0903
256
XXXXXXXXXX MCP6024ISL
0903256
XXXXXXXXXX
MCP6024
E/P^^
0903256
OR
MCP6024
0903256
E/SL^^
OR
3
e
3
e
© 2009 Microchip Technology Inc. DS21685D-page 27
MCP6021/1R/2/3/4
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MCP6021/1R/2/3/4
DS21685D-page 28 © 2009 Microchip Technology Inc.
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© 2009 Microchip Technology Inc. DS21685D-page 29
MCP6021/1R/2/3/4
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".+ % 0$ $-#$##0%%#$  
 .# #$#/!- 0  #1/%##!#
##+22---2/
3# 44""
 4# 5 56 7
5$8%1 5 ;
1# )*
6,9# : : (
!!1//  ( : :
#!%%
?
  : (
6,<!# " =)*
!!1/<!# " )*
6,4# )*
*%A#B ( : (
.#4# 4  : 
.## 4 ".
.# > : ;>
4!/  : (
4!<!# 8  : (
!%# (> : (>
!%#)## (> : (>
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
  - *()
MCP6021/1R/2/3/4
DS21685D-page 30 © 2009 Microchip Technology Inc.
"&'()#$%!*
 .# #$#/!- 0  #1/%##!#
##+22---2/
© 2009 Microchip Technology Inc. DS21685D-page 31
MCP6021/1R/2/3/4
+,-++

 1, $!&%#$,08$#$ #8#!-###!
   !"!#$!!% #$  !% #$   #&!( !
  !#"'(
)*+ )  #&#,$ --#$## 
".+ % 0$ $-#$##0%%#$  
 .# #$#/!- 0  #1/%##!#
##+22---2/
3# 44""
 4# 5 56 7
5$8%1 5 ;
1# =()*
6,9# : : 
!!1//  ( ;( (
#!%%   : (
6,<!# " )*
!!1/<!# " )*
6,4# )*
.#4# 4  = ;
.## 4 (".
.# I> : ;>
4!/ ; : 
4!<!# 8  : 
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
  - *)
MCP6021/1R/2/3/4
DS21685D-page 32 © 2009 Microchip Technology Inc.
./ !"##$% !

 1, $!&%#$,08$#$ #8#!-###!
 ?%#*# #
   !"!#$!!% #$  !% #$   #&!@ !
  !#"'(
)*+)  #&#,$ --#$## 
 .# #$#/!- 0  #1/%##!#
##+22---2/
3# 5*9"
 4# 5 56 7
5$8%1 5 
1# )*
##1 : : 
!!1//  (  (
) ##1  ( : :
$!#$!<!# "   (
!!1/<!# "  ( ;
6,4# ( ( (
##1 4 (  (
4!/ ;  (
34!<!# 8 ( = 
4-4!<!# 8  ; 
6,-? ) : : 
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1
b1
be
  - *()
© 2009 Microchip Technology Inc. DS21685D-page 33
MCP6021/1R/2/3/4
./"&'()#$%!*

 1, $!&%#$,08$#$ #8#!-###!
 ?%#*# #
   !"!#$!!% #$  !% #$   #&!( !
  !#"'(
)*+ )  #&#,$ --#$## 
".+ % 0$ $-#$##0%%#$  
 .# #$#/!- 0  #1/%##!#
##+22---2/
3# 44""
 4# 5 56 7
5$8%1 5 
1# )*
6,9# : : (
!!1//  ( : :
#!%%?   : (
6,<!# " =)*
!!1/<!# " )*
6,4# ;=()*
*%A#B ( : (
.#4# 4  : 
.## 4 ".
.# I> : ;>
4!/  : (
4!<!# 8  : (
!%# D(> : (>
!%#)## E(> : (>
NOTE 1
N
D
E
E1
123
b
e
A
A1
A2
L
L1
c
h
hα
β
φ
  - *=()
MCP6021/1R/2/3/4
DS21685D-page 34 © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. DS21685D-page 35
MCP6021/1R/2/3/4
./00,"/(/$%

 1, $!&%#$,08$#$ #8#!-###!
   !"!#$!!% #$  !% #$   #&!( !
  !#"'(
)*+ )  #&#,$ --#$## 
".+ % 0$ $-#$##0%%#$  
 .# #$#/!- 0  #1/%##!#
##+22---2/
3# 44""
 4# 5 56 7
5$8%1 5 
1# =()*
6,9# : : 
!!1//  ;  (
#!%%  ( : (
6,<!# " =)*
!!1/<!# "   (
!!1/4#  ( (
.#4# 4 ( = (
.## 4 ".
.# I> : ;>
4!/  : 
4!<!# 8  : 
NOTE 1
D
N
E
E1
12
e
b
c
A
A1
A2
L1 L
φ
  - *;)
MCP6021/1R/2/3/4
DS21685D-page 36 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 37
MCP6021/1R/2/3/4
APPENDIX A: REVISION HISTORY
Revision D (February 2009)
The following is the list of modificatio ns:
1. Changed all references to 6.0V back to 5.5V
throughout document.
2. Design Aids: Name change for Mindi Simula-
tion Tool.
3. Section 1.0 “Electrical Characteristics”, DC
Electrical Specifications: Corrected “Maxi-
mum Output V oltage Swing” condition from 0.9V
Input Overdrive to 0.5V Input Overdrive.
4. Section 1.0 “Electrical Characteristics”, AC
Electrical Specifications: Changed Phase
Margin condition from G = +1 to G= +1 V/V.
5. Section 1.0 “Electrical Characteristics”, AC
Electrical Specifications: Changed Settling
T ime, 0.2% condition from G = +1 to G = +1 V/V.
6. Section 1.0 “Electrical Characteristics”:
Added Section 1.1 Test Circuits.
7. Section 5.0 “Desig n AIDS”: Name change for
Mindi Simulation Tool. Added new boards to
Section 5.5 “Analog Demonstration and
Evaluation Boards” and new application notes
to Section 5.6 “Application Notes”.
8. Updates Append ix A: “Revision History”
Revision C (March 2006)
The following is the list of modificatio ns:
1. Added SOT-23-5 package option for single op
amps MCP6021 and MCP6021R (E-temp only).
2. Added MSOP-8 package option for E-temp
single op amp (MCP6021).
3. Corrected package drawing on front page for
dual op amp (MCP6022).
4. Clarified spe c conditions (ISC, PM and THD+N)
in Section 2.0 “Typical Performance
Curves”.
5. Added Section 3.0 “Pin Descriptions”.
6. Updated Section 4.0 “Applications informa-
tion” for THD+N, unused op amps, and gain
peaking discussions.
7. Corrected and updated package marking infor-
mation in Section 6.0 “Packaging Informa-
tion”.
8. Added Appendix A: “Revision History” .
Revision B (November 2003)
• Second Release of this Document
Revision A (November 2001)
• Original Release of this Document.
MCP6021/1R/2/3/4
DS21685D-page 38 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 39
MCP6021/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information , e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6021 Single Op Amp
MCP6021T Single Op Amp
(Tape and Reel for SOT-23, SOIC, TSSOP,
MSOP)
MCP6021R Single Op Amp
MCP6021RT Single Op Amp
(Tape and Reel for SOT-23)
MCP6022 Dual Op Amp
MCP6022T Dual Op Amp
(Tape and Reel for SOIC and TSSOP)
MCP6023 Single Op Amp w/ CS
MCP6023T Single Op Amp w/ CS
(Tape and Reel for SOIC and TSSOP)
MCP6024 Quad Op Amp
MCP6024T Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6021, E-Temp; MCP6021R, E-Temp)
MS = Plastic MSOP, 8-lead
(MCP6021, E-Temp)
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP, 8-lead
(MCP6021,I-Temp; MCP6022, I-Temp, E-Temp;
MCP6023, I-Temp, E-Temp;)
ST = Plastic TSSOP, 14-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6021T-E/OT: Tape and Reel,
Extended temperature,
5LD SOT-23.
b) MCP6021-E/P: Extended temperature,
8LD PDIP.
c) MCP6021-E/SN: Extended temperature,
8LD SOIC.
a) MCP6021RT-E/OT:Tape and Reel,
Extended temperature,
5LD SOT-23.
a) MCP6022-I/P: Industrial temperature,
8LD PDIP.
b) MCP6022-E/P: Extended temperature,
8LD PDIP.
c) MCP6022T-E/ST: Tape and Reel,
Extended temperature,
8LD TSSOP.
a) MCP6023-I/P: Industrial temperature,
8LD PDIP.
b) MCP6023-E/P: Extended temperature,
8LD PDIP.
c) MCP6023-E/SN: Extended temperature,
8LD SOIC.
a) MCP6024-I/SL: Industrial temperature,
14LD SOIC.
b) MCP6024-E/SL: Extended temperature,
14LD SOIC.
c) MCP6024T-E/ST: Tape and Reel,
Extended temperature,
14LD TSSOP.
MCP6021/1R/2/3/4
DS21685D-page 40 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21685D-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21685D-page 42 © 2009 Microchip Technology Inc.
AMERICAS
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Tel: 480-792-7200
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Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
02/04/09