DS90CF364A, DS90CF384A
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SNLS040I –JUNE 2000–REVISED APRIL 2013
DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65
MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz
Check for Samples: DS90CF364A,DS90CF384A
1FEATURES DESCRIPTION
The DS90CF384A receiver converts the four LVDS
2• 20 to 65 MHz Shift Clock Support data streams (Up to 1.8 Gbps throughput or 227
• 50% Duty Cycle on Receiver Output Clock Megabytes/sec bandwidth) back into parallel 28 bits
• Best-in-Class Set & Hold Times on of CMOS/TTL data (24 bits of RGB and 4 bits of
RxOUTPUTs Hsync, Vsync, DE and CNTL). Also available is the
DS90CF364A that converts the three LVDS data
• Rx Power Consumption <142 mW (typ) streams (Up to 1.3 Gbps throughput or 170
@65MHz Grayscale Megabytes/sec bandwidth) back into parallel 21 bits
• Rx Power-down Mode <200μW (max) of CMOS/TTL data (18 bits of RGB and 3 bits of
• ESD Rating >7 kV (HBM), >700V (EIAJ) Hsync, Vsync and DE). Both Receivers' outputs are
Falling edge strobe. A Rising edge or Falling edge
• Supports VGA, SVGA, XGA and Dual Pixel strobe transmitter (DS90C383A/DS90C363A) will
SXGA. interoperate with a Falling edge strobe Receiver
• PLL Requires no External Components without any translation logic.
• Compatible with TIA/EIA-644 LVDS Standard The DS90CF384A / DS90CF364A devices are
• Low Profile 56-lead or 48-lead Packages enhanced over prior generation receivers and
provided a wider data valid time on the receiver
output.
This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
TTL interfaces.
BLOCK DIAGRAMS
Figure 1. DS90CF384A Figure 2. DS90CF364A
DGG-56 (TSSOP) DGG-48 (TSSOP)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90CF364A, DS90CF384A
SNLS040I –JUNE 2000–REVISED APRIL 2013
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Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)−0.3V to +4V
CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V)
CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V)
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4 sec) +260°C
Solder Reflow Temperature (20 sec for FBGA) +220°C
DGG-56 (TSSOP) Package 1.61 W
DS90CF384A
Maximum Package Power Dissipation
Capacity @ 25°C DGG-48 (TSSOP) Package 1.89 W
DS90CF364A
Package Derating DS90CF384AMTD 12.4 mW/°C above +25°C
DS90CF364AMTD 15 mW/°C above +25°C
ESD Rating (HBM, 1.5 kΩ, 100 pF) > 7 kV
(EIAJ, 0Ω, 200 pF) > 700V
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply
that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Recommended OperatingConditions Min Nom Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air Temperature (TA)−10 +25 +70 °C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (VCC) 100 mVPP
Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS (For Power Down Pin)
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
VCL Input Clamp Voltage ICL =−18 mA −0.79 −1.5 V
IIN Input Current V IN = 0.4V, 2.5V or VCC +1.8 +10 μA
VIN = GND −10 0 μA
CMOS/TTL DC SPECIFICATIONS
VOH High Level Output Voltage IOH =−0.4 mA 2.7 3.3 V
VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V
IOS Output Short Circuit Current VOUT = 0V −60 −120 mA
(1) Typical values are given for VCC = 3.3V and TA= +25C.
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SNLS040I –JUNE 2000–REVISED APRIL 2013
Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVDS RECEIVER DC SPECIFICATIONS
VTH Differential Input High Threshold V CM = +1.2V +100 mV
VTL Differential Input Low Threshold −100 mV
IIN Input Current V IN = +2.4V, VCC = 3.6V ±10 μA
VIN = 0V, VCC = 3.6V ±10 μA
RECEIVER SUPPLY CURRENT(2)
ICCRW Receiver Supply Current Worst Case CL= 8 pF, f = 32.5 MHz 49 65 mA
Worst Case Pattern, f = 37.5 MHz 53 70 mA
DS90CF384A (Figure 3 f = 65 MHz 81 105 mA
Figure 6)
ICCRW Receiver Supply Current Worst Case CL= 8 pF, f = 32.5 MHz 49 55 mA
Worst Case Pattern, f = 37.5 MHz 53 60 mA
DS90CF364A (Figure 3 f = 65 MHz 78 90 mA
Figure 6)
ICCRG Receiver Supply Current, 16 Grayscale CL= 8 pF, f = 32.5 MHz 28 45 mA
16 Grayscale Pattern, f = 37.5 MHz 30 47 mA
(Figure 4 Figure 5 Figure 6)f = 65 MHz 43 60 mA
ICCRZ Receiver Supply Current Power Down = Low 10 55 μA
Power Down Receiver Outputs Stay Low during
Power Down Mode
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except VOD and ΔVOD).
Receiver Switching Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 6) 2 5 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 6) 1.8 5 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13, f = 25 MHz 1.20 1.96 2.82 ns
Figure 14)
RSPos1 Receiver Input Strobe Position for Bit 1 6.91 7.67 8.53 ns
RSPos2 Receiver Input Strobe Position for Bit 2 12.62 13.38 14.24 ns
RSPos3 Receiver Input Strobe Position for Bit 3 18.33 19.09 19.95 ns
RSPos4 Receiver Input Strobe Position for Bit 4 24.04 24.80 25.66 ns
RSPos5 Receiver Input Strobe Position for Bit 5 29.75 30.51 31.37 ns
RSPos6 Receiver Input Strobe Position for Bit 6 35.46 36.22 37.08 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 13, f = 65 MHz 0.7 1.1 1.4 ns
Figure 14)
RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns
RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns
RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns
RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns
RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns
RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns
RSKM RxIN Skew Margin (2) (Figure 15) f = 25 MHz 750 ps
f = 65 MHz 500 ps
(1) Typical values are given for VCC = 3.3V and TA= +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window -
RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
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Receiver Switching Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
RCOP RxCLK OUT Period (Figure 7) 15 T 50 ns
RCOH RxCLK OUT High Time (Figure 7) f = 65 MHz 5.0 7.6 9.0 ns
RCOL RxCLK OUT Low Time (Figure 7) 5.0 6.3 9.0 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 7) 4.5 7.3 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 7) 4.0 6.3 ns
RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 8) 3.5 5.0 7.5 ns
RPLLS Receiver Phase Lock Loop Set (Figure 9) 10 ms
RPDD Receiver Power Down Delay (Figure 12 ) 1 μs
AC Timing Diagrams
Figure 3. “Worst Case” Test Pattern
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SNLS040I –JUNE 2000–REVISED APRIL 2013
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 4. “16 Grayscale” Test Pattern (DS90CF384A)
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Product Folder Links: DS90CF364A DS90CF384A
f
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
HSYNC
VSYNC
ENA
Device Pin Name Signal Signal Pattern Signal Frequency
DS90CF364A, DS90CF384A
SNLS040I –JUNE 2000–REVISED APRIL 2013
www.ti.com
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
(2) The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
(3) Figure 3 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
(4) Recommended pin to signal mapping. Customer may choose to define differently.
Figure 5. “16 Grayscale” Test Pattern (DS90CF364A)
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SNLS040I –JUNE 2000–REVISED APRIL 2013
Figure 6. DS90CF384A/DS90CF364A (Receiver) CMOS/TTL Output Load and Transition Times
Figure 7. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times
Figure 8. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay
Figure 9. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time
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Figure 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A
Figure 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A
Figure 12. DS90CF384A/DS90CF364A (Receiver) Power Down Delay
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Figure 14. DS90CF364A (Receiver) LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(1) + ISI (Inter-symbol interference)(2)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 15. Receiver LVDS Input Skew Margin
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SNLS040I –JUNE 2000–REVISED APRIL 2013
DS90CF384A PIN DESCRIPTIONS — 56 Lead TSSOP Package — 24-Bit FPD Link Receiver
Pin Name I/O No. Description
RxIN+ I 4 Positive LVDS differentiaI data inputs.
RxIN−I 4 Negative LVDS differential data inputs.
RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN−I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
VCC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL VCC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS VCC I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
DS90CF364A PIN DESCRIPTIONS — 48 Lead TSSOP Package — 18-Bit FPD Link Receiver
Pin Name I/O No. Description
RxIN+ I 3 Positive LVDS differentiaI data inputs.
RxIN−I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN−I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe.
PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
VCC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL VCC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS VCC I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
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Pin Diagram for TSSOP Packages
Figure 16. DS90CF384A Figure 17. DS90CF364A
DGG-56 Package DGG-48 Package
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SNLS040I –JUNE 2000–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90CF364AMTD NRND TSSOP DGG 48 38 TBD Call TI Call TI -10 to 70 DS90CF364AMTD
>B
DS90CF364AMTD/NOPB ACTIVE TSSOP DGG 48 38 Green (RoHS
& no Sb/Br) SN Level-2-260C-1 YEAR -10 to 70 DS90CF364AMTD
>B
DS90CF364AMTDX NRND TSSOP DGG 48 1000 TBD Call TI Call TI -10 to 70 DS90CF364AMTD
>B
DS90CF364AMTDX/NOPB ACTIVE TSSOP DGG 48 1000 Green (RoHS
& no Sb/Br) SN Level-2-260C-1 YEAR -10 to 70 DS90CF364AMTD
>B
DS90CF384AMTD/NOPB ACTIVE TSSOP DGG 56 34 Green (RoHS
& no Sb/Br) SN Level-2-260C-1 YEAR -10 to 70 DS90CF384AMTD
>B
DS90CF384AMTDX/NOPB ACTIVE TSSOP DGG 56 1000 Green (RoHS
& no Sb/Br) SN Level-2-260C-1 YEAR -10 to 70 DS90CF384AMTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90CF364AMTDX TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1
DS90CF364AMTDX/NOP
BTSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1
DS90CF384AMTDX/NOP
BTSSOP DGG 56 1000 330.0 24.4 8.6 14.5 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90CF364AMTDX TSSOP DGG 48 1000 367.0 367.0 45.0
DS90CF364AMTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0
DS90CF384AMTDX/NOPB TSSOP DGG 56 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
8.3
7.9
1.2 MAX
54X 0.5
56X 0.27
0.17
2X
13.5
(0.15) TYP
0 - 8
0.15
0.05
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
14.1
13.9
B6.2
6.0
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
156
0.08 C A B
29
28
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
56X (1.5)
56X (0.3)
54X (0.5)
(R )
TYP
0.05
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
28 29
56
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(7.5)
54X (0.5)
56X (0.3)
56X (1.5)
(R ) TYP0.05
4222167/A 07/2015
TSSOP - 1.2 mm max heightDGG0056A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
28 29
56
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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