DSC6102MI2A-052.0000T - MICROCHIP TECHNOLOGY

 2017 Microchip Technology Inc. DS20005624B-page 1

DSC61XX

Features

• Wide Frequency Range: 2 kHz to 100 MHz

• Ultra-Low Power Consumption: 3 mA/12 µA

(Active/Standby)

• Ultra-Small Footprints

-1.6mm

1.2 mm

-2.0mm

1.6 mm

-2.5mm2.0 mm

-3.2mm

2.5 mm

• Frequency Select Input Supports Two

Pre-Defined Frequencies

• High Stability: ±25 ppm, ±50 ppm

• Wide Temperature Range

- Industrial: –40°C to 85°C

- Ext. Commercial: –20° to 70°C

• Excellent Shock and Vibration Immunity

- Qualified to MIL-STD-883

• High Reliability

- 20x Better MTF Than Quartz Oscillators

• Supply Range of 1.71V to 3.63V

• Short Sample Lead Time: <2 weeks

• Lead Free & RoHS Compliant

Applications

• Low Power/Portable Applications: IoT,

Embedded/Smart Devices

• Consumer: Home Healthcare, Fitness Devices,

Home Automation

• Automotive: Rear View/Surround View Cameras,

Infotainment System

• Industrial: Building/Factory Automation,

Surveillance Camera

General Description

The DSC61xx family of MEMS oscillators combines the

industry leading low power consumption and

ultra-small packages with exceptional frequency

stability and jitter performance over temperature. The

single-output DSC61xx MEMS oscillators are excellent

choices for use as clock references in small,

battery-powered devices such as wearable and

Internet of Things (IoT) devices in which small size, low

power consumption, and long-term reliability are

paramount. They also meet the stringent mechanical

durability and reliability requirements within Automotive

Electronics Council standard Q100 (AEC-Q100), so

they are well suited for under-hood applications as well.

The DSC61xx family is available in ultra-small

1.6 mm x 1.2 mm and 2.0 mm x 1.6 mm packages.

Other package sizes include: 2.5 mm x 2.0 mm and

3.2 mm x 2.5 mm. These packages are “drop-in”

replacements for standard 4-pin CMOS quartz crystal

oscillators.

Package Types

DSC61XX

3.2 mm x 2.5 mm DFN

2.5 mm x 2.0 mm LGA

2.0 mm x 1.6 mm LGA

1.6 mm x 1.2 mm LGA

(Top View)

OE/STBY/FS

GND

VDD

OUT

Ultra-Small, Ultra-Low Power MEMS Oscillator

DSC61XX

DS20005624B-page 2  2017 Microchip Technology Inc.

Block Diagram

DSC6101/02/11/12/21/22/41/42/51/52/61/62

DSC6183 (kHz Output)

MEMS

RESONATOR

TEMP SENSOR

CONTROL &

COMPENSATION

PLL

VCO OUTPUT

DIVIDER DRIVER

SUPPLY

REGULATION

PIN 1

OE/STBY/FS

PIN 2

GND

PIN 4

VDD

PIN 3

OUTPUT

DIGITAL

CONTROL

MEMS

RESONATOR

TEMP SENSOR

CONTROL &

COMPENSATION

PLL

VCO OUTPUT

DIVIDER

SUPPLY

REGULATION

OUTPUT

GND

VDD

DNC

DRIVER

 2017 Microchip Technology Inc. DS20005624B-page 3

DSC61XX

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Supply Voltage .......................................................................................................................................... –0.3V to +4.0V

Input Voltage (VIN) ..............................................................................................................................–0.3V to VDD+0.3V

ESD Protection ............................................................................................................ 4 kV HBM, 400V MM, 2 kV CDM

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to 85°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Supply Voltage, Note 1 VDD 1.71 — 3.63 V —

Power Supply Ramp tPU 0.1 — 100 ms Note 8

Active Supply Current IDD —3.0 — mA

FOUT = 27 MHz, VDD = 1.8V,

No Load

Standby Supply Current

Note 2 ISTBY

—12 — µA VDD = 1.8/2.5V

—80 — V

DD = 3.3V

Frequency Stability Note 3 f——

±25

±50 ppm All temp ranges

Aging f—— ±5 ppm 1st year @ 25°C

— — ±1 Per year after first year

Startup Time tSU —— 1.3 ms

From 90% VDD to valid clock

output, T = 25°C

Input Logic Levels Note 4 VIH 0.7 x VDD — — V Input Logic High

VIL — — 0.3 x VDD V Input Logic Low

Output Disable Time

Note 5 tDA — — 200+Period ns —

Output Enable Time

Note 6 tEN —— 1 µs —

Enable Pull-up Resistor

Note 7 ——300—kIf configured

Output Logic Levels

VOH 0.8 x VDD —— V

Output Logic High, I = 3 mA,

Std. Drive

Output Logic High, I = 6 mA,

High Drive

VOL — — 0.2 x VDD V

Output Logic Low, I = –3 mA,

Std. Drive

Output Logic Low, I = –3 mA,

High Drive

Note 1: Pin 4 VDD should be filtered with 0.1 µF capacitor.

2: Not including current through pull-up resistor on EN pin (if configured). Higher standby current seen at

>3.3V VDD.

3: Includes frequency variations due to initial tolerance, temp. and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to one period of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

DSC61XX

DS20005624B-page 4  2017 Microchip Technology Inc.

Output Transition Time

Rise Time/Fall Time

tRX/tFX

—1 1.5 ns

DSC61x2

High Drive,

20% to 80%

CL = 15 pF

VDD = 1.8V

—0.5 1.0 ns V

DD = 2.5V/3.3V

tRY/tFY

—1.2 2.0 ns

DSC61x1

Std Drive,

20% to 80%

CL = 10 pF

VDD = 1.8V

—1.5 2.2 ns V

DD = 2.5V/3.3V

Frequency f00.002 — 100 MHz Output on Pin 1 for < 1 MHz

Output Duty Cycle SYM 45 — 55 % —

Period Jitter, RMS JPER

—9.5 11psRMS

FOUT =

27 MHz

VDD = 1.8V

—7.5 9 V

DD = 2.5V/3.3V

Cycle-to-Cycle Jitter

(peak) JCy–Cy

—50 70 ps FOUT =

27 MHz

VDD = 1.8V

—35 60 V

DD = 2.5V/3.3V

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to 85°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: Pin 4 VDD should be filtered with 0.1 µF capacitor.

2: Not including current through pull-up resistor on EN pin (if configured). Higher standby current seen at

>3.3V VDD.

3: Includes frequency variations due to initial tolerance, temp. and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to one period of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

 2017 Microchip Technology Inc. DS20005624B-page 5

DSC61XX

TEMPERATURE SPECIFICATIONS (Note 1)

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Junction Operating Temperature TJ— — +150 °C —

Ambient Operating Temperature TA–40 — +85 °C Industrial

Ambient Operating Temperature TA–20 — +70 °C Extended Commercial

Storage Ambient Temperature Range TA–55 — +150 °C —

Soldering Temperature TS— +260 — °C 40 sec. max.

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the max-

imum allowable power dissipation will cause the device operating junction temperature to exceed the max-

imum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability.

DSC61XX

DS20005624B-page 6  2017 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1 and Table 2-2.

Note 1: DSC610x/1x/2x has 300 k internal pull-up resistor on pin1. DSC614x/5x/6x has no internal pull-up resistor

on pin1 and needs external pull-up or being driven by other chip.

2: Two pre-programmed frequencies can be configured at http://clockworks.microchip.com/timing/

3: Bypass with 0.1 µF capacitor placed as close to VDD pin as possible.

Note 1: Bypass with 0.1 µF capacitor placed as close to VDD pin as possible.

2.1 Output Buffer Options

DSC61xx family is available in multiple output driver configurations.

The standard-drive (61x1) and high-drive (61x2) deliver respective output currents of greater than 3 mA and 6 mA at

20%/80% of the supply voltage. For heavy loads of 15 pF or higher, the high-drive option is recommended.

TABLE 2-1: DSC6101/02/11/12/21/22/41/42/51/52/61/62 PIN FUNCTION TABLE (OUTPUT

FREQUENCY ≥1MHZ)

Pin Number Pin Name Pin Type Description

Output Enable: H = Specified Frequency Output, Note 1

L = Output is high impedance

STBY

Standby: H = Specified Frequency Output, Note 1

L = Output is high impedance. Device is in low power

mode, supply current is at ISTBY

FS Frequency Select: H = Output Frequency 1, Note 2

L = Output Frequency 2

2 GND Power Power supply ground

3 Output O Oscillator clock output

4 VDD Power Power supply

TABLE 2-2: DSC6183 PIN FUNCTION TABLE (OUTPUT FREQUENCY <1 MHZ)

Pin Number Pin Name Pin Type Description

1 Output O Kilohertz Oscillator clock output

2 GND Power Power supply ground

3 DNC DNC Do Not Connect

4 VDD Power Power supply, Note 1

 2017 Microchip Technology Inc. DS20005624B-page 7

DSC61XX

3.0 DIAGRAMS

FIGURE 3-1: Output Waveform.

FIGURE 3-2: Test Circuit.

FIGURE 3-3: Recommended Board Layout.

VOH

VOL

VIL

1/fo

OUTPU

ENABLE

tDA

tEN

VIH

VDD 0.1μF

VDA

IDD

VDD

GND

Enable

Output

Via to GND Layer

DSC61XX

DS20005624B-page 8  2017 Microchip Technology Inc.

4.0 SOLDER REFLOW PROFILE

FIGURE 4-1: Solder Reflow Profile.

60-180

Seconds

Temperature (°C)

260

°C

C/sec max.

217

°C

200

°C

150

°C

8 minutes max.

Pre-Heat

C/sec max.

Reflow

Cool

Time

C/sec max.

60-150

Seconds

20-40

Seconds

MSL 1 @ 260°C refer to JSTD-020C

Ramp-Up Rate (200°C to Peak Temp) 3°C/sec. max.

Preheat Time 150°C to 200°C 60 to 180 sec.

Time maintained above 217°C 60 to 150 sec.

Peak Temperature 255°C to 260°C

Time within 5°C of actual Peak 20 to 40 sec.

Ramp-Down Rate 6°C/sec. max.

Time 25°C to Peak Temperature 8 minutes max.

 2017 Microchip Technology Inc. DS20005624B-page 9

DSC61XX

5.0 PACKAGING INFORMATION

4-Lead VFLGA 1.6 mm x 1.2 mm Package Outline

0.07 C A B

0.03 C

(DATUM B)

(DATUM A)

SEATING

PLANE

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

0.10 C

0.08 C

Microchip Technology Drawing C04-1199A Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

4-Lead Very Thin Fine Pitch Land Grid Array (ARA) - 1.6x1.2 mm Body [VFLGA]

0.05 C

4X L

(A3)

3X b1

DSC61XX

DS20005624B-page 10  2017 Microchip Technology Inc.

4-Lead VFLGA 1.6 mm x 1.2 mm Package Outline

Microchip Technology Drawing C04-1199A Sheet 2 of 2

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

4-Lead Very Thin Fine Pitch Land Grid Array (ARA) - 1.6x1.2 mm Body [VFLGA]

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Overall Width

Terminal Length

Substrate Thickness (with Terminals)

Terminal Pitch

Standoff

Units

Dimension Limits

1.20 BSC

0.20 REF

0.325

0.30

0.79

0.00

0.35

0.375

0.84

0.02

1.20 BSC

MILLIMETERS

MIN NOM

0.425

0.40

0.89

0.05

MAX

CH 0.125--Terminal 1 Index Chamfer

Overall Length D 1.60 BSC

Terminal Width

b1 0.25 0.30 0.35Terminal Width

Terminal Pitch e1 0.75 BSC

 2017 Microchip Technology Inc. DS20005624B-page 11

DSC61XX

4-Lead VFLGA 1.6 mm x 1.2 mm Recommended Land Pattern

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Contact Width

Contact Pitch

MILLIMETERS

1.20 BSC

MIN

MAX

Space Between Contacts (X4)

Contact Pad Length (X6)

Y0.50

Microchip Technology Drawing C04-3199A

NOM

4-Lead Very Thin Fine Pitch Land Grid Array (ARA) - 1.6x1.2 mm Body [VFLGA]

SILK SCREEN

X1Contact Width (X3)

Space Between Contacts (X3) G2 0.25

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

(CH)

CContact Spacing 0.75

0.43

0.35

0.85

Contact 1 Index Chamfer CH 0.13 X 45° REF

Contact Pitch 1.16 BSCE2

DSC61XX

DS20005624B-page 12  2017 Microchip Technology Inc.

4-Lead VFLGA 2.0 mm x 1.6 mm Package Outline

0.07 C A B

0.03 C

(DATUM B)

(DATUM A)

SEATING

PLANE

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

0.10 C

0.08 C

Microchip Technology Drawing C04-1200A Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

4-Lead Very Thin Fine Pitch Land Grid Array (ASA) - 2.0x1.6 mm Body [VFLGA]

0.05 C

4X L

(A3)

3X b1

 2017 Microchip Technology Inc. DS20005624B-page 13

DSC61XX

4-Lead VFLGA 2.0 mm x 1.6 mm Package Outline

Microchip Technology Drawing C04-1200A Sheet 2 of 2

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

4-Lead Very Thin Fine Pitch Land Grid Array (ASA) - 2.0x1.6 mm Body [VFLGA]

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Overall Width

Terminal Length

Substrate Thickness (with Terminals)

Terminal Pitch

Standoff

Units

Dimension Limits

1.55 BSC

0.20 REF

0.40

0.50

0.79

0.00

0.55

0.45

0.84

0.02

1.60 BSC

MILLIMETERS

MIN NOM

0.50

0.60

0.89

0.05

MAX

CH 0.15--Terminal 1 Index Chamfer

Overall Length D 2.00 BSC

Terminal Width

b1 0.30 0.35 0.40Terminal Width

Terminal Pitch e1 0.95 BSC

DSC61XX

DS20005624B-page 14  2017 Microchip Technology Inc.

4-Lead VFLGA 2.0 mm x 1.6 mm Package Outline

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Contact Width (X2)

Contact Pitch

MILLIMETERS

1.55 BSC

MIN

MAX

Space Between Contacts (X4)

Contact Pad Length (X6)

Y0.70

Microchip Technology Drawing C04-3200A

NOM

4-Lead Very Thin Fine Pitch Land Grid Array (ASA) - 2.0x1.6 mm Body [VFLGA]

SILK SCREEN

X1Contact Width (X4)

Space Between Contacts (X3) G2 0.25

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

YG2

(CH)

CContact Spacing 0.95

0.40

0.50

1.05

Contact 1 Index Chamfer CH 0.13 X 45° REF

 2017 Microchip Technology Inc. DS20005624B-page 15

DSC61XX

4-Lead VLGA 2.5 mm x 2.0 mm Package Outline

0.07 C A B

0.03 C

(DATUM B)

(DATUM A)

SEATING

PLANE

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 1

0.10 C

0.08 C

Microchip Technology Drawing C04-1202A Sheet 1 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

4-Lead Very Thin Land Grid Array (AUA) - 2.5x2.0 mm Body [VLGA]

0.05 C

4X L

(A3)

4X b1

DSC61XX

DS20005624B-page 16  2017 Microchip Technology Inc.

4-Lead VLGA 2.5 mm x 2.0 mm Package Outline

Microchip Technology Drawing C04-1202A Sheet 2 of 2

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

4-Lead Very Thin Land Grid Array (AUA) - 2.5x2.0 mm Body [VLGA]

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Overall Width

Terminal Length

Substrate Thickness (with Terminals)

Terminal Pitch

Standoff

Units

Dimension Limits

1.65 BSC

0.20 REF

0.60

0.79

0.00

0.65

0.84

0.02

2.00 BSC

MILLIMETERS

MIN NOM

0.70

0.89

0.05

MAX

CH 0.225--Terminal 1 Index Chamfer

Overall Length D 2.50 BSC

b1 0.60 0.65 0.70Terminal Width

Terminal Pitch e1 1.25 BSC

 2017 Microchip Technology Inc. DS20005624B-page 17

DSC61XX

4-Lead VLGA 2.5 mm x 2.0 mm Recommended Land Pattern

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Contact Pitch

MILLIMETERS

1.65 BSC

MIN

MAX

Space Between Contacts (X4)

Contact Pad Length (X6)

Y0.80

Microchip Technology Drawing C04-3202A

NOM

4-Lead Very Thin Land Grid Array (AUA) - 2.5x2.0 mm Body [VLGA]

SILK SCREEN

XContact Width (X4)

Space Between Contacts (X3) G2 0.45

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

G2C

(CH)

CContact Spacing 1.25

0.70

0.95

Contact 1 Index Chamfer CH 0.13 X 45° REF

DSC61XX

DS20005624B-page 18  2017 Microchip Technology Inc.

4-Lead CDFN 3.2 mm x 2.5 mm Package Outline and Recommended Land Pattern

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

TITLE

4 LEAD CDFN 3.2x2.5mm COL PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING # CDFN3225-4LD-PL-1 UNIT MM

NOTE:

1. Green shaded rectangles in Recommended Land Pattern are solder stencil opening.

 2017 Microchip Technology Inc. DS20005624B-page 19

DSC61XX

APPENDIX A: REVISION HISTORY

Revision A (September 2016)

• Initial release of DSC61xx Microchip data sheet

DS20005624A.

Revision B (September 2017)

• Added Power Supply Ramp value in Electrical

Characteristics table.

• Redrew diagrams for clarity. No technical content

affected.

DSC61XX

DS20005624B-page 20  2017 Microchip Technology Inc.

NOTES:

 2016 Microchip Technology Inc. DS20005624B-page 21

DSC61XX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Note 1: Please visit Microchip ClockWorks® Configurator Website to configure the part number for customized fre-

quency. http://clockworks.microchip.com/timing/.

PART NO. X

Package

Device

Device: DSC61xx: Ultra-Low Power MEMS Oscillator

Pin Definition: Selection Pin 1 Internal Pull-Up Register

0 OE Pull-up

1 STBY Pull-up

2 FS Pull-up

4 OE None

5 STBY None

6 FS None

8kHz

Output

None

Output Drive

Strength:

Standard

High

Packages: C = 4-Lead 3.2 mm x 2.5 mm DFN

J = 4-Lead 2.5 mm x 2.0 mm VLGA

M = 4-Lead 2.0 mm x 1.6 mm VFLGA

H = 4-Lead 1.6 mm x 1.2 mm VFLGA

Temperature

Range:

E = –20C to +70C (Extended Commercial)

I = –40C to +85C (Industrial)

Frequency

Stability:

1 = ± 50 ppm

2 = ± 25 ppm

Revision: A = Revision A

Frequency: xxx.xxxx = User-Defined Frequency between

001.0000 MHz and 100.0000 MHz

xxxkxxx = User-Defined Frequency between 002.000 kHz

and 999.999 kHz

xxxx = Frequency configuration code when pin 1 = FS.

Configure the part online through ClockWorks

Tape and Reel: <blank>= 100/Bag

T = 1,000/Reel

Pin 1

Definition

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

Output

Drive

Strength

Temperature

Range

Frequency

Stability

Revision

XXX.XXXX

Frequency

Tape

and

Reel

–

Examples:

a) DSC6112JI2A-100.0000:

Ultra–Low Power MEMS Oscillator, Pin1 = Standby

with Internal Pull-Up, High Drive Strength, 4-Lead

2.5 mm x 2.0 mm VLGA, Industrial Temperature,

±25 ppm Stability, Revision A, 100 MHz Frequency,

100/Bag

b) DSC6101HE1A-016.0000T:

Ultra–Low Power MEMS Oscillator, Pin1 = OE with

Internal Pull–Up, Standard Drive Strength, 4-Lead

1.6 mm x 1.2 mm VFLGA, Extended Commercial

Temp., ±50 ppm Stability, Revision A, 16 MHz

Frequency, 1,000/Reel

c) DSC6121MI2A-005Q:

Ultra–Low Power MEMS Oscillator, Pin1 = Freq. Select

with Internal Pull-Up, Standard Drive Strength, 4-Lead

2.0 mm x 1.6 mm VFLGA, Industrial Temperature,

±25 ppm Stability, Revision A, Two Frequencies

Configured through ClockWorks, 100/Bag

DSC61XX

DS20005624B-page 22  2016 Microchip Technology Inc.

NOTES:

 2017 Microchip Technology Inc. DS20005624B-page 23

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,

CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,

KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,

maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip

Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST

Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,

CodeGuard, CryptoAuthentication, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0961-8

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certif ication for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, micro perip hera ls, n onvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 ce rtified.

QUALITYMANAGEMENTS

YSTEM

CERTIFIEDBYDNV

== ISO/TS16949==

DS20005624B-page 24  2017 Microchip Technology Inc.

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11/07/16