PIC16C6XX/7XX/9XX Programming Specifications for PIC16C6XX/7XX/9XX OTP MCUs This document includes the programming specifications for the following devices: 1.0 * * * * * * * * * * * * * * * PIC16C72A PIC16C73 PIC16C73A PIC16C73B PIC16C74 PIC16C74A PIC16C74B PIC16C76 PIC16C77 PIC16C620 PIC16C620A PIC16C621 PIC16C621A PIC16C622 PIC16C622A * * * * * * * * * * * * * PIC16CE623 PIC16CE624 PIC16CE625 PIC16C710 PIC16C711 PIC16C712 PIC16C716 PIC16C745 PIC16C765 PIC16C773 PIC16C774 PIC16C923 PIC16C924 PROGRAMMING THE PIC16C6XX/7XX/9XX The PIC16C6XX/7XX/9XX can be programmed using a serial method. In serial mode the PIC16C6XX/7XX/ 9XX can be programmed while in the users system. This allows for increased design flexibility. This programming specification applies to PIC16C6XX/7XX/ 9XX devices in all packages. 1.1 PDIP, Windowed CERDIP MCLR/VPP RA0 RA1 RA2 RA3 RA4/T0CKI RA5 RE0 RE1 RE2 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0 RC1 RC2 RC3 RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PDIP, SOIC, Windowed CERDIP MCLR/VPP *1 RA0 2 RA1 3 RA2 4 RA3 5 RA4/T0CKI 6 RA5 7 VSS 8 OSC1/CLKIN 9 OSC2/CLKOUT 10 RC0 11 RC1 12 RC2 13 RC3 14 PIC16C62/62A/63/66/72/72A PIC16C73/73A/73B/76/745 PIC16C61 PIC16C62 PIC16C62A PIC16C62B PIC16C63 PIC16C63A PIC16C64 PIC16C64A PIC16C65 PIC16C65A PIC16C65B PIC16C66 PIC16C67 PIC16C71 PIC16C72 PIC16C64/64A/65/65A/67 PIC16C74/74A/74B/77/765 * * * * * * * * * * * * * * * Pin Diagrams RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 (300 mil) 28 RB7 27 RB6 26 RB5 25 RB4 24 RB3 23 RB2 22 RB1 21 RB0/INT 20 VDD 19 VSS 18 RC7 17 RC6 16 RC5 15 RC4 Hardware Requirements The PIC16C6XX/7XX/9XX requires two programmable power supplies, one for VDD (2.0V to 6.5V recommended) and one for VPP (12V to 14V). Both supplies should have a minimum resolution of 0.25V. 1.2 Programming Mode The programming mode for the PIC16C6XX/7XX/9XX allows programming of user program memory, special locations used for ID, and the configuration word for the PIC16C6XX/7XX/9XX. 2000 Microchip Technology Inc. DS30228J-page 1 PIC16C6XX/7XX/9XX Pin Diagrams (Con't) 300 mil. SDIP, SOIC, Windowed CERDIP, SSOP PDIP, SOIC, Windowed CERDIP RA2 *1 RA3 2 RA4/T0CKI 3 MCLR/VPP 4 VSS 5 RB0/INT 6 RB1 7 RB2 RB3 18 RA1 17 RA0 16 OSC1/CLKIN 15 OSC2/CLKOUT 14 RB7 27 RB6 RA1/AN1 3 26 RB5 RA2/AN2/VREF-/VRL 4 25 RB4 VDD RA3/AN3/VREF+/VRH 5 24 RB3/AN9/LVDIN 13 RB7 RA4/T0CKI 6 23 RB2/AN8 12 RB6 8 11 RB5 AVDD AVSS 7 8 22 21 RB1/SS RB0/INT 9 10 RB4 OSC1/CLKIN 9 20 VDD 19 VSS 18 RC7/RX/DT PIC16C773 28 2 PIC16C61/71 PIC16C710/711 PIC16C62X *1 RA0/AN0 MCLR/VPP OSC2/CLKOUT 10 RC0/T1OSO/T1CKI 11 RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 18 pin PDIP, SOIC, Windowed CERDIP RA2/AN2 RA3/AN3/VREF 18 2 17 3 16 4 5 6 7 8 PIC16C712 PIC16C716 RA4/T0CKI MCLR/VPP VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1 *1 15 14 13 12 11 9 10 *1 20 2 19 3 18 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7 RB6 RB5 RB4 20 pin SSOP 5 6 7 8 17 16 15 14 13 9 12 10 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7 RB6 RB5 RB4 RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 4 PIC16C712 PIC16C716 RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 PIC16C923 PIC16C924 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 AVDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI DS30228J-page 2 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 2.0 PROGRAM MODE ENTRY 2.1 User Program Memory Map The user memory space extends from 0x0000 to 0x1FFF (8K). Table 2-1 shows actual implementation of program memory in the PIC16C6XX/7XX/9XX family. TABLE 2-1: IMPLEMENTATION OF PROGRAM MEMORY IN THE PIC16C6XX/7XX/9XX Device PIC16C61 Program Memory Size 0x000 - 0x3FF (1K) PIC16C620/620A 0x000 - 0x1FF (0.5K) PIC16C621/621A 0x000 - 0x3FF (1K) PIC16C622/622A 0x000 - 0x7FF (2K) PIC16C62/62A/62B 0x000 - 0x7FF (2K) PIC16C63/63A 0x000 - 0xFFF (4K) PIC16C64/64A 0x000 - 0x7FF (2K) PIC16C65/65A/65B 0x000 - 0xFFF (4K) PIC16CE623 0x000 - 0x1FF (0.5K) PIC16CE624 0x000 - 0x3FF (1K) PIC16CE625 0x000 - 0x7FF (2K) PIC16C71 0x000 - 0x3FF (1K) PIC16C710 0x000 - 0x1FF (0.5K) PIC16C711 0x000 - 0x3FF (1K) PIC16C712 0x000 - 0x3FF (1K) PIC16C716 0x000 - 0x7FF (2K) PIC16C72/72A 0x000 - 0x7FF (2K) PIC16C73/73A/73B 0x000 - 0xFFF (4K) PIC16C74/74A/74B 0x000 - 0xFFF (4K) PIC16C66 0x000 - 0x1FFF (8K) PIC16C67 0x000 - 0x1FFF (8K) PIC16C76 0x000 - 0x1FFF (8K) PIC16C77 0x000 - 0x1FFF (8K) PIC16C745 0x000 - 0x1FFF (8K) PIC16C765 0x000 - 0x1FFF (8K) PIC16C773 0x000 - 0xFFF (4K) PIC16C774 0x000 - 0xFFF (4K) PIC16C923/924 0x000 - 0xFFF (4K) A user may store identification information (ID) in four ID locations. The ID locations are mapped in [0x2000 : 0x2003]. It is recommended that the user use only the four least significant bits of each ID location. In some devices, the ID locations read-out in a scrambled fashion after code protection is enabled. For these devices, it is recommended that ID location is written as "11 1111 1bbb bbbb" where 'bbbb' is ID information. Note: All other locations are reserved and should not be programmed. In other devices, the ID locations read out normally, even after code protection. To understand how the devices behave, refer to Table 4-1. To understand the scrambling mechanism after code protection, refer to Section 3.1. When the PC reaches the last location of the implemented program memory, it will wrap around and address a location within the physically implemented memory (see Figure 2-1). Once in configuration memory, the highest bit of the PC stays a '1', thus always pointing to the configuration memory. The only way to point to user program memory is to reset the part and reenter program/verify mode, as described in Section 2.2. 2000 Microchip Technology Inc. DS30228J-page 3 PIC16C6XX/7XX/9XX FIGURE 2-1: PROGRAM MEMORY MAPPING 0.5K words 2000h ID Location 0h 1FFh 2001h 2002h 2003h ID Location ID Location ID Location 2004h Reserved 2005h Reserved 2006h Reserved Implemented 1K words 2K words 4K words 8K words Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented Implemented 3FFh 400h 7FFh 800h Reserved BFFh C00h Reserved FFFh 1000h Reserved Implemented Reserved Implemented Implemented 2007h Configuration Word Implemented 1FFFh 2008h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2100h 3FFFh DS30228J-page 4 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 2.2 have a minimum delay of 1 s between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSb first. Therefore, during a read operation the LSb will be transmitted onto pin RB7 on the rising edge of the second cycle, and during a load operation the LSb will be latched on the falling edge of the second cycle. A minimum 1 s delay is also specified between consecutive commands. Program/Verify Mode The program/verify mode is entered by holding pins RB6 and RB7 low while raising MCLR pin from VSS to the appropriate VIHH (high voltage). Once in this mode the user program memory and the configuration memory can be accessed and programmed in serial fashion. The mode of operation is serial, and the memory that is accessed is the user program memory. RB6 is a Schmitt Trigger input in this mode. The sequence that enters the device into the programming/verify mode places all other logic into the reset state (the MCLR pin was initially at VSS). This means that all I/O are in the reset state (High impedance inputs). All commands are transmitted LSb first. Data words are also transmitted LSb first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1 s is required between a command and a data word (or another command). Note 1: The MCLR pin should be raised as quickly as possible from VIL to VIHH. this is to ensure that the device does not have the PC incremented while in valid operation range. The commands in Table 2-2. 2.2.1.1 2: Do not power any pin before VDD is applied. 2.2.1 are available The RB6 pin is used as a clock input pin, and the RB7 pin is used for entering command bits and data input/ output during serial operation. To input a command, the clock pin (RB6) is cycled six times. Each command bit is latched on the falling edge of the clock with the least significant bit (LSb) of the command being input first. The data on pin RB7 is required to have a minimum setup and hold time (see AC/DC specs) with respect to the falling edge of the clock. Commands that have data associated with them (read and load) are specified to listed LOAD CONFIGURATION TABLE 2-2: COMMAND MAPPING Mapping (MSb ... LSb) Data Load Configuration 0 0 0 0 0 0 0, data(14), 0 Load Data 0 0 0 0 1 0 0, data(14), 0 Read Data 0 0 0 1 0 0 0, data(14), 0 Increment Address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End Programming 0 0 1 1 1 0 Note: are After receiving this command, the program counter (PC) will be set to 0x2000. By then applying 16 cycles to the clock pin, the chip will load 14-bits a "data word" as described above, to be programmed into the configuration memory. A description of the memory mapping schemes for normal operation and configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the program/verify test mode by taking MCLR low (VIL). PROGRAM/VERIFY OPERATION Command that The clock must be disabled during In-Circuit Serial Programming. 2000 Microchip Technology Inc. DS30228J-page 5 PIC16C6XX/7XX/9XX FIGURE 2-2: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX PROGRAM MEMORY Start Set VDD = VDDP* Set VPP = VIHH1 N=1 No Program Cycle N > 25? Read Data Command Increment Address Command Data correct? Yes Report programming failure N=N+1 N=# of Program Cycles No Yes Apply 3N Additional Program Cycles Program Cycle No Load Data Command All locations done? Yes Begin Programming Command Verify all locations @ VDD min.* VPP = VIHH2 Wait 100 s Data correct? No Report verify @ VDD min. Error Yes End Programming Command Verify all locations @ VDD max.* VPP = VIHH2 Data correct? No Report verify @ VDD max. Error Yes Done * VDDP = VDD range for programming (typically 4.75V - 5.25V). VDDmin = Minimum VDD for device operation. VDDmax = Maximum VDD for device operation. DS30228J-page 6 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX FIGURE 2-3: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX CONFIGURATION WORD & ID LOCATIONS Start Set VDD = VDDP* Set VPP = VIHH1 Load Configuration Command N=1 No Program ID Loc? Yes Read Data Command Program Cycle Increment Address Command N=N+1 N=# of Program Cycles No Data Correct? Yes No Address = 2004 No N > 25 Yes Yes Increment Address Command Report ID Configuration Error Apply 3N Program Cycles Program Cycle 100 Cycles Read Data Command Increment Address Command Increment Address Command No Data Correct? Yes Report Program ID/Config. Error No No Done Yes Data Correct? Data Correct? Set VDD = VVDD DDmin min Read Data Command Set VPP = VIHH2 Yes Set VDD = VVDD DDmax max Read Data Command Set VPP = VIHH2 VDDP = VDD Range for programming (Typically 4.25V - 5.25V) VDDMIN = minimum VDD for device operation VDDMAX = maximum VDD for device operation 2000 Microchip Technology Inc. DS30228J-page 7 PIC16C6XX/7XX/9XX 2.2.1.2 LOAD DATA After receiving this command, the chip will load in a 14-bit "data word" when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 4-1. 2.2.1.3 READ DATA After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The RB7 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. A timing diagram of this command is shown in Figure 4-2. 2.2.1.4 INCREMENT ADDRESS The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 4-3. 2.2.1.5 BEGIN PROGRAMMING A load command (load configuration or load data) must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100s programming pulses. A programming pulse is defined as the time between the begin programming command and the end programming command. 2.2.1.6 2.3 Programming Algorithm Requires Variable VDD The PIC16C6XX/7XX/9XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VCC range required during programming. VDD min. = minimum operating VDD spec for the part. VDDmax = maximum operating VDD spec for the part. Programmers must verify the PIC16C6XX/7XX/9XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC16C6XX/7XX/9XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. END PROGRAMMING After receiving this command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. DS30228J-page 8 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 3.0 CONFIGURATION WORD The PIC16C6XX/7XX/9XX family members have several configuration bits. These bits can be programmed (reads '0') or left unprogrammed (reads '1') to select various device configurations. Figure 3-1 and Figure 3-2 provides an overview of configuration bits. 2000 Microchip Technology Inc. DS30228J-page 9 PIC16C6XX/7XX/9XX FIGURE 3-1: CONFIGURATION WORD BIT MAP Bit 13 Number: PIC16C61/71 -- PIC16C62/64/65/73/74 -- PIC16C62A/62B/63A/CR62/ 63/ 64A/CR64/65A/65B/66/67/ 72/72A/73A/73B/74A/74B/76/ 77/620/620A/621/621A/622/ 622A/ 712/716 CP1 CP0 CP1 CP0 CP1 PIC16C9XX/745/765 CP0 CP1 CP0 CP1 CP1 12 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- CP1 CP0 CP0 PWRTE PWRTE WDTE WDTE FOSC1 FOSC1 FOSC0 FOSC0 CP0 -- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 CP0 -- -- CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Reserved, '-' write as '1' for PIC16C6XX/7XX/9XX CP <1:0>, Code Protect Device PIC16C622/622A PIC16C62/62A/62B PIC16C63/63A PIC16C64/64A/712/716 PIC16C65/65A/65B PIC16C66/67/72/72A PIC16C73/73A/73B PIC16C74/74A/74B/76/77 PIC16C745/765 PIC16C9XX PIC16C61/71 PIC16C710/711 PIC16C620 PIC16C621 bit 6: bit 4: CP1 CP0 Code Protection 0 0 All memory protected 0 1 Upper 3/4 memory protected 1 0 Upper 1/2 memory protected 1 1 Code protection off -- -- 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 All memory protected Off All memory protected Do not use Do not use Code protection off All memory protected Upper 1/2 memory protected Code protection off BODEN, Brown Out Enable Bit 1 = Enabled 2 = Disable PWRTE/PWRTE, Power Up Timer Enable Bit PIC16C61/62/64/65/71/73/74: 1 = Power up timer enabled 0 = Power up timer disabled PIC16C620/620A/621/621A/622/622A/62A/63/63A/65A/65B/66/67/72/72A/73A/73B/74A/74B/76/77/710/ 711/923/924/745/765: 0 = Power up timer enabled 1 = Power up timer disabled bit 3-2: WDTE, WDT Enable Bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC<1:0>, Oscillator Selection Bit 11: RC oscillator 10: HS oscillator 01: XT oscillator 00: LP oscillator bit 1-0: FOSC<1:0>, PIC16C745/765 11: E external clock with 4k PLL 10: H HS oscillator with 4k PL enabled 01: EC exteranl clock, clkout on osc2 00: HS Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. DS30228J-page 10 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX FIGURE 3-2: CP1 CONFIGURATION WORD FOR PIC16C773/774 DEVICE CP0 BORV1 BORV0 CP1 bit13 12 11 10 CP0 - BODEN CP1 8 7 6 5 9 CP0 PWRTE 4 3 WDTE FOSC1 2 1 FOSC0 Register: Address CONFIG 2007h bit0 CP <1:0> Code Protection bits (2) Device PIC16C773/774 CP1 CP0 Code Protection 0 0 All memory protected 0 1 Upper 3/4 memory protected 1 0 Upper 1/2 memory protected1 1 1 Code protection off bit 11-10: BORV <1:0>: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 7: Unimplemented, Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC <1:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP <1:0> pairs have to be given the same value to enable the code protection scheme listed. 2000 Microchip Technology Inc. DS30228J-page 11 PIC16C6XX/7XX/9XX FIGURE 3-3: CP0 CP0 CONFIGURATION WORD, PIC16C710/711 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 bit13 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-7 CP0: Code protection bits (2) 5-4: 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC <1:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed. DS30228J-page 12 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 3.1 Embedding Configuration Word and ID Information in the Hex File. To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Microchip Technology Inc. feels strongly that this feature is beneficial to the end customer. 2000 Microchip Technology Inc. DS30228J-page 13 PIC16C6XX/7XX/9XX 3.2 Checksum 3.2.1 CHECKSUM CALCULATIONS Checksum is calculated by reading the contents of the PIC16C6XX/7XX/9XX memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1FF for the PIC16C74. Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for each member of the PIC16C6XX/7XX/9XX devices is shown in Table 3-1. The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. The least significant 16 bits of this sum is the checksum. TABLE 3-1: Device CHECKSUM COMPUTATION Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C61 OFF ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF 0xFC6F 0x07CD 0xFC15 PIC16C620 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C PIC16C620A OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C PIC16C621 OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16C621A OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16C622 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C622A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16CE623 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3F7F SUM_ID + CFGW & 0x3F7F 0x3D7F 0x3DCE 0x094D 0x099C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 14 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16CE624 OFF 1/2 ALL SUM[0x000:0x3FF] + CFGW & 0x3F7F SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x3B7F 0x4EDE 0x3BCE 0x074D 0x0093 0x079C PIC16CE625 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C62 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x37AF 0x379F 0x378F 0x038D 0x1D69 0x1D59 0x3735 PIC16C62A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C62B OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C63 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C63A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C64 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x37AF 0x379F 0x378F 0x038D 0x1D69 0x1D59 0x3735 PIC16C64A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C65 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR 2000 Microchip Technology Inc. DS30228J-page 15 PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C65A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C65B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C66 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C67 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C710 OFF ON SUM[0x000:0x1FF] + CFGW & 0x3FFF SUM[0x00:0x3F] + CFGW & 0x3FFF + SUM_ID 0x3DFF 0x3E0E 0x09CD 0xEFC3 PIC16C71 OFF ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF 0xFC6F 0x07CD 0xFC15 PIC16C711 OFF ON SUM[0x000:0x03FF] + CFGW & 0x3FFF SUM[0x00:0x3FF] + CFGW & 0x3FFF + SUM_ID 0x3BFF 0x3C0E 0x07CD 0xEDC3 PIC16C712 OFF 1/2 ALL SUM[0x000:0x07FF] + CFGW & 0x3F7F SUM[0x000:0x03FF] + CFGW & 3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x37CE 0x034D 0xF58A 0x039C PIC16C716 OFF 1/2 3/4 ALL SUM[0x000:0x07FF] + CFGW & 0x3F7F SUM[0x000:0x03FF] + CFGW & 0x3F7F + SUM_ID SUM]0x000:0x01FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C72 OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C72A OFF 1/2 3/4 ALL SUM[0x000:0x7FF] + CFGW & 0x3F7F SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x377F 0x5DEE 0x4ADE 0x37CE 0x034D 0x0FA3 0xFC93 0x039C PIC16C73 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 PIC16C73A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 16 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX TABLE 3-1: Device CHECKSUM COMPUTATION (CONTINUED) Code Protect Checksum* Blank Value 0x25E6 at 0 and max address PIC16C73B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C74 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x3F80 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x3F80 SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0x2FAF 0x2F9F 0x2F8F 0xFB8D 0x1569 0x1559 0x2F35 PIC16C74A OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C74B OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F7F SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x51EE 0x40DE 0x2FCE 0xFB4D 0x03A3 0xF293 0xFB9C PIC16C76 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C77 OFF 1/2 3/4 ALL SUM[0x000:0x1FFF] + CFGW & 0x3F7F SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x1F7F 0x39EE 0x2CDE 0x1FCE 0xEB4D 0xEBA3 0xDE93 0xEB9C PIC16C773 OFF 1/2 3/4 ALL SUM[0x000:0x0FFF] + CFGW & 0x3F7F SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0x55EE 0x48DE 0x3BCE 0xFB4D 0x07A3 0xFA93 0x079C PIC16C774 OFF 1/2 3/4 ALL SU:M[0x000:0FFF] + CFGW & 0x3F7F SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID CFGW & 0x3F7F + SUM_ID 0x2F7F 0X55EE 0X48DE 0x3BCE 0xFB4D 0x07A3 0xFA93 0X079C PIC16C923 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F3F SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 0x2F3F 0x516E 0x405E 0x2F4E 0xFB0D 0x0323 0xF213 0xFB1C PIC16C924 OFF 1/2 3/4 ALL SUM[0x000:0xFFF] + CFGW & 0x3F3F SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID CFGW & 0x3F3F + SUM_ID 0x2F3F 0x516E 0x405E 0x2F4E 0xFB0D 0x0323 0xF213 0xFB1C PIC16C745 OFF 1000:1FFF 800:1FFF ALL 1F3F 396E 2C5E 1F4E EB0D EB23 DE13 EB1C SUM(0000:1FFF) + CFGW & 0x3F3F SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID CFGW * 0x3F3F + SUM_ID Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR 2000 Microchip Technology Inc. DS30228J-page 17 PIC16C6XX/7XX/9XX TABLE 3-1: Device PIC16c765 CHECKSUM COMPUTATION (CONTINUED) Code Protect OFF 1000:1FFF 800:1FFF ALL Checksum* Blank Value 0x25E6 at 0 and max address SUM(0000:1FFF) + CFGW & 0x3F3F SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID CFGW * 0x3F3F + SUM_ID 1F3F 396E 2C5E 1F4E EB0D EB23 DE13 EB1C Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a through b inclusive] SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036. SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example, ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746. *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND | = Bitwise OR DS30228J-page 18 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX 4.0 PROGRAM/VERIFY MODE TABLE 4-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: +10C TA +40C, unless otherwise stated, (20C recommended) Operating Voltage: 4.5V VDD 5.5V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units 4.75 5.0 5.25 V - - 20 mA Conditions General PD1 VDDP Supply voltage during programming PD2 IDDP Supply current (from VDD) during programming PD3 VDDV Supply voltage during verify VDDmin - VDDmax V Note 1 PD4 VIHH1 Voltage on MCLR/VPP during programming 12.75 - 13.25 V Note 2 PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.5 - 13.25 - - - 50 mA PD6 IPP Programming supply current (from VPP) PD9 VIH (RB6, RB7) input high level 0.8 VDD - - V Schmitt Trigger input PD8 VIL (RB6, RB7) input low level 0.2 VDD - - V Schmitt Trigger input - - 8.0 s Serial Program Verify P1 TR MCLR/VPP rise time (VSS to VHH) for test mode entry Tf MCLR Fall time - - 8.0 s P3 Tset1 Data in setup time before clock 100 - - ns P4 Thld1 Data in hold time after clock 100 - - ns P5 Tdly1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 - - s P6 Tdly2 Delay between clock to clock of next command or data 1.0 - - s P7 Tdly3 Clock to date out valid (during read data) 200 - - ns P8 Thld0 Hold time after MCLR 2 - - s P2 Note 1: Program must be verified at the minimum and maximum VDD limits for the part. 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode. 2000 Microchip Technology Inc. DS30228J-page 19 PIC16C6XX/7XX/9XX FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 0 0 0 RB6 (CLOCK) RB7 (DATA) 0 1 2 1s min. 1 6 4 5 15 0 0 0 P5 P3 P4 1s min. P3 P4 } } } } 100ns min. Program/Verify Test Mode Reset FIGURE 4-2: 3 100ns min. READ DATA COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP 100ns P8 1 P6 2 3 4 5 100ns 1 0 0 RB6 (CLOCK) RB7 (DATA) 0 0 2 1s min. 1 6 3 4 5 15 P7 0 P5 P3 P4 1s min. } } 100ns min. RB7 input RB7 = output Program/Verify Test Mode Reset FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY) VIHH MCLR/VPP P6 1 2 0 1 3 4 5 6 0 0 0 Next Command 1s min. 1 2 RB6 (CLOCK) RB7 (DATA) 1 0 0 P5 P3 P4 1s min. } } 100ns min Program/Verify Test Mode Reset DS30228J-page 20 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX NOTES: 2000 Microchip Technology Inc. DS30228J-page 21 PIC16C6XX/7XX/9XX NOTES: DS30228J-page 22 2000 Microchip Technology Inc. PIC16C6XX/7XX/9XX NOTES: 2000 Microchip Technology Inc. DS30228J-page 23 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) ASIA/PACIFIC (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-786-7200 Fax: 480-786-7277 Technical Support: 480-786-7627 Web Address: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Microchip Technology, Beijing Unit 915, 6 Chaoyangmen Bei Dajie Dong Erhuan Road, Dongcheng District New China Hong Kong Manhattan Building Beijing 100027 PRC Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 4570 Westgrove Drive, Suite 160 Addison, TX 75248 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Detroit Microchip Technology Inc. Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 ASIA/PACIFIC Beijing Taiwan, R.O.C Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Hong Kong Denmark Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 India Microchip Technology Inc. India Liaison Office No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062 Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan Germany Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Munchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Shanghai Microchip Technology Unit B701, Far East International Plaza, No. 317, Xianxia Road Shanghai, 200051 P.R.C Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 France Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5858 Fax: 44-118 921-5835 01/21/00 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. (c) 2/1/00 Microchip Technology Incorporated. Printed in the USA. Tuesday, February 01, 2000 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30228J-page 24 2000 Microchip Technology Inc.