2000 Microchip Technology Inc. DS30228J-page 1
PIC16C6XX/7XX/9XX
This document includes the progr amming
specifications for the following devices:
1.0 PROGRAMMING THE
PIC16C6XX/7XX/9XX
The PIC16C6XX/7XX/9XX can be programmed using a
serial method. In serial mode the PIC16C6XX/7XX/
9XX can be programmed while in the users system.
This allows for increased design flexibility. This pro-
gramming specification applies to PIC16C6XX/7XX/
9XX devices in all packages.
1.1 Hardware Requirements
The PIC1 6C6XX/7XX/9X X requires tw o prog ram mab le
power supplies, one for VDD (2.0V to 6.5V recom-
mended) and one for VPP (12V to 14V). Both supplies
should have a minimum resolution of 0.25V.
1.2 Programming Mode
The programming mode for the PIC16C6XX/7XX/9XX
allows programming of user program memory, special
locatio ns used for ID, and the config uration wor d for the
PIC16C6XX/7XX/9XX.
Pin Diagrams
• PIC16C61 • PIC16C72A • PIC16CE623
• PIC16C62 • PIC16C73 • PIC16CE624
• PIC16C62A • PIC16C73A • PIC16CE625
• PIC16C62B • PIC16C73B • PIC16C710
• PIC16C63 • PIC16C74 • PIC16C711
• PIC16C63A • PIC16C74A • PIC16C712
• PIC16C64 • PIC16C74B • PIC16C716
• PIC16C64A • PIC16C76 • PIC16C745
• PIC16C65 • PIC16C77 • PIC16C765
• PIC16C65A • PIC16C620 • PIC16C773
• PIC16C65B • PIC16C620A • PIC16C774
• PIC16C66 • PIC16C621 • PIC16C923
• PIC16C67 • PIC16C621A • PIC16C924
• PIC16C71 • PIC16C622
• PIC16C72 • PIC16C622A
PIC16C62/62A/63/66/72/72A
PIC16C73/73A/73B/76/745
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5
RE0
RE1
RE2
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PDIP, Windowed CERDIP
PDIP, SOI C, Windowed CER DIP (300 mil)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5
RC4
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RC1
RC2
RC3
PIC16C64/64A/65/65A/67
PIC16C74/74A/74B/77/765
Programming Specifications for PIC16C6XX/7XX/9XX OTP MCUs
PIC16C6XX/7XX/9XX
DS30228J-page 2 2000 Microchip Technology Inc.
Pin Diagrams (Con’t)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PIC16C924
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RG7/SEG28
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
RA4/T0CKI
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
VLCD2
VLCD3
AVDD
VDD
VSS
C1
C2
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RA3/AN3/VREF
RA2/AN2
VSS
RA1/AN1
RA0/AN0
RB2
RB3
MCLR/VPP
N/C
RB4
RB5
RB7
RB6
VDD
COM0
RD7/SEG31/COM1
RD6/SEG30/COM2
RC1/T1OSI
RC2/CCP1
VLCD1
VLCDADJ
RD0/SEG00
RD1/SEG01
RD2/SEG02
RD3/SEG03
RD4/SEG04
RE7/SEG27
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE6/SEG11
RE5/SEG10
PLCC
PDIP, SO IC, Wind o we d C E R D I P
18
17
16
15
14
13
12
11
10
• 1
2
3
4
5
6
7
8
9
RA2
RA3
RA4/T0CKI
MCLR/VPP
VSS
RB0/INT
RB1
RB2
RB3
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
PIC16C61/71
PIC16C62X
PIC16C710/711
PIC16C923
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
AVDD
AVSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3/AN9/LVDIN
RB2/AN8
RB1/SS
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
300 mil. SDIP, SOIC, Windowed CERDIP, SSOP
PIC16C773
PIC16C712
RA2/AN2
RA4/T0CKI
RB0/INT
RB1/T1OSO/T1CKI
RA0/AN0
OSC1/CLKIN
RB7
RB6
• 1
2
3
4
5
6
7
18
17
16
15
14
13
12
8
9
11
10
18 pin PDIP, SOIC, Windowed CERDIP
MCLR/VPP
RA3/AN3/VREF
RB2/T1OSI
RB3/CCP1 RB4
RB5
RA1/AN1
VDD
OSC2/CLKOUT
VSS
PIC16C716 PIC16C712
RA2/AN2
RA4/T0CKI
RB0/INT
RB1/T1OSO/T1CKI
RA0/AN0
OSC1/CLKIN
RB7
RB6
• 1
2
3
4
5
6
7
20
19
18
17
16
15
14
8
9
13
12
20 pin SSOP
MCLR/VPP
RA3/AN3/VREF
RB2/T1OSI
RB3/CCP1 RB4
RB5
RA1/AN1
VDD
OSC2/CLKOUT
VSS
PIC16C716
10
VSS VDD
11
2000 Microchip Technology Inc. DS30228J-page 3
PIC16C6XX/7XX/9XX
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC16C6XX/7XX/9XX fam-
ily.
TABLE 2-1: IMPLEMENTATION OF
PROGRAM MEMORY IN THE
PIC16C6XX/7XX/9XX
When the PC reaches the last location of the imple-
mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
Once i n configura tion memory, the highest bit of t he PC
stays a ’1’, thus always pointing to the configuration
memory. The only way to point to user program mem-
ory is to reset the part and reenter program/verify
mode, as described in Section 2.2.
A user may store identification infor mation (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
0x2003]. It is recommended that the user use only the
four least significant bits of each ID location. In some
devices, the ID locations read-out in a scrambled fash-
ion after code protec tio n is enabl ed. For these d evices,
it is recommended that ID location is written as “11
1111 1bbb bbbb” where 'bbbb' is ID information.
Note: All other locations are reserved and should
not be programmed.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 4-1.
To understand the scrambling mechanism after code
protection, refer to Section 3.1.
Device Program Memory
Size
PIC16C61 0x000 – 0x3FF (1K)
PIC16C620/620A 0x000 – 0x1FF (0.5K)
PIC16C62 1/6 21A 0x000 – 0x3FF (1K)
PIC16C62 2/6 22A 0x000 – 0x7FF (2K)
PIC16C62/62A/62B 0x000 – 0x7FF (2K)
PIC16C63/63A 0x000 – 0xFFF (4K)
PIC16C64/64A 0x000 – 0x7FF (2K)
PIC16C65/65A/65B 0x000 – 0xFFF (4K)
PIC16CE623 0x000 – 0x1FF (0.5K)
PIC16CE62 4 0x 00 0 – 0x3FF (1K)
PIC16CE62 5 0x 00 0 – 0x7FF (2K)
PIC16C71 0x000 – 0x3FF (1K)
PIC16C710 0x000 – 0x1FF (0.5K)
PIC16C711 0x000 – 0x3FF (1K)
PIC16C712 0x000 – 0x3FF (1K)
PIC16C716 0x000 – 0x7FF (2K)
PIC16C72/72A 0x000 – 0x7FF (2K)
PIC16C73/73A/73B 0x000 – 0xFFF (4K)
PIC16C74/74A/74B 0x000 – 0xFFF (4K)
PIC16C66 0x000 – 0x1FFF (8K)
PIC16C67 0x000 – 0x1FFF (8K)
PIC16C76 0x000 – 0x1FFF (8K)
PIC16C77 0x000 – 0x1FFF (8K)
PIC16C745 0x000 – 0x1FFF (8K)
PIC16C765 0x000 – 0x1FFF (8K)
PIC16C773 0x000 – 0xFFF (4K)
PIC16C774 0x000 – 0xFFF (4K)
PIC16C923/924 0x000 – 0xFFF (4K)
PIC16C6XX/7XX/9XX
DS30228J-page 4 2000 Microchip Technology Inc.
FIGURE 2-1: PROGRAM MEMORY MAPPING
0.5K
words 1K
words 2K
words 4K
words 8K
words
Implemented Implemented Implemented Implemented Implemented
Implemented Implemented Implemented
Reserved Implemented Implemented
Reserved Implemented Implemented
Reserved Implemented
Reserved Implemented
Implemented
Implemented
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved
ID Location
ID Location
ID Location
ID Location
Reserved
Reserved
Reserved
Configuration Word
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
0h
1FFh
3FFh
400h
7FFh
800h
BFFh
C00h
FFFh
1000h
1FFFh
2008h
2100h
3FFFh
2000 Microchip Technology Inc. DS30228J-page 5
PIC16C6XX/7XX/9XX
2.2 Program/Verify Mode
The program/verify mode is entered by holding pins
RB6 and RB7 low while raising MCLR pin from VSS to
the appropriate VIHH (high voltage). Once in this mode
the user program memory and the configuration mem-
ory can be accessed and programmed in serial fash-
ion. The mode of operation is serial, and the memory
that is ac ce ss ed is the user p r og r am m em ory. RB6 is a
Schmitt Trigger input in this mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at VSS). This means
that all I/O are in the reset state (High impedance
inputs).
2.2.1 PROGRAM/VERIFY OPERATION
The RB6 pin is used as a clock input pin, and the RB7
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB 6) is cyc led six tim es. Each co mman d bit
is latched on the falling edge of the clock with the least
significant bit (LSb) of the command being input first.
The data on pin RB7 is required to have a minimum
setup an d hold time (s ee A C /DC spec s) wi th respe ct to
the fallin g edge of the clock . Commands that ha v e data
associated with them (read and load) are specified to
have a minimum delay of 1 µs between the command
and the data. After this delay the clock pin is cycled 16
times with the first cycle being a start bit and the last
cycle being a stop bi t. Data is als o input and o utput LSb
first. Th erefore, during a read op er ati on the LSb will be
tran sm it ted onto pin RB7 on the rising edg e of the sec-
ond cycle, and dur ing a load operation the LSb will be
latched on the falling edge of the second cycle. A min-
imum 1 µs dela y is al so spec ified betw een co nse cutive
commands .
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
cloc k. To allow for dec oding of commands and re v e rsal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are listed
in Table 2-2.
2.2.1.1 LOAD CONFIGURATION
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as des cribed above, to be p rog rammed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
operation is shown in Figure 2-1. After the configura-
tion memory is ente red , th e o nly way to get back to the
user program memory is to ex it the program/verify test
mode by taking MCLR low (VIL).
TABLE 2-2: COMMAND MAPPING
Note 1: The MC LR pin should be r aised as qui ckly
as possible from VIL to VIHH. this is to
ensure that the device does not have the
PC incremented while in valid operation
range.
2: Do not power any pin before VDD is
applied.
Command Mapping (MSb ... LSb) Data
Load Configuration 0000000, data(14), 0
Load Data 0000100, data(14), 0
Read Data 0001000, data(14), 0
Increment Address 000110
Begin programming 001000
End Programming 001110
Note: The clock must be disabled during In-Circuit Serial Programming.
PIC16C6XX/7XX/9XX
DS30228J-page 6 2000 Microchip Technology Inc.
FIGURE 2-2: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX PROGRAM MEMORY
* VDDP = VDD range for programming (typically 4.75V - 5.25V).
VDDmin = Minimum VDD for device operation.
VDDmax = Maximum VDD for device operation.
Start
N = 1
Set VDD = VDDP*
Program Cycle
Read Data
Command
Data correct?
Apply 3N Additional
Program Cycles
All locations done?
Verify all locations
@ VDD min.*
VPP = VIHH2
Data correct?
Verify all locations
@ VDD max.*
VPP = VIHH2
Data correct?
Done
N > 25? Report programming
failure
N = N + 1 N = #
of Program Cycles
Increment Address
Command
Report verify
@ VDD min. Error
Report verify
@ VDD max. Error
Load Data
Command
Begin Programming
Command
End Programming
Command
Wait 100 µs
Program Cycle
Yes
No
No Yes
No
Yes
No
No
Yes
Yes
Set VPP = VIHH1
2000 Microchip Technology Inc. DS30228J-page 7
PIC16C6XX/7XX/9XX
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX CONFIGURATION WORD & ID
LOCATIONS
VDDmin
VDDmax
Start
Load Configuration
Command
Increment Address
Command N = N + 1 N = #
of Program Cycles
Report ID
Configuration Error
Increment Address
Command
Increment Address
Command
Increment Address
Command Program Cycle
100 Cycles Read Data
Command
Apply 3N
Program Cycles
Read Data
Command
Report Program
ID/C o nfig. Err o r
Set VDD = V DDmax
Program Cycle
N = 1
Data Correct?
Data Correct?
Data Correct?
Data Correct?
N > 25
Address = 2004
Program ID Loc?
Done
Yes
No
No
Yes
No
Yes
Yes
Yes
No
Yes
No
No
No Yes
Read Data Command
Set VPP = VIHH2
Set VDD = VDDmin
Read Data Command
Set VPP = VIHH2
Set VDD = VDDP*
Set VPP = VIHH1
VDDP = VDD Range for programming (Typically 4.25V – 5.25V)
VDDMIN = minimum VDD for device operation
VDDMAX = maximum VDD for de vice operation
PIC16C6XX/7XX/9XX
DS30228J-page 8 2000 Microchip Technology Inc.
2.2.1.2 LOAD DATA
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described p revious ly . A timing diagram fo r the load data
command is shown in Figure 4-1.
2.2.1.3 READ DATA
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second risin g edge of the cloc k input. Th e RB7
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped-
ance) after the 16th rising edge. A timing diagram of
this command is shown in Figure 4-2.
2.2.1.4 INCREMENT ADDRESS
The PC is incremented when this command is
recei ved. A timing diagram of this command is shown
in Figure 4-3.
2.2.1.5 BEGIN PROGRAMMING
A load command (load configuration or load data)
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.
2.2.1.6 END PROGRAMMIN G
After receiv ing this command, the chip stops program-
ming the memory (configuration program memory or
user program memory) that it was programming at the
time.
2.3 Programming Algorithm Requires
Variable VDD
The PIC16C6XX/7XX/9XX uses an intelligent algo-
rithm. The algorithm calls for program verification at
VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
VDDmax guarantees good “program margin”.
The actual programming must be done w ith V DD in the
VDDP range (4.75 - 5.25V).
VDDP =VCC range required during programming.
VDD min. = minimum operating VDD spec for the part.
VDDmax = maximum operating VDD spec for the part.
Programmers must ver ify the PIC16C6XX/7XX/9XX at
its specified VDDmax and VDDmin levels. Since
Microchip may introduce future versions of the
PIC16C6XX/7XX/9XX with a broader VDD range, it is
best that these levels are user selectable (defaults are
ok).
Note: Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
bu t not a “pro ducti on” qual ity prog ram mer .
2000 Microchip Technology Inc. DS30228J-page 9
PIC16C6XX/7XX/9XX
3.0 CONFIGURATION WORD
The PIC16C6XX/7XX/9XX family members have sev-
eral co nfi gura tion bit s. The se bi ts c an be pro gramm ed
(reads ’0’) or left unprogrammed (reads ’1’) to select
various device configurations. Figure 3-1 and
Figure 3-2 provides an overview of configuration bits.
PIC16C6XX/7XX/9XX
DS30228J-page 10 2000 Microchip Technology Inc.
FIGURE 3-1: CONFIGURATION WORD BIT MAP
Bit
Number: 13 12 11 10 9 8 7 6543 2 1 0
PIC16C61/71 ——————— — —CP0PWRTEWDTEFOSC1FOSC0
PIC16C62/64/65/73/74——————— 0 CP1CP0PWRTEWDTEFOSC1FOSC0
PIC16C62A/62B/63A/CR62/
63/
64A/CR64/65A/65B/66/67/
72/72A/73A/73B/74A/74B/76/
77/620/620A/621/621A/622/
622A/
712/716 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C9XX/745/765 CP1 CP0 CP1 CP0 CP1 CP0 — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0
Reserved, '–' write as '1' for PIC16C6XX/7XX/9XX
CP <1:0>, Code Protect
bit 6: BODEN, Brown Out Enable Bit
1 = Enabled
2 = Disable
bit 4: PWRTE/PWRTE, P ower Up Timer Enable Bit
PIC16C61/62/64/65/71/73/74:
1 = Power up timer enabled
0 = Power up timer disabled
PIC16C620/620A/621/621A/622/622A/62A/63/63A/65A/65B/66/67/72/72A/73A/73B/74A/74B/76/77/710/
711/923/924/745/765:
0 = Power up timer enabled
1 = Power up timer disabled
bit 3-2: WDTE, WDT Enable Bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC<1:0>, Oscillator Selection Bit
11: RC oscillator
10: HS oscillator
01: XT oscillator
00: LP oscillator
bit 1-0: FOSC<1:0>, PIC16C745/765
11: E external clock with 4k PLL
10: H HS oscillator with 4k PL enabled
01: EC exteranl clock, clkout on osc2
00: HS
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit
PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
Device CP1 CP0 Code Protection
PIC16C622/622A
PIC16C62/62A/62B 0 0 All memory protected
PIC16C63/63A
PIC16C64/64A/712/716 0 1 Upper 3/4 memo ry protecte d
PIC16C65/65A/65B
PIC16C66/67/72/72A 1 0 Up per 1/2 memory protecte d
PIC16C73/73A/73B
PIC16C74/74A/74B/76/77
PIC16C745/765
PIC16C9XX
1 1 Code protection off
PIC16C61/71
PIC16C710/711 — 0 All memory protected
—1Off
PIC16C620 0 0 All memory protected
0 1 Do not use
1 0 Do not use
1 1 Code protection off
PIC16C621 0 0 All memory protected
1 0 Upper 1/2 memory prote c ted
1 1 Code protection off
2000 Microchip Technology Inc. DS30228J-page 11
PIC16C6XX/7XX/9XX
FIGURE 3-2: CONFIGURATION WORD FOR PIC16C773/774 DEVICE
CP1 CP0 BORV1 BORV0 CP1 CP0 - BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0
CP <1:0> Code Protection bits (2)
bit 11-10: BOR V <1:0>: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 7: Unimplemented, Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP <1:0> pairs have to be given the same value to enable the code protection scheme listed.
Device CP1 CP0 Code Protection
PIC16C773/774 0 0 All memory protected
0 1 Upper 3/4 mem ory protected
1 0 Upper 1/2 mem ory protected1
1 1 Code protection off
PIC16C6XX/7XX/9XX
DS30228J-page 12 2000 Microchip Technology Inc.
FIGURE 3-3: CONFIGURATION WORD, PIC16C710/711
CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 bit0
bit 13-7 CP0: Code protection bits (2)
5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disab led
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits hav e to be given the same value to enable the code protection scheme listed.
2000 Microchip Technology Inc. DS30228J-page 13
PIC16C6XX/7XX/9XX
3.1 Embedding Configuration Word a nd ID Information in the Hex File.
To allow po rtability of code, the program me r is req uire d to rea d the c onfi guration word and ID lo ca tion s fro m the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
mes sa ge may be is su ed . Si mi la r l y, w hil e saving a hex file, co n fi gur at i on word an d ID in form at i on must be in cl u ded.
An option to not include this information may be provided.
Microchip Technology Inc. feels strongly that this feature is beneficial to the end customer.
PIC16C6XX/7XX/9XX
DS30228J-page 14 2000 Microchip Technology Inc.
3.2 Checksum
3.2.1 CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the
PIC16C6XX/7XX/9XX memory locations and adding
up the opcodes up to the maximum user addressable
location, e.g., 0x1FF for the PIC16C74. Any carry bits
e xcee ding 16-b its are ne glecte d. Finally, the config ur a-
tion w ord (appropriately mask ed) is added to the chec k-
sum. Checksum computation for each member of the
PIC16C6XX/7XX/9XX devices is shown in Table 3-1.
The checksum is calculated by summing the following:
• The contents of all program memory loca tions
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
ently depending on the code protect setting, the table
des c ri bes how to manipulate the actual program mem-
ory values to simulate the values that would be read
from a protec ted de v ice . When ca lcul ating a ch ec ksum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
Note that some older devices have an additional value
added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.
TABLE 3-1: CHECKSUM COMPUTATION
Device Code
Protect Checksum* Blank
Value
0x25E6 at
0 and max
address
PIC16C61 OFF
ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0
SUM_XNOR 7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF
0xFC6F 0x07CD
0xFC15
PIC16C620 OFF
ON SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F 0x3D7F
0x3DCE 0x094D
0x099C
PIC16C620A OFF
ON SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F 0x3D7F
0x3DCE 0x094D
0x099C
PIC16C621 OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
PIC16C621A OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
PIC16C622 OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C622A OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16CE623 OFF
ON SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F 0x3D7F
0x3DCE 0x094D
0x099C
Legend: CFGW = Configuration W ord
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a: b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. F or example ,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
2000 Microchip Technology Inc. DS30228J-page 15
PIC16C6XX/7XX/9XX
PIC16CE624 OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
PIC16CE625 OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C62 OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x3FF ] + SUM_XN OR7[0x400:0x 7FF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x1FF ] + SUM_XN OR7[0x200:0x 7FF] + CFGW & 0x003F +
0x3F80
SUM_XNOR7[0x 000:0x7FF] + CFGW & 0x003F + 0x3F80
0x37BF
0x37AF
0x379F
0x378F
0x038D
0x1D69
0x1D59
0x3735
PIC16C62A OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C62B OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C63 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF ] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF ] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C63A OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF ] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF ] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C64 OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x3FF ] + SUM_XN OR7[0x400:0x 7FF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x1FF ] + SUM_XN OR7[0x200:0x 7FF] + CFGW & 0x003F +
0x3F80
SUM_XNOR7[0x 000:0x7FF] + CFGW & 0x003F + 0x3F80
0x37BF
0x37AF
0x379F
0x378F
0x038D
0x1D69
0x1D59
0x3735
PIC16C64A OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C65 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF ] + SUM_XN OR7[0x 800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF ] + SUM_XN OR7[0x 400:FFF] + CFGW & 0x003F +
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum* Blank
Value
0x25E6 at
0 and max
address
Legend: CFGW = Configuration W ord
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a: b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. F or example ,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
PIC16C6XX/7XX/9XX
DS30228J-page 16 2000 Microchip Technology Inc.
PIC16C65A OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C65B OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C66 OFF
1/2
3/4
ALL
SUM[0x000:0x1F FF] + CFGW & 0x3F7F
SUM[0x000:0xF FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
PIC16C67 OFF
1/2
3/4
ALL
SUM[0x000:0x1F FF] + CFGW & 0x3F7F
SUM[0x000:0xF FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
PIC16C710 OFF
ON SUM[0x000:0x1FF] + CFGW & 0x3FFF
SUM[0x00:0x3F] + CFGW & 0x3FFF + SUM_ID 0x3DFF
0x3E0E 0x09CD
0xEFC3
PIC16C71 OFF
ON SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0
SUM_XNOR 7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0x3BFF
0xFC6F 0x07CD
0xFC15
PIC16C711 OFF
ON SUM[0x000:0x03FF] + CFGW & 0x3FFF
SUM[0x00:0x3FF] + CFGW & 0x3FFF + SUM_ID 0x3BFF
0x3C0E 0x07CD
0xEDC3
PIC16C712 OFF
1/2
ALL
SUM[0x000:0x07FF] + CFGW & 0x3F7F
SUM[0x000:0x03FF] + CFGW & 3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x37CE
0x034D
0xF58A
0x039C
PIC16C716 OFF
1/2
3/4
ALL
SUM[0x000:0x07FF] + CFGW & 0x3F7F
SUM[0x000:0x03FF] + CFGW & 0x3F7F + SUM_ID
SUM]0x000:0x01FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C72 OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C72A OFF
1/2
3/4
ALL
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
PIC16C73 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF ] + SUM_XN OR7[0x 800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF ] + SUM_XN OR7[0x 400:FFF] + CFGW & 0x003F +
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
PIC16C73A OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum* Blank
Value
0x25E6 at
0 and max
address
Legend: CFGW = Configuration W ord
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a: b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. F or example ,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
2000 Microchip Technology Inc. DS30228J-page 17
PIC16C6XX/7XX/9XX
PIC16C73B OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C74 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF ] + SUM_XN OR7[0x 800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF ] + SUM_XN OR7[0x 400:FFF] + CFGW & 0x003F +
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
PIC16C74A OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C74B OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
PIC16C76 OFF
1/2
3/4
ALL
SUM[0x000:0x1F FF] + CFGW & 0x3F7F
SUM[0x000:0xF FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
PIC16C77 OFF
1/2
3/4
ALL
SUM[0x000:0x1F FF] + CFGW & 0x3F7F
SUM[0x000:0xF FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
PIC16C773 OFF
1/2
3/4
ALL
SUM[0x000:0x0F FF] + CFGW & 0x3F7F
SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x55EE
0x48DE
0x3BCE
0xFB4D
0x07A3
0xFA93
0x079C
PIC16C774 OFF
1/2
3/4
ALL
SU:M[0x000:0FFF] + CFGW & 0x3F7F
SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0X55EE
0X48DE
0x3BCE
0xFB4D
0x07A3
0xFA93
0X079C
PIC16C923 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F3F
SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID
CFGW & 0x3F3F + SUM_ID
0x2F3F
0x516E
0x405E
0x2F4E
0xFB0D
0x0323
0xF213
0xFB1C
PIC16C924 OFF
1/2
3/4
ALL
SUM[0x000:0xF FF] + CFGW & 0x3F3F
SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID
CFGW & 0x3F3F + SUM_ID
0x2F3F
0x516E
0x405E
0x2F4E
0xFB0D
0x0323
0xF213
0xFB1C
PIC16C745 OFF
1000:1FFF
800:1FFF
ALL
SUM(0000:1FFF) + CFGW & 0x3F3F
SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID
SUM(0000:07FF ) + CFGW & 0x3F3F + SUM_ID
CFGW * 0x3F3F + SUM_ID
1F3F
396E
2C5E
1F4E
EB0D
EB23
DE13
EB1C
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum* Blank
Value
0x25E6 at
0 and max
address
Legend: CFGW = Configuration W ord
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a: b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. F or example ,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
PIC16C6XX/7XX/9XX
DS30228J-page 18 2000 Microchip Technology Inc.
PIC16c765 OFF
1000:1FFF
800:1FFF
ALL
SUM(0000:1FFF) + CFGW & 0x3F3F
SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID
SUM(0000:07FF ) + CFGW & 0x3F3F + SUM_ID
CFGW * 0x3F3F + SUM_ID
1F3F
396E
2C5E
1F4E
EB0D
EB23
DE13
EB1C
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
Device Code
Protect Checksum* Blank
Value
0x25E6 at
0 and max
address
Legend: CFGW = Configuration W ord
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a: b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. F or example ,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
2000 Microchip Technology Inc. DS30228J-page 19
PIC16C6XX/7XX/9XX
4.0 PROGRAM/VERIFY MODE
TABLE 4-1: AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, un less otherwise stated, (20°C recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.
Parameter
No. Sym. Characteristic Min. Typ. Max. Units Conditions
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD)
during programming ––20 mA
PD3 VDDV Supply voltage during verify VDDmin – VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during
programming 12.75 – 13.25 V Note 2
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.5 – 13.25 –
PD6 IPP Programming supply current (from
VPP)––50mA
PD9 VIH (RB6, RB7) input high level 0.8 VDD – – V Schmitt Trigger input
PD8 VIL (RB6, RB7) input low level 0.2 VDD – – V Schmitt Trigger inpu t
Serial Program Ve rify
P1 TRMCLR/VPP r i se time (VSS to VHH)
for test mode entry ––8.0µs
P2 Tf MCLR Fall time – – 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 – – ns
P4 Thld1 Data in hold time after clock ↓ 100 – – ns
P5 Tdly1 Data input not driven to next clock
input (delay required between com-
mand/data or command/command)
1.0 – – µs
P6 Tdly2 Delay between clock ↓ to clock ↑ of
next command or data 1.0 – – µs
P7 Tdly3 Clock ↑ to date out valid
(during read data) 200 – – ns
P8 Thld0 Hold time after MCLR ↑2––µs
Note 1: Program must be ver ified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
PIC16C6XX/7XX/9XX
DS30228J-page 20 2000 Microchip Technology Inc.
FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
FIGURE 4-2: READ DATA COMMAND (PROGRAM/VERIFY)
FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
}
}
0
0
0
1µs min.
P5
1µs min.
P6
0
15
5432
1
6
5
Program/Verify Test Mode
0
43
0
100ns
P4
1
100ns
min.
P3
Reset
21
100ns
P8
VIHH
RB6
(CLOCK)
RB7
(DATA) 0
MCLR/VPP
}
}
P4
100ns
min.
P3
}
00
1µs min.
P5
1µs min.
P6 15
5432
1
6
5
Program/Verify Test Mode
0
43
0100ns
P4
1
100ns
min.
P3
Reset
21
100ns
P8
VIHH
RB6
(CLOCK)
RB7
(DATA) 0
MCLR/VPP
RB7 = output RB7
input
P7
}
}
}
0
000
00
11
12345 61
2
100ns
min
P3 P4
P6
1µs min. Next Command
P5
1µs min.
VIHH
MCLR/VPP
RB6
(CLOCK)
(DATA)
RB7
Reset Program/Verify Test Mode
2000 Microchip Technology Inc. DS30228J-page 21
PIC16C6XX/7XX/9XX
NOTES:
PIC16C6XX/7XX/9XX
DS30228J-page 22 2000 Microchip Technology Inc.
NOTES:
2000 Microchip Technology Inc. DS30228J-page 23
PIC16C6XX/7XX/9XX
NOTES:
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.
It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is giv en and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights
arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with e xpress written
approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellect ual proper ty
rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S .A. and other countries. All rights reserv ed. Al l other
trademarks mentioned herein are the property of their respective companies.
DS30228J-pa
g
e 24
2000 Microchip Technology Inc.
All rights reserved. © 2/1/00 Microchip Technology Incorporated. Printed in the USA. Tuesda y, February 01, 2000 Printed on recycled paper.
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PICmicro
®
8-bit MCUs, KEELOQ
®
code hopping
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products. In addition, Microchip’s quality
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