Low Cost Low Power Instrumentation Amplifier AD620 FEATURES CONNECTION DIAGRAM Weigh scales ECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controls Battery-powered and portable equipment -IN 2 7 +VS +IN 3 6 -VS 4 AD620 RG OUTPUT 5 REF Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages PRODUCT DESCRIPTION The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 V max, and offset drift of 0.6 V/C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Supereta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/Hz at 1 kHz, 0.28 V p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 s to 0.01%, and its cost is low enough to enable designs with one in-amp per channel. 30,000 TOTAL ERROR, PPM OF FULL SCALE Comment Better specs at lower price Dual channel or differential out Low power, wide input range JFET input Best gain accuracy +2 precision op amps or differential out Ultra low noise 8 TOP VIEW Table 1. Next Generation Upgrades for AD620 Part AD8221 AD8222 AD8226 AD8220 AD8228 AD8295 AD8429 1 25,000 3 OP AMP IN-AMP (3 OP-07s) 20,000 15,000 AD620A 10,000 RG 5,000 0 0 5 10 SUPPLY CURRENT (mA) 15 20 00775-0-002 APPLICATIONS RG 00775-0-001 Easy to use Gain set with one external resistor (Gain range 1 to 10,000) Wide power supply range (2.3 V to 18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 V max, input offset voltage 0.6 V/C max, input offset drift 1.0 nA max, input bias current 100 dB min common-mode rejection ratio (G = 10) Low noise 9 nV/Hz @ 1 kHz, input voltage noise 0.28 V p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications 120 kHz bandwidth (G = 100) 15 s settling time to 0.01% Figure 2. Three Op Amp IA Designs vs. AD620 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703(c) 2003-2011 Analog Devices, Inc. All rights reserved. AD620 TABLE OF CONTENTS Specifications .....................................................................................3 RF Interference............................................................................15 Absolute Maximum Ratings ............................................................5 Common-Mode Rejection.........................................................16 ESD Caution ..................................................................................5 Grounding....................................................................................16 Typical Performance Characteristics..............................................6 Ground Returns for Input Bias Currents.................................17 Theory of Operation .......................................................................12 AD620ACHIPS Information .........................................................18 Gain Selection..............................................................................15 Outline Dimensions........................................................................19 Input and Output Offset Voltage ..............................................15 Ordering Guide ...........................................................................20 Reference Terminal .....................................................................15 Input Protection ..........................................................................15 REVISION HISTORY 7/11--Rev. G to Rev. H Changes to Input Protection section ............................................15 Deleted Figure 3.................................................................................1 Deleted Figure 9 ..............................................................................15 Added Table 1 ....................................................................................1 Changes to RF Interference section..............................................15 Moved Figure 2 ..................................................................................1 Edit to Ground Returns for Input Bias Currents section...........17 Added ESD Input Diodes to Simplified Schematic ....................12 Added AD620CHIPS to Ordering Guide ....................................19 Changes to Input Protection Section............................................15 Added Figure 41; Renumbered Sequentially ...............................15 7/03--Data Sheet Changed from Rev. E to Rev. F Changes to AD620ACHIPS Information Section ......................18 Edit to FEATURES............................................................................1 Updated Ordering Guide ...............................................................20 Changes to SPECIFICATIONS .......................................................2 Removed AD620CHIPS from ORDERING GUIDE ...................4 Removed METALLIZATION PHOTOGRAPH...........................4 12/04--Rev. F to Rev. G Updated Format.................................................................. Universal Change to Features............................................................................1 Change to Product Description.......................................................1 Changes to Specifications.................................................................3 Added Metallization Photograph....................................................4 Replaced Figure 4-Figure 6 ..............................................................6 Replaced Figure 15 ............................................................................7 Replaced Figure 33 ..........................................................................10 Replaced Figure 34 and Figure 35.................................................10 Replaced Figure 37 ..........................................................................10 Changes to Table 3 ..........................................................................13 Replaced TPCs 1-3 ...........................................................................5 Replaced TPC 12 ...............................................................................6 Replaced TPC 30 ...............................................................................9 Replaced TPCs 31 and 32...............................................................10 Replaced Figure 4 ............................................................................10 Changes to Table I...........................................................................11 Changes to Figures 6 and 7 ............................................................12 Changes to Figure 8 ........................................................................13 Edited INPUT PROTECTION section........................................13 Added new Figure 9........................................................................13 Changes to RF INTERFACE section ............................................14 Changes to Figure 41 and Figure 42 .............................................14 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section...............................................................................................15 Changes to Figure 43 ......................................................................15 Updated OUTLINE DIMENSIONS .............................................16 Change to Figure 44 ........................................................................17 Rev. H | Page 2 of 20 AD620 SPECIFICATIONS Typical @ 25C, VS = 15 V, and RL = 2 k, unless otherwise noted. Table 2. AD620A Parameter GAIN Gain Range Gain Error2 G=1 G = 10 G = 100 G = 1000 Nonlinearity G = 1-1000 G = 1-100 Gain vs. Temperature VOLTAGE OFFSET Input Offset, VOSI Overtemperature Average TC Output Offset, VOSO Overtemperature Average TC Offset Referred to the Input vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Overtemperature Average TC Input Offset Current Overtemperature Average TC INPUT Input Impedance Differential Common-Mode Input Voltage Range3 Overtemperature Overtemperature Conditions Min G = 1 + (49.4 k/RG) 1 VOUT = 10 V VOUT = -10 V to +10 V RL = 10 k RL = 2 k Typ AD620B Max Min 10,000 1 Typ Max Min 10,000 1 AD620S1 Typ Max Unit 10,000 0.03 0.15 0.15 0.40 0.10 0.30 0.30 0.70 0.01 0.10 0.10 0.35 0.02 0.15 0.15 0.50 0.03 0.15 0.15 0.40 0.10 0.30 0.30 0.70 % % % % 10 10 40 95 10 10 40 95 10 10 40 95 ppm ppm 10 -50 ppm/C ppm/C 125 V 225 V G=1 Gain >12 (Total RTI Error = VOSI + VOSO/G) VS = 5 V 30 to 15 V VS = 5 V to 15 V VS = 5 V 0.3 to 15 V VS = 15 V 400 VS = 5 V VS = 5 V to 15 V VS = 5 V 5.0 to 15 V 10 -50 10 -50 125 15 185 50 30 85 1.0 0.1 0.6 0.3 1.0 V/C 1000 1500 2000 200 500 750 1000 400 1000 1500 2000 V V V 15 2.5 7.0 5.0 15 V/C VS = 2.3 V to 18 V 80 95 110 110 100 120 140 140 0.5 3.0 0.3 VS = 2.3 V -VS + 1.9 to 5 V -VS + 2.1 VS = 5 V -VS + 1.9 to 18 V -VS + 2.1 80 100 120 120 2.0 2.5 100 120 140 140 0.5 3.0 0.3 1.0 1.5 80 95 110 110 1.0 1.5 100 120 140 140 0.5 8.0 0.3 0.5 0.75 1.5 1.5 8.0 10||2 10||2 10||2 10||2 10||2 10||2 dB dB dB dB 2 4 1.0 2.0 nA nA pA/C nA nA pA/C +VS - 1.2 -VS + 1.9 +VS - 1.2 -VS + 1.9 +VS - 1.2 G_pF G_pF V +VS - 1.3 +VS - 1.4 -VS + 2.1 -VS + 1.9 +VS - 1.3 +VS - 1.4 -VS + 2.1 -VS + 1.9 +VS - 1.3 +VS - 1.4 V V +VS - 1.4 -VS + 2.1 +VS + 2.1 -VS + 2.3 +VS - 1.4 V Rev. H | Page 3 of 20 AD620 AD620A AD620B Parameter Conditions Min Typ Max Common-Mode Rejection Ratio DC to 60 Hz with 1 k Source Imbalance VCM = 0 V to 10 V G=1 73 90 G = 10 93 110 G = 100 110 130 G = 1000 110 130 OUTPUT Output Swing RL = 10 k VS = 2.3 V -VS + +VS - 1.2 to 5 V 1.1 Overtemperature -VS + 1.4 +VS - 1.3 VS = 5 V -VS + 1.2 +VS - 1.4 to 18 V Overtemperature -VS + 1.6 +VS - 1.5 Short Circuit Current 18 DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 1000 G = 10 800 G = 100 120 G = 1000 12 Slew Rate 0.75 1.2 Settling Time to 0.01% 10 V Step G = 1-100 15 G = 1000 150 NOISE Voltage Noise, 1 kHz Total RTI Noise = (e 2 ni ) + (e / G)2 Min Typ 80 100 120 120 90 110 130 130 Max Min AD620S 1 Typ Max 73 93 110 110 90 110 130 130 Unit dB dB dB dB -VS + 1.1 +VS - 1.2 -VS + 1.1 +VS - 1.2 V -VS + 1.4 -VS + 1.2 +VS - 1.3 +VS - 1.4 -VS + 1.6 -VS + 1.2 +VS - 1.3 +VS - 1.4 V V +VS - 1.5 -VS + 2.3 +VS - 1.5 -VS + 1.6 0.75 18 18 V mA 1000 800 120 12 1.2 1000 800 120 12 1.2 kHz kHz kHz kHz V/s 15 150 s s 0.75 15 150 no Input, Voltage Noise, eni Output, Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100-1000 Current Noise 0.1 Hz to 10 Hz REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY Operating Range 4 Quiescent Current 9 72 3.0 0.55 0.28 100 10 f = 1 kHz 20 50 VIN+, VREF = 0 -VS + 1.6 1 0.0001 2.3 VS = 2.3 V to 18 V Overtemperature TEMPERATURE RANGE For Specified Performance 13 100 60 +VS - 1.6 0.9 18 1.3 1.1 1.6 -40 to +85 9 72 13 100 9 72 13 100 nV/Hz nV/Hz 3.0 0.55 0.28 100 10 6.0 0.8 0.4 3.0 0.55 0.28 100 10 6.0 0.8 0.4 V p-p V p-p V p-p fA/Hz pA p-p 20 50 -VS + 1.6 1 0.0001 2.3 -40 to +85 1 See Analog Devices military data sheet for 883B tested specifications. Does not include effects of external resistor RG. 3 One input grounded. G = 1. 4 This is defined as the same supply range that is used to specify PSR. 2 Rev. H | Page 4 of 20 60 +VS - 1.6 0.9 18 1.3 1.1 1.6 20 50 60 +VS - 1.6 k A V 0.9 18 1.3 V mA 1.1 1.6 mA -VS + 1.6 1 0.0001 2.3 -55 to +125 C AD620 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Internal Power Dissipation 1 Input Voltage (Common-Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (Q) Storage Temperature Range (N, R) Operating Temperature Range AD620 (A, B) AD620 (S) Lead Temperature Range (Soldering 10 seconds) 1 Rating 18 V 650 mW VS 25 V Indefinite -65C to +150C -65C to +125C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -40C to +85C -55C to +125C ESD CAUTION 300C Specification is for device in free air: 8-Lead Plastic Package: JA = 95C 8-Lead CERDIP Package: JA = 110C 8-Lead SOIC Package: JA = 155C Rev. H | Page 5 of 20 AD620 TYPICAL PERFORMANCE CHARACTERISTICS (@ 25C, VS = 15 V, RL = 2 k, unless otherwise noted.) 2.0 50 SAMPLE SIZE = 360 1.5 INPUT BIAS CURRENT (nA) PERCENTAGE OF UNITS 40 30 20 10 1.0 +IB -I B 0.5 0 -0.5 -1.0 -40 0 40 80 INPUT OFFSET VOLTAGE (V) -2.0 -75 -25 25 75 TEMPERATURE (C) 125 175 00775-0-008 -80 00775-0-005 0 5 00775-0-009 -1.5 Figure 6. Input Bias Current vs. Temperature Figure 3. Typical Distribution of Input Offset Voltage 2.0 50 CHANGE IN OFFSET VOLTAGE (V) SAMPLE SIZE = 850 PERCENTAGE OF UNITS 40 30 20 0 -1200 -600 0 600 1200 INPUT BIAS CURRENT (pA) 00775-0-006 10 1.5 1.0 0.5 0 0 1 2 3 WARM-UP TIME (Minutes) 4 Figure 7. Change in Input Offset Voltage vs. Warm-Up Time Figure 4. Typical Distribution of Input Bias Current 1000 50 SAMPLE SIZE = 850 GAIN = 1 VOLTAGE NOISE (nV/ Hz) 30 20 10 100 GAIN = 10 10 GAIN = 100, 1,000 0 -400 -200 0 200 400 INPUT OFFSET CURRENT (pA) 1 1 Figure 5. Typical Distribution of Input Offset Current 10 100 1k FREQUENCY (Hz) 10k 100k 00775-0-010 GAIN = 1000 BW LIMIT 00775-0-007 PERCENTAGE OF UNITS 40 Figure 8. Voltage Noise Spectral Density vs. Frequency (G = 1-1000) Rev. H | Page 6 of 20 AD620 10 1 10 100 FREQUENCY (Hz) 1000 00775-0-014 100 00775-0-011 CURRENT NOISE (fA/ Hz) 1000 Figure 12. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div Figure 9. Current Noise Spectral Density vs. Frequency TOTAL DRIFT FROM 25C TO 85C, RTI (V) 10,000 FET INPUT IN-AMP 1000 AD620A 100 10 1k 10k 100k 1M SOURCE RESISTANCE () 10M 00775-0-015 TIME (1 SEC/DIV) 00775-0-012 RTI NOISE (2.0V/DIV) 100,000 Figure 13. Total Drift vs. Source Resistance Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) 160 140 RTI NOISE (0.1V/DIV) 120 CMR (dB) 100 G = 1000 G = 100 G = 10 G=1 80 60 40 Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 0 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 00775-0-016 00775-0-013 TIME (1 SEC/DIV) 20 Figure 14. Typical CMR vs. Frequency, RTI, Zero to 1 k Source Imbalance Rev. H | Page 7 of 20 AD620 180 35 160 30 G = 100 80 G = 10 60 G=1 10 1 100 1k FREQUENCY (Hz) 10k 100k 10 1M 0 G = 1000 1k 10k 100k FREQUENCY (Hz) Figure 15. Positive PSR vs. Frequency, RTI (G = 1-1000) 160 -0.5 INPUT VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) +VS -0.0 140 PSR (dB) 120 G = 1000 80 G = 100 60 G = 10 G=1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M 00775-0-018 40 20 0.1 -1.5 +1.5 +1.0 +0.5 0 5 10 15 SUPPLY VOLTAGE Volts 20 20 Figure 19. Input Voltage Range vs. Supply Voltage, G = 1 1000 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES) +VS -0.0 100 10 1 1k 10k 100k FREQUENCY (Hz) 1M 10M 00775-0-019 GAIN (V/V) -1.0 -VS +0.0 Figure 16. Negative PSR vs. Frequency, RTI (G = 1-1000) 0.1 100 1M Figure 18. Large Signal Frequency Response 180 100 G = 100 00775-0-021 20 0.1 15 5 00775-0-017 40 G=1 20 00775-0-022 PSR (dB) 100 25 00775-0-020 G = 1000 120 BW LIMIT 140 OUTPUT VOLTAGE (V p-p) G = 10, 100, 1000 -0.5 RL = 10k -1.0 RL = 2k -1.5 +1.5 RL = 2k +1.0 RL = 10k +0.5 -VS +0.0 0 5 10 15 SUPPLY VOLTAGE Volts Figure 20. Output Voltage Swing vs. Supply Voltage, G = 10 Figure 17. Gain vs. Frequency Rev. H | Page 8 of 20 AD620 .... .... .... .... .... .... .... .... .... .... VS = 15V G = 10 20 10 0 100 1k LOAD RESISTANCE () 10k Figure 21. Output Voltage Swing vs. Load Resistance 00775-0-023 0 00775-0-026 .... .... .... .... .... .... .... .... .... .... Figure 24. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%) .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 00775-0-027 00775-0-024 .... .... .... .... .... .... .... .... .... .... Figure 22. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%) Figure 25. Small Signal Response, G = 10, RL = 2 k, CL = 100 pF .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... Figure 23. Small Signal Response, G = 1, RL = 2 k, CL = 100 pF 00775-0-030 00775-0-025 OUTPUT VOLTAGE SWING (V p-p) 30 Figure 26. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%) Rev. H | Page 9 of 20 AD620 20 .... .... .... .... .... .... .... .... ........ SETTLING TIME (s) 15 TO 0.01% TO 0.1% 10 0 5 10 OUTPUT STEP SIZE (V) 20 00775-0-032 00775-0-029 0 1000 00775-0-033 5 .... .... .... .... .... .... .... .... ........ 15 Figure 30. Settling Time vs. Step Size (G = 1) Figure 27. Small Signal Pulse Response, G = 100, RL = 2 k, CL = 100 pF 1000 SETTLING TIME (s) .... .... .... .... .... .... .... .... .... .... 100 10 00775-0-030 .... .... .... .... .... .... .... .... .... .... 1 1 10 100 GAIN Figure 28. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01% ) Figure 31. Settling Time to 0.01% vs. Gain, for a 10 V Step .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... ........ .... .... .... .... .... .... .... .... .... .... 00775-0-031 00775-0-034 .... .... .... .... .... .... .... .... ........ Figure 29. Small Signal Pulse Response, G = 1000, RL = 2 k, CL = 100 pF Rev. H | Page 10 of 20 Figure 32. Gain Nonlinearity, G = 1, RL = 10 k (10 V = 1 ppm) AD620 10k * INPUT 10V p-p .... .... .... .... .... .... .... .... ........ 1k 10T 10k 100k VOUT +VS 1k 2 100 7 1 G = 1000 G=1 AD620 G = 100 G = 10 .... .... .... .... .... .... .... .... ........ 49.9 499 5.49k 00775-0-035 8 3 5 4 -VS *ALL RESISTORS 1% TOLERANCE Figure 33. Gain Nonlinearity, G = 100, RL = 10 k (100 V = 10 ppm) Figure 35. Settling Time Test Circuit .... .... .... .... .... .... .... .... ........ 00775-0-036 .... .... .... .... .... .... .... .... ........ Figure 34. Gain Nonlinearity, G = 1000, RL = 10 k (1 mV = 100 ppm) Rev. H | Page 11 of 20 6 00775-0-037 11k AD620 THEORY OF OPERATION The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 36), yet offer 10x lower input bias current thanks to Supereta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. +VS VB 20A I2 20A A1 A2 10k C2 C1 10k OUTPUT A3 10k +VS R3 400 REF +VS R1 - IN 10k R2 Q1 Q2 RG GAIN SENSE R4 400 +IN GAIN SENSE -VS 00775-0-038 I1 Figure 36. Simplified Schematic of AD620 The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 k, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then G= 49.4 k RG = RG +1 49.4 k G-1 Make vs. Buy: a Typical Bridge Application Error Budget The AD620 offers improved performance over "homebrew" three op amp IA designs, along with smaller size, fewer components, and 10x lower supply current. In the typical application, shown in Figure 37, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of -40C to +85C. Table 4 shows how to calculate the effect various error sources have on circuit accuracy. Rev. H | Page 12 of 20 AD620 Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by 2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error. Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle removes all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy. 10V R = 350 00775-0-039 PRECISION BRIDGE TRANSDUCER AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX 100 ** OP07D 10k ** OP07D 00775-0-040 R = 350 10k * 10k ** REFERENCE R = 350 10k * OP07D AD620A 10k * 10k* "HOMEBREW" IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3ppm/C TRACKING **DISCRETE 1% RESISTOR, 100ppm/ C TRACKING SUPPLY CURRENT = 15mA MAX Figure 37. Make vs. Buy Table 4. Make vs. Buy Error Budget Error Source ABSOLUTE ACCURACY at TA = 25C Input Offset Voltage, V Output Offset Voltage, V Input Offset Current, nA CMR, dB DRIFT TO 85C Gain Drift, ppm/C Input Offset Voltage Drift, V/C Output Offset Voltage Drift, V/C RESOLUTION Gain Nonlinearity, ppm of Full Scale Typ 0.1 Hz to 10 Hz Voltage Noise, V p-p Error, ppm of Full Scale AD620 Homebrew AD620 Circuit Calculation "Homebrew" Circuit Calculation 125 V/20 mV 1000 V/100 mV/20 mV 2 nA x350 /20 mV 110 dB(3.16 ppm) x5 V/20 mV (150 V x 2)/20 mV ((150 V x 2)/100)/20 mV (6 nA x350 )/20 mV (0.02% Match x 5 V)/20 mV/100 6,250 500 18 791 10,607 150 53 500 Total Absolute Error 7,559 11,310 100 ppm/C Track x 60C (2.5 V/C x 2 x 60C)/20 mV (2.5 V/C x 2 x 60C)/100 mV/20 mV 3,600 3,000 450 6,000 10,607 150 Total Drift Error 7,050 16,757 40 14 54 14,663 40 27 67 28,134 (50 ppm + 10 ppm) x60C 1 V/C x 60C/20 mV 15 V/C x 60C/100 mV/20 mV 40 ppm 0.28 V p-p/20 mV 40 ppm (0.38 V p-p x 2)/20 mV Total Resolution Error Grand Total Error G = 100, VS = 15 V. (All errors are min/max and referred to input.) Rev. H | Page 13 of 20 00775-0-041 R = 350 RG 499 AD620 5V 3k 3k 3k 3k 20k 7 3 REF 8 AD620B G = 100 499 6 5 1 IN 10k ADC 4 2 20k 1.7mA AD705 AGND 0.6mA MAX 0.10mA 00775-0-042 1.3mA MAX DIGITAL DATA OUTPUT Figure 38. A Pressure Monitor Circuit that Operates on a 5 V Single Supply Pressure Measurement Medical ECG Although useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. The low current noise of the AD620 allows its use in ECG monitors (Figure 39) where high source resistances of 1 M or higher are not uncommon. The AD620's low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for batterypowered data recorders. Figure 38 shows a 3 k pressure transducer bridge powered from 5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it also serves applications such as diagnostic noninvasive blood pressure measurement. R1 10k R4 1M The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. +3V PATIENT/CIRCUIT PROTECTION/ISOLATION C1 Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance. R3 24.9k R2 24.9k RG 8.25k AD620A G=7 0.03Hz HIGHPASS FILTER G = 143 OUTPUT 1V/mV OUTPUT AMPLIFIER -3V Figure 39. A Medical ECG Monitor Circuit Rev. H | Page 14 of 20 00775-0-043 AD705J AD620 Precision V-I Converter INPUT AND OUTPUT OFFSET VOLTAGE The AD620, along with another op amp and two resistors, makes a precision current source (Figure 40). The op amp buffers the reference terminal to maintain good CMR. The output voltage, VX, of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load. The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total VOS for a given gain is calculated as Total Error RTI = input error + (output error/G) +VS Total Error RTO = (input error x G) + output error 7 3 8 1 VIN- 6 The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. R1 5 2 4 IL -VS I L= REFERENCE TERMINAL + VX - AD620 RG Vx R1 = AD705 [(V IN+) - (V IN- )] G R1 LOAD 00775-0-044 VIN+ Figure 40. Precision Voltage-to-Current Converter (Operates on 1.8 mA, 3 V) GAIN SELECTION The AD620 gain is resistor-programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 5 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ). For any arbitrary gain, RG can be calculated by using the formula: RG = 49.4 k G -1 INPUT PROTECTION The AD620 safely withstands an input current of 60 mA for several hours at room temperature. This is true for all gains and power on and off, which is useful if the signal source and amplifier are powered separately. For longer time periods, the input current should not exceed 6 mA. For input voltages beyond the supplies, a protection resistor should be placed in series with each input to limit the current to 6 mA. These can be the same resistors as those used in the RFI filter. High values of resistance can impact the noise and AC CMRR performance of the system. Low leakage diodes (such as the BAV199) can be placed at the inputs to reduce the required protection resistance. +SUPPLY To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TC--less than 10 ppm/C--for the best performance. R +IN Table 5. Required Values of Gain Resistors Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 0.1% Std Table Value of RG( ) 49.3 k 12.4 k 5.49 k 2.61 k 1.01 k 499 249 98.8 49.3 Calculated Gain 2.002 4.984 9.998 19.93 49.91 100.0 199.4 501.0 1,003.0 VOUT AD620 R REF -IN -SUPPLY 00775-0-052 1% Std Table Value of RG() 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Figure 41. Diode Protection for Voltages Beyond Supply RF INTERFERENCE All instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 42 demonstrates such a configuration. The filter limits the input Rev. H | Page 15 of 20 AD620 signal according to the following relationship: +VS - INPUT FilterFreq DIFF = FilterFreq CM = 1 2R(2C D + C C ) 100 1 2RC C AD648 RG 100 AD620 VOUT -VS REFERENCE 00775-0-046 where CD 10CC. + INPUT CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R x CC degrades the AD620 CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that CC is at least one magnitude smaller than CD. The effect of mismatched CCs is reduced with a larger CD:CC ratio. -VS Figure 43. Differential Shield Driver +VS - INPUT +15V R CC CD CC +IN -IN RG 2 AD620 VOUT REFERENCE + + INPUT AD620 499 RG 2 AD548 - 00775-0-047 R 100 10 F 0.1 F VOUT -VS REF Figure 44. Common-Mode Shield Driver Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate "local ground." Figure 42. Circuit to Attenuate RF Interference COMMON-MODE REJECTION Instrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 43 and Figure 44 show active data guards that are configured to improve ac common-mode rejections by "bootstrapping" the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 45). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 45. ANALOG P.S. +15V C -15V 0.1 F 0.1 F DIGITAL P.S. C +5V 1 F 1 F 1 F + AD620 AD585 S/H AD574A ADC Figure 45. Basic Grounding Practice Rev. H | Page 16 of 20 DIGITAL DATA OUTPUT 00775-0-048 -15V 00775-0-045 GROUNDING 10 F 0.1 F AD620 +VS GROUND RETURNS FOR INPUT BIAS CURRENTS - INPUT Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying "floating" input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 46, Figure 47, and Figure 48. Refer to A Designer's Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications. AD620 RG VOUT LOAD REFERENCE + INPUT TO POWER SUPPLY GROUND +VS - INPUT 00775-0-050 -VS Figure 47. Ground Returns for Bias Currents with Thermocouple Inputs RG AD620 VOUT +VS - INPUT LOAD + INPUT REFERENCE -VS VOUT LOAD REFERENCE + INPUT Figure 46. Ground Returns for Bias Currents with Transformer-Coupled Inputs 100k 100k -VS TO POWER SUPPLY GROUND Figure 48. Ground Returns for Bias Currents with AC-Coupled Inputs Rev. H | Page 17 of 20 00775-0-051 TO POWER SUPPLY GROUND AD620 00775-0-049 RG AD620 AD620ACHIPS INFORMATION Die size: 1803 m x 3175 m Die thickness: 483 m Bond Pad Metal: 1% Copper Doped Aluminum To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 1A and Pad 1B in parallel to one end of RG and Pad 8A and Pad 8B in parallel to the other end of RG. For unity gain applications where RG is not required, Pad 1A and Pad 1B must be bonded together as well as the Pad 8A and Pad 8B. 1A 8A LOGO 1B 2 8B 7 6 4 5 00775-0-053 3 Figure 49. Bond Pad Diagram Table 6. Bond Pad Information Pad No. 1A 1B 2 3 4 5 6 7 8A 8B 1 Mnemonic RG RG -IN +IN -VS REF OUTPUT +VS RG RG Pad Coordinates 1 Y (m) +1424 +628 +453 -294 -1419 -1429 -1254 +139 +1423 +372 X (m) -623 -789 -790 -790 -788 +570 +693 +693 +505 +693 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 49. Rev. H | Page 18 of 20 AD620 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 5 1 4 5.00 (0.1968) 4.80 (0.1890) 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 4.00 (0.1574) 3.80 (0.1497) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 070606-A 0.055 (1.40) MAX 5 0.310 (7.87) 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) SEATING PLANE 15 0 4 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Rev. H | Page 19 of 20 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8). Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 5 1.27 (0.0500) BSC 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 8 1 Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 012407-A 8 AD620 ORDERING GUIDE Model1 AD620AN AD620ANZ AD620BN AD620BNZ AD620AR AD620ARZ AD620AR-REEL AD620ARZ-REEL AD620AR-REEL7 AD620ARZ-REEL7 AD620BR AD620BRZ AD620BR-REEL AD620BRZ-RL AD620BR-REEL7 AD620BRZ-R7 AD620ACHIPS AD620SQ/883B 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 13" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel 8-Lead SOIC_N, 7" Tape and Reel Die Form 8-Lead CERDIP Z = RoHS Compliant Part. (c) 2003-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00775-0-7/11(H) Rev. H | Page 20 of 20 Package Option N-8 N-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 Q-8