P1817A/B
Low-Power Mobile VGA
EMI Reduction IC
©2010 SCILLC. All rights reserved. Publication Order Number:
NOVEMBER 2010 – Rev. 2.1 P1817/D
Features
• FCC approved method of EMI attenuation.
• Generates a low EMI spread spectrum clock of the
input frequency.
• Optimized for frequency range from:
P1817A – 20 to 32MHz
P1817B – 10 to 20MHz
• Internal loop filter minimizes external components
and board space.
• Two selectable spread ranges.
• Low inherent cycle-to-cycle jitter.
• 3.3V or 5V operating voltage range.
• TTL or CMOS compatible inputs and outputs.
• Ultra-low power CMOS design.
3.17mA @ 3.3V, 10MHz | 6.20mA @ 5.0V, 10MHz
4.28mA @ 3.3V, 14MHz | 7.50mA @ 5.0V, 14MHz
5.50mA @ 3.3V, 20MHz | 9.50mA @ 5.0V, 20MHz
• Supports notebook VGA and other LCD timing
controller applications.
• SSON / SBM pin for Spread Spectrum On/Off
and Standby Mode controls.
• Available in 8-pin SOIC package.
Product Description
The P1817 is a versatile spread spectrum frequency
modulator designed specifically for input clock
frequencies. The P1817 reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of downstream clock and data
dependent signals. The P1817 allows significant system
cost savings by reducing the number of circuit board
layers, ferrite beads, shielding and other passive
components that are traditionally required to pass EMI
regulations.
The P1817 modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock, and
more importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
The P1817 uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
Applications
The P1817 is targeted towards notebook LCD displays,
and other displays using an LVDS interface, PC
peripheral devices, and embedded systems.
Block Diagram
SR0
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter VCO Output
Divider
PLL
REF
XOUT
VSS
CLKIN / XIN
ModOUT
VDD
SSON
P1817A/B
Rev. 2 | Page 2 of 8 | www.onsemi.com
Pin Configuration
Pin Description
Pin#
Pin Name Type Description
1 CLKIN / XIN I
Crystal connection or external reference frequency input. This pin has dual
functions. It can be connected either to an external crystal or an external reference
clock. To put the part into standby mode, disable the input clock signal to this pin
and pull SSON/SBM (pin4) low. Refer to Standby Mode Selection Table.
2 VSS P Ground Connection. Connect to system ground.
3 SR0 I Digital logic input used to select Spreading Range. Refer to Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
4 SSON / SBM I Spread Spectrum On/Off and standby mode control.
Refer to Standby Mode Selection Table.
5 ModOUT O Spread spectrum clock output or Reference output.
Refer to Standby Mode Selection Table.
6 REF O Reference Output.
7 VDD P Connect to +3.3V or 5.0V.
8 XOUT O Connect to crystal. No connect if externally generated clock signal is used.
ModOUT
1
2
3
4 5
6
7
8
P1817A/B
CLKIN / XIN
VSS
SR0
SSON / SBM
REF
VDD
XOUT
P1817A/B
Rev. 2 | Page 3 of 8 | www.onsemi.com
Standby Mode Selection
CLKIN SSON / SBM
Spread
Spectrum ModOUT PLL Mode
Disabled 0 N/A Disabled Disabled Standby
Disabled 1 N/A Disabled Free Running Free Running
Enabled 0 OFF Reference Disabled Buffer out
Enabled 1 ON Normal Normal Normal
Spread Range Selection, VDD = 5V
CLKIN Frequency SR0 Spreading Range Modulation Rate
10MHz
1 ±1.50%
(CLKIN/10)*20.83KHz
0 ±1.90%
14.318MHz
1 ±1.36%
0 ±1.64%
15MHz
1 ±1.30%
0 ±1.50%
20MHz
1 ±0.95%
0 ±1.125%
Spread Range Selection, VDD = 3.3V
CLKIN Frequency SR0 Spreading Range Modulation Rate
10MHz
1 ±1.50%
(CLKIN/10)*20.83KHz
0 ±1.65%
14.318MHz
1 ±1.40%
0 ±1.70%
15MHz
1 ±1.37%
0 ±1.63%
20MHz
1 ±1.10%
0 ±1.28%
P1817A/B
Rev. 2 | Page 4 of 8 | www.onsemi.com
Schematic for Notebook VGA Application
1
To set the P1817 to standby mode, disable the input clock (pin 1, CLKIN) and pull pin 4 SSON / SBM low.
Absolute Maximum Ratings
Symbol Parameter Rating Unit
VDD, V
IN
Voltage on any pin with respect to GND -0.5 to +7.0 V
T
STG
Storage temperature -65 to +125 °C
T
s
Max. Soldering Temperature (10 sec) 260 °C
T
J
Junction Temperature 150 °C
T
DV
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
Reference clock output.
P1817A/B
CLKIN / XIN
VSS VDD
ModOUT
SR0
SSON /
SBM
1
2
3
4 5
7
8
XOUT VDD
Ferrite Bead
10 to 20MHz and 20 to 32MHz
EMI reduced clock output.
27pF
REF 6
GND
GND
VDD
VDD
0Ω
0Ω
0Ω
0Ω
Pull pin 4 low to turn Spread Spectrum
OFF and enable Standby Mode
1
.
0.1uF
GND
27pF
Crystal
Use either pull-up or pull-down
Resistor with 0Ω.
0.1uF
GND
P1817A/B
Rev. 2 | Page 5 of 8 | www.onsemi.com
Operating Conditions
Parameter Description Min Max Unit
VDD Supply Voltage 2.7 5.5 V
T
A
Operating Temperature (Ambient Temperature) -40 +85 °C
C
L
Load Capacitance 15 pF
C
IN
Input Capacitance 7 pF
DC Electrical Characteristics
Symbol
Parameter Min Typ Max Unit
V
IL
Input low voltage GND-0.3 0.8 V
V
IH
Input high voltage 2.0 VDD+0.3 V
I
IL
Input low current (pull-up resistors on inputs SR0, and SSON
/ SBM) -35 µA
I
IH
Input high current (pull-down resistors on inputs SR0, and
SSON / SBM) 35 µA
I
XOL
X
OUT
output low current
@ 0.4V, VDD = 3.3V 3
mA
@ 0.4V, VDD = 5.0V 20
I
XOH
X
OUT
output high current
@ 2.5V, VDD = 3.3V 3
mA
@ 4.5V, VDD = 5.0V 20
V
OL
Output low voltage
VDD = 3.3V, I
OL
= 20mA 0.4
V
VDD = 5.0V, I
OL
= 20mA
V
OH
Output high voltage
VDD = 3.3V, I
OH
= 20mA 2.5
V
VDD = 5.0V, I
OH
= 20mA 4.5
I
CC
Dynamic supply current
standby mode
Normal Mode f
IN-min
f
IN-typ
f
IN-max
mA 3.3Vand 10pF loading 3.2 7.0
5.0Vand 10pF loading 6.2 13.6
I
DD
Static supply current standby mode 0.6 mA
VDD Operating voltage 2.7 3.3 5.5 V
t
ON
Power up time (first locked clock cycle after power up) 0.18 mS
Z
OUT
Clock output impedance 50 Ω
P1817A/B
Rev. 2 | Page 6 of 8 | www.onsemi.com
AC Electrical Characteristics
Symbol Parameter Min Typ Max Unit
f
IN
Input frequency (See device type P1817A or 1817B) 10 32 MHz
f
OUT
Output frequency (See device type P1817A or 1817B) 10 32 MHz
t
LH1
Output rise time
Measured at 0.8V to 2.0V 0.7 0.9 1.1
nS
Measured at 1.2V to 3.75V 0.75
t
HL1
Output fall time
Measured at 0.8V to 2.0V 0.6 0.8 1.0
nS
Measured at 1.2V to 3.75V 0.75
t
JC
Jitter (cycle-to-cycle) 360 pS
t
D
Output duty cycle 45 50 55 %
Note: 1. tLH and tHL are measured into a capacitive load of 15pF.
P1817A/B
Rev. 2 | Page 7 of 8 | www.onsemi.com
Package Information
8-lead (150-mil) SOIC Package
D
EH
D
A1
A2
A
θ
L
C
B
e
Symbol
Dimensions
Inches Millimeters
Min Max Min Max
A1 0.004 0.010 0.10 0.25
A 0.053 0.069 1.35 1.75
A2 0.049 0.059 1.25 1.50
B 0.012 0.020 0.31 0.51
C 0.007 0.010 0.18 0.25
D 0.193 BSC 4.90 BSC
E 0.154 BSC 3.91 BSC
e 0.050 BSC 1.27 BSC
H 0.236 BSC 6.00 BSC
L 0.016 0.050 0.41 1.27
θ 0° 8° 0° 8°
P1817A/B
Rev. 2 | Page 8 of 8 | www.onsemi.com
Ordering Code
Part Number Marking Package Type Temperature
P1817AF-08SR ABA 8-Pin SOIC, Tape & Reel, Pb free 0°C to 70°C
P1817BF-08SR ABC 8-Pin SOIC, Tape & Reel, Pb free 0°C to 70°C
A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free
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