DECEMBER 2003
DSC-5311/07
1
©2002 Integrated Device Technology, Inc.
A
0
-A
18
Address Inputs Input Synchronous
CE Chip Enab le Inp ut Sy nchrono us
CS
0
, CS
1
Chip Selects Input Synchronous
OE Output Enable Input Asynchronous
GW Global Write Enable Input Synchronous
BWE By te Write Enable Inp ut Sy nc hro no us
BW
1
, BW
2
, BW
3
, BW
4
(1) Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV Burst Address Ad vance Input Synchronous
ADSC Address Status (Cache Controller) Input Synchronous
ADSP Address Status (Processor) Input Synchronous
LBO Linear / Interleaved Burst Order Input DC
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/O Sy nc hro no us
V
DD
, V
DDQ
Co re P o we r, I/ O Po we r Sup p ly N/ A
V
SS
Ground Supply N/A
53 11 t b l 01
Features
◆◆
◆◆
◆256K x 36, 512K x 18 memory configurations
◆◆
◆◆
◆Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆◆
◆◆
◆LBOLBO
LBOLBO
LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GWGW
GWGW
GW), byte
write enable (BWEBWE
BWEBWE
BWE), and byte writes (BWBW
BWBW
BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆2.5V I/O supply (VDDQ)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67602
IDT71V67802
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
6.42
2
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Symbol
Pin Function
I/O
Active
Description
A
0
-A
18
Address Inputs I N/A Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK and ADSC Lo w or ADSP Lo w and CE Lo w.
ADSC Address Status
(Cache Contro lle r) I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW inp ut that is
used to load the address registers with new addresses.
ADSP Address Status
(Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW in put that is use d to
load the address registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance I LOW Synchronous Address Advance. ADV is an active LOW inp ut that is use d to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is , there is no address advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW
1
-BW
4
Individual Byte
Write Enables I LOW Synchronous byte write enables. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc.
Any active byte write causes all outputs to be disabled.
CE Chip Enab le I LOW Sy nc hrono us chip e nab le . CE i s us e d with CS
0
and CS
1
to e nab le the IDT71V67602/7802.
CE also gates ADSP.
CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS
0
Chip S e lec t 0 I HIGH Sy nc hro nou s a cti v e HIGH chip s e le c t. CS
0
is used with CE and CS
1
to enable the chip.
CS
1
Chip Select 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to enable the chip.
GW Glo bal Write
Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Inp ut/ Outp ut I/ O N/ A S ync hrono us d ata i np ut/ o utp ut (I/ O) p i ns . Bo th the d ata i np ut p ath and d ata o utp ut p ath a re
registered and triggered by the rising edge of CLK.
LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the inte rleav e d burst
sequence is selected. When LBO is LOW the Line ar burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE Outp ut Enable I LOW As ync hro nous outp ut e nable . When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O p ins are in a hig h-
impedance state.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Powe r Supply N/A N/A 2.5V I/O Sup ply.
V
SS
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
ZZ Sleep Mode I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67602/7802 to its lowest p ower consumption level. Data retention is guaranteed in
Sleep Mode.
53 11 t bl 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Functional Block Diagram
A0–A17/18 ADDRESS
REGISTER
CLR A1*
A0* 18/19
2
18/19 A2–A18
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A0,A1
BW 4
BW 3
BW 2
BW 1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS0
CS1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BW E
LBO
I/O0–I/O31
I/OP1–I/OP4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
OUTPUT
REGISTER
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2Burst
Logic
Binary
Counter
5311 drw 01
ZZ Powerdown
,
6.42
4
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
100-pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial
Unit
V
TERM
(2)
Terminal Vo ltage with
Re s p e ct to G ND
-0.5 to +4.6
V
V
TERM
(3,6)
Terminal Vo ltage with
Re s p e ct to G ND
-0.5 to V
DD
V
V
TERM
(4,6)
Terminal Vo ltage with
Re s p e ct to G ND
-0.5 to V
DD
+0.5
V
V
TERM
(5,6)
Terminal Vo ltage with
Re s p e ct to G ND
-0.5 to V
DDQ
+0.5
V
T
A
(7)
Commercial
-0 to +70
o
C
Industrial
-40 to +85
o
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Outp ut Current
50
mA
5 311 tbl 03
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Co mme rcial 0°C to + 70° C 0V 3.3V±5% 2.5V±5%
Industrial -40°C to +85° C 0V 3. 3V± 5% 2.5V±5%
5311 t bl 04
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap ac itance
V
IN
= 3dV
5
pF
C
I/O
I/O Cap ac itance
V
OUT
= 3dV
7
pF
5311 tbl 07
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core S up p ly Voltag e 3.135 3.3 3. 465 V
V
DDQ
I/O Supp ly Vo ltag e 2.375 2.5 2.625 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage - Inputs 1.7 ____ V
DD
+0.3 V
V
IH
Inpu t Hi gh Voltage - I/O 1 . 7 ____ V
DDQ
+0.3 V
V
IL
Inp ut L o w Vo ltag e -0. 3(1) ____ 0.7 V
5311 t bl 06
Recommended DC Operating
Conditions
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. TA is the "instant on" case temperature.
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap ac itance
V
IN
= 3dV
7
pF
C
I/O
I/O Cap acitanc e
V
OUT
= 3dV
7
pF
5311 tbl 07a
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap ac itance
V
IN
= 3dV
7
pF
C
I/O
I/O Cap ac itanc e
V
OUT
= 3dV
7
pF
5311 t bl 07b
6.42
5
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Pin Configuration 256K x 36, 100-Pin TQFP
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
17
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
5311 drw 02
VDD /NC
(1)
I/O15
I/OP3
NC
I/OP4
A
15
A
16
I/OP1
NC
I/OP2
ZZ(2)
,
Top View
6.42
6
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Pin Configuration 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
5311 drw 03
VDD /NC
(1)
NC
NC
NC
NC
A
16
A
17
NC
NC
A10
ZZ(2)
,
A
18
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
7
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Pin Configuration 512K x 18, 119 BGA
Pin Configuration 256K x 36, 119 BGA
Top View
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. Pin U6 will be internally pulled to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, TRST should be tied low
and TCK, TDI, and TMS should be pulled through a resistor to 3.3V. TDO should be left unconnected.
4. On future 18M device CS0 will be removed, B2 will be be used for address expansion.
1234567
AVDDQ A6A4ADSP A8A16 VDDQ
BNC CS0A3ADSC A9A17 NC
CA7A2VDD A12 A15 NC
DI/O16 I/OP3 VSS NC VSS I/OP2 I/O15
EI/O17 I/O18 VSS CE VSS I/O13 I/O14
FVDDQ I/O19 VSS OE VSS I/O12 VDDQ
GI/O20 I/O21 BW3ADV BW2I/O11 I/O10
HI/O22 I/O23 VSS GW VSS I/O9I/O8
JVDDQ VDD NC VDD NC VDD VDDQ
KI/O24 I/O26 VSS CLK VSS I/O6I/O7
LI/O25 I/O27 BW4NC BW1I/O4I/O5
MVDDQ I/O28 VSS BWE VSS I/O3VDDQ
NI/O29 I/O30 VSS A1VSS I/O2I/O1
PI/O31 I/OP4 VSS A0VSS I/O 0
I/O
P1
RNC A5LBO VDD A13
TNC NC A10 A11 A14 NC ZZ
UVDDQ DNU(3) DNU(3) DNU(3) DNU(3)
DNU(3) VDDQ
5311 drw 04
VDD /NC
NC
NC ,
(1)
(2)
(4)
1234567
A
V
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
B
NC CS0
(4)
A
3
ADSC A
9
A
18
NC
C
A
7
A
2
V
DD
A
13
A
17
NC
D
I/O
8
NC V
SS
NC V
SS
I/O
P1
NC
E
NC I/O
9
V
SS
CE V
SS
NC I/O
7
F
V
DDQ
NC V
SS
OE V
SS
I/O
6
V
DDQ
G
NC I/O
10
BW
2
ADV NC I/O
5
H
I/O
11
NC V
SS
GW V
SS
I/O
4
NC
J
V
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
K
NC I/O
12
V
SS
CLK V
SS
NC I/O
3
L
I/O
13
NC NC BW
1
I/O
2
NC
M
V
DDQ
I/O
14
V
SS
BWE V
SS
NC V
DDQ
N
I/O
15
NC V
SS
A
1
V
SS
I/O
1
NC
P
NC I/O
P2
V
SS
A
0
V
SS
NC I/O
0
R
NC A
5
LBO V
DD
A
12
T
NC A
10
A
15
NC A
14
A
11
ZZ
U
V
DDQ
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
V
DDQ
5311 drw 05
NC
V
DD
/NC NC
V
SS
V
SS
,
(1)
(2)
6.42
8
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
1234567891011
ANC
(3) A7CE BW3BW2CS1BWE ADSC ADV A8NC
BNC A
6CS0BW4BW1CLK GW OE ADSP A9NC(3)
CI/O
P3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2
DI/O
17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14
EI/O
19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12
FI/O
21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10
GI/O
23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9I/O8
HV
DD(1) NC NC VDD VSS VSS VSS VDD NC NC ZZ(2)
JI/O
25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7I/O6
KI/O
27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5I/O4
LI/O
29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3I/O2
MI/O
31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1I/O0
NI/O
P4 NC VDDQ VSS NC NC(3) NC VSS VDDQ NC I/OP1
PNCNC
(3) A5A2DNU(4) A1DNU(4) A10 A13 A14 A17
RLBO NC(3) A4A3DNU(4) A0DNU(4) A11 A12 A15 A16
5311 tb l 17a
1234567891011
ANC
(3) A7CE BW2NC CS1BWE ADSC ADV A8A10
BNC A
6CS0NC BW1CLK GW OE ADSP A9NC(3)
CNC NCV
DDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1
DNC I/O
8VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7
ENC I/O
9VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6
FNCI/O
10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5
GNC I/O
11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4
HV
DD(1) NC NC VDD VSS VSS VSS VDD NC NC ZZ(2)
JI/O
12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3NC
KI/O
13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2NC
LI/O
14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1NC
MI/O
15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0NC
NI/O
P2 NC VDDQ VSS NC NC(3) NC VSS VDDQ NC NC
PNC NC
(3) A5A2DNU(4) A1DNU(4) A11 A14 A15 A18
RLBO NC(3) A4A3DNU(4) A0DNU(4) A12 A13 A16 A17
5311 tb l 17b
Pin Configuration 512K x 18, 165 fBGA
Pin Configuration 256K x 36, 165 fBGA
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
6.42
9
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
L
I
| Input Leak ag e Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___ 5µA
|I
LZZ
|ZZ and LBO Input Leak age Curre nt(1) V
DD
= Max., V
IN
= 0V to V
DD
___ 30 µA
|I
LO
| Output Le ak age Current V
OUT
= 0V to V
DDQ
, Device Deselected ___ 5µA
V
OL
Outp ut Lo w Voltage I
OL
= +6mA, V
DD
= Min. ___ 0.4 V
V
OH
Outp ut Hig h Voltag e I
OH
= -6mA, V
DD
= Min. 2.0 ___ V
5311 tb l 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 2.5V)
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
50Ω
I/O Z0=50Ω
5311 drw 06 ,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5311 drw 07 ,
Symbol
Parameter
Test Conditions
166MHz
150MHz
133MHz
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
IDD Operating Power S upply Current Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) 340 305 325 260 280 mA
ISB1 CM OS S ta nd by Powe r S upp l y
Current Device Dese lected , Outputs Op en, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3) 50 50 70 50 70 mA
ISB2 Clo c k Runni ng P owe r
Supply Current De vice Dese le cte d, Outputs Ope n, V DD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3) 160 155 175 150 170 mA
IZZ Full Sleep Mode Supp ly Current ZZ > VHD, VDD = Max. 50 50 70 50 70 mA
5311 tbl 09
Inp ut P ul se Le v e ls
Inp ut Ri s e /Fal l Tim e s
Inp ut Timing Refere nc e Leve ls
Outp ut Timing Re ference Leve ls
AC Test Load
0 to 2.5V
2ns
V
DDQ
/2
V
DDQ
/2
See Figure 1
5 311 t bl 10
6.42
10
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Synchronous Truth Table(1,3)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation
Address
Used
CE
CS
0
CS
1
ADSP ADSC ADV GW BWE BW
x
OE
(2)
CLK
I/O
De se le cte d Cy cl e, P o wer Do wn No ne H X X X L X X X X X - HI-Z
De se le cte d Cy cl e, P o wer Do wn No ne L X H L X X X X X X - HI-Z
De se le cte d Cy cl e, P o wer Do wn No ne L L X L X X X X X X - HI-Z
De se le cte d Cyc le , P o wer Do wn No ne L X H X L X X X X X - HI-Z
De se le cte d Cy cl e, P o wer Do wn No ne L L X X L X X X X X - HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L - DOUT
Read Cycle, Begin Burst ExternalL HL L XXXXXH-HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - DOUT
Read Cycle, Begin Burst External L H L H L X H L H L - DOUT
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - DIN
Write Cycle, Begin Burst External L H L H L X L X X X - DIN
Re ad Cycle , Continue Burst Next X X X H H L H H X L - DOUT
Re ad Cy cle , Co ntinue Burs t Nex t X X X H H L H H X H - HI-Z
Re ad Cycle , Continue Burst Next X X X H H L H X H L - DOUT
Re ad Cy cle , Co ntinue Burs t Nex t X X X H H L H X H H - HI-Z
Re ad Cycle , Continue Burst Next H X X X H L H H X L - DOUT
Re ad Cy cle , Co ntinue Burs t Nex t H X X X H L H H X H - HI-Z
Re ad Cycle , Continue Burst Next H X X X H L H X H L - DOUT
Re ad Cy cle , Co ntinue Burs t Nex t H X X X H L H X H H - HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X - DIN
Write Cycle, Continue Burst Next X X X H H L L X X X - DIN
Write Cycle, Continue Burst Next H X X X H L H L L X - DIN
Write Cycle, Continue Burst Next H X X X H L L X X X - DIN
Read Cycle, Suspend Burst Curre nt X X X H H H H H X L - DOUT
Read Cycle, Suspend Burst Curre nt X X X H H H H H X H - HI-Z
Read Cycle, Suspend Burst Curre nt X X X H H H H X H L - DOUT
Read Cycle, Suspend Burst Curre nt X X X H H H H X H H - HI-Z
Read Cycle, Suspend Burst Curre nt H X X X H H H H X L - DOUT
Read Cycle, Suspend Burst Curre nt H X X X H H H H X H - HI-Z
Read Cycle, Suspend Burst Curre nt H X X X H H H X H L - DOUT
Read Cycle, Suspend Burst CurrentHX X X HHHXHH-HI-Z
Write Cycle, Suspend Burst Curre nt X X X H H H H L L X - DIN
Write Cycle, Suspend Burst Curre nt X X X H H H L X X X - DIN
Write Cycle, Suspend Burst Curre nt H X X X H H H L L X - DIN
Write Cycle, Suspend Burst Curre nt H X X X H H L X X X - DIN
5311 tbl 11
6.42
11
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table(1, 2)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67802.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation
GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes L X X X X X
Write all Bytes H L L L L L
Writ e B y te 1 (3) HLLHHH
Writ e B y te 2 (3) HLHLHH
Writ e B y te 3 (3) HLHHLH
Writ e B y te 4 (3) HLHHHL
5 311 tb l 12
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Add ress 1 0 1 1 0 0 0 1
Fourth Address(1) 11000110
5 311 tb l 15
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Add ress 1 0 1 1 0 0 0 1
Fourth Address(1) 11100100
5 311 tb l 14
Operation
(2)
OE
ZZ
I/O Status
Power
Re ad L L Data Out Ac tiv e
Read H L High-Z Active
Write X L High-Z – Data In Activ e
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
5 311 tb l 13
6.42
12
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
166MHz
150MHz
133MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CYC
Clo c k Cyc le Time 6 ____ 6.7 ____ 7.5 ____ ns
t
CH
(1) Clock High Pulse Width 2.4 ____ 2.6 ____ 3____ ns
t
CL
(1) Cl o ck Lo w P uls e Wid th 2. 4 ____ 2.6 ____ 3____ ns
Output Parameters
t
CD
Clock High to Valid Data ____ 3.5 ____ 3.8 ____ 4.2 ns
t
CDC
Cloc k Hig h to Data Cha ng e 1.5 ____ 1.5 ____ 1.5 ____ ns
t
CLZ
(2) Cl o c k Hi gh to Outp ut Ac tiv e 0 ____ 0____ 0____ ns
t
CHZ
(2) Cloc k Hi gh to Data Hi gh - Z 1. 5 3. 5 1.5 3.8 1.5 4.2 ns
t
OE
Output Enable Access Time ____ 3.5 ____ 3.8 ____ 4.2 ns
t
OLZ
(2) Output Enable Low to Output A ctive 0 ____ 0____ 0____ ns
t
OHZ
(2) Outp ut Enable Hig h to Outp ut High-Z ____ 3.5 ____ 3.8 ____ 4.2 ns
Set Up Ti mes
t
SA
Address Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SS
Address Status Se tup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SD
Data In S e tup Time 1. 5 ____ 1.5 ____ 1.5 ____ ns
t
SW
Write Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SAV
Address Advance Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SC
Chip Enable/Sele ct Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
Hol d Times
t
HA
Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HS
Ad d re ss S tatus Ho ld Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HD
Data In Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HW
Write Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HAV
Address Advance Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HC
Chip E nab l e /S ele c t Ho ld Ti me 0. 5 ____ 0.5 ____ 0.5 ____ ns
S l e ep M ode and Conf ig ur atio n Par am eter s
t
ZZPW
ZZ Pul s e Wi d th 10 0 ____ 100 ____ 100 ____ ns
t
ZZR
(3) ZZ Rec ov ery Ti me 10 0 ____ 100 ____ 100 ____ ns
t
CFG
(4) Confi g uratio n S e t-up Time 24 ____ 27 ____ 30 ____ ns
5 311 t b l 16
6.42
13
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in
the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Pipelined Read Cycle(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE, BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay) O3(Ay) O2(Ay)
O2(Ay)
t
CLZ
ADV
CE,C
S
1
(Note 3)
Pipelined
Read Burst Pipelined Read
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burst wraps around
to its initial state)
O4(Ay)
5311 drw 08
ADSP
ADVHIGHsuspends
burst
,
6.42
14
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address
Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state
of the LBO input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
CLK
ADSP
A
DDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
O1(Az)
Single Read Pipelined Burst Read
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
5311 drw 09
t
CD
,
6.42
15
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2 . O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Write Cycle No. 1 GW Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
D
ATA
OUT
OE
t
HC
t
SD
I1(Ax) I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,C
S
1
t
HW
GWt
SW
(Note 3)
I2(Az)
Burst Write
Burst Read Burst Write
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVHIGHsuspends burst)
I1(Ay)
GWis ignored when ADSPinitiates acycle and is sampled on the next clock rising edge
t
SC
5311 drw 10
,
6.42
16
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Timing Waveform of Write Cycle No. 2 Byte Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
Write Burst Write
I1(Ax) I2(Ay) I2(Ay)
(ADVsuspends burst)
I2(Az)
tHD
Burst
Read Extended
Burst Write
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,C
S
1
t
HW
BWEt
SW
(Note 3)
I1(Az)
Az
I4(Ay)
I1(Ay) I4(Ay)
I3(Ay)
t
SC
BWEis ignored when ADSPinitiates acycle and is sampled on next clock rising edge
BWxis ignored when ADSPinitiates acycle and is sampled on next clock rising edge
I3(Az)
O3(Aw)
5311 drw 11
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2 . O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
17
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
Single Read Snooze Mode
tZZPW
5311 drw 12
O1(Ax)
Ax
(Note 4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
18
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
CLK
ADSP
GW,BWE,BWx
CE, CS1
CS0
ADDRESS
ADSC
DATAOUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5311 drw 14 ,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5311 drw 15 ,
6.42
19
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
100-Pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42
20
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
21
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
22
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Ordering Information
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 fine pitch Ball Grid Array
S
Power
X
Speed
XX
Package
PF
BG
BQ
XXX
166*
150
133 Frequency in Megahertz
5311 drw13
Device
Type
71V67602
71V67802 256K x 36 Pipelined Burst Synchronous SRAM
512K x 18 Pipelined Burst Synchronous SRAM ,
Blank
I
XX
Process/Temp
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
* Industrial temperature not available on 166MHz devices
6.42
23
IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created datasheet from 71V676 and 71V678 datasheets.
I/O voltage and speed grade offerings have been split into separate part numbers.
See the following datasheets for:
3.3V I/O, 133–166MHz 71V67603
2.5V I/O, 133–166MHz 71V67602
3.3V I/O, 183–200MHz 71V67613
2.5V I/O, 183–200MHz 71V67612
04/26/00 Pg. 4 Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended
Operating Temperature tables.
Pg. 7 Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Pg. 18 Inserted 100 pin TQFP Package Diagram Outline
05/24/00 Pg. 1,4,8,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 on BGA and TQFP pin configuration
Pg. 20 Correction in the 119 BGA Package Diagram Outline
07/12/00 Pg. 5,6,8 Remove note from TQFP and BQ165 pinouts
Pg. 7 Remove/Add reference note from BG119 pinout
Pg. 20 Update BG119 Package Diagram Outline
08/27/02 Pg. 4,9,12 Added Industrial information to the datasheet.
22
10/28/02 Pg. 1-23 Changed datasheet from Advanced Information to Final Release.
11/19/02 Pg. 1,9,12,22Added 166MHz to datasheet.
04/15/03 Pg .4 Updated 165fBGA table from TBD to 7.
12/20/03 Pg. 7 Updated 119BGA pin configurations- reordered I/O signals on P6, P7 (128K x 36) and P7, N6, L6, K7,
H6, G7, F6,E7, D6 (256K x 18).
