5962-9858701QZC - Aeroflex Incorporated

Standard Products

UT69151 SµMMITTM RTE

Product Handbook

June 1999

FEATURES

rComprehensive MIL-STD-1553 dual redundant Remote

Terminal (RT) with integrated bus transceivers, Memory,

and Memory Management Unit (MMU)

rMIL-STD-1553B, Notice II RT

-Internal command illegalization

-16-bit read/write time-tag with user-defined resolution

-Subaddress data buffering

rProgrammable interrupt architecture with automatic

interrupt logging available

rAutonomous operation

-External initialization bus

-Ideal for low cost remote terminals

rInternal Memory Management Unit (MMU) interfaces host

subsystem to 64Kbit SRAM

-Wait state and zero-wait state configurations

rBuilt-In Test capability

rSupports IEEE Standard 1149.1 (JTAG)

rFlexible power supply configurations

-+5-volt only operation

rFlexible packaging offering:

-139-pin pingrid array (PGA)

-140-lead flatpack

- 132-lead flatpack

r Standard Microcircuit Drawing 5962-98587

TRANSCEIVER

CHA

TRANSCEIVER

CHB

SµMMIT

Protocol

Handler

MMU

ADDRESS

DATA

INTERFACE

CONTROL

REMOTE

TERMINAL

ADDRESS

MEMORY

MODE STATUS INTERRUPTSJTAG

Figure 1. UT69151 SµMMIT RTE Block Diagram

Auto-Init Bus

2SµMMIT RTE

2.0 REMOTE TERMINAL ARCHITECTURE

The SµMMIT Remote Terminal (RTE) is an interface device

linking a MIL-STD-1553 serial data bus to a host

microprocessor and/or subsystem. The SµΜΜIT RTE’s MIL-

STD-1553 interface includes encoding/decoding logic, error

detection, command recognition, DMA interface, control/

configuration registers, clock, and reset logic. The following

sections review the architecture and use. Each section supplies

information on the SµΜΜIT RTE’s configuration and

operation.

2.1 Register Descriptions

The following list provides the bit descriptions of the 32 internal

registers that control SµΜΜIT RTE operation. All register bits

are active high and reflect a logic zero condition (0000 hex) after

Master Reset (except those reflecting input pins).

Note: Reference section 7.1, Table 12 for SµMMIT RTE 8-bit register address numbers.

2.1.1 Control Register (Read/Write) - Register 0

This 16-bit register controls SµΜΜIT RTE configuration. To make changes to the SµΜΜIT RTE and this register, the STEX bit

(Bit 15 of the Control Register) must be logic zero. Note: The user has 5µs after TERACT active to stop execution.

Number Name Register Address

0Control Register 0000 (hex)

1 Operational Status Register 0001 (hex)

2 Current Command Register 0002 (hex)

3 Interrupt Mask Register 0003 (hex)

4Pending Interrupt Register 0004 (hex)

5Interrupt Log List Pointer Register 0005 (hex)

6BIT Word Register 0006 (hex)

7Time-Tag Register 0007 (hex)

8RT Descriptor Pointer Register 0008 (hex)

91553 Status Word Bits Register 0009 (hex)

10-15 Not Applicable 000A to 000F (hex)

16-31 Illegalization Registers 0010 to 001F (hex)

Bit Mnemonic Description

Number

15 STEX Start Execution. Assertion of this bit initiates SµΜΜIT RTE operation. A

Control Register write negating this bit inhibits SµΜΜIT RTE operation. A

remote terminal address parity error prevents SµΜΜIT RTE operation

regardless of the logical state of this bit. If a RT address parity error exists, bit

3 of Register 1 will be set low and bit 2 of Register 1 will be set high.

14 SBIT Start BIT. Assertion of this bit places the SµΜΜIT RTE into the Built-In Test

routine. The BIT test has a fault coverage of 93.4%. If the SµΜΜIT RTE has

been started, the host must halt the device in order to place the SµΜΜIT RTE

into the Built-In Test routine (STEX = 0) (see section 6.0 for additional

information).

Note: If Start BIT (SBIT) and Start Execution (STEX) are both set on one register

write, BIT has priority.

SµMMIT RTE

13 SRST Software Reset. Assertion of this bit immediately places the SµΜΜIT RTE into

a software reset. The software reset (which takes 5µs to execute), like MRST,

clears all internal logic.

Note: During auto-initialization this bit should not be loaded with a logic one.

SRST will only function after READY is asserted.

12 CHAEN Channel A Enable. Setting this bit enables Channel A operation. If negated, the

SµΜΜIT RTE does not recognize commands received over Channel A.

11 CHBEN Channel B Enable. Setting this bit enables Channel B operation. If negated, the

SµΜΜIT RTE does not recognize commands received over Channel B.

10 ETCE External Timer Clock Enable. Assertion of this bit to a logic one allows the

external timer clock input to supply stimulus to the internal time-tag counter.

Refer to section 2.1.8 for additional information.

Note: The user can only change the clock frequency before starting the device

(i.e., setting bit 15 of Register 0 to a logic one).

9PPACK Ping-pong acknowledge made. See section 3, Circular Buffer and Ping-Pong

Operation for additional information.

8CBSEL1 Circular buffer mode select. See section 3, Circular Buffer and Ping-Pong

Operation for additional information.

7CBSEL2 Circular buffer mode select. See section 3, Circular Buffer and Ping-Pong

Operation for additional information.

6N/A Always set this bit to logical zero.

5N/A Always set this bit to logical zero.

4BCEN Broadcast Enable. Assertion of this bit enables the SµΜΜIT RTE broadcast

option. Negation of this bit enables remote terminal address 31 as a unique

remote terminal address.

3 DYNBC Dynamic Bus Control Acceptance. This bit controls the SµΜΜIT RTE’s ability

to accept the dynamic bus control mode code. Assertion of this bit allows the

SµΜΜIT RTE to respond to a dynamic bus control mode code with status word

bit 18 set to a logic one. Negation of this bit prevents the assertion of status word

bit 18 upon reception of the dynamic mode code.

2PPEN Ping-Pong Enable. Assertion of this bit enables the ping-pong buffer feature of

the SµΜΜIT RTE and disables the message indexing feature. Negation of this

bit disables the ping-pong feature and enables the message indexing feature. See

section 3, Circular Buffer and Ping-Pong Operation for additional information.

1INTEN Interrupt Log Enable. Assertion of this bit enables the SµΜΜIT interrupt logging

feature. Negation of this bit prevents the logging of interrupts.

0XMTSW Transmit Status Word. Assertion of this bit allows the SµΜΜIT RTE to

automatically execute the TRANSMIT STATUS WORD mode code when

configured for MIL-STD-1553A mode operation. Refer to section 2.9 for

additional information.

Bit Mnemonic Description

Number

Bit Mnemonic Description

Number

4SµMMIT RTE

2.1.2 Operational Status Register (Read/Write) - Register 1

This register reflects pertinent status information for the SµΜΜIT RTE and is not reset to 0000 (hex) on MRST. Instead, the register

reflects the actual stimulus applied to input pins RTA(4:0), RTPTY, A/B STD, and LOCK. Assertion of the LOCK input prevents

the modification of the remote terminal address, mode selects, and A or B Standard. In this case, a write to this register’s most

significant nine bits is meaningless. If LOCK is negated, a read of this register reflects the information written into this register’s

most significant nine bits.

Note: To make changes to the SµΜΜIT RTE and this register, the STEX bit (Bit 15 in Register 0) must be logic zero.

Bit Mnemonic Description

Number

15 RTA4 Terminal Address Bit 4. This bit is the most significant bit of the remote terminal address.

This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is

active.

14 RTA3 Terminal Address Bit 3. This bit is Bit 3 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

13 RTA2 Terminal Address Bit 2. This bit is Bit 2 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

12 RTA1 Terminal Address Bit 1. This bit is Bit 1 of the remote terminal address. This bit is latched

on the rising edge of MRST and is a read only bit if the LOCK pin is active.

11 RTA0 Terminal Address Bit 0. This bit is the least significant bit of the remote terminal address.

This bit is latched on the rising edge of MRST and is a read only bit if the LOCK pin is

active.

10 RTPTY Terminal Address Parity Bit. This bit is appended to the remote terminal address bus

(RTA(4:0)) to supply odd parity. The SµΜΜIT RTE requires odd parity for proper

operation. This bit is latched on the rising edge of MRST and is a read only bit if the

LOCK pin is active.

9N/A Always set this bit to logical zero.

8Logical one Always set this bit to logical one.

7 A/B STD Military Standard 1553A or 1553B Standard. This bit determines whether the SµΜΜIT

RTE will be set to operate under MIL-STD-1553A or B. Assertion of this bit enables the

XMTSW bit (Bit 0 of the Control Register). Negation of this bit automatically allows the

SµΜΜIT RTE to operate under the MIL-STD-1553B protocol. This bit is latched on the

rising edge of MRST and is a read only bit if the LOCK pin is active. See section 2.9 for

further definition.

6LOCK LOCK Pin. This read-only bit reflects the inverted state of input pin LOCK and is latched

on the rising edge of MRST.

5AUTOEN AUTOEN Pin. This read-only bit reflects the inverted state of input pin AUTOEN.

Assertion of this input enables SµΜΜIT RTE auto-initialization.

4SSYSF SSYSF Pin. This read-only bit reflects the inverted state of the input pin SSYSF.

3EX SµΜΜIT RTE Executing. This read-only bit indicates whether the SµΜΜIT RTE is

presently executing or whether it is idle. A logic one indicates that the SµΜΜIT RTE is

executing; logic zero indicates that the SµΜΜIT RTE is idle.

2TAPF Terminal Address Parity Fail. This bit indicates the observance of a terminal address parity

error. The SµΜΜIT RTE checks for odd parity. This read only bit reflects the parity of

Operational Status Register bits 15-10, and is latched on the rising edge of MRST.

SµMMIT RTE

Note: Remote Terminal Address and Parity checked on start of execution.

2.1.3 Current Command Register (Read-only) - Register 2

This 16-bit register contains the last valid command processed by the SµΜΜIT RTE.

1READY READY Pin. This read-only bit reflects the inverted state of the output pin READY and

is cleared on reset.

0TERACT TERACT Pin. Assertion of this bit indicates that the SµΜΜIT RTE is presently processing

a message. This read only bit reflects the inverted state of output pin TERACT and is

cleared on reset.

Bit Mnemonic Description

Number

15 to 0 CC15-CC0 Current Command Bits. This register contains the last valid command received by the

SµΜΜIT RTE. This register is valid 13µs after TERACT is negated. (Bit 15 MSB - Bit

0 LSB).

Bit Mnemonic Description

Number

6SµMMIT RTE

2.1.4 Interrupt Mask Register (Read/Write) - Register 3

The SµΜΜIT RTE interrupt architecture allows for the masking of all interrupts. An interrupt is masked if the corresponding bit

of this register is set to logic zero. This feature allows the host or subsystem to temporarily disable the service of interrupts. While

masked, interrupt activity does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for

that event.

2.1.5 Pending Interrupt Register (Read-only) - Register 4

The Pending Interrupt Register contains information that identifies events that generate interrupts. The assertion of any bit in this

register asserts an output pin, MSG_INT or YF_INT (three clock cycles). Writing to the most significant 4 bits of this register

generates a YF_INT.

Bit Mnemonic Description

Number

15 MAB Memory Access Blocked Interrupt

14 WRAPF Wrap Fail Interrupt

13 TAPF Terminal Address Parity Fail Interrupt

12 BITF BIT Fail Interrupt

11 MERR Message Error Interrupt

10 SUBAD Subaddress Accessed Interrupt

9BDRCV Broadcast Command Received Interrupt

8IXEQ0 Index Equal Zero Interrupt

7ILLCMD Illegal Command Interrupt

6-0 N/A Not Applicable

SµMMIT RTE

Bit Mnemonic Description

Number

15 MAB Memory Access Blocked. Once the SµΜΜIT RTE begins internal DMA activity, an

internal timer starts. If all internal DMA activity is not completed by the time the counter

decrements to zero, the interrupt is generated. In the SµΜΜIT RTE mode, the YF_INT

interrupt is generated (if not masked), current command processing ends, and the

SµΜΜIT RTE will remain on-line. Current cycle terminated, bus released.

14 WRAPF Wrap Fail Interrupt. The RTE automatically compares the transmitted word (encoder

word) to the reflected decoder word via the continuous loop-back feature. If the encoder

word and reflected word do not match, the WRAPF bit is asserted in the BIT Word Register

and a YF_INT interrupt is generated (if not masked). The loop-back path is via the MIL-

STD-1553 bus transceiver.

13 TAPF Terminal Address Parity Fail Interrupt. This bit reflects the outcome of the remote terminal

address parity check. A logic one indicates a parity failure. When a parity error occurs,

the SµΜΜIT RTE does not begin operation (STEX bit forced to logic zero), channel A

and B do not enable, the TAPF bit is asserted here and in the BIT Word Register, and a

YF_INT interrupt is generated (if not masked).

12 BITF BIT Fail Interrupt. Assertion of this bit indicates a BIT failure. Status word bit 19 is

automatically set to a logic one when a BIT failure occurs. If a BIT fails, the BITF bit is

asserted here and in the BIT Word Register, and a YF_INT interrupt is generated (if not

masked). Operation continues.

11 MERR Message Error Interrupt. Assertion of this bit indicates that a message error condition

exists. The SµΜΜIT RTE can detect Manchester errors, sync-field, word count errors

(too many or too few), MIL-STD-1553 word parity errors, bit count errors (too many or

too few), and protocol errors. If not masked, this bit is always set when the SµΜΜIT RTE

asserts bit 9 of the status word (e.g., illegal commands, invalid data word, etc.). MSG_INT

interrupt generated (if not masked).

10 SUBAD Subaddress Accessed Interrupt. Assertion of this bit indicates a pre-selected subaddress

has transacted a message. To determine the exact subaddress, the host interrogates the

interrupt log IAW. MSG_INT interrupt generated (if not masked).

9BDRCV Broadcast Command Received Interrupt. This bit is set to a logic one to indicate the

SµΜΜIT RTE’s receipt of a valid broadcast command. The SµΜΜIT RTE suppresses

status word transmission. MSG_INT interrupt generated (if not masked).

8IXEQ0 Index Equal Zero Interrupt. The SµΜΜIT RTE asserts this bit to indicate the completion

of a pre-defined number of commands by the SµΜΜIT RTE. Upon assertion of this

interrupt, the host or subsystem updates the subaddress descriptor to prevent the potential

loss of data. MSG_INT interrupt generated (if not masked).

7ILLCMD Illegal Command Interrupt. This bit is set to a logic one to indicate the reception of an

illegal command by the SµΜΜIT RTE. Upon receipt of this command, the SµΜΜIT

RTE responds with a status word only; Bit 9 of the status word is set to a logic one.

MSG_INT interrupt generated (if not masked).

6-0 N/A Always set these bits to logical zero.

8SµMMIT RTE

2.1.6 Interrupt Log List Pointer Register (Read/Write) - Register 5

The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List. The Interrupt Log List is a 32 word ring-

buffer that contains information pertinent to the service of interrupts. The SµΜΜIT RTE architecture requires the location of the

Interrupt Log List on a 32-word boundary. The most significant 4 bits of this register should be initialized to logical zero. The 7

bits ranging from bit 11 to bit 5 designate the location of the Interrupt Log List within a 4K memory space. The lower 5 bits of this

register should be initialized to a logic zero. The SµΜΜIT RTE controls the lower 5 bits to implement the ring-buffer architecture.

The host or subsystem reads this register to determine the location and number of interrupts within the Interrupt Log List (least

significant 5 bits).

Note: Bits 15-12 are not used. Bits 11-5 indicate the starting base address of the Interrupt Log List, and bits 4-0 indicate the ring

location of the Interrupt Log List. See section 4.0 for a description of the Interrupt Architecture.

2.1.7 BIT Word Register (Read/Write) - Register 6

This register contains information on the SµΜΜIT RTE’s current health. The SµΜΜIT RTE transmits the contents of this register

upon reception of a Transmit Bit Word Mode Code. The lower 8 bits of this register are user-defined.

Bit Mnemonic Description

Number

15-12 N/A Always set these bits to logical zero.

11-5 INTA(11:5) Interrupt Log List Pointer Base Address Bits. (Bit 11 MSB - Bit 5 LSB).

4-0 INTA(4:0) Always set these bits to logical zero.

Bit Mnemonic Description

Number

15 MAB Memory Access Blocked. This bit is set if all internal DMA activity is not completed

between the time internal DMA activity begins and when the timer decrements to zero.

In the event of a DMA failure, current message processing terminates; remote terminal

waits for next 1553 message.

14 WRAPF Wrap Fail. The SµΜΜIT RTE automatically compares the transmitted word

(encoder word) to the reflected decoder word via the continuous loop-back feature. If the

encoder word and reflected word do not match, the WRAPF bit asserts and a YF_INT

interrupt is generated (if not masked). The loop-back path is via the MIL-STD-1553 bus

transceiver. A wrap failure does not result in the terminal flag bit being set to a logical

one. Message processing continues.

13 TAPF Terminal Address Parity Fail. This bit reflects the outcome of the remote terminal address

parity check. A logic one indicates a parity failure. When a parity error occurs theSµΜΜIT

RTE does not begin operation (STEX bit forced to a logic zero), channel A and B do not

enable, and a YF_INT interrupt is generated (if not masked).

12 BITF BIT Fail. Assertion of this bit indicates a BIT failure. Bits 11 through 8 should be

interrogated to determine the specific failure. Status word bit 19 is automatically set to a

logic one when a BIT failure occurs. If a BIT fails, the BITF bit is asserted, and a YF_INT

interrupt is generated (if not masked). Operation continues.

11 CHAF Channel A Fail. Assertion of this bit indicates a BIT test failure in Channel A.

10 CHBF Channel B Fail. Assertion of this bit indicates a BIT test failure in Channel B.

9N/A Always set this bit to logical zero.

8MTF Memory Test Fail.

7-0 UDB(7:0) User-Defined Bits.

SµMMIT RTE

The Time-Tag Register reflects the state of a 16-bit free running counter. The resolution of this counter is user-defined via input

TCLK (0 to 4MHz) or fixed at 64µs/bit. The Time-Tag counter is automatically reset when the SµΜΜIT RTE receives a valid

synchronize without data mode code. The SµΜΜIT RTE automatically loads the Time-Tag counter with the data associated with

reception of a valid synchronize with data mode code. The Time-Tag counter begins operation on the rising edge of MRST or within

64µs; after the receipt of a valid mode code, reset remote terminal, or sync with/without data. When the SµΜΜIT RTE is halted

(STEX = 0), the Time-Tag continues to run.Time-Tag value is captured upon command word-validation.

2.1.9 Remote Terminal Descriptor Pointer Register (Read/Write) - Register 8

The SµΜΜIT RTE accesses a block of external memory to gain information on how to process a valid command. Each subaddress

and mode code has a block of memory reserved for this task. Located contiguously in memory, these reserved memory locations

are called a descriptor space. The Remote Terminal Descriptor Pointer Register contains an address that points to the top of this

memory space. The SµΜΜIT RTE uses the T/R bit, subaddress/mode code field, and mode code to select one block within the

descriptor table for message processing. The Remote Terminal Descriptor Pointer Register is static during message processing.

Bit Mnemonic Description

Number

15-0 TT(15:0) Time-Tag Counter Bits. (Bit 15 MSB - Bit 0 LSB)

Bit Mnemonic Description

Number

15-12 N/A Always set these bits to logical zero.

11-0 RTDA(11:0) Remote Terminal Descriptor Address Bits. (Bit 11 MSB - Bit 0 LSB)

10 SµMMIT RTE

2.1.10 1553 Status Word Bits Register (Read/Write) - Register 9

The host or subsystem accesses this register to control the outgoing MIL-STD-1553 status word. The host or subsystem controls

the Instrumentation, Busy, Terminal Flag, Service Request, and Subsystem Flag by writing to bits 9 through 0 of this register. The

SµΜΜIT RTE’s status word response reflects assertion of these bit(s) until negated by the host or subsystem unless the Immediate

Clear Function is enabled. The Immediate Clear Function automatically clears these bits after being transmitted in a status word.

The Immediate Clear Function does not affect the operation of the Transmit Status word and Transmit Last Command word Mode

Codes. Transaction of a legal valid command with the INS bit set to a logic one and the Immediate Clear Function enabled, results

in the transmission of a status word with Bit 10 asserted. If the ensuing command is a Transmit Status word or Last Command mode

code, Bit 10 of the outgoing status word remains a logic one. For MIL-STD-1553B applications, the register is as follows:

Bit Number Mnemonic Description

15 IMCLR Immediate Clear Function. Assertion of this bit enables the Immediate Clear Function

(IMF) of the SµΜΜIT RTE. Enabling the IMF results in the clearing of the INS, BUSY,

TF, SRQ, and/or SUBF bit immediately after a message is completed. This function is

enabled by asserting this bit when asserting bit(s) INS, BUSY, TF, SRQ, and/or SSYSF.

This bit should be used consistently since once set, it will remain set, and once cleared,

it will remain cleared.

14-10 N/A Always set these bits to logical zero.

9INS Instrumentation Bit. This bit asserts the Instrumentation bit of the MIL-STD-1553B status

word. (Bit time 10 of the Status Word).

8SRQ Service Request Bit. This bit asserts the Service Request bit of the MIL-STD-1553B status

word. (Bit time 11of the Status Word).

7-4 N/A Always set these bits to logical zero.

3BUSY Busy Bit. Assertion of this bit is reflected in the outgoing MIL-STD-1553B status word.

Assertion of this bit prevents memory accesses. (Bit time 16 of the Status Word).

2SSYSF Subsystem Flag Bit. This bit asserts the Subsystem Flag bit of the MIL-STD-1553B status

word and may also be set with the SSYSF input pin. (Bit time 17 of the Status Word).

1N/A Always set this bit to logical zero.

0TF Terminal Flag. Assertion of this bit is reflected in the outgoing MIL-STD-1553B status

word. The SµΜΜIT RTE automatically asserts this bit if a BIT failure occurs. Inhibit

Terminal Flag mode code prevents the assertion by the host or subsystem. Override Inhibit

Terminal Flag Mode Code re-establishes the Terminal Flag option (Bit time 19 of the

Status Word).

SµMMIT RTE

For MIL-STD-1553A applications, the register is as follows:

Bit Number Mnemonic Description

15 IMCLR Immediate Clear Function. Assertion of this bit enables the Immediate Clear Function

(IMF) of the SµΜΜIT RTE. Enabling the IMF results in the clearing of the bit times 10-

19 immediately after a status word is transmitted. This function is enabled by asserting

this bit when asserting bit times 10-19. This bit should be used consistently since once

set, it will remain set, and once cleared, it will remain cleared.

14-10 N/A Always set these bits to logical zero.

9SB10 Status bit time 10.

8SB11 Status bit time 11.

7SB12 Status bit time 12.

6SB13 Status bit time 13.

5SB14 Status bit time 14.

4SB15 Status bit time 15.

3SB16 Status bit time 16.

2SB17 Status bit time 17.

1SB18 Status bit time 18.

0SB19 Status bit time 19.

12 SµMMIT RTE

2.1.11 Illegalization Registers

The 16 registers are divided into 8 blocks, 2 registers per block (see table 1).

Table 1. Illegalization Register Blocks

The blocks correspond to the following types of commands. Register address 0010 (hex) and 0011 (hex) illegalize receive commands

to 32 subaddresses. The most significant bit of register 0010 (hex) controls the illegalization of subaddress 01111. The least

significant bit controls subaddress 00000. Register 0011 (hex) controls illegalization of subaddresses 10000 through 11111. The

least significant bit relates to subaddress 10000; the most significant bit relates to subaddress 11111. Transmit commands and

broadcast commands (both receive and transmit) use the same encoding scheme as receive subaddress illegalization.

Registers 18 (hex) through 1F (hex) control the illegalization of mode codes. Register 18 governs the illegalization of receive mode

codes (T/R bit = 0) 00000 through 01111 and register 19 mode codes 10000 through 11111. Register blocks Transmit Mode Code

(T/R bit = 1), Broadcast Receive Mode Codes, and Broadcast Transmit Mode Codes use the same decode scheme as receive mode

codes.

Table 2 shows the illegalization register map. For each block, the numbers shown in the column under each bit number identifies

the specific subaddress or mode code (in hex) that the register bit illegalizes (Logical 0 = legal, Logical 1 = illegal).

Block Name Address (hex)

Receive 0010 and 0011

Transmit 0012 and 0013

Broadcast Receive 0014 and 0015

Broadcast Transmit (Automatically

Illegalized) 0016 and 0017

Mode Code Receive 0018 and 0019

Mode Code Transmit 001A and 001B

Broadcast Mode Code Receive 001C and 001D

Broadcast Mode Code Transmit 001E and 001F

SµMMIT RTE

Table 2. Illegalization Register Map

Notes:

1. Brd = Broadcast.

2. Mode = Mode code.

3. XX= Automatically illegalized by SµMMIT RTE.

4. YY= Automatically illegalized by SµMMIT RTE in 1553B only.

5. ZZ= Automatically illegalized by SµMMIT RTE in 1553B and 1553A if XMTSW is enabled.

6. WW = Automatically illegalized in 1553A.

7. UU = Automatically illegalized in 1553A if XMTSW enabled.

Name Register

Number

Bit Number 15 14 13 12 11 109876543210

Receive 16 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

17 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Transmit 18 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

19 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Brd Receive 20 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

21 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Brd Transmit 22 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX

23 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX

Mode Receive 24 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

25 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Mode Transmit 26 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00

27 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Mode Brd Receive 28 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 UU 01 WW

29 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10

Mode Brd Transmit 30 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 ZZ 01 XX

31 YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY YY

14 SµMMIT RTE

2.2 Descriptor Block

To process messages, the SµΜΜIT RTE uses data supplied in

the internal registers with data stored in internal memory. The

SµΜΜIT RTE accesses a four word descriptor block stored in

internal memory. The descriptor block is accessed at the

beginning and end of command processing. Multiple descriptor

blocks are sequentially entered into memory to form a descriptor

table. The following paragraphs discuss the descriptor block in

detail.

The host or subsystem controlling the SµΜΜIT RTE allocates

512 consecutive memory spaces for the subaddress and mode

code descriptor table. The top of the descriptor table can reside

at any address location except locations 0-31. Defined and

entered into memory by the host, the SµΜΜIT RTE is linked

to the descriptor table via the Descriptor Address Register

contents (see figures 2a and 2b). Each descriptor block contains

a Control Word, Data Pointer A, Data Pointer B, and Broadcast

Data Pointer. Each subaddress and mode code is assigned a

descriptor for receive and transmit commands (T/R bit equal

zero or one).

Control word information allows the SµΜΜIT RTE to generate

interrupts, buffer messages, and control message processing.

For a receive command, the Data Pointer is read to determine

the top of the data buffer. The SµΜΜIT RTE stores data

sequentially from the top of data buffer plus two locations (e.g.,

0100, 0101, 0102, 0103, etc.). When processing a transmit

command, the Data Pointer is read to determine where data

words are retrieved. The SµΜΜIT RTE retrieves data words

sequentially from the address the Data Pointer designates plus

a two address location offset.

The Broadcast Data Pointer allows for separate storage of non-

broadcast data from broadcast data per MIL-STD-1553B Notice

II. The host or subsystem enables or disables this feature via the

Control Word’s least significant bit.

When disabled, the non-broadcast and broadcast data is stored

via Data List Pointer A or B. For transmit commands, the

Broadcast Data Pointer is not used. The SµMMIT RTE does not

transmit any information on the receipt of a broadcast transmit

command.

The SµΜΜIT RTE reads the descriptor block during command

processing (i.e., after assertion of TERACT). The SµΜΜIT

RTE reads the control word and three Data Pointers. The

SµΜΜIT RTE then begins the acquisition of data words for

either transmission or storage.

After transmission or reception, the SµΜΜIT RTE begins post-

processing. The SµΜΜIT RTE performs a DMA burst during

post-processing. An optional interrupt log entry is performed

after a descriptor update. During the descriptor update, the

SµΜΜIT RTE modifies the Control Word index field and bits

4, 2, and 1, if required. The SµΜΜIT RTE updates Data Pointer

A if no message errors occurred during the message transaction.

Reception of a broadcast command, with no message errors,

results in the update of the Broadcast Data Pointer. Neither Data

Pointer A, B or Broadcast is updated if the SµΜΜIT RTE has

the ping-pong mode of operation enabled.

See section 3, Circular Buffer and Ping-Pong Operation for

additional information.

Subaddress/Mode Code

Address Equation

Subaddress Descriptor Address Register Contents + [(SA# x 4) + 0]

Subaddress Descriptor Address Register Contents + [(SA# x 4) + 128]

Descriptor Address Register Contents + [(MC# x 4) + 256]

Descriptor Address Register Contents + [(MC# x 4) + 384]

Figure 2a. Descriptor Table

Descriptors

T/R

Mode Codes

SµMMIT RTE

RECEIVE

•

RECEIVE

TRANSMIT

SUBADDRESS #0

SUBADDRESS #1

SUBADDRESS #30

SUBADDRESS #31

SUBADDRESS #0

SUBADDRESS #1

TRANSMIT

•

SUBADDRESS #30

SUBADDRESS #31

RELATIVE ADDRESS 0000 (hex)

RELATIVE ADDRESS 00FC (hex)

RECEIVE

•

RECEIVE

TRANSMIT

MODE CODE #0

MODE CODE #1

MODE CODE #30

MODE CODE #31

MODE CODE #0

MODE CODE #1

TRANSMIT

•

MODE CODE #30

MODE CODE #31

RELATIVE ADDRESS 0100 (hex)

RELATIVE ADDRESS 01FC (hex)

Figure 2b. Descriptor Table

16 SµMMIT RTE

2.2.1 Receive Control Word

The following bits describe the receive subaddress Descriptor Control Word. Information contained in this word assists the SµΜΜIT

RTE in message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SµΜΜIT RTE

during command post-processing.

Bit Mnemonic Description

Number

15-8 INDX Index Field. These bits define multiple message buffer length. The host or subsystem uses

this field to instruct the SµΜΜIT RTE to buffer “N” messages. “N” can range from 0 (00

hex) to 104 (68 hex). If buffer ping-ponging is enabled, the INDX field is “don’t care”

(i.e., does not contain applicable information). During ping-pong mode operation,

initialize the index field to 00 (hex). TheSµΜΜIT RTE does not perform multiple message

buffering in the ping-pong mode of operation. The index decrements each time a complete

message is transacted (no message errors). The index does not decrement if the subaddress

is illegalized. The SµΜΜIT RTE can generate an interrupt when the index field transitions

from one to zero (see bit 7).

7INTX Interrupt Index Equals Zero. Assertion of this bit enables the generation of an interrupt

when the index field transitions from one to zero. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

6IWA Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when

the subaddress receives a valid command. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

5IBRD Interrupt Broadcast Received. Assertion of this bit enables the generation of an interrupt

when the subaddress receives a valid broadcast command. The interrupt is entered into

the Pending Interrupt Register if not masked in the Mask Register. Output pin MSG_INT

asserts after message processing.

4BAC Block Accessed. The subsystem or host initializes this bit to zero; the SµΜΜIT RTE

overwrites the zero with a logic one upon completion of message processing. After

interrogating this bit, the host resets this bit to zero to observe further accesses.

3N/A Always set this bit to logical zero.

2 A/BBuffer A/B. Indicates the last buffer accessed when buffer ping-pong is enabled. During

initialization, the host designates the first buffer used by asserting or negating this bit. A

logic one indicates buffer A; a logic zero indicates buffer B. This bit is a “don’t care” if

buffer ping-ponging is not enabled.

1BRD Broadcast Received. Assertion of this bit indicates the reception of a valid broadcast

command.

0NII Notice II. Assertion of this bit enables the use of the Broadcast Data Pointer as a buffer

for broadcast command information. When negated, broadcast information is stored in

the same buffer as non-broadcast information.

SµMMIT RTE

2.2.2 Transmit Control Word

The following bits describe the transmit subaddress Descriptor Control Word. Information contained in this word assists the SµΜΜIT

RTE in message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SµΜΜIT RTE

during command post-processing.

Bit Mnemonic Description

Number

15-7 N/A Always set these bits to logical zero.

6IWA Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when

the subaddress receives a valid command. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

5N/A Always set this bit to logical zero.

4BAC Block Accessed. The subsystem or host initializes this bit to zero, the SµΜΜIT RTE

overwrites the zero with a logic one upon completion of message processing. After

interrogation, the host should reset this bit to zero to observe further accesses.

3N/A Always set this bit to logical zero.

2 A/BBuffer A/B. Indicates the data pointer to access when buffer ping-pong is enabled. During

initialization, the host designates the first buffer used by asserting or negating this bit. A

logic one indicates buffer A; a logic zero indicates buffer B. This bit is a “don’t care” if

buffer ping-ponging is not enabled.

1BRD Broadcast Received. Assertion of this bit indicates the reception of a broadcast command.

0N/A Always set this bit to logical zero.

18 SµMMIT RTE

2.2.3 Mode Code Receive Control Word

The following bits describe the receive mode code Descriptor Control Word. Information contained in this word assists the SµΜΜIT

RTE in message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SµΜΜIT RTE

during command post-processing.

Note: In MIL-STD-1553A, all mode codes are without data, and the T/R bit is ignored. See section 2.9 for the MIL-STD-1553A

operation.

Bit Mnemonic Description

Number

15-8 INDX Index Field. These bits define message buffer length. The host or subsystem uses this

field to instruct the SµΜΜIT RTE to buffer “N” messages. “N” can range from 0 (00

hex) to 104 (68 hex). If buffer ping-ponging is enabled, the INDX field is “don’t care”

(i.e., does not contain applicable information). The SµΜΜIT RTE does not perform

message buffering in the ping-pong mode of operation. The index decrements each time

a complete message is transacted (no message errors). The index does not decrement if

the mode code is illegalized. The SµΜΜIT RTE can generate an interrupt when the index

field transitions from one to zero (see bit 7).

7INTX Interrupt Index Equals Zero. Assertion of this bit enables the generation of an interrupt

when the index field transitions from one to zero. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

6IWA Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when

mode code command is received. The interrupt is entered into the Pending Interrupt

processing.

5IBRD Interrupt Broadcast Received. Assertion of this bit enables the generation of an interrupt

when a valid broadcast mode code command is received. The interrupt is entered into the

Pending Interrupt Register if not masked in the Mask Register. Output pin MSG_INT

asserts after message processing.

4BAC Block Accessed. The subsystem or host initializes this bit to zero; the SµΜΜIT RTE

overwrites the zero with a logic one upon completion of message processing. After

interrogating this bit, the host resets this bit to zero to observe further accesses.

3N/A Always set this bit to logical zero.

2 A/BBuffer A/B. Indicates the last buffer accessed when buffer ping-pong is enabled. During

initialization, the host designates the first buffer used by asserting or negating this bit. A

logic one indicates buffer A; logic zero indicates buffer B. This bit is a “don’t care” if

buffer ping-ponging is not enabled.

1BRD Broadcast Received. Assertion of this bit indicates the reception of a valid broadcast

command.

0NII Notice II. Asserting this bit enables the use of the Broadcast Data Pointer as a buffer for

broadcast command information. When negated, broadcast information is stored in the

same buffer as non-broadcast information.

SµMMIT RTE

2.2.4 Mode Code Transmit Control Word

The following bits describe the transmit mode code Descriptor Control Word. Information contained in this word assists the SµΜΜIT

RTE in message processing. The Descriptor Control Word is initialized by the host or subsystem and updated by the SµΜΜIT RTE

during command post-processing.

Note: In MIL-STD-1553A, all mode codes are without data, and the T/R bit is ignored. See section 2.9 for the MIL-STD-1553A

operation.

Bit Mnemonic Description

Number

15-7 N/A Always set these bits to logical zero.

6IWA Interrupt When Accessed. Assertion of this bit enables the generation of an interrupt when

mode code command is received. The interrupt is entered into the Pending Interrupt

processing.

5IBRD Interrupt Broadcast Received. Assertion of this bit enables the generation of an interrupt

when a valid broadcast mode code is received. The interrupt is entered into the Pending

Interrupt Register if not masked in the Mask Register. Output pin MSG_INT asserts after

message processing.

4BAC Block Accessed. The subsystem or host initializes this bit to zero; the SµΜΜIT RTE

overwrites the zero with a logic one upon completion of message processing. After

interrogating this bit, the host resets this bit to zero to observe further accesses.

3N/A Always set this bit to logical zero.

2 A/BBuffer A/B. This bit indicates the last buffer accessed when buffer ping-pong is enabled.

During initialization, the host designates the first buffer used by asserting or negating this

bit. A logic one indicates buffer A; a logic zero indicates buffer B. This bit is a “don’t

care” if buffer ping-ponging is not enabled.

1BRD Broadcast Received. Assertion of this bit indicates the reception of a broadcast command.

0N/A Always set this bit to logical zero.

20 SµMMIT RTE

2.2.5 Data Pointer A and B

Data Pointer A and B contain address information for the retrieval and storage of message data words. In the index mode of operation,

the SµΜΜIT RTE reads Data Pointer A to determine the location of data for retrieval or storage. The SµΜΜIT RTE uses the Data

Pointer to initialize an internal counter; the counter increments after each data word. For a receive command, the SµΜΜIT RTE

stores the incoming data word sequentially into memory. As part of command post-processing, the SµΜΜIT RTE writes a new

data pointer into the descriptor block. The SµΜΜIT RTE continues to update the data pointer until the Control Word index field

decrements to zero. An example is shown in figure 3.

Note: The index feature is not applicable for transmit commands (i.e., T/R bit = 1).

For ping-pong buffer operation, the host uses either Data Pointer A or Data Pointer B. The SµΜΜIT RTE determines which pointer

to access via the state of Control Word bit 2. The SµΜΜIT RTE retrieves or stores data words from the address contained in the

data pointer, automatically incrementing the data pointer as data words are received. The data pointer is never updated as part of

command post-processing in the ping-pong mode of operation. See figures 3 and 4.

2.2.6 Broadcast Data Pointer

The following bits describe the receive subaddress/mode code descriptor Broadcast Data Pointer. This word contains the address

for the Message Information word, Time-Tag word, and data words associated with a broadcast command. The SµΜΜIT RTE

automatically increments this data pointer during command post-processing, if ping-pong operation disabled.

2.3 Data Structures

The following sections discuss the data structures that result

from command processing. For each complete message

processed, the SµΜΜIT RTE generates a Message Information

word and Time-Tag word. These words aid the host or

subsystem in further message processing. The Message

Information word contains word count, message type, and

message error information. The Time-Tag word is a 16-bit word

containing the command validity time. The Time-Tag word data

comes from the SµΜΜIT RTE’s internal Time-Tag counter.

See section 3, Circular Buffer and Ping-Pong Operation for

additional data structure information

Bit Mnemonic Description

Number

15-0 DP(15:0) Data Pointer Bits. The second and third words of the descriptor block contain the data

buffer location. The SµΜΜIT RTE accesses either Data Pointer A or Data Pointer B

depending on the state of Control Word Bit 2 during ping-pong operation. For index

operation, the SµΜΜIT RTE accesses only Data Pointer A. The SµΜΜIT RTE updates

Data Pointer A after message processing is complete and the index field is not equal to

zero and ping-pong operation disabled. Bit 15 is the most significant bit; bit 0 is the least

significant bit.

Bit Mnemonic Description

Number

15-0 BP(15:0) Broadcast Data Pointer. The fourth word of the descriptor block contains the broadcast

data buffer location. This pointer can reside anywhere inside of a 64K data space. The

SµΜΜIT RTE accesses this pointer when Control Word bit 0 is a logic one and broadcast

is enabled. Bit 15 is the most significant bit; bit 0 is the least significant bit.

Note: If ping-pong is enabled, this pointer does not update.

Note: When the broadcast command is followed by a Transmit Last Command or Transmit

Status Word mode code, the SµΜΜIT RTE transmits a status word with bit time 15 of

the status word set to a logic one. The broadcast bit is cleared by reception of the next

valid non-broadcast command.

SµMMIT RTE

Figure 3. Non-Broadcast Receive Message Indexing

0100 (hex)

0101 (hex)

0102 (hex)

0103 (hex)

0104 (hex)

0105 (hex)

0106 (hex)

0107 (hex)

0108 (hex)

0109 (hex)

010A (hex)

010B (hex)

010C (hex)

010D (hex)

Index equals two

Index decrements to one

Index equals one

Index decrements to zero

(interrupt generated if enabled)

Index equals zero

Index remains zero

(Data Pointer A = 109)

Message Info Word

Time-Tag

Data Word #1

Data Word #2

Data Word #3

Message Info Word

Time-Tag

Data Word #1

Data Word #2

Message Info Word

Time-Tag

Data Word #1

Data Word #2

Data Word #3

Command #1

Receive three words

Command #2

Receive two words

Command #3

Receive three words

CONTROL WORD

DATA POINTER A

DATA POINTER B

BROADCAST

DATA POINTER

Receive Subaddress #1

Descriptor Block Index field contents: 02XX (hex)

Data Pointer A: 0100 (hex)

Data Pointer B: XXXX (hex)

Broadcast Data Pointer: XXXX (hex)

Note:

x = “don’t care”

22 SµMMIT RTE

Figure 4. SµΜΜIT RTE Descriptor Block

(Receive)

DATA POINTER A

DATA POINTER B

BROADCAST

DATA POINTER

DATA

BUFFER

DATA

BUFFER

BROADCAST

BUFFER

MESSAGE

# N

MESSAGE INFORMATION

WORD

TIME-TAG

N - DATA WORDS

CONTROL WORD

DATA POINTER A

DATA POINTER B

XXXX (hex)

DATA

BUFFER

DATA

BUFFER

MESSAGE

MESSAGE INFORMATION

WORD

TIME-TAG

N - DATA WORDS

Figure 5. SµΜΜIT RTE Descriptor Block

(Transmit)

CONTROL WORD

SµMMIT RTE

2.3.1 Subaddress Receive Data

For receive commands, the SµΜΜIT RTE stores data words plus two additional words. The SµΜΜIT RTE adds a Receive

Information word and Time-Tag word to each receive command data packet. The SµΜΜIT RTE places the Receive Information

word and Time-Tag word ahead of the data words associated with a receive command (see figures 3, 4 and 5). When message errors

occur, the SµΜΜIT RTE enters the Receive Information word, and Time-Tag word. Once a message error condition is observed,

all data words are considered invalid.

Data storage occurs at the memory location pointed to by the data pointer plus two locations.

2.3.1.1 Receive Information (Info) Word

The following bits describe the Receive Information Word contents.

Bit Mnemonic Description

Number

15-11 WC(4:0) Word Count Bits. These five bits contain word count information extracted from the

receive command word bit times 15 to 19.

10 N/A Not applicable.

9 CHA/BChannel A/B. Assertion of this bit indicates that the message was received on channel A.

Conversely, if this bit is set to logic zero, the message was received on channel B.

8RTRT Remote Terminal to Remote Terminal transfer. The command processed was a RT-to-RT

transfer.

7ME Message Error. Assertion of this bit indicates a message error condition was observed

during processing. See bits 0 to 4 for details.

6-5 N/A Not applicable.

4 ILL Illegal Command Received. Assertion of this bit indicates the command received was an

illegal command.

3 TO Time-Out Error. Assertion of this bit indicates the SµΜΜIT RTE did not receive the

proper number of data words, i.e., the number of data words received was less than the

word count specified in the command word.

2 OVR Overrun Error. Assertion of this bit indicates the SµΜΜIT RTE received a word when

none was expected or the number of data words received was greater than expected.

1PRTY Parity Error. Assertion of this bit indicates the SµΜΜIT RTE observed a parity error in

the incoming data words.

0MAN Manchester Error. Assertion of this bit indicates the SµΜΜIT RTE observed a Manchester

error in the incoming data words.

24 SµMMIT RTE

2.3.2 Subaddress Transmit Data

The host or subsystem is responsible for organization of the data packet (i.e., N data words) into memory and establishing the

applicable data pointer. The host or subsystem allocates two memory locations at the top of the data packet for the storage of the

Transmit Information word and Time-Tag word. An example transmit data structure for three words is shown below.

Data Pointer A -----> 0100 (hex) XXXX ;reserved for Transmit Info word

equals 0100 (hex) 0101 (hex) XXXX ;reserved for Time-Tag word

0102 (hex) FFFF ;data word

0103 (hex) FFFF ;data word

0104 (hex) FFFF ;data word

Note: Data Pointer A points to the top of the data structure not to the top of the data words.

2.3.2.1 Transmit Information (Info) Word

The following bits describe the Transmit Information word contents.

Bit Mnemonic Description

Number

15-11 WC(4:0) Word Count Bits. These five bits contain word count information extracted from the

transmit command word bit times 15 to 19.

10 N/A Not applicable.

9CHA/BChannel A/B. Assertion of this bit indicates that the message was received on the A bus.

Conversely, if this bit is set to logic zero, the message was received on the B bus.

8N/A Not applicable.

7ME Message Error. Assertion of this bit indicates a message error condition was observed

during processing. See bits 0 to 4 for more detail.

6-5 N/A Not applicable.

4ILL Illegal Command Received. Assertion of this bit indicates the command received was an

illegal command.

3N/A Not applicable.

2OVR Overrun Error. Assertion of this bit indicates the SµΜΜIT RTE received a data word with

a Transmit Command.

1-0 N/A Not applicable.

SµMMIT RTE

2.3.3 Mode Code Data

The transmit and receive data structures for mode codes are similar to those for subaddress. The receive data structure contains an

Information word, Time-Tag word, and message data word. All receive mode codes with data have one associated data word. Data

storage occurs at the memory location pointed to by the data pointer plus two locations. Reception of the synchronize with data

mode code automatically loads the Time-Tag counter and stores the data word at the address defined by the data pointer plus two

locations.

The transmit mode code data structure contains an Information word, Time-Tag word, and associated data word. The subsystem or

host is responsible for linking the SµΜΜIT RTE Data Pointer to the data (e.g., Transmit Vector word). For mode codes with

internally generated data words (e.g., Transmit BIT word, Transmit Last Command), the transmitted data word is added to the data

structure.

For MIL-STD-1553A mode of operation, all mode codes are defined without data words. For mode codes without data, the data

structure contains the Message Information word and Time-Tag word only.

Note: In MIL-STD-1553A, all mode codes are without data and the T/R bit is ignored. See section 2.9 for the MIL-STD-1553A

operation.

2.3.3.1 Mode Code Receive Information (Info) Word

The following bits describe the Mode Code Receive Information word contents.

Bit Mnemonic Description

Number

15-11 MC (4:0) Mode Code. These five bits contain the mode code information extracted from the receive

command word bits times15 to 19.

10 N/A Not applicable.

9CHA/BChannel A/B. Assertion of this bit indicates that the message was received on the A bus.

Conversely, if this bit is set to logic zero, the message was received on the B bus.

8RTRT Remote Terminal to Remote Terminal transfer. Assertion of this bit indicates the command

processed was a RT-to-RT transfer.

7ME Message Error. Assertion of this bit indicates a message error condition was observed

during processing. See bits 0 to 4 for details.

6-5 N/A Not applicable.

4ILL Illegal Command Received. Assertion of this bit indicates the command received was an

illegal command.

3TO Time-out Error. Assertion of this bit indicates the SµΜΜIT RTE did not receive the proper

number of data words, i.e., the number of data words received was less than the word

count specified in the command word.

2OVR Overrun Error. Assertion of this bit indicates the SµΜΜIT RTE received a word when

none was expected, or the number of data words received was greater than expected.

1PRTY Parity Error. Assertion of this bit indicates the SµΜΜIT RTE observed a parity error in

the incoming data words.

0MAN Manchester Error. Assertion of this bit indicates the SµΜΜIT RTE observed a Manchester

error in the incoming data words.

26 SµMMIT RTE

2.3.3.2 Mode Code Transmit Information (Info) Word

The following bits describe the Mode Code Transmit Information word contents.

Bit Mnemonic Description

Number

15-11 MC (4:0) Mode Code. These five bits contain the mode code information extracted from the

command word bit times 15 to 19.

10 N/A Not applicable.

9CHA/BChannel A/B. Assertion of this bit indicates that the message was received on the A bus.

Conversely, if this bit is set to logic zero, the message was received on the B bus.

8N/A Not applicable.

7ME Message Error. Assertion of this bit indicates a message error condition was observed

during processing. See bits 0 to 4 for details.

6-5 N/A Not applicable.

4ILL Illegal Command Received. Assertion of this bit indicates the command received was an

illegal command.

3N/A Not applicable.

2OVR Overrun Error. Assertion of this bit indicates the SµΜΜIT RTE received a data word with

a Transmit Command.

1-0 N/A Not applicable.

SµMMIT RTE

2.4 Mode Code and Subaddress

The SµΜΜIT RTE provides subaddress and mode code

decoding that meets MIL-STD-1553B requirements. In

addition, the device has automatic internal illegal command

decoding for reserved MIL-STD-1553B mode codes. Table 3

shows the SµΜΜIT RTE’s response to all possible mode code

combinations.

Table 3. Mode Code Descriptions

T/R Mode Code Function Operation

000000-01111 Undefined (w/o data) 1. Command word stored

2. Status word transmitted

010000 Undefined (with data) 1. Command word stored

2. Data word stored

3. Status word transmitted

010001 Synchronize (with data) 1. Command word stored

2. Data word stored

3. Time-Tag counter loaded with data word value

4. Status word transmitted

010010 Undefined 1. Command word stored

2. Data word stored

3. Status word transmitted

010011 Undefined 1. Command word stored

2. Data word stored

3. Status word transmitted

010100 Selected Transmitter

Shutdown 1. Command word stored

2. Data word stored

3. Status word transmitted

010101 Override Selected

Transmitter Shutdown 1. Command word stored

2. Data word stored

3. Status word transmitted

010110-11111 Reserved 1. Command word stored

2. Data word stored

3. Status word transmitted

100000 Dynamic Bus Control 1. Command word stored

2. Dynamic Bus Acceptance bit set in outgoing

status word if enabled in the Control Register

3. Status word transmitted

100001 Synchronize 1. Command word stored

2. Time-Tag counter reset to 0000 (hex)

3. Status word transmitted

100010 Transmit Status Word 1. Command word stored

2. Last status word transmitted

3. Status word cleared after master reset

Note: SµΜΜIT RTE updates status word if

illegalized.

100011 Initiate Self-Test 1. Command word stored

2. Status word transmitted

3. BIT initiated

4. TF bit set if BITF bit asserted

100100 Transmitter Shutdown 1. Command word stored

2. Status word transmitted

3. Alternate bus disabled

28 SµMMIT RTE

Table 3. Mode Code Descriptions (Cont.)

T/R Mode Code Function Operation

100101 Override Transmitter

Shutdown 1. Command word stored

2. Status word transmitted

3. Alternate bus enabled

Note: Reception of the override transmitter

shutdown mode code does not enable a channel not

previously enabled in the Control Register. Reset

remote terminal mode code clears the transmitter

shutdown function.

100110 Inhibit Terminal Flag Bit 1. Command word stored

2. Terminal flag bit set to zero and assertion

disabled

3. Status word transmitted

100111 Override Inhibit

Terminal Flag 1. Command word stored

2. Terminal Flag bit enabled for assertion

3. Status word transmitted

101000 Reset Remote Terminal 1. Command word stored

2. Status word transmitted

3. SµΜΜIT RTE reset, see section 2.8 for more

information on software reset

101001-01111 Reserved 1. Command word stored

2. Status word transmitted

110000 Transmit Vector Word 1. Command word stored

2. Service request bit set to a logic zero in out going

status

3. Status word transmitted

4. Data word transmitted

5. Clears the SRQ bit in the 1553 status word bits

110001 Reserved 1. Command word stored

2. Status word transmitted

3. Data word transmitted

110010 Transmit Last Command 1. Command word not stored

2. Last status word transmitted

3. Last command word transmitted

4. Data word stored (Transmit Last Command)

5. Transmitted data word is all zero after reset

Note: The SµΜΜIT RTE stores the Transmit Last

Command mode code if illegalized and updates

status word.

110011 Transmit BIT Word 1. Command word stored

2. Status word transmitted

3. BIT word transmitted from BIT Word Register

4. Data word stored (Transmit BIT Word)

110100-10101 Undefined (with data) 1. Command word stored

2. Status word transmitted

3. Data word transmitted

110110-11111 Reserved 1. Command word stored

2. Status word transmitted

3. Data word transmitted

SµMMIT RTE

2.5 Encoder and Decoder

The SµΜΜIT RTE interfaces directly to a transmitter/receiver

via theSµΜΜIT RTE Manchester II encoder/decoder. The

SµΜΜIT RTE receives the command word from the MIL-STD-

1553 bus and processes it either by the primary or secondary

decoder. Each decoder checks for the proper sync pulse and

Manchester waveform, edge skew, correct number of bits, and

parity. If the command is a receive command, the SµΜΜIT RTE

processes each incoming data word for correct format, word

count, and contiguous data. If a message error is detected, the

SµΜΜIT RTE stops processing the remainder of the message

(i.e., DMAs), suppresses status word transmission, and asserts

bit 9 (ME bit) of the status word. The SµΜΜIT RTE will track

the message until proper word count is finished.

The SµΜΜIT RTE automatically compares the transmitted

word (encoder word) to the reflected decoder word by way of

the continuous loop-back feature. If the encoder word and

reflected word do not match, the WRAPF bit is asserted in the

BIT Word Register and the YF_INT will be generated, if

enabled. In addition to the loop-back compare test, a timer

precludes a transmission greater than 800µs by the assertion of

Fail-Safe Timer. This timer is reset upon receipt of another

command. Remote Terminal Response Time:

MIL-STD-1553A = 7µs

MIL-STD-1553B = 10µs

Data Contiguity Time-Out = 1.0µs

2.6 RT-RT Transfer Compare

The RT-to-RT Terminal Address compare logic ensures that the

incoming status word’s Terminal Address matches the Terminal

Address of the transmitting RT specified in the command word.

An incorrect match results in setting the message-error bit and

suppressing transmission of the status word. (RT-to-RT transfer

time-out = 55 to 59µs). The receiving SµΜΜIT RTE does not

check ME or SSYSF of the transmitting remote terminal.

2.7 Terminal Address

The SµΜΜIT RTE Terminal Address is programmed via six

input pins: RTA(4:0) and RTPTY. Negating MRST latches the

SµΜΜIT RTE’s Terminal Address from pins RTA(4:0) and

parity bit RTPTY. The address and parity cannot change until

the next assertion and negation of the MRST input (for LOCK

= 0). The Terminal Address parity is odd; input pin RTPTY is

set to a logic state to satisfy this requirement. Assertion of

Operational Status Register bit 2 (TAPF) indicates incorrect

Terminal Address parity. The Operational Status Register bit 2

is valid after the rising edge of MRST.

For example:

RTA(4:0) = 05 (hex) = 00101 (binary)

RTPTY = 1, Sum of 1s = 3 (odd), Operational Status Register

Bit 2 = 0

RTA(4:0) = 04 (hex) = 00100 (binary)

RTPTY = 0, Sum of 1s = 1 (odd), Operational Status Register

Bit 2 = 0

RTA(4:0) = 04 (hex) = 00100 (binary)

RTPTY = 1, Sum of 1s = 2 (even), Operational Status Register

Bit 2 = 1

Note:

• The SµΜΜIT RTE checks the Terminal Address and

parity after the SµΜΜIT RTE has been started. With

Broadcast disabled, RTA(4:0)=11111 operates as a

normal RT address.

• The BIT Word Register parity fail bit is valid after the

SµΜΜIT RTE has been started.

• The Terminal Address is also programmed via a write to

the Operational Status Register (LOCK = 1).The

SµΜΜIT RTE loads the Terminal Address on the

completion of the Control Register write which starts the

SµΜΜIT RTE.

• YF_INT occurs if enabled.

2.8 Reset

The SµΜΜIT provides for several different reset mechanisms.

The SµΜΜIT software reset (Control Register Bit 13) is equal

to a master reset and takes 5µs to complete. Assertion of this bit

results in the immediate reset of the SµΜΜIT RTE and

termination of command processing. The host or subsystem is

responsible for the re-initialization of the SµΜΜIT RTE for

operation. Configuration of the device for auto-initialization

frees the host or subsystem from this task.

A Reset Remote Terminal mode code (Mode Code 01000, T/R

=1) is equal to a master reset only if AUTOEN is enabled. If

AUTOEN is not enabled, the reset remote terminal mode code

clears the encoder/decoders, resets the time-tag, enables the

channels to the programmed host state, and re-enables the

Terminal Flag for assertion. This reset is performed after the

transmission of the 1553 Status word. All outputs have

asynchronous reset except MSG_INT. To reset this signal, apply

two clock cycles before the rising edge of MRST.

30 SµMMIT RTE

Caution: Per the MIL-STD-1553 specification (sections

4.3.3.5.1.7.9 and 30.4.3), a remote terminal must “complete the

reset function within 5µs following transmission of the status

word.” If the AUTOEN function is enabled in the SµΜΜIT,

reset may require additional time depending on the application.

2.9 MIL-STD-1553A Operation

To maximize flexibility, the SµΜΜIT has been designed to

operate in many different systems which use various protocols.

Specifically, two of the protocols that the SµΜΜIT may be

interfaced to are MIL-STD-1553A and MIL-STD-1553B. To

meet these protocols, the SµΜΜIT may be configured through

an external pin or through control register bits (depending on

the state of the LOCK pin). Table 4 defines the three ways to

program the SµΜΜIT.

Table 4. MIL-STD-1553A Operation

When configured to meet MIL-STD-1553A, the SµΜΜIT will

operate as follows:

•Responds with a status word within 7µs;

•Ignores the T/R bit for all mode codes;

•All mode codes are defined without data;

•All mode codes use mode code transmit control and

information words;

•Mode code 00000 is defined as Dynamic Bus Control

(DBC);

•Subaddress 00000 defines a mode code;

•ME and TF bits are defined in the 1553 status word; all

other status word bits are programmable (i.e., NO

BUSY mode, etc.);

•Broadcast of all mode codes, except Mode Code 00000

(DBC) and Mode Code 00010 (Transmit Status word if

enabled), is allowed;

•To illegalize a Mode Code, the user needs to

illegalize both the receive and transmit versions;

•Illegalization of row 1F (hex) is not automatic.

A/B STD

(pin or bit) XMTSW

(bit only) RESULT

(protocol selected)

0X1553B response, 1553B

Standard

1 0 1553A response, 1553A

Standard

1 1 1553A response, Auto execute

the TRANSMIT STATUS

WORD mode code

SµMMIT RTE

1.0 INTRODUCTION

1.1 Remote Terminal Features

The SµMMIT Remote Terminal (RTE) conforms to the

requirements of MIL-STD-1553B, Notice II. In addition to

meeting the requirements of the standard, the SµMMIT RTE

has an extensive list of flexible features to meet any MIL-STD-

1553 interface requirement.

1.1.1 Indexing

The SµMMIT RTE can buffer up to 256 receive messages on a

subaddress-by-subaddress basis. Upon reception of a specified

number of messages, the SµMMIT RTE can generate an

interrupt by signaling either the host or subsystem that data is

ready for processing. The indexing feature is commonly used

to implement bulk data transfer algorithms.

1.1.2 Buffer Ping-Pong

To support the transfer of periodic data, double buffering

schemes are often incorporated into remote terminal designs.

Periodic data transfer incorporates the use of two data buffers

per subaddress. The remote terminal processes messages

(receive or transmit) via the designated primary buffer. The host

or subsystem uses the secondary buffer to collect new data for

transmission or processing data received during the defined time

interval. Upon completion of the defined interval, the remote

terminal will switch the primary and secondary data buffers (i.e.,

ping-pong). The SµMMIT RTE supports ping-pong buffering

via a user-selected ping-pong architecture consisting of dual

subaddress data pointers.

1.1.3 Circular Buffers

SµMMIT RTE circular buffer modes simplify the software

service of remote terminals implementing bulk or periodic data

transfers. The SµMMIT RTE architecture allows the user to

select one of two circular buffer modes. The user selects the

preferred mode, at start-up, by writing to bits 7 and 8 of the

Control Register bits.

1.1.4 Internal Illegalization

An internal 256-bit (16 x 16) RAM allows for the illegalization

of all mode codes and subaddresses. The illegalization RAM is

accessed at the beginning of message processing to determine

if the valid command is prohibited. To eliminate host or

subsystem overhead, the SµΜΜIT RTE can initialize the 256-

bit illegalization RAM during the auto-initialization sequence.

1.1.5 Broadcast

Designed to meet the requirements of MIL-STD-1553B Notice

II, the SµMMIT RTE can store all data associated with a

broadcast command in separate memory from non-broadcast

commands. This feature is user-selected via the Descriptor

Control word and internal Control Register.

1.1.6 Interrupt History

A programmable interrupt structure allows the host or

subsystem the flexibility to enter 16 interrupts into a 32-word

buffer before service. This feature allows the logging of multiple

interrupts if immediate service is restricted. The interrupt

structure enters an Interrupt Identification Word (IIW) and an

Interrupt Address Word (IAW) indicating what subaddress or

mode-code descriptor generated the interrupt.

1.1.7 Message Information

The SµMMIT RTE generates a Message Information Word and

16-bit time-tag for all transacted messages. This information is

written into memory along with message data words. The

Message Information Word contains word count, message

errors, and message type information.

1.2 Protocol Definition

For maximum flexibility, the SµΜΜIT RTE has been designed

to operate in many different systems which use various

protocols. Specifically, two of the protocols that the SµMMIT

RTE may interface are MIL-STD-1553A and MIL-STD-1553B.

To meet these protocols, the SµΜΜIT RTE may be configured

through an external pin or through control register bits.

1.3 SµMMIT RTE Transceivers

Internal monolithic transceivers are complete transmitter and

receiver pairs for MIL-STD-1553A and 1553B applications.

The receiver section accepts biphase-modulated Manchester II

bipolar data from MIL-STD-1553 data bus and produces TTL-

level signal data at its internal RXOUT and RXOUT outputs.

The transmitter section accepts biphase TTL-level signal data

at its internal TXIN and TXIN inputs and produces MIL-STD-

1553 data signals. The transmitter’s output voltage is typically

10VP-P,LL for the SµΜΜIT RTE.

1.4 SµMMIT RTE Memory

The SµMMIT RTE contains 64Kbits of internal memory for

message processing. Internal logic generates a RDY signal for

the subsystem interface. The internal memory is memory

mapped.