LMH7322SQ/NOPB - NATIONAL SEMICONDUCTOR

LMH7322

LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs

Literature Number: SNOSAU8H

LMH7322

May 11, 2011

Dual 700 ps High Speed Comparator with RSPECL Outputs

General Description

The LMH7322 is a dual comparator with 700 ps propagation

delay, low dispersion of 75 ps and an input voltage range that

extends from VCC-1.5V to VEE. The devices can be operated

from a wide supply voltage range of 2.7V to 12V. The ad-

justable hysteresis adds flexibility and prevents oscillations.

Both the outputs and latch inputs of the LMH7322 are

RSPECL compatible. When used in combination with a

VCCO supply voltage of 2.5V the outputs have LVDS compat-

ible levels.

The LMH7322 is available in a 24-pin LLP package.

Features

(VCCI = +5V, VCCO = +5V)

■Propagation delay 700 ps

■Overdrive dispersion 20 mV-1V 75 ps

■Fast rise and fall times 160 ps

■Wide supply range 2.7V to 12V

■Input common mode range extends 200 mV below

negative rail

■Adjustable hysteresis

■(RS)PECL outputs (see application note)

■(RS)PECL latch inputs (see application note)

Applications

■Digital receivers

■High-speed signal restoration

■Zero-crossing detectors

■High-speed sampling

■Window comparators

■High-speed signal triggering

Typical Application

(RS)ECL to RSPECL Converter

20183205

LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

ESD Tolerance (Note 2)

Human Body Model 2.5 kV

Machine Model 250V

Output Short Circuit Duration (Note 3, Note 4)

Supply Voltages (VCCx–VEE)13.2V

Differential Voltage at Input Pins ±13V

Voltage at Input Pins VEE-0.2V to VCCI + 0.2V

Voltage at LE Pins VEE-0.2V to VCCO+0.2V

Current at Output Pins 25mA

Soldering Information:

See Product Folder at www.national.com and http://

www.national.com/ms/MS/MS-SOLDERING.pdf

Storage Temperature Range −65°C to +150°C

Junction Temperature (Note 7) +150°C

Operating Conditions (Note 1)

Supply Voltage (VCCx–VEE) 2.7V to 12V

Operating Temperature Range

(Note 5, Note 6) −40°C to +125°C

Package Thermal Resistance

(Note 5, Note 6)

24-Pin LLP 38°C/W

12V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ. Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

INPUT CHARACTERISTICS

IBInput Bias Current VIN Differential = 0V; RHYS = 8 kΩ Biased

at VCM

−5 −2.9 µA

IOS Input Offset Current VIN Differential = 0V −250 40 +250 nA

TC IOS Input Offset Current TC VIN Differential = 0V 0.2 nA/°C

VOS Input Offset Voltage −8 −2 +8 mV

TC VOS Input Offset Voltage TC 12 µV/°C

VRI Input Voltage Range for CMRR ≥ 50 dB VEE−0.2 VCCI−1.5 V

VRID Input Differential Voltage Range −1 +1 V

CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ VCC1−0.2 80 dB

PSRR Power Supply Rejection Ratio 80 dB

AVActive Gain 53 dB

Hyst Hysteresis VHYS = V(HYS+) -V(HYS-) , RHYS = 0Ω 25 50 75 mV

LATCH ENABLE CHARACTERISTICS

IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 10 µA

VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level −5 mV

VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VEE+1.4 VCCO-0.8 V

VRID-LE Latch Enable Differential Voltage

Range

±0.4 V

OUTPUT CHARACTERISTICS

VOH Output Voltage High VIN Differential = 50 mV VCCO−1.1V mV

VOL Output Voltage Low VIN Differential = 50 mV VCCO−1.5V mV

VOD Output Voltage Differential VIN Differential = 50 mV 360 mV

POWER SUPPLIES

IVCCI VCCI Supply Current/ Channel 6.5 10

12 mA

IVCCO VCCO Supply Current/ Channel Load Current Excluded 16.3 20

www.national.com 2

LMH7322

12 AC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 12V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none.Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

TR Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

4 Gb/s

Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

255 ps

tjitter-RMS RMS Random Jitter Overdrive = ±100 mV; CL = 2 pF

Center Frequency = 140 MHz

Bandwidth = 10 Hz–20 MHz

702 fs

tPDH Propagation Delay.

(see Figure 3 application note)

Overdrive 20 mV 818 ps

Overdrive 50 mV 723

Input SR = Constant

VIN Startvalue = VREF −100 mV

Overdrive 100 mV 708 ps

Overdrive 1V 703

tOD-disp Input Overdrive Dispersion tPDH @ Overdrive 20 mV ↔ 100 mV 110

tPDH @ Overdrive 100 mV ↔ 1V 5

tSR-disp Input Slew Rate Dispersion 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 48 ps

tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV;

0V ≤ VCM ≤ VCCI- 1.5V

43 ps

ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 24 ps

ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 45 ps

trOutput Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps

tfOutput Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 155 ps

tsLE Latch Setup Time 77 ps

thLE Latch Hold Time 33 ps

tPD_LE Latch to Output Delay Time 944 ps

3 www.national.com

LMH7322

5V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ.Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

INPUT CHARACTERISTICS

IBInput Bias Current VIN Differential = 0V; RHYS = 8 kΩ

Biased at VCM

−5 −2.6 µA

IOS Input Offset Current VIN Differential = 0V −250 40 +250 nA

TC IOS Input Offset Current TC VIN Differential = 0V 0.3 nA/°C

VOS Input Offset Voltage −8 −2 +8 mV

TC VOS Input Offset Voltage TC 12 µV/°C

VRI Input Voltage Range for CMRR ≥ 50 dB VEE−0.2 VCCI−1.5 V

VRID Input Differential Voltage

Range

−1 +1 V

CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ VCC1−0.2 80 dB

PSRR Power Supply Rejection Ratio 80 dB

AVActive Gain 53 dB

Hyst Hysteresis VHYS = V(HYS+) -V(HYS-) , RHYS = 0Ω 25 50 75 mV

LATCH ENABLE CHARACTERISTICS

IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 10 µA

VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level +5 mV

VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VEE+1.4 VCCO-0.8 V

VRID-LE Latch Enable Differential

Voltage Range

±0.4 V

OUTPUT CHARACTERISTICS

VOH Output Voltage High VCCO−1.1V mV

VOL Output Voltage Low VCCO−1.5V mV

VOD Output Voltage Differential 355 mV

POWER SUPPLIES

IVCCI VCCI Supply Current/ Channel 6.3 10

IVCCO VCCO Supply Current/ Channel Load Current Excluded 15.8 20

www.national.com 4

LMH7322

5V AC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 5V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none. Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

TR Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

3.9 Gb/s

Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

260 ps

tjitter_RMS RMS Random Jitter Overdrive = ±100 mV; CL = 2 pF

Center Frequency = 140 MHz

Bandwidth = 10 Hz–20 MHz

572 fs

tPDLH Propagation Delay.

(see Figure 3 application note)

Overdrive 20 mV 783 ps

Overdrive 50 mV 718

Input SR = Constant

VIN startvalue = VREF – 100 mV

Overdrive 100 mV 708 ps

Overdrive 1V 708

tOD-disp Input Overdrive Dispersion tPDH @ Overdrive 20 mV ↔ 100 mV 75

tPDH @ Overdrive 100 mV ↔ 1V 5

tSR-disp Input Slew Rate Dispersion 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 50 ps

tCM-disp Input Common Mode Dispersion SR = 1 V/ns; Overdrive = 100 mV;

0V ≤ VCM ≤ VCCI- 1.5V

24 ps

ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 29 ps

ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 47 ps

trOutput Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 160 ps

tfOutput Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 160 ps

tsLE Latch Setup Time 95 ps

thLE Latch Hold Time 29 ps

tPD_LE Latch to Output Delay Time 893 ps

5 www.national.com

LMH7322

2.7V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 2.7V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = 1 kΩ. Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

INPUT CHARACTERISTICS

IBInput Bias Current VIN Differential = 0V; RHYS = 8 kΩ

Biased at VCM

−5 −2.5 µA

IOS Input Offset Current VIN Differential = 0V −250 40 +250 nA

TC IOS Input Offset Current TC VIN Differential = 0V 0.2 nA/°C

VOS Input Offset Voltage −8 −2 +8 mV

TC VOS Input Offset Voltage TC 12 µV/°C

VRI Input Voltage Range for CMRR ≥ 50 dB VEE−0.2 VCCI−1.5 V

VRID Input Differential Voltage

Range

−1 +1 V

CMRR Common Mode Rejection

Ratio

0V ≤ VCM ≤ VCC1−2 80 dB

PSRR Power Supply Rejection Ratio 80 dB

AVActive Gain 53 dB

Hyst Hysteresis VHYS = V(HYS+) -V(HYS-) , RHYS = 0Ω 25 50 75 mV

LATCH ENABLE CHARACTERISTICS

IB-LE Latch Enable Bias Current Biased at RSPECL Level 3 10 µA

VOS-LE Latch Enable Offset Voltage Biased at RSPECL Level −5 mV

VRI-LE Latch Enable Voltage Range for CMRR ≥ 50 dB VEE+1.4 VCCO-0.8 V

VRID-LE Latch Enable Differential

Voltage Range

±0.4 V

OUTPUT CHARACTERISTICS

VOH Output Voltage High VCCO−1.1V mV

VOL Output Voltage Low VCCO−1.5V mV

VOD Output Voltage Differential 350 mV

POWER SUPPLIES

IVCCI VCCI Supply Current/ Channel 6.2 10

IVCCO VCCO Supply Current/ Channel Load Current Excluded 15.5 20

www.national.com 6

LMH7322

2.7V AC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = 25°C,

VCCI = VCCO = 2.7V, VEE = 0V, RL = 50Ω to VCCO-2V, VCM = 300 mV, RHYS = none. Boldface limits apply at temperature extremes.

Symbol Parameter Conditions Min

(Note 8)

Typ

(Note 7)

Max

(Note 8)Units

TR Maximum Toggle Rate Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

3.8 Gb/s

Minimum Pulse Width Overdrive = ±50 mV; CL = 2 pF

@ 50% of Output Swing

265 ps

tjitter_RMS RMS Random Jitter Overdrive = ±50 mV; CL = 2 pF

Center Frequency = 140 MHz

Bandwidth = 10 Hz–20 MHz

551 fs

tPDH Propagation Delay.

(see Figure 3 application note)

Overdrive 20 mV 783 ps

Overdrive 50 mV 728

Input SR = Constant

VIN startvalue = VREF – 100 mV

Overdrive 100 mV 713 ps

Overdrive 1V 718

tOD-disp Input Overdrive Dispersion tPDH @ Overdrive 20 mV ↔ 100 mV 70

tPDH @ Overdrive 100 mV ↔ 1V 5

tSR-disp Input Slew Rate Dispersion 0.1 V/ns to 1 V/ns; Overdrive = 100 mV 54 ps

tCM-disp Input Common Mode

Dispersion

SR = 1 V/ns; Overdrive = 100 mV;

0V ≤ VCM ≤ VCCI- 1.5V

12 ps

ΔtPDLH Q to Q Time Skew |tPDH – tPDL| Overdrive = 100 mV; CL = 2 pF 35 ps

ΔtPDHL Q to Q Time Skew |tPDL – tPDH| Overdrive = 100 mV; CL = 2 pF 53 ps

trOutput Rise Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 165 ps

tfOutput Fall Time (20%–80%) Overdrive = 100 mV; CL = 2 pF 165 ps

tsLE Latch Setup Time 102 ps

thLE Latch Hold Time 37 ps

tPD_LE Latch to Output Delay Time 906 ps

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the

maximum allowed junction temperature of 150°C.

Note 4: Short circuit test is a momentary test. See next note.

Note 5: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is

PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

Note 6: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating

of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >

TA. See Applications section for information on temperature de-rating of this device.

Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will

also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 8: All limits are guaranteed by testing or statistical analysis.

Note 9: Positive current corresponds to current flowing into the device.

Note 10: Slew rate is the average of the positive and negative slew rate.

Note 11: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change.

7 www.national.com

LMH7322

Connection Diagrams

Schematic

20183202

Footprint

20183201

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

24-Pin LLP

NOPB

LMH7322SQ

L7322SQ

1k Units Tape and Reel

SQA24ALMH7322SQE 250 Units Tape and Reel

LMH7322SQX 4.5 Units Tape and Reel

www.national.com 8

LMH7322

Typical Performance Characteristics At TJ = 25°C; VCCI = +5V; VCCO = +3.3V; VEE = −5V; unless

otherwise specified.

Propagation Delay vs. Supply Voltage

20183226

Propagation Delay vs. Temperature

20183227

Propagation Delay vs. Supply Voltage

20183228

Propagation Delay vs. Overdrive Voltage

20183229

Propagation Delay vs. Common Mode Voltage

20183230

Propagation Delay vs. Slew Rate

20183231

9 www.national.com

LMH7322

TPD Dispersion vs. Supply Voltage

20183232

Slew Rate Dispersion vs. Voltage Supply

20183233

Common Mode Dispersion vs. Supply Voltage

20183234

Bias Current vs. Temperature

20183235

Input Current vs. Differential Input Voltage

20183236

Maximum Toggle Rate

20183237

www.national.com 10

LMH7322

Output Voltage vs. Input Voltage

20183238

Hysteresis Voltage vs. Hysteresis Resistor

20183239

11 www.national.com

LMH7322

Application Information

INTRODUCTION

The LMH7322 is a high speed comparator with RS(P)ECL

(Reduced Swing Positive Emitter Coupled Logic) outputs,

and is compatible with LVDS (Low Voltage Differential Sig-

naling) if VCCO is set to 2.5V. The use of complementary

outputs gives a high level of suppression for common mode

noise. The very fast rise and fall times of the LMH7322 enable

data transmission rates up to several Gigabits per second

(Gbps). The LMH7322 inputs have a common mode voltage

range that extends 200 mV below the negative supply voltage

thus allowing ground sensing in case of single supply. The

rise and fall times of the LMH7322 are about 160 ps, while the

propagation delay time is about 700 ps. The LMH7322 can

operate over the full supply voltage range of 2.7V to 12V,

while using single or dual supply voltages. This is a very useful

feature because it provides a flexible way to interface be-

tween several high speed logic families. Several setups are

shown in the application information section “INTERFACE

BETWEEN LOGIC FAMILIES”. The outputs are referenced

to the positive VCCO supply rail. The supply current is 23 mA

at 5V (per comparator, load current excluded.) The LMH7322

is available in a 24-Pin LLP package.

The following topics will be discussed in this application sec-

tion.

•Input and output topology

•Specification definitions

•Propagation delay and dispersion

•Hysteresis and oscillations

•Output

•Applying transmission lines

•PCB layout

INPUT & OUTPUT TOPOLOGY

All input and output pins are protected against excessive volt-

ages by ESD diodes. These diodes are conducting from the

negative supply to the positive supply. As can be seen in

Figure 1, both inputs are connected to these diodes. Further

protection of the inputs is provided by the two resistors of

250Ω, in conjunction with the string of anti-parallel diodes

connected between both bases of the input stage. This com-

bination of resistors and diodes reduces excessive input volt-

ages over the input stage, but is low enough to maintain

switching speed to the output signal.

Protection against excessive supply voltages is provided by

a power clamp between VCC and GND.

When using this part be aware of situations in which the dif-

ferential input voltage level is such that these diodes are

conducting. In this case the input current is raised far above

the normal value stated in the datasheet tables because input

current is flowing through the bypass diode string between

both inputs.

20183209

FIGURE 1. Equivalent Input Circuitry

The output stage of the LMH7322 is built using two emitter

followers, which are referenced to the VCCO (see Figure 2.)

Each of the output transistors is active when a current is flow-

ing through any external output resistor connected to a lower

supply rail. The output structure is actually the same as for all

other ECL devices. Activating the outputs is done by con-

necting the emitters to a termination voltage which lies 2V

below the VCCO. In this case a termination resistor of 50Ω can

be used and a transmission line of 50Ω can be driven. Another

method is to connect the emitters through a resistor to the

most negative supply by calculating the right value for the

emitter current in accordance with the datasheet tables. Both

methods are useful, and it is up to the customer which method

is used. Using 50Ω to the termination voltage means the in-

troduction of an extra supply in the system, while using resis-

tors to a negative supply means the use of resistors that are

much larger than 50Ω and a more constant output current per

stage. The following calculation will show the difference. In

this example a VCCO of 2.5V is used and a VT of VCCO-2V and

a negative supply of −5V. When connecting the outputs

through a 50Ω resistor to the VT, the output currents for the

high and the low state are respectively 18 mA and 10 mA.

Connecting the outputs through a 400Ω resistor to the −5V

supply the output currents for the high and the low state are

respectively 16 mA and 15 mA. Higher resistor values to the

VEE will further reduce power consumption but will cause a

slower transition of the output stage. In the case that this will

not harm your application it is a useful method to reduce pow-

er consumption.

www.national.com 12

LMH7322

20183210

FIGURE 2. Equivalent Output Circuitry

The output voltages for ‘1’ and ‘0’ have a difference of ap-

proximately 400 mV and are respectively 1.1V (for the ‘1’) and

1.5V (for the ‘0’) below the VCCO. This swing of 400 mV is

enough to drive any LVDS input but can also be used to drive

any ECL or PECL input, when the right supply voltage is cho-

sen, especially the right level for the VCCO.

Definitions

Symbol Text Description

IBInput Bias Current Current flowing in or out of the input pins, when both are biased at the VCM

voltage as specified in the tables.

IOS Input Offset Current Difference between the input bias current of the inverting and non-inverting

inputs.

TC IOS Average Input Offset Current Drift Temperature coefficient of IOS.

VOS Input Offset Voltage Voltage difference needed between IN+ and IN- to make the outputs change

state, averaged for H to L and L to H transitions.

TC VOS Average Input Offset Voltage Drift Temperature coefficient of VOS .

VRI Input Voltage Range Voltage which can be applied to the input pin maintaining normal operation.

VRID Input Differential Voltage Range Differential voltage between positive and negative input at which the input

clamp is not working. The difference can be as high as the supply voltage but

excessive input currents are flowing through the clamp diodes and protection

resistors.

CMRR Common Mode Rejection Ratio Ratio of input offset voltage change and input common mode voltage change.

PSRR Power Supply Rejection Ratio Ratio of input offset voltage change and supply voltage change from VS-MIN

to VS-MAX.

AVActive Gain Overall gain of the circuit.

Hyst Hysteresis Difference between the switching point ‘0’ to ‘1’ and vice versa.

IB-LE Latch Enable Bias Current Current flowing in or out of the input pins, when both are biased at normal

PECL levels.

IOS-LE Latch Enable Offset Current Difference between the input bias current of the LE and LE pin.

TC IOS-LE Temp Coefficient Latch Enable Offset

Current

Temperature coefficient of IOS-LE.

VOS-LE Latch Enable Offset Voltage Voltage difference needed between LE and LE to place the part in the latched

or the transparent state.

TC VOS-LE Temp Coefficient Latch Enable Offset

Voltage

Temperature coefficient of VOS-LE.

VRI-LE Latch Enable Voltage Range Voltage which can be applied to the LE input pins without damaging the

device.

VRID-LE Latch Enable Differential Voltage

Range

Differential Voltage between LE and LE at which the clamp isn’t working. The

difference can be as high as the supply voltage but excessive input currents

are flowing through the clamp diodes and protection resistors.

VOH Output Voltage High High state single ended output voltage (Q or Q) (see Figure 18).

13 www.national.com

LMH7322

Symbol Text Description

VOL Output Voltage Low Low state single ended output voltage (Q or Q) (see Figure 18).

VOD average of VODH and VODL (VODH + VODL)/2.

IVCCI Supply Current Input Stage Supply current into the input stage.

IVCCO Supply Current Output Stage Supply current into the output stage while current through the load resistors

is excluded.

IVEE Supply Current VEE pin Current flowing to the negative supply pin.

TR Maximum Toggle Rate Maximum frequency at which the outputs can toggle between the nominal

VOH and VOL.

PW Pulse Width Time from 50% of the rising edge of a signal to 50% of the falling edge.

tPDH resp

tPDL

Propagation Delay Delay time between the moment the input signal crosses the switching level

L to H and the moment the output signal crosses 50% of the rising edge of Q

output (tPDH), or delay time between the moment the input signal crosses the

switching level H to L and the moment the output signal crosses 50% of the

falling edge of Q output (tPDL).

tPDL resp

tPDH

Delay time between the moment the input signal crosses the switching level

L to H and the moment the output signal crosses 50% of the falling edge of

Q output (tPDL), or delay time between the moment the input signal crosses

the switching level H to L and the moment the output signal crosses 50% of

the rising edge of Q output (tPDH).

tPDLH Average of tPDH and tPDL .

tPDHL Average of tPDL and tPDH.

tPD Average of tPDLH and tPDHL.

tPDHd resp

tPDLd

Delay time between the moment the input signal crosses the switching level

L to H and the zero crossing of the rising edge of the differential output signal

(tPDHd), or delay time between the moment the input signal crosses the

switching level H to L and the zero crossing of the falling edge of the differential

output signal (tPDLd).

tOD-disp Input Overdrive Dispersion Change in tPD for different overdrive voltages at the input pins.

tSR-disp Input Slew Rate Dispersion Change in tPD for different slew rates at the input pins.

tCM-disp Input Common Mode Dispersion Change in tPD for different common mode voltages at the input pins.

ΔtPDLH resp

ΔtPDHL

Q to Q Time Skew Time skew between 50% levels of the rising edge of Q output and the falling

edge of output (ΔtPDLH), or time skew between 50% levels of falling edge of

Q output and rising edge of Q output (ΔtPDHL).

ΔtPD Average Q to Q Time Skew Average of tPDLH and tPDHL for L to H and H to L transients.

ΔtPDd Average Diff. Time Skew Average of tPDHd and tPDLd for L to H and H to L transients.

tr / trd Output Rise Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change

from 20% of its nominal value to 80%.

tf / tfd Output Fall Time (20% - 80%) Time needed for the (single ended or differential) output voltage to change

from 80% of its nominal value to 20%.

tsLE Latch Setup Time Time the input signal has to be stable before enabling the latch functionality.

thLE Latch Hold Time Time the input signal has to remain stable after enabling the latch functionality.

tPD-LE Latch to Output Delay Time Delay time between the moment the latch input crosses the switching level H

to L and the moment the differential output signal crosses the 50% level.

Note: input signal is opposite to output signal when latch becomes enabled.

www.national.com 14

LMH7322

20183204

FIGURE 3. Timing Definitions

20183203

FIGURE 4. LE Timing

15 www.national.com

LMH7322

Pin Descriptions

Pin Name Description Comment

1. VCCOA Positive Supply Output Stage part A The supply pin for the output stage is independent of the supply

pin for the input pin. This allows output levels of different logic

families.

2. LEA Latch Enable Input part A Logic ‘1’ sets the part on hold. Logic levels are RSPECL (Reduced

Swing PECL) compatible.

3. LEA Latch Enable Input Not part A Logic ‘0’ sets the part on hold. Logic levels are RSPECL

compatible.

4. VEEA Negative Supply part A The supply pin for the negative supply is connected to the VEEB

via a string of two anti-parallel diodes (see Figure 1)

5. VCCIA Positive Supply for Input

Stage

part A The supply pin for the input stage is independent of the supply for

the output stage.

6. RHYSA Hysteresis Resistor part A The hysteresis voltage is determined by connecting a resistor from

this pin to RHREFA.

7. INA- Negative Input part A Input for analog voltages between 200 mV below VEEA and 2V

below VCCIA.

8. INA+ Positive Input part A Input for analog voltages between 200 mV below VEEA and 2V

below VCCIA.

9. RHREFA Reference Voltage Hysteresis

Resistor

part A The hysteresis voltage is determined by connecting a resistor from

this pin to RHYSA.

10. RHREFB Reference Voltage Hysteresis

Resistor

part B The hysteresis voltage is determined by connecting a resistor from

this pin to RHYSB.

11. INB+ Positive Input part B Input for analog voltages between 200 mV below VEEB and 2V

below VCCIB.

12. INB− Negative Input part B Input for analog voltages between 200 mV below VEEB and 2V

below VCCIB.

13. RHYSB Hysteresis Resistor part B The hysteresis voltage is determined by connecting a resistor from

this pin to RHREFB.

14. VCCIB Positive Supply for Input

Stage

part B The supply pin for the input stage is independent of the supply for

the output stage.

15. VEEB Negative Supply part B The supply pin for the negative supply is connected to the VEEA

via a string of two anti-parallel diodes (see Figure 1).

16. LEB Latch Enable Input Not part B Logic ‘0’ sets the part on hold. Logic levels are RSPECL

compatible.

17. LEB Latch Enable Input Logic part B ‘1’ sets the part on hold. Logic levels are RSPECL compatible.

18. VCCOB Positive Supply for Output

Stage

part B The supply pin for the output stage is independent of the supply

pin for the input pin. This allows output levels of different logic

families.

19. QB Inverted Output part B Output levels are determined by the choice of VCCOB.

20. QB Output part B Output levels are determined by the choice of VCCOB.

21. VCCOB Positive Supply for Output

Stage

part B See other VCCOB

22. VCCOA Positive Supply for Output

Stage

part A See other VCCOA.

23. QA Output part A Output levels are determined by the choice of VCCOA.

24. QA Inverted Output part A Output levels are determined by the choice of VCCOA.

25. DAP Central pad at the bottom of

the package

A & B This pad is connected to the VEE pins and its purpose is to transfer

heat outside the part.

www.national.com 16

LMH7322

TIPS & TRICKS USING THE LMH7322

In this section several aspects are discussed concerning spe-

cial applications using the LMH7322.

This concerns the LE function, the connection of the DAP in

conjunction to the VEE pins and the use of this part as an in-

terface between several logic families.

THE LATCH ENABLE PINS

The latch function is intended to stop the device from com-

paring the signals on both input pins. If the latch function is

enabled, the output is frozen and the logic information on the

output pins, present at that moment, is held until the latch

function is disabled. The timing of this process can be seen

in Figure 4. The input levels for the latch pins should comply

with RSPECL, but can also be driven with PECL type of sig-

nals if the minimum supply (VCCO –VEE) is larger or equal to

3.3V. The minimum differential latch input voltage should be

100 mV. Another possibility to set the LE function in a steady

state is to connect the pins via a resistor to the power supply.

If the LE pin is connected to VEE via a resistor of 10 kΩ and

the LE-not pin is connected via 10 kΩ to the VCCO pin the part

is continuously on. Since the latch input stage is referenced

to VCCO, the resistors to set the LE function should be con-

nected to this voltage. This is very important when working

with different voltages for VCCI and VCCO. If connected to the

wrong supply, the latch function will not work.

THE DAP AND THE VEE PINS

To ensure that both VEE pins are operating at the same volt-

age, both pins are connected to the DAP, and thus to each

other, through bond wires. As a consequence, the DAP is at

the same potential as the VEE pins and can be used to con-

nect the device to the minimum supply voltage. A more solid

VEE connection is obtained if the two VEE pins and the DAP

are all connected to the minimum supply on the PCB, rather

than an indirect connection through the internal bond wires.

To protect the device during handling and production two anti-

parallel connected diodes are connected between both VEE

pins. Under normal operating conditions these diodes are

shorted via the DAP.

The DAP (Die Attach Paddle) functions as a heat sink which

means that heat can be transferred using vias below this pad

to the copper plane VEE is connected to.

20183225

FIGURE 5. DAP Connection

INTERFACE BETWEEN LOGIC FAMILIES

As can be seen in the typical schematics (see the first part of

the datasheet) the LMH7322 can be used to interface be-

tween different logic families. The feature that facilitates this

property is the fact that the input stage and the output stage

use different positive power supply pins which can be used at

different supply voltages. The negative supply pins are con-

nected together for both parts. Using the power pins at differ-

ent supply voltages makes it possible to create several

translations for logic families. It is possible to translate from

logic at negative voltage levels such as ECL to logic at positive

levels such as RSPECL and LVDS and vice versa. The draw-

ings in the next paragraphs do not show the output resistors

except the first one. This is intentionally done for simplicity.

All outputs need an output resistor to a termination voltage or

to the negative rail as can be seen on the front page in the

typical application of an ECL to RSPECL converter.

Interface from ECL to RSPECL

The supply pin VCCI can be connected to ground because the

input levels are negative and the VCCO pin must operate at 5V

to create the RSPECL levels (see Figure 6). When working

with ECL, the negative supply pin (VEE) can be connected to

the −5.2V ECL supply voltage.

20183205

FIGURE 6. ECL TO RSPECL

17 www.national.com

LMH7322

Interface from PECL to (RS)ECL

The conversion from PECL to RS-ECL is possible when con-

necting the VCCI pin to +5V, which allows the input stage to

handle these positive levels. The VCCO pin must be connected

to the ground level in order to create the RSECL levels. The

high level of the output of the LMH7322 is normally 1.1V below

the VCCO supply voltage, and the low level is 1.5V below this

supply. The output levels are now −1100 mV for the logic ‘1’

and −1500 mV for the logic ‘0’ (see Figure 7). In the same way

the VEE can be connected to the ECL supply voltage of −5.2V.

20183206

FIGURE 7. PECL TO RSECL

Interface from Analog to LVDS

As seen in Figure 8, the LMH7322 can be configured to create

LVDS levels. This is done by connecting the VCCO to 2.5V. As

discussed before the output levels are now at VCCO –1.1V for

the logic ‘1’ and at VCCO −1.5V for the logic ‘0’. These levels

of 1000 mV and 1400 mV comply with the LVDS levels. As

can be seen in this setup, an AC coupled signal via a trans-

mission line is used. This signal is terminated with 50Ω.

20183207

FIGURE 8. ANALOG TO LVDS

Figure 9 shows a standard comparator setup which creates

RSPECL levels because the VCCO supply voltage is +5V. In

this case the VEE pin is connected to the ground level. The

VCCI pin is connected to the VCCO pin because there is no

need to use different positive supply voltages. The input sig-

nal is AC coupled to the positive input. To maintain reliable

results the input pins IN+ and IN− are biased at 1.4V through

a resistive divider using a resistor of 1 kΩ to ground and a

resistor of 2.5 kΩ to the VCC and by adding two decoupling

capacitors. Both inputs are connected to the bias level by the

www.national.com 18

LMH7322

use of a 10 kΩ resistor. With this input configuration the input

stage can work in a linear area with signals of approximately

3 VPP (see input level restrictions in the data tables.)

20183208

FIGURE 9. Standard Setup

DELAY AND DISPERSION

Comparators are widely used to connect the analog world to

the digital one. The accuracy of a comparator is dictated by

its DC properties, such as offset voltage and hysteresis, and

by its timing aspects, such as rise and fall times and delay.

For low frequency applications most comparators are much

faster than the analog input signals they handle. The timing

aspects are less important here than the accuracy of the input

switching levels. The higher the frequencies, the more impor-

tant the timing properties of the comparator become, because

the response of the comparator can make a noticeable

change in critical parameters such as time frame or duty cy-

cle. A designer has to know these effects and has to deal with

them. In order to predict what the output signal will do, several

parameters are defined which describe the behavior of the

comparator. For a good understanding of the timing parame-

ters discussed in the following section, a brief explanation is

given and several timing diagrams are shown for clarification.

PROPAGATION DELAY

The propagation delay parameter is described in the definition

section. Due to this definition there are two parameters, tPDH

and tPDL (Figure 10). Both parameters do not necessarily have

the same value. It is possible that differences will occur due

to a different response of the internal circuitry. As a derivative

of this effect another parameter is defined: ΔtPD. This param-

eter is defined as the absolute value of the difference between

tPDH and tPDL.

20183211

FIGURE 10. Propagation Delay

If ΔtPD is not zero, duty cycle distortion will occur. For example

when applying a symmetrical waveform (e.g. a sinewave) at

the input, it is expected that the comparator will produce a

symmetrical square wave at the output with a duty cycle of

50%. When tPDH and tPDL are different, the duty cycle of the

output signal will not remain at 50%, but will be increased or

decreased. In addition to the propagation delay parameters

for single ended outputs discussed before, there are other

parameters in the case of complementary outputs. These pa-

rameters describe the delay from input to each of the outputs

and the difference between both delay times (See Figure

11.) When the differential input signal crosses the reference

level from L to H, both outputs will switch to their new state

with some delay. This is defined as tPDH for the Q output and

tPDL for the Q output, while the difference between both sig-

nals is defined as ΔtPDLH. Similar definitions for the falling

slope of the input signal can be seen in Figure 3.

19 www.national.com

LMH7322

20183212

FIGURE 11. tPD with Complementary Outputs

Both output circuits should be symmetrical. At the moment

one output is switching ‘on’ the other is switching ‘off’ with

ideally no skew between both outputs. The design of the

LMH7322 is optimized so that this timing difference is mini-

mized. The propagation delay, tPD, is defined as the average

delay of both outputs at both slopes: (tPDLH + tPDHL)/2.

Both overdrive and starting point should be equally divided

around the VREF (absolute values).

DISPERSION

There are several circumstances that will produce a variation

of the propagation delay time. This effect is called dispersion.

Amplitude Overdrive Dispersion

One of the parameters that causes dispersion is the amplitude

variation of the input signal. Figure 12 shows the dispersion

due to a variation of the input overdrive voltage. The overdrive

is defined as the ‘go to’ differential voltage applied to the in-

puts. Figure 12 shows the impact it has on the propagation

delay time if the overdrive is varied from 10 mV to 100 mV.

This parameter is measured with a constant slew rate of the

input signal.

20183213

FIGURE 12. Overdrive Dispersion

The overdrive dispersion is caused by the switching currents

in the input stage which is dependent on the level of the dif-

ferential input signal.

Slew Rate Dispersion

The slew rate is another parameter that affects propagation

delay. The higher the input slew rate, the faster the input stage

switches (See Figure 13).

20183214

FIGURE 13. Slew Rate Dispersion

A combination of overdrive and slew rate dispersion occurs

when applying signals with different amplitudes at constant

frequency. A small amplitude will produce a small voltage

change per time unit (dV/dt) but also a small maximum switch-

ing current (overdrive) in the input transistors. High ampli-

tudes produce a high dV/dt and a larger overdrive.

www.national.com 20

LMH7322

Common Mode Dispersion

Dispersion will also occur when changing the common mode

level of the input signal (Figure 14). When VREF is swept

through the CMVR (Common Mode Voltage Range), It results

in a variation of the propagation delay time. This variation is

called Common Mode Dispersion.

20183215

FIGURE 14. Common Mode Dispersion

All of the dispersion effects described previously influence the

propagation delay. In practice the dispersion is often caused

by a combination of more than one varied parameter.

HYSTERESIS & OSCILLATIONS

In contrast to an op amp, the output of a comparator has only

two defined states ‘0’ or ‘1.’ Due to finite comparator gain

however, there will be a small band of input differential voltage

where the output is in an undefined state. An input signal with

fast slopes will pass this band very quickly without problems.

During slow slopes however, passing the band of uncertainty

can take a relatively long time. This enables the comparators

output to switch back and forth several times between ‘0’ and

‘1’ on a single slope. The comparator will switch on its input

noise, ground bounce (possible oscillations), ringing etc.

Noise in the input signal will also contribute to these undesired

switching actions. The next sections explain these phenom-

ena in situations where no hysteresis is applied, and discuss

the possible improvement hysteresis can give.

Using No Hysteresis

Figure 15 shows what happens when the input signal rises

from just under the threshold VREF to a level just above it.

From the moment the input reaches the lowest dotted line

around VREF at t=0, the output toggles on noise etc. Toggling

ends when the input signal leaves the undefined area at t=1.

In this example the output was fast enough to toggle three

times. Due to this behavior digital circuitry connected to the

output will count a wrong number of pulses. One way to pre-

vent this is to choose a very slow comparator with an output

that is not able to switch more than once between ‘0’ and ‘1’

during the time the input state is undefined.

20183216

FIGURE 15. Oscillations on Output Signal

In most circumstances this is not an option because the slew

rate of the input signal will vary.

Using Hysteresis

Hysteresis can be introduced to avoid oscillations, e.g. due to

noise on the input signal, especially for slow edges. For this

purpose the switching level without hysteresis (VREF) is forced

to a new level (A or B) at the moment the input signal crosses

one of these levels. This can be seen in Figure 16.

20183218

FIGURE 16. Hysteresis

In this picture the two dotted lines A and B, represent the re-

sulting reference level at which the comparator will compare

the input level against. Assume that for this situation the input

signal is connected to the negative input and the switching

level (VREF) to the positive input. The input level drawn in

Figure 16 starts much lower as the reference level and this

means that the input stage is well defined with the inverting

input much lower than the non-inverting input. As a result the

output will be in the high state. Internally the switching level

is at level A, with the input signal sloping up, this situation

remains until VIN crosses level A at t=1. Now the output tog-

gles, and the internal switching level is lowered to level B. So

before the output has the possibility to toggle again, the volt-

age difference between the inputs is sufficient to have a stable

situation again. When the input signal comes down from high

21 www.national.com

LMH7322

to low, the situation is stable until level B is reached at t=0. At

this moment the output will toggle back, and the circuit returns

to the starting situation with the inverting input at a much lower

level than the non inverting input. Varying the levels A and B

due to the change of the hysteresis resistor will also vary the

timing of t=0 and t=1. When designing a circuit be aware of

this effect. Introducing hysteresis will cause some time shift

between output and input (e.g. duty cycle variations), but will

eliminate undesired switching of the output.

Configuring Hysteresis for the LMH7322

The LMH7322 offers the possibility to introduce hysteresis by

connecting a resistor between the RHYS pin and the RHREF

pin. This hysteresis setting resistor may vary between zero

ohm and infinite. The current drawn from the RHYS pin de-

termines the setting of the internal reference voltage. When

no resistor is present the internal used reference voltage is

set to zero (the difference between A and B level is zero, see

explanation Using Hysteresis) and no hysteresis is config-

ured. This means the output will change state when the

difference between the positive en negative input signals

crosses zero level. Connecting a resistor between the RHYS

pin and the RHREF pin produces a difference for the A and

B levels which means hysteresis is introduced and the output

will change state at different levels for an up or down transition

of the input signal. Due to the internal structure a current must

be drawn from the RHYS pin. This can be done by connecting

a resistor to the lowest supply voltage. In order to assure the

RHYS pin is connected to the correct voltage level, and un-

wanted current variations in the hysteresis level are avoided,

the RHREF and VEE are connected internally within the

LMH7322. Therefore, the hysteresis resistor should only be

connected between RHYS and RHREF or left open if no hys-

teresis is required. To select the correct resistor for the de-

sired hysteresis voltage see Figure 17.

20183239

FIGURE 17. Hysteresis Voltage vs. Hysteresis Resistor

With the use of a resistor to set the hysteresis voltage no ex-

ternal conditions will effect these setting as long as they stay

within the normal operating ranges. Temperature changes

may cause a variation of the hysteresis resistor dictated by

the temperature coefficient of the used type. Connecting the

RHYS pin to another voltage as provided by the RHREF pin

is not covered in the resistor selection plot and the designer

of such a circuit must be aware of abnormal behavior.

The Output

OUTPUT SWING PROPERTIES

The LMH7322 has differential outputs which means that both

outputs have the same swing but in opposite directions (See

Figure 18). Both outputs swing around the common mode

output voltage (VO). This voltage can be measured at the

midpoint between two equal resistors connected to each out-

put. The absolute value of the difference between both volt-

ages is called VOD. The outputs cannot be held at the VO level

because of their digital nature. They only cross this level dur-

ing a transition. Due to the symmetrical structure of the circuit,

both output voltages cross at VO regardless of whether the

output changes from ‘0’ to ‘1’ or vise versa.

20183219

FIGURE 18. Output Swing

LOADING THE OUTPUT

Both outputs are activated when current is flowing through a

resistor that is externally connected to VT. The termination

voltage should be set 2V below the VCCO. This makes it pos-

sible to terminate each of the outputs directly with 50Ω, and

if needed to connect through a transmission line with the

same impedance (see Figure 19). Due to the low ohmic na-

ture of the output emitter followers and the 50Ω load resistor,

a capacitive load of several pF does not dramatically affect

the speed and shape of the signal. When transmitting the sig-

nal from one output to any input the termination resistor

should match the transmission line. The capacitive load (CP)

will distort the received signal. When measuring this input with

a probe, a certain amount of capacitance from the probe is

parallel to the termination resistor. The total capacitance can

be as large as 10 pF. In this case there is a pole at:

f = 1/(2*π*C*R)

f = 1e9/ π

f = 318 MHz

In this case the current IP has the same value as the current

through the termination resistor. This means that the voltage

drops at the input and the rise and fall times are dramatically

different from the specified numbers for this part.

Another parasitic capacitance that can affect the output signal

is the capacitance directly between both outputs, called

CPAR (see Figure 19). The LMH7322 has two complementary

outputs so there is the possibility to transport the output signal

by a symmetrical transmission line. In this case both output

tracks form a coupled line with their own parasitics and both

receiver inputs connected to the transmission line. Actually

the line termination looks like 100Ω and the input capaci-

tances, which are in series, are parallel to the 100Ω termina-

tion. The best way to measure the input signal is to use a

differential probe directly across both inputs. Such a probe is

very suitable for measuring these fast signals because it has

good high frequency characteristics and low parasitic capac-

itance.

www.national.com 22

LMH7322

20183221

FIGURE 19. Parasitic Capacitance

TRANSMISSION LINES & TERMINATION

TECHNOLOGIES

The LMH7322 uses complementary RSPECL outputs and

emitter followers, which means high output current capability

and low sensitivity to parasitic capacitance. The use of Re-

duced Swing Positive Emitter Coupled Logic reduces the

supply voltage to 2.7V, being the lowest possible value, and

raises the maximum frequency response. Data rates are

growing, which requires increasing speed. Data is not only

connected to other IC’s on a single PCB board but, in many

cases, there are interconnections from board to board or from

equipment to equipment. Distances can be short or long but

it is always necessary to have a reliable connection, which

consumes low power and is able to handle high data rates.

The complementary outputs of the LMH7322 make it possible

to use symmetrical transmission lines The advantage over

single ended signal transmission is that the LMH7322 has

higher immunity to common mode noise. Common mode sig-

nals are signals that are equally apparent on both lines and

because the receiver only looks at the difference between

both lines, this noise is canceled.

Maximum Bit Rates

The maximum toggle rate is defined at an amplitude of 50%

of the nominal output signal. This toggle rate is a number for

the maximum transfer rate of the part and can be given in Hz

or in Bps. When transmitting signals in a NRZ (Non Return to

Zero) format the bitrate is double this frequency number, be-

cause during one period two bits can be transmitted. (See

Figure 20.) The rise and fall times are very important specifi-

cations in high speed circuits. In fact these times determine

the maximum toggle rate of the part. Rise and fall times are

normally specified at 20% and 80% of the signal amplitude

(60% difference). Assuming that the edges at 50% amplitude

are coming up and down like a sawtooth it is possible to cal-

culate the maximum toggle rate but this number is too opti-

mistic. In practice the edges are not linear while the pulse

shape is more or less a sinewave.

20183222

FIGURE 20. Bit Rates

Need for Terminated Transmission Lines

During the 1980’s and 90’s, National fabricated the 100K ECL

logic family. The rise and fall time specifications were 0.75 ns,

which are considered very fast. If sufficient care has not been

given in designing the transmission lines and choosing the

correct terminations, then errors in digital circuits are intro-

duced. To be helpful to designers that use ECL with “old”

PCB-techniques, the 10K ECL family was introduced with a

rise and fall time specification of 2 ns. This was much slower

and easier to use. The RSPECL output signals of the

LMH7322 have transition times that extend the fastest ECL

family. A careful PCB design is needed using RF techniques

for transmission and termination. Transmission lines can be

formed in several ways. The most commonly used types are

the coaxial cable and the twisted pair telephony cable (Figure

21).

20183223

FIGURE 21. Cable Types

23 www.national.com

LMH7322

These cables have a characteristic impedance determined by

their geometric parameters. Widely used impedances for the

coaxial cable are 50Ω and 75Ω. Twisted pair cables have

impedances of about 120Ω to 150Ω.

Other types of transmission lines are the strip line and the

micro strip line. These last types are used on PCB boards.

They have the characteristic impedance dictated by the phys-

ical dimensions of a track placed over a metal ground plane

(see Figure 22).

20183224

FIGURE 22. PBC Lines

Differential Microstrip

Line The transmission line which is ideally suited for comple-

mentary signals is the differential microstrip line. This is a

double microstrip line with a narrow space in between. This

means both lines have strong coupling and this determines

the characteristic impedance. The fact that they are routed

above a copper plane does not affect differential impedance,

only CM-capacitance is added. Each of the structures above

has its own geometric parameters, so for each structure there

is different formula to calculate the right impedance. For cal-

culations on these transmission lines visit the National web-

site or order RAPIDESIGNER. At the end of the transmission

line there must be a termination having the same impedance

as that of the transmission line itself. It does not matter what

impedance the line has, if the load has the same value no

reflections will occur. When designing a PCB board with

transmission lines on it, space becomes an important item

especially on high density boards. With a single microstrip

line, line width is fixed for given impedance and a board ma-

terial. Other line widths will result in different impedances.

Advantages of Differential MicrostripLines

Impedances of transmission lines are always dictated by their

geometric parameters. This is also true for differential mi-

crostrip lines. Using this type of transmission line, the distance

of the track determines the resulting impedance. So, if the

PCB manufacturer can produce reliable boards with low track

spacing the track width for a given impedance is also small.

The wider the spacing, the wider tracks are needed for a spe-

cific impedance. For example two tracks of 0.2 mm width and

0.1 mm spacing have the same impedance as two tracks of

0.8 mm width and 0.4 mm spacing. With high-end PCB pro-

cesses, it is possible to design very narrow differential mi-

crostrip transmission lines. It is desirable to use these to

create optimal connections to the receiving part or the termi-

nating resistor, in accordance to their physical dimensions.

Seen from the comparator, the termination resistor must be

connected at the far end of the line. Open connections after

the termination resistor (e.g. to an input of a receiver) must

be as short as possible. The allowed length of such connec-

tions varies with the received transients. The faster the tran-

sients, the shorter the open lines must be to prevent signal

degradation.

PCB LAYOUT CONSIDERATIONS AND COMPONENT

VALUE SELECTION

High frequency designs require that both active and passive

components be selected from those that are specially de-

signed for this purpose. The LMH7322 is fabricated in a 24-

pin LLP package intended for surface mount design. For

reliable high speed design it is highly recommended to use

small surface mount passive components because these

packages have low parasitic capacitance and low inductance

simply because they have no leads to connect them to the

PCB. It is possible to amplify signals at frequencies of several

hundreds of MHz using standard through-hole resistors. Sur-

face mount devices however, are better suited for this pur-

pose. Another important issue is the PCB itself, which is no

longer a simple carrier for all the parts and a medium to in-

terconnect them. The PCB becomes a real component itself

and consequently contributes its own high frequency proper-

ties to the overall performance of the circuit. Good practice

dictates that a high frequency design have at least one ground

plane, providing a low impedance path for all decoupling ca-

pacitors and other ground connections. Care should be given

especially that on-board transmission lines have the same

impedance as the cables to which they are connected. Most

single ended applications have 50Ω impedance (75Ω for

video and cable TV applications). Such low impedance, single

ended microstrip transmission lines usually require much

wider traces (2 to 3 mm) on a standard double sided PCB

board than needed for a ‘normal’ trace. Another important is-

sue is that inputs and outputs should not ‘see’ each other. This

occurs if input and output tracks are routed in parallel over the

PCB with only a small amount of physical separation, partic-

ularly when the difference in signal level is high. Furthermore,

components should be placed as flat and low as possible on

the surface of the PCB. For higher frequencies a long lead

can act as a coil, a capacitor or an antenna. A pair of leads

can even form a transformer. Careful design of the PCB min-

imizes oscillations, ringing and other unwanted behavior. For

ultra high frequency designs only surface mount components

will give acceptable results. (For more information see

OA-15).

NSC suggests the following evaluation board as a guide for

high frequency layout and as an aid in device testing:

LMH7322EVAL

www.national.com 24

LMH7322

Physical Dimensions inches (millimeters) unless otherwise noted

24-Pin LLP Package

NS Package Number SQA24A

25 www.national.com

LMH7322

Notes

LMH7322 Dual 700 ps High Speed Comparator with RSPECL Outputs

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

www.national.com

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench

Audio www.national.com/audio App Notes www.national.com/appnotes

Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns

Data Converters www.national.com/adc Samples www.national.com/samples

Interface www.national.com/interface Eval Boards www.national.com/evalboards

LVDS www.national.com/lvds Packaging www.national.com/packaging

Power Management www.national.com/power Green Compliance www.national.com/quality/green

Switching Regulators www.national.com/switchers Distributors www.national.com/contacts

LDOs www.national.com/ldo Quality and Reliability www.national.com/quality

LED Lighting www.national.com/led Feedback/Support www.national.com/feedback

Voltage References www.national.com/vref Design Made Easy www.national.com/easy

PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions

Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero

Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic

PLL/VCO www.national.com/wireless PowerWise® Design

University

www.national.com/training

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

www.national.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Audio www.ti.com/audio Communications and Telecom www.ti.com/communications

Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers

Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps

DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy

DSP dsp.ti.com Industrial www.ti.com/industrial

Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical

Interface interface.ti.com Security www.ti.com/security

Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265