Power Management ICs for Automotive Body Control LED Indicator Driver BD8105FV No.11039ECT01 Description The BD8105FV is a serial parallel control LED driver with 35V input voltage rating. Responding to the 3-line serial data, it turns the 12ch open drain output on/off. Due to its compact size, it is optimal for small spaces. Features 1) Open Drain Output 2) 3-line Serial Control + Enable Signal 3) Internal Temperature Protection Circuit (TSD) 4) Cascade Connection Compatible 5) SSOP-B20W 6) Internal 12 ch Power Transistor Applications These ICs can be used with car and consumer electronic. Absolute Maximum Ratings (Ta=25) Parameter Symbol Ratings Unit VCC 7 V Output Voltage(Pin No : 49, 1116) VDmax 35 V Input Voltage(Pin No : 1, 2, 3, 17, 18) VIN -0.3VCC V Power Dissipation Pd 1187* mW Operating Temperature Range Topr -40+105 Storage Temperature Range Tstg -55+150 Drive Current (DC) IomaxD 50 mA Drive Current(Pulse) IomaxP 150** mA Junction Temperature Tjmax 150 Power Supply Voltage * ** Pd decreased at 9.50mW/ for temperatures above Ta=25,mounted on 70x70x1.6mm Glass-epoxy PCB. Do not however exceed Pd. Time to impress200msec www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 1/12 2011.05 - Rev.C Technical Note BD8105FV Operational Conditions (Ta=-40~105) Parameter Power Supply Voltage Symbol Ratings Unit Min. Typ. Max. Vcc 4.5 5 5.5 V Io - 20 40 mA Drive Current * This product is not designed for protection against radioactive rays. Electrical Characteristics (Unless specified, Ta=-40~105 Vcc=4.55.5V) Limits Parameter Symbol Min. Typ. Max. Unit Conditions Output D0D11(Pin No : 49, 1116) ON Resistor RON - 6 12 ID=20mA IDL - 0 5 A VD=34V Upper limit threshold voltage VTH Vcc x0.8 - - V Bottom limit threshold voltage VTL - - Vcc x0.2 V FCLK - - 1 MHz Input Current IIN 20 50 100 A VIN=5V Input leakage Current IINL - 0 5 A VIN=0V Circuit Current ICC - 0.3 5 mA Static Current ISTN - 0 50 A Output Voltage high VOH 4.6 4.8 - V VCC=5V, ISO=-5mA Output voltage Low VOL - 0.2 0.4 V VCC=5V, ISO=5mA Output leakage current Logic input(Pin No : 1, 2, 3, 17, 18) Serial clock frequency WHOLE Serial Data Input, VCC=5V,CLK=500KHz, SEROUT=OPEN RST_B=OPEN, SEROUT=OPEN SER OUT(Pin No. : 20) * This product is not designed for protection against radioactive rays. www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 2/12 2011.05 - Rev.C Technical Note BD8105FV Electrical Characteristic Diagrams (Unless otherwise specified Ta=25) 10 230 250 9 105 -40 100 50 225 OUTPU T RESISTANCERON[] 150 SUPPLY CURRENTIcc[A] SUPPLY CURRENTIcc[A] 5.5V 25 200 5.0V 220 4.5V 215 210 105 8 7 25 6 5 -40 4 3 2 1 205 0 1 2 3 4 SUPPLY VOLTAGEVcc[V] 0 -40 5 5V 5 5.5V 3 2 1 0 85 4.5 -15 10 35 60 5.6 4.5V 5.4 5.2 5V 5.0 4.8 5.5V 4.6 4.4 4.2 85 20 30 40 Fig.4 Dxx on resistance 2 (at IDD=20mA) Fig.5 Dxx on resistance 6.0 4.0 3.5 3.0 -15 10 35 60 85 AMBIENT TEMPERATURE Ta[] Fig.7 SEROUT high side voltage 2 (at ISO=-5mA) www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 25 4.4 105 4.2 4.7 4.9 5.1 5.3 SUPPLY VOLTAGE Vcc[V] 5.5 0.35 0.30 25 0.25 0.20 0.15 -40 0.10 0.05 4.5V 0.25 0.20 5V 0.15 5.5V 0.10 0.05 0.00 0.00 -40 4.6 Fig.6 SEROUT high side voltage 1 (at ISO=-5mA) OUTPUT VOLTAGE VOL[V] OUTPU T VOLTAGE VOL[V] 4.5V 4.5 4.8 4.5 105 0.30 5.5 5.0 50 0.35 5.5V -40 5.2 4.0 10 INPUT CURRENT ID [mA] 5V 5.5 5.4 5.8 AMBIENT TEMPERATURE Ta[] 5.0 4.7 4.9 5.1 5.3 SUPPLYVOLTAGEVcc[V] Fig.3 Dxx on resistance 1 (at IDD=20mA) 4.0 -40 OUTPU T VOLTAGE VOH[V] 60 6.0 OUTPUT ON RESISTANCE RON[] OUTPU T ON RESISTANCE RON[] 7 4 35 Fig.2 Circuit current 2 4.5V 6 10 AMBIENT TEMPERATURE Ta[] Fig.1 Circuit current 1 8 -15 OUTPU T VOLTAGE VOH[V] 0 4.5 4.7 4.9 5.1 5.3 5.5 SUPPLY VOLTAGE Vcc[V] Fig.8 SEROUT low side voltage 1 (at ISO=5mA) 3/12 -40 -15 10 35 60 85 AMBIENT TEMPERATURE Ta[] Fig.9 SEROUT low side voltage 2 (at ISO=5mA) 2011.05 - Rev.C Technical Note BD8105FV Block Diagram SDWN 3 TSD <11:0> 17 1 18 2 SERIN Driver LATCH Serial I/F CLK <11:0> <11:0> <11:0> RST_B 4 D11 5 D10 6 D9 7 D8 8 D7 9 D6 11 D5 12 D4 13 D3 14 D2 15 D1 16 D0 VCC 10 SEROUT SEROUT 19 20 GND Fig.10 Pin Setup Diagram BD8105FV(SSOP-B20W) Terminal NumberTerminal Name Pin Terminal Function Number Name Latch Signal Input Terminal 1 LATCH (H: Latches Data) SEROUT Reset Reversal Input Terminal 2 RST_B (L: FF Data 0) VCC Shutdown Input Terminal 3 SDWN CLK (H: Output Off) LATCH 1 20 RST_B 2 19 SDWN 3 18 D11 4 17 SERIN D10 5 16 D0 D9 6 15 D1 D8 7 14 D2 D7 8 13 D3 D6 9 12 D4 GND 10 11 D5 Fig.11 www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 4/12 4 D11 Drain Output Terminal 11 5 D10 Drain Output Terminal 10 6 D9 Drain Output Terminal 9 7 D8 Drain Output Terminal 8 8 D7 Drain Output Terminal 7 9 D6 Drain Output Terminal 6 10 GND 11 D5 Drain Output Terminal 5 12 D4 Drain Output Terminal 4 13 D3 Drain Output Terminal 3 14 D2 Drain Output Terminal 2 15 D1 Drain Output Terminal 1 16 D0 Drain Output Terminal 0 17 SERIN Ground Terminal Serial Data Input Terminal 18 CLK Clock Input Terminal 19 VCC Supply Voltage Input Terminal 20 SEROUT Serial Data Output Terminal 2011.05 - Rev.C Technical Note BD8105FV Block Operation 1)Serial I/F The I/F is a 3-line serial (LATCH, CLK, SERIN) style. 12-bit output ON/OFF can be set-up. This is composed of shift register. + 12-bit register. 2)Driver It is a 12-bit open drain output. 3)TSD (Thermal Shut Down) To prevent heat damage and overheating, when the chip temperature goes over approximately 175, the output turns off. When the temperature goes back down, normal operation resumes. However, the intended use of the temperature protection circuit is to protect the IC, so please construct thermal design with the junction temperature Tjmax under 150. Application Circuit VCC 10uF VBAT 10uF IF Rres VF VCC SDWN LATCH RST_B CLK SERIN SEROUT GND Microcomputer D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VCC 10uF VCC SDWN LATCH RST_B CLK SERIN SEROUT GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 IF= VBAT - VF Rres + RON Fig.12 www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 5/12 2011.05 - Rev.C Technical Note BD8105FV Serial Communication The serial I/F is composed of a shift register which changes the CLK and SERIN serial signals to parallel signals, and a register to remember those signals with a LATCH signal. The registers are reset by applying a voltage under VCCx0.2 to the RST_B terminal or opening it, and D11~D0 become open. To prevent erroneous LED lighting, please apply voltage under VCCx0.2 to RST_B or make it open during start-up. CLK 12bit Shift Register SERIN 12bit Driver Register LATCH Fig.13 1)Serial Communication Timing The 12-bit serial data input from SERIN is taken into the shift register by the rise edge of the CLK signal, and is recorded in the register by the rise edge of the LATCH signal. The recorded data is valid until the next rise edge of the LATCH signal. 2)Serial Communication Data The serial data input configuration of SERIN terminal is shown below: First Last d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Data Terminal Name Output Status d11 d10 d9 ON 1 * * D11 OFF 0 * * ON * 1 * D10 OFF * 0 * ON * * 1 D9 OFF * * 0 ON * * * D8 OFF * * * ON * * * D7 OFF * * * ON * * * D6 OFF * * * ON * * * D5 OFF * * * ON * * * D4 OFF * * * ON * * * D3 OFF * * * ON * * * D2 OFF * * * ON * * * D1 OFF * * * ON * * * D0 OFF * * * * represents "Don't care". www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. Data d8 * * * * * * 1 0 * * * * * * * * * * * * * * * * d7 * * * * * * * * 1 0 * * * * * * * * * * * * * * d6 * * * * * * * * * * 1 0 * * * * * * * * * * * * d5 * * * * * * * * * * * * 1 0 * * * * * * * * * * 6/12 d4 * * * * * * * * * * * * * * 1 0 * * * * * * * * d3 * * * * * * * * * * * * * * * * 1 0 * * * * * * d2 * * * * * * * * * * * * * * * * * * 1 0 * * * * d1 * * * * * * * * * * * * * * * * * * * * 1 0 * * d0 * * * * * * * * * * * * * * * * * * * * * * 1 0 2011.05 - Rev.C Technical Note BD8105FV 3)Enable Signal By applying voltage at least VCCx0.8 or more to the SDWN terminal, D0 (16 pin)~D11 (4 pin) become open forcibly. At this time, the temperature protection circuit (TSD) stops. D11D0 become PWM operation by inputting PWM to SDWN(3 pin). 4)SEROUT A cascade connection can be made (connecting at least 2 or more IC's in serial). Serial signal input from SERIN is transferred into receiver IC by the fall edge of the CLK signal. Since this functionality gives enough margins for the setup time prior to the rise edge of the CLK signal on the receiver IC (using the exact same CLK signal of sender IC), the application reliability can be improved as cascade connection functionality. LATCH SERIN d11 d10 CLK 1 d9 2 d8 3 d7 4 d5 d6 5 6 d3 d4 7 8 d2 9 d1 10 d0 11 12 SEROUT 13 D11 Fig.14 Cascade Connection By using (at least) 2 ICs, each IC's D11~D0, at (at least) 24ch, can be controlled by the 24-bit SERIN signal. input to the sender IC can be transferred to the receiver IC by inputting 12CLK to the CLK terminal. Send side IC The serial data Receive side IC LATCH SERIN CLK d23 d22 d21 d20 1 2 3 4 d19 d18 d17 5 6 7 d16 d15 d14 d13 8 9 10 11 d12 d11 d10 12 13 14 d9 15 d8 16 d7 17 d6 18 d5 19 d4 20 d3 21 d2 22 d1 23 d0 24 Fig.15 www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 7/12 2011.05 - Rev.C Technical Note BD8105FV INPUT SIGNAL'S TIMING CHART TCK 50% CLK TCKH TCKL TSESTTSEHD SERIN 50% TLADZ TSEW 50% LATCH TLAH Fig.16 INPUT SIGNAL'S TIMING RULE(Ta=-40105 Vcc=4.55.5V) Parameter Symbol Min Unit TCK 1000 ns CLK high pulse width TCKH 480 ns CLK low pulse width TCKL 480 ns SERIN high and low pulse width TSEW 980 ns SERIN setup time prior to CLK rise TSEST 150 ns SERIN hold time after CLK fall TSEHD 150 ns TLAH 480 ns TLADZ 250 ns CLK period LATCH high pulse time Last CLK rise to LATCH rise www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 8/12 2011.05 - Rev.C Technical Note BD8105FV OUTPUT SIGNAL'S DELAY CHART SDWN 50% TDSNL TDSNH OUTPUT (D11D0) LATCH 50% 50% TDLAH OUTPUT (D11D0) CLK 50% 50% TDSOH SEROUT TDSOL 50% Fig.17 OUTPUT SIGNAL'S DELAY TIME(Ta=-40105 Vcc=4.55.5V) Parameter Symbol Max Unit SDWN Switching Time(LH) TDSNH 300 ns SDWN Switching Time(HL) TDSNL 300 ns LATCH Switching Delay Time TDLAH 300 ns SEROUT Propagation Delay Time(LH) TDSOH 350 ns SEROUT Propagation Delay Time (HL) TDSOL 350 ns www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 9/12 2011.05 - Rev.C Technical Note BD8105FV INPUT/OUTPUT EQUIVALENT CIRCUIT(PIN NAME) 4PIN(D11),5PIN(D10) 1PIN(LATCH) 6PIN(D9),7PIN(D8) 2PIN(RST_B) 8PIN(D7),9PIN(D6) 3PIN(SDWN) 11PIN(D5),12PIN(D4) 17PIN(SERIN) 13PIN(D3),14PIN(D2) 18PIN(CLK) 15PIN(D1),16PIN(D0) VCC 20PIN(SEROUT) VCC VCC 100k (TYP) Fig.18 www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 10/12 2011.05 - Rev.C Technical Note BD8105FV Notes for use (1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) Reverse connection of a power supply connector If the connector of power is wrong connected, it may result in IC breakage. In order to prevent the breakage from the wrong connection, the diode should be connected between external power and the power terminal of IC as protection solution. (3) GND potential Ensure a minimum GND pin potential in all operating conditions. (4) Setting of heat Use a setting of heat that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (5) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. (6) Actions in strong magnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. (7) Thermal shutdown circuit(TSD) This IC built-in a Thermal shutdown circuit (TSD circuit). If Chip temperature becomes 175(TYP.), make the output an Open state. Eventually, warmly clearing the circuit is decided by the condition of whether the heat excesses over the assigned limit, resulting the cutoff of the circuit of IC, and not by the purpose of preventing and ensuring the IC. Therefore, the warm switch-off should not be applied in the premise of continuous employing and operation after the circuit is switched on. (8) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process (9) IC terminal input This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when a resistor and transistor are connected to pins. (See the chart below.) the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN). Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a parasitic NPN transistor. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input pins. Transistor (NPN) (Pin B) C B E (Pin B) B (Pin A) GND P+ P+ N N P P N N N Parasitic elements GND Parasitic elements Parasitic elements P+ N P substrate GND E GND N P P+ C (Pin A) Resistor Parasitic elements (10) Ground wiring patterns GND When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 11/12 2011.05 - Rev.C Technical Note BD8105FV Ordering part number B D 8 Part No. 1 0 5 F Part No. V - Package FV: SSOP-B20W E 2 Packaging and forming specification E2: Embossed tape and reel SSOP-B20W <Tape and Reel information> 6.5 0.2 Embossed carrier tape Quantity 2000pcs 0.3Min. Direction of feed 1 E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 10 0.15 0.1 0.11 1.7 0.2 Tape 11 6.1 0.2 8.1 0.3 20 0.1 0.65 0.22 0.1 1pin Reel (Unit : mm) www.rohm.com (c) 2011 ROHM Co., Ltd. All rights reserved. 12/12 Direction of feed Order quantity needs to be multiple of the minimum quantity. 2011.05 - Rev.C Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. 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