MIAAILM Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down General Description The MAX191 is a monolithic, CMOS, 12-bit analog-to- digital converter (ADC) featuring differential inputs, track/hold (T/H), internal voltage reference, internal or external clock, and parallel or serial pP interface. The MAX191 has a 7.5us conversion time, a 2us acquisition time, and a guaranteed 100ksps sample rate. The MAX191 operates from a single +5V supply or from dual +5V supplies, allowing ground-referenced bipolar input signals. The device features a logic power-down input, which reduces the 3mA Vpp supply current to 50yuA max, including the internal-reference current. Decoupling capacitors are the only external compo- Features 12-Bit Resolution, 1/2LSB Linearity +5V or t5V Operation Built-In Track/Hold Internal Reference with Adjustment Capability Low Power: 3mA Operating Mode 20pA Power-Down Mode 100ksps Tested Sampling Rate Serial and 8-Bit Parallel pP Interface 24-Pin Narrow DIP and Wide SO Packages Ordering Information ef ef + @ of nents needed for the power supply and reference. This PART TEMP. RANGE PIN-PACKAGE ERROR ADC operates with either an external reference, or an (LSB) internal reference that features an adjustment input for MAX191ACNG 0C to +70C 24 Narrow Plastic DIP _+1/2 trimming system gain errors. MAX191BCNG _0C to +70C_ 24 Narrow Plastic DIP_ +1 The MAX191 provides three interface modes: two 8-bit MAX191ACWG 0C to +70C 24 Wide SO +1/2 parallel modes, and a serial interface mode that is com- MAX191BCWG 0C to +70C 24 Wide SO +4 patible with SPIT, QSPITM, and MICROWIRE serial- MAX191BC/D 0C to +70C Dice* H interface standards. MAX191AENG -40C to +85C 24 Narrow Plastic DIP_ +1/2 App lications MAX191BENG = -40C to +85C._ 24 Narrow Plastic DIP +1 Battery-Powered Data Logging MAXI91AEWG -40C to +85C_ 24 Wide SO +1/2 PC Pen Digitizers MAX191BEWG -40C to +85C 24 Wide SO +1 High-Accuracy Process Control MAX191AMRG -55C to +125C_ 24 Narrow CERDIP +1/2 Electromechanical Systems MAX191BMRG -55C to + 125C 24 Narrow CERDIP +1 Data-Acquisition Boards for PCs Automatic Testing Systems Telecommunications Digital Signal Processing (DSP) * Dice are specified at T, = +25C, DC parameters only. Contact factory for availability and processing to MIL-STD-883. Pin Configuration Functional Diagram TOP VIEW W PD [4 | ba] Von Vi CLK/SCLK 4 23 Vss [2 | b3] CLK/SCLK I va 2 080 | [ome HP Dou AIN+ [| bo] PAR AEFAD output [16 eee AN [a] AWLAXLAA [ei] 485 | | fis 15 me eet p04 var [5] MAX191 ~ ho] CS Oo AGY , NS Ts D3/D11 REFADJ [6 9 AD REF rt,,_ D2/D10 1 SEAL aH DY/D9 AGND [7 | 1] D7/DOUT ane 2 = : H Do/D8 BIP [a 17] D6/SCLKouyr + i Cd _ . PN | BUSY [9 | 6 | D5/SSTRB AIN- }o : 20 Ae ! Hi CS DO/D8 |10 H5| D4 MAAXIAAT: IN ae | CONTROL L419 AD [i] 15] MAX191 _?_ SARADC LOGIC or BUSY D1/D9 [11] 14 | D3/D14 = ! ty DGND D2/D10 7tLvt al t]22] 8] [r2| i3] acno penn SS PD pap Bl? DIP/SO SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAXLSV Maxim Integrated Products 1 For free samples & the latest literature: http://)www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ABSOLUTE MAXIMUM RATINGS Vpp to DGNDviececsesssssssssssessssssssssessssssssesssssssssseseeee -0.3V to +7V Vgg to AGND ..... -7V to +0.3V Vop to Vss were nee ence eee nee een en eaee nee ea ee naeeaeseasenaaeneeeenenaaneneeeneenaee 12V AGND, VREF, REFADJ to DGND.............. -0.3V to (Vpp + 0.3V) AIN+, AIN-, PD to Veggeesssssssssssesssseeseseeseese -0.3V to (Vpp + 0.3V) CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (Vpp + 0.3V) BUSY, DO-D7 to DGND viesesccsssssttstesesssseee -0.3V to (Vpp + 0.3V) Continuous Power Dissipation (T, = +70C) Narrow Plastic DIP (derate 13.33mW/C above +70C)....1067mW Wide SO (derate 11.76mMW/C above +70C) .o.ceceseeseae 941mW Narrow CERDIP (derate 12.50mW/C above +70C) ........ 1000mW Operating Temperature Ranges MAX191 Cece cece ne eane sates ee nee neeieennneney 0C to +70C MAX191 Fo eee e een eeeeennenneee nanan -40C to +85C MAX191_M__ oo. eee 55C to +125C Storage Temperature Range... 65C to + 160C Lead Temperature (soldering, 10SC)........ cece +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vpp = 5V 5%, Ves = OV or -5V t5%, fox = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = OV, slow-memory mode, internal-reference mode, reference compensation modeexternal, synchronous operation, Figure 6, Ta = Tryin to Tax, unless otherwise noted.) (Note 1) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS DC ACCURACY (Note 2) Resolution 12 Bits . . MAX191A +1/2 Integral Nonlinearity INL LSB MAX191B +1 Differential Nonlinearity DNL No missing codes over temperature +1 LSB MAX191A +1 Offset Error LSB MAX191B +2 . MAX191A +2 Gain Error (Note 3) LSB MAX191B +3 Gain-Error Tempco (Note 4) Excludes internal-reference drift +0.2 ppm/c DYNAMIC ACCURACY (sample rate = 100kHz, VIN = 4Vp-p) pen alto-Nolse plus Distortion SINAD 1kHz input signal, Ta = +25C 70 dB Total Harmonic Distortion : : 1kH t I, Ta = +25C - (up to the 5th Harmonic) THD Zinpmr signals want 80 dB Spurious-Free Dynamic Range SFDR 1kHz input signal, Ta = +25C 80 dB CONVERSION RATE . . Synchronous CLK (12 to 13 CLKs) 7.50 8.125 Conversion Time (Note 5) tconv HS Internal CLK, CL = 120pF 6 12 18 Track/Hold Acquisition Time 2 ys Aperture Delay 25 ns Aperture Jitter 50 ps External Clock Frequency f Range (Note 6) CLK 0.1 1.6 MHz MAXUMLow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (Vpp = 5V 5%, Veg = OV or -5V t5%, fo. ~ = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = OV, slow-memory mode, internal-reference mode, reference compensation modeexternal, synchronous operation, Figure 6, Ta = Tryin to Tax, unless otherwise noted.) (Note 1) MAXIM PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS ANALOG INPUT Input Voltage Range (Note 7) Vss Vpp V Input Leakage Current Vin = Vss to Vop +10 pA Input Capacitance (Note 6) 45 80 pF Small-Signal Bandwidth 2 MHz INTERNAL REFERENCE VREF Output Voltage Ta = +25C 4.076 4.096 4.116 V MAX191_C 50 VREF Output Tempco (Note 8) MAX191_E 60 ppm/C MAX191_M 80 Output Current Capability (Note 9) Ta = +25C 2 mA Load Regulation Ta = +25C, lout = OMA to 2mA 4 mV Output Short-Circuit Current 18 mA Capacitive Load Required Reference compensation modeexternal 4.7 PF Power-Supply Rejection Vop = +5%, Vgg = +5% +300 HV (Note 10) Adjustment Range -60 30 mV REFADJ Disable Threshold 4.5 Vv REFADJ Output Voltage 2.4 Vv REFADJ Input Current REFADJ = 5V 60 pA REFERENCE INPUT Input Voltage Range External-reference mode 2.5 5.0 Vv Input Current External-reference = 5V 1 mA Input Resistance External-reference mode 5 10 kQ LOGIC INPUTS Input Low Voltage Vit CS, RD, CLK, HBEN, PAR, BIP 0.8 V Input High Voltage Vin CS, RD, CLK, HBEN, PAR, BIP 2.4 Vv Input Current lin Vin = OV to Vop +10 pA PD = high/float +200 Input Current CLK lin pA PD = low +0.1 Input Capacitance (Note 6) Cin 10 pF PD Input Low Voltage Vit 0.5 V PD Input High Voltage Vin 4.5 V PD Input Current lin PD = OV to Vpp (Note 11) +20 pA State (Note eal for Float Maximum current allowed for floating state +100 nA PD Hloating-State Voltage VeLt Reference compensation modeexternal 2.8 Vv 3 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (Vpp = 5V 5%, Vgg = OV or -5V +5%, folk = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = OV, slow-memory mode, internal-reference mode, reference compensation modeexternal, synchronous operation, Figure 6, Ta = Tryin to Tax, unless otherwise noted.) (Note 1) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX | UNITS LOGIC OUTPUTS Output Low Voltage VoL louT = 1.6mA 0.4 Vv Output High Voltage VOH louT = -200pA 4.0 Vv Three-State Leakage Current IL DO/D8-D7/DOUT +10 pA Capacitance (Note 6) Court 1S] PF POWER REQUIREMENTS Positive Supply Voltage VbbD 4.75 5.25 Vv Negative Supply Voltage Vss -6.25 0 Vv Positive Supply Current IDD hd oy en _D7/ PD = high/float 8 mA =e" PD = low 20 50 pA DOUT = OVor Vpp, -== Negative Supply Current Iss HBEN = PAR = BIP PO = highMloat 20 100 pA = OVor Vpp PD = low 1 20 Positive Supply Rejection (Note 13) FS change, VoD = 5V+5% +1/2 LSB Negative Supply Rejection (Note 13) FS change, Vss = -5V +5% +1/2 LSB TIMING CHARACTERISTICS (Figures 610) (Vpp =5V 5%, Vgg = OV or -5V +5%, Ta = Tyx tO Tax, unless otherwise noted.) (Note 14) PARAMETER SYMBOL | CONDITIONS wine =i MAX MIN. rye AX MIN ye WAX UNITS CS to RD Setup Time t 0 0 0 ns RD to BUSY Delay te CL = 50pF 120 140 160 ns Data Access Time (Note 15) t3 CL = 100pF 120 140 160 ns RD Pulse Width ta 150 150 150 ns CS to RD Hold Time t5 0 0 0 ns Bey nee 5) After te 80 100 120 ] ns Bus-Relinquish Time (Note 16) t7 100 110 120 ns HBEN to RD Setup Time tg 80 100 120 ns HBEN to RD Hold Time to 0 0 0 ns Operations (No toe) tio 200 200 200 ns Delay Between Conversions t14 2 2 2 ys Aperture Delay te Jitter < 50ps 25 ns CLK to BUSY Delay (Note 6) t13 200 230 260 ns Bee yo SSTRB 14 100 130 150 ns Fall Dolay to SSTRB tts 400 130 150 | ns 4 MAXIMLow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down TIMING CHARACTERISTICS (Figures 610) (continued) (Vpp =5V 5%, Vgg = OV or -5V 5%, Ta = Tryin tO Tyax, unless otherwise noted.) (Note 14) PARAMETER SYMBOL | CONDITIONS wine =i MAX MIN rye Or AX MIN ye WAX UNITS CS or RD Hold Time t16 10 10 10 ns CS or RD Setup Time t17 150 150 150 ns CS to DOUT Three-State tig 100 110 120 ns SCLK to SCLKouT Delay t20 160 180 200 ns SCLKouT to DOUT Delay to4 100 130 150 ns SCLK to DOUT Delay tee 240 260 280 ns SCLK to SSTRB Delay te3 260 310 350 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Performance at power-supply tolerance limits guaranteed by power-supply rejection test. VbpD = 5V, Vss = OV, FS = VREF. FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB. Gain-Error Tempco = AGE is the gain-error change from Ta = +25C to TMIN or TMAX. Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Guaranteed by design, not production tested. AIN+, AIN- must not exceed supplies for specified accuracy. VREF TC = AT, where AVREF is reference-voltage change from Ta = +25C to TMIN or TMAX. Output current should not change during conversion. This current is in addition to the current required by the internal DAC. REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V. This will typically result in a 1.7 times larger change in the REF output (Figure 19a). This current is included in the PD supply current specification. Floating the PD pin guarantees external compensation mode. VREF = 4.096V, external reference. All input control signals are specified with ty = tt = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. tg and tg are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. MAXIM 5 LOLXVNLow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Typical Operating Characteristics MAX191 CLOCK FREQUENCY POWER- DOWN SUPPLY CURRENT NEGATIVE SUPPLY CURRENT vs. TIMING CAPACITOR vs. TEMPERATURE vs. TEMPERATURE 10 5 5 Ta= 425C y = 20 20 Nw = DD 2 g 3 & 15 _, 15 G fe = i 3 g = 49 Yoo #8 ~ 40 x< a Veg =-5V g 04 z PD = ov 5 5 Isg L 0.01 0 0 0.1 1 10 60 -30 0 30 6 90 120 150 60 -30 0 30 6 90 120 150 TIMING CAPACITOR (nF) TEMPERATURE (C) TEMPERATURE (C) POSITIVE SUPPLY CURRENT vs. TEMPERATURE 1kHz FFT PLOT 10kHz FFT PLOT 35 0 w 0 % -20 fly = 1kH 7 | fin = 10kHz & ie 100K 70 fg = 100kHz 95 ar -40 SNR=72dB Z 49 SNR=71.2dB in Ty=425C a Ta=425'C a a = 20 Ee -60 E -60 8 = = -86,0dB | -90.8dB ~ 48 = -80 = 20 z -94,3dB-96.1dB-98.0dB -93.8dB z 1.0 Z -100 Z -100 05 -120 -120 0 -140 -140 60 -30 0 3 6 90 120 150 0 1 2 3 4 5 6 0 5 10 15 2 2 30 3 40 TEMPERATURE (C) FREQUENCY (kHz) FREQUENCY (kHz) 6 MAXIMLow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Pin Description PIN NAME FUNCTION __ Power-Down Input. A logic low at PD deactivates the ADConly the bandgap reference is active. A logic 1 PD high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference compensation mode. 2 Vss Negative Supply, OV to -5.25V 3 AIN+ Sampled Analog Input 4 AIN- Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section). 5 VREF Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to VppD. 6 REFADJ Reference Adjust. Connect to Vpp to use an extended reference at VREF. 7 AGND Analog Ground 8 BIP BIP = low selects unipolar mode BIP = high selects bipolar mode (see Gain and Offset Adjustment section) 9 BUSY BUSY Output is low during a conversion. 10 DO/D8 Three-State Data Outputs: LSB = DO 11 D1/D9 Three-State Data Outputs 12 DGND Digital Ground 13 D2/D10 Three-State Data Outputs 14 D3/D11 Three-State Data Outputs: MSB = D11 15 D4 Three-State Data Output 16 D5/SSTRB Three-State Data Output/Serial Strobe Output in serial mode 17 | D6/SCLKouUT | Three-State Data Output/Serial Clock Output in serial mode 18 D7/DOUT Three-State Data Output/Data Output in serial mode Read Input. In parallel mode, a low signal starts a conversion when CS and HBEN are low (memory 19 RD mode). RD also enables the outputs when CS is low. In serial mode, RD = low enables SCLKouT and SSTRB when CS is low. RD = high forces SCLKQUT and SSTRB into a high-impedance state. __ Chip-Select Input must be low for the ADC to recognize RD and HBEN inputs in parallel mode. The falling 20 CS edge of CS starts a conversion in serial mode. CS = high in serial mode forces SCLKoutT, SSTRB, and DOUT into a high-impedance state. High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result 24 HBEN into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs onto the data bus. In serial mode, HBEN = low enables SCLKQUT to operate during the conversion only, HBEN = high enables SCLKOUT to operate continuously, provided CS is low. 22 PAR Sets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode. Clock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to 23 CLK/SCLK this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal oscillator. 24 Vbb Positive Supply, +5V +5% MAXIM LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V DN 3k t CL = DG = a. High-Z to Voy and Vo) to Voy CL I DGND b. High-Z to Vo, and Vou to VoL Figure 1. Load Circuits for Access Time +5V DN : I 10pF 10pF = penn = I DGND a. Voy to High-Z b. Vo. to High-Z Figure 2. Load Circuits for Bus-Relinquish Time Detailed Description The MAX191 uses successive approximation and input track/hold (T/H) circuitry to convert an analog input sig- nal to a 12-bit digital output. Flexible control logic pro- vides easy interface to microprocessors (Ps), so most applications require only the addition of passive com- ponents. No external hold capacitor is required for the T/H. Figure 3 shows the MAX191 in its simplest opera- tional configuration. Pseudo-Differential Input The sampling architecture of the ADCs analog com- parator is illustrated in the Equivalent Input Circuit (Figure 4). A capacitor switching between the AIN+ and AIN- inputs acquires the signal at the ADCs ana- log input. At the end of the conversion, the capacitor reconnects to AIN+ and charges to the input signal. An external input buffer is usually not needed for low- bandwidth input signals (<100Hz) because the ADC = _ 24 open 4] PD Vop = 45V CLK/SCLK e | ( ST AINe PAR F22- = Fi >, __. SERAUPARALLE. CY naan | \NEFACEMCDE 5 VREF MAXIO? CS 20. uPCONTROL 4muFl4 lotr INPUTS ul uF |g 19 "Cc REFADJ ap EY te AGND p7pout #8 0.1yF = 8 IT pip be/SCLKoyr LZ ourpuT _9 Jz 16 eras | eY D5/SSTRB 10 neype on 3 11} 4/09 pep11 4 127 DenD pep1o P3 2| OV TO-5V uP DATA BUS NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK. Figure 3. Operational Diagram disconnects from the input during the conversion. In unbuffered applications, an input filter capacitor reduces conversion noise, but also may limit input bandwidth. When converting a single-ended input signal, AIN- should be connected to AGND. If a differential signal is connected, consider that the configuration is pseudo differentialonly the signal side to the input channel is held by the T/H. The return side (AIN-) must remain sta- ble within +0.5LSB (+0.1LSB for best results) with respect to AGND during a conversion. Accomplish this by connecting a 0.1pF capacitor from AIN- to AGND. Analog InputTrack/Hold The T/H enters its tracking mode when the ADC is des- elected (CS pin is held high and BUSY pin is high). Hold mode starts approximately 25ns after a conver- sion is initiated. The variation in this delay from one conversion to the next (aperture jitter) is about 50ps. Figures 6-10 detail the T/H and interface timing for the MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down AIN+ TRACK COMPARATOR 12-BIT DAC MAXIM MAX191 wt b NOTE: Cext = 120pF GENERATES 1MHz NOMINAL CLOCK Figure 4. Equivalent Input Circuit various interface modes. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. Acquisition time is cal- culated by: tacg = 10(Rg + Rin)CHotp (but never less than 2us), where Riy = 2kQ, Rg = source impedance of the input signal, and Cyo,p = 32pF (see Figure 4). Input Bandwidth The ADCs input tracking circuitry has a 1MHz typical large-signal bandwidth characteristic, and a 30V/us slew rate. It is possible to digitize high-speed transients and measure periodic signals with bandwidths exceed- ing the ADCs sample rate of 100ksps by using under- sampling techniques. Note that if undersampling is used to measure high-frequency signals, special care must be taken to avoid aliasing errors. Without ade- quate input bandpass filtering, out-of-band signals and noise may be aliased into the measurement band. Input Protection Internal protection diodes, which clamp the analog input to Vpp and Veg, allow AIN+ to swing from (Vgg - 0.3V) to (Vpp + 0.3V) with no risk of damage to the ADC. However, for accurate conversions near full scale, AIN+ should not exceed the power supplies by more than 50mV because ADC accuracy is affected when the pro- MAXIM Figure 5. Internal Clock Circuit tection diodes are even slightly forward biased. Digital Interface Starting a Conversion In parallel mode, the ADC is controlled by the CS, RD, and HBEN inputs, as shown in Figure 6. The T/H enters hold mode and a conversion starts at the falling edge of CS and RD while HBEN (not shown) is low. BUSY goes low as soon as the conversion starts. On the falling edge of the 13th input clock pulse after the conversion starts, BUSY goes high and the conversion result is latched into three-state output buffers. In seri- al mode, the falling edge of CS initiates a conversion, and the T/H enters hold mode. Data is shifted out seri- ally as the conversion proceeds (Figure 10). See the Parallel Digital-Interface Mode and Serial-interface Mode sections for details. Internal/External Clock Figure 5 shows the MAX191 clock circuitry. The ADC includes internal circuitry to generate a clock with an external capacitor. As indicated in the Typical Operating Characteristics, a 120pF capacitor con- nected between the CLK and DGND pins generates a 1MHz nominal clock frequency (Figure 5). Alternatively, an external clock (between 100kHz and 1.6MHz) can be applied to CLK. When using an exter- nal clock source, acceptable clock duty cycles are LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down NSA VNS NSS | C$. 116 j<|tom t + Xs Z +] to = Se BUSY at iconv - od b jt tconv > Figure 6. CS, RD, and CLK Synchronous Operation between 45% and 55%. Clock and Control Synchronization For best analog performance on the MAX191, the clock should be synchronized to the conversion start signals (CS and RD) as shown in Figure 6. A conversion should not be started in the 50ns before a clock edge nor in the 100ns after it. This ensures that CLK transitions are not coupled to the analog input and sampled by the T/H. The magnitude of this feedthrough can be a few millivolts. When the clock and conversion start signals are synchronized, small end-point errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these errors (which can be trimmed out) can be avoided by ensuring that the start of a con- version (RD or CS falling edge) does not occur close to a clock transition (Figure 6), as described above. Parallel Digital-Interface Mode Output-Data Format The data output from the MAX191 is straight binary in the unipolar mode. In the bipolar mode, the MSB is inverted (see Figure 22). The 12 data bits can be out- put either in two 8-bit bytes or as a serial output. Table 1 shows the data-bus output format. A 2-byte read uses outputs D7-DO. Byte selection is controlled by HBEN. When HBEN is low, the lower 8 bits appear at the data outputs. When HBEN is high, the upper 4 bits appear at DO-D3 with the leading 4 bits low in locations D4D7. Timing and Control Conversion-start and data-read operations are con- trolled by the HBEN, CS, and RD digital inputs. A logic low is required on all three inputs to start a conversion, and once the conversion is in progress it cannot be 10 restarted. BUSY remains low during the entire conver- sion cycle. The timing diagrams of Figures 7-10 outline two paral- lel-interface modes and one serial mode. Slow -Memory Mode In slow-memory mode, the device appears to the pP as a slow peripheral or memory. Conversion is initiated with a read instruction (see Figure 7 and Table 2). Set the PAR pin high for parallel interface mode. Beginning with HBEN low, taking CS and RD low starts the con- version. The analog input is sampled on the falling edge of RD. BUSY remains low while the conversion is in progress. The previous conversion result appears at the digital outputs until the end of conversion, when BUSY returns high. The output latches are then updat- ed with the newest results of the 8 LSBs on D7-D0. A second read operation with HBEN high places the 4 MSBs, with 4 leading Os, on data outputs D7-DO. The second read operation does not start a new conversion because HBEN is high. ROM Mode As in slow-memory mode, D7D0 are used for 2-byte reads. A conversion starts with a read instruction with HBEN and CS low. The 1/H samples the input on the falling edge of RD (see Figure 8 and Table 3). PAR is set high. At this point the data outputs contain the 8 LSBs from the previous conversion. Two more read operations are needed to access the conversion result. The first occurs with HBEN high, where the 4 MSBs with 4 leading Os are accessed. The second read, with HBEN low, out- puts the 8 LSBs and also starts a new conversion. Figure 9 and Table 4 show how to read output data within one conversion cycle without starting another conversion. Trigger the falling edge of a read on the ris- MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN } tg cs mi, < aad q J {| }~<t- ly t> ft \ > > | al lg tconv <a_|__@ tio | |< tio } ttt a X\ 13 oo | 7 - i? ~<a * ee ts OLD DATA ' NEW DATA f ~~ NEWDATA }__ D7-D0 | D7-D0 - D11-D8 qT I BUSY DATA tia TRACK INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High. Figure 7. Slow-Memory Mode Timing HBEN f- tg < to eet tg r| ig |< tg > | to r| th ty | ob be | th ~< t te | | ot [ t t | t a, KS a, re} ip |~<F !corrv e a4 t19 | fo |< BUSY / t4. _ : | | y | (3 |< | 7 -| 13 [~<- | ty T| 3 |< | 7 DATA _ OLD DATA \____{ NEW DATA >____H NEW DATA - D7-D0 D11-D8 N D7-D0 _ \+~< tr t2 |~ HOLDS - ---- = TRACK INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High. Figure 8. ROM Mode Timing MAXIM " LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN ig >| }at ty ig VI NIVS ANI NINN NNN INI NIN I _ I cs ty }<_ ty o] N | a ee _ te) 1 cow, > }<e tio >] BUSY f Saal _+ 7 OLD DATA DATA Dy_DO et IS HODY - ----- 2 Rk I INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion HOLD j TRACK = KS NY YY NO Saad too }~<} THRESTA | t20 i290 4 THREE STATE SCLKOUT yy -< t7 - tie ~<? \ t H et to3 a ee # {03 THREE STATE SSTRB ~ . > 15 <t tg See jad 121 ve DOUT He , THREE STATE 12 >} too _ ia | Ii9 rsoikovorss sJ__ Figure 10. Serial-interface Mode Timing Diagram (RD = low) 12 MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Table 1. Data-Bus Output, CS = RD = Low PIN NAME D7/DOUT | D6/SCLKout | D5/SSTRB D4 D3/D11 D2/D10 D1/D9 DO/D8 HBEN = 0, PAR= 1, PARALLEL MODE D7 D6 D5 D4 D3 D2 D1 DO HBEN = 1, PAR= 1, PARALLEL MODE Low Low Low Low D141 D10 D9 D8 HBEN = X, PAR = 0, SERIAL MODE, RD = 0 DOUT SCLKOUT SSTRB Low Low Low Low Low HBEN = X, PAR = 0, Three- Three- SERIAL MODE, RD = 1 DOUT Stated Stated Low Low Low Low Low Note: D7/DOUT-DO/D8 are the ADC data output pins. D11-D0 are the 12-bit conversion results. D11 is the MSB. DOUT = Three-state data output. Data output in serial mode. SCLKouT = Three-state data output. Clock output in serial mode. SSTRB = Three-state data output. Strobe output in serial mode. Table 2. Slow-Memory Mode, 2-Byte Read Data-Bus Status PIN NAME D7/DOUT | D6/SCLKouT | D5/SSTRB D4 D3/D11 | D2/D10 D1/D9 DO/D8 FIRST READ (New Data) D7 D6 D5 D4 D3 D2 D1 DO SECOND READ (New Data) Low Low Low Low D11 D10 D9 D8 Table 3. ROM Mode, 2-Byte Read Data-Bus Status PIN NAME D7/DOUT | D6/SCLKout | D5/SSTRB D4 D3/D11 | D2/D10 D1/D9 DO/D8 FIRST READ (Old Data) D7 D6 D5 D4 D3 D2 D1 DO SECOND READ (New Data) Low Low Low Low D11 D10 D9 D8 THIRD READ (New Data) D7 D6 D5 D4 D3 D2 D1 DO Table 4. ROM Mode, 2-Byte Read Data-Bus Status without Starting a Conversion Cycle PIN NAME D7/DOUT | D6/SCLKout | D5/SSTRB D4 D3/D11 | D2/D10 D1/D9 D0/D8 FIRST READ (Old Data) D7 D6 D5 D4 D3 D2 D1 DO SECOND READ (New Data) D7 D6 D5 D4 D3 D2 D1 DO THIRD READ (New Data) Low Low Low Low D11 D10 D9 D8 MAXIM 13 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V 23 20 19 IF SCLK cs RD DOUT MAXIM 1 MAX191 = SCLKour HBEN SSTRB +5V J 2 B 8 CLOCK LOGIC INPUT - - == - > 9 CLEAR 74HC164 | | Qp_ -}>- Qe |-?> Qe -> aT" CLOCK CLEAR 74HC164 SCLK SCLKout NOTE: USE SSTRB TOGATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED. Figure 11. Simple Serial-to-Parallel Interface 14 MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ing edge of the first clock cycle after conversion end (when BUSY goes high). As mentioned previously, two more read operations (after BUSY goes high) are needed to access the conversion results. The only dif- ference is that now the low byte can be read first. This happens by allowing the first read operation to occur with HBEN low, where the 8 LSBs are accessed. The second read, with HBEN high, accesses the 4 MSBs with 4 leading Os. Serial-Interface Mode The serial mode is compatible with Microwire, SPI and QSPI serial interfaces. In addition, a framing signal (SSTRB) is provided that allows the devices to interface with the TMS320 family of DSPs. Set PAR low for serial mode. A falling edge on CS causes the T/H to sample the input (Figure 10). Conversion always begins on the next falling edge of SCLK, regardless of where CS occurs. The DOUT line remains high-impedance until a conversion begins. During the MSB decision, DOUT remains low (leading 0), while SSTRB goes high to indi- cate that a data frame is beginning. The data is avail- able at DOUT on the rising edge of SCLK (SCLKgyt when using an internal clock) and transitions on the falling edge. DOUT remains low after all data bits have been shifted out, inserting trailing Os in the data stream until CS returns high. The SCLKoyr signal is synchro- nous with the internal or external clock. For interface flexibility, DOUT, SCLKgy7 and SSTRB signals enter a high-impedance state when CS is high. When CS is low, RD controls the status of SCLKoy7 and SSTRB outputs. A logic low RD enables SCLKoy7 and SSTRB, while a logic high forces both outputs into a high-impedance state. Also, with CS low and HBEN high, SCLKgyr drives continuously, regardless of con- version status. This is useful with pPs that require a SCLK \ a Se i cS # DOUT 5 tt tsetup (MIN) 1 1 fscLk (MAX) == Comyrea) tsu(M) IS THE SETUP TIME REQUIRED AT THE SERIAL DATA INPUT TO THE uP. too IS THE MAXIMUM SCLK TO DOUT DELAY. Figure 12. fsCLK(MAX) is limited by the setup time required by the serial data input to the pP. MAXIM continuous serial clock. If CS and HBEN are low, SCLKouT is output only during the conversion cycle, while the converter internal clock runs continuously. This is useful for creating a simple serial-to-parallel interface without shift-register overflow (Figure 11). Maximum Clock Rate in Serial Mode The maximum SCLK rate depends on the minimum setup time required at the serial data input to the pP and the ADCs DOUT to SCLK delay (tes) (see Figure 12). The maximum fscLk is as follows: ie) cs SCK SCLK MISO; DOUT +5V MAXIM : MAX191 $s a. SPI cs cs SCK wei SCLK MISO DOUT wv MAXIM : MAX191 $s b. QSPI V0 cs SK PT SCLK Sl beg DOUT MAXIM MAX191 c. MICROWIRE cs SCLK MAXIM MAX191 DR FSR d. TMS320 SERIAL INTERFACE Figure 13. Common Serial-Interface Connections to the MAX191 15 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down fsciK(MAX) = (1/2) x 1/ (tsu(M) + t22) where tg,(M) is the minimum data-setup time re- quired at the serial data input to the pP. For example, Motorolas MC68HC11A8 data book specifies a 100ns minimum data-setup time. Using the worst case for a military grade part of ten = 280ns (see Timing Characteristics) and substituting in the above equation indicates a maximum SCLK frequency of 1.3MHz. Using the MAX191 with SPI, QSPI and MICROWIRE Serial Interfaces Figure 13 shows interface connections to the MAX191 for common serial-interface standards. SPI and MICROWIRE (CPOL=0, CPHA=0) The MAX191 is compatible with SPI, QSPI and MICROWIRE serial-interface standards. When using SPI or QSPI, two modes are available to interface with the MAX191. You can set CPOL = 0 and CPHA = 0 (Figure 14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When using CPOL = 0 and CPHA = 0, the conversion begins on the first falling edge of SCLK following CS going low. Data is available from DOUT on the rising edge of SCLK, and transitions on the falling edge. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. The first byte contains the following, in this order: a leading unknown bit (DOUT will still be high-impedance on the first bit), a 0, and the six MSBs. The second byte contains the remaining six LSBs and two trailing Os. SPI (CPOL=1, CPHA=1) Setting CPOL = 1 and CPHA = 1 starts the clock high during a read instruction. The MAX191 will shift out a leading 0 followed by the 12 data bits and three trailing Os (Figure 14b). QSPI Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the mini- mum number of clock cycles required to clock in the data (Figure 15). TMS320 Serial Interface Figure 13d shows the pin connections to interface the MAX191 to the TMS320. Since the MAX191 makes data available on the rising edge of SCLK and the TMS320 shifts data in on the falling edge of CLKR, use CLKX of the DSP to drive SCLK, and CLKX to drive the DSPs CLKR input. The inverters propagation delay also provides more data-setup time at the DSP. For example, with no inverter delay, and using ton = 280ns and fgco_k = 1.6MHz, the available setup time before the SCLK transition is: setup time = 1/ (2 X fgcik) - to = 1/ (2 x 1.66) - 280ns = 32ns This still exceeds the 13ns minimum DR setup time before the CLKR goes low (tsu(DR)), however, a generic 74HC04 provides an additional 20ns setup time (see Figure 13d). Figure 16 shows the DSP interface timing characteris- tics. The DSP begins clocking data in on the falling edge of CLKR after the falling edge of SSTRB. }?-_ 1ST BYTE READ 2ND BYTE READ + ZR + a. CPOL=0, CPHA=0 I I I I I 1 I I I I I t I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I l I I I I I I I I I \ I I I I I I I I I I 1 I I I I I I I I I I I I / | T T T T | T T T T T T T | T T T T | T | | | T I I I I I I I I 1 I 1 I I I I I I 1 I 1 I I 1 I I I I I I I I I I I I I I I I I I I I I I I HIGH-Z Y v I I I I I I I I I I I I I Y I Y I HIGH-Z pour HORN ton EXCH py X ps X py X ps X os X 14 X os X we Ki XK iss \ suk NP NAP NPN NANA NANA NANNY NS NS NSN STN 1 1 1 I I I I I I I I I / T T T I I I I I I HIGH-Z y v Y YuicHz DOUT ADING/ MSBX Dio XR Do X ps X p7 KX ps KR 5 X ps X Pp KX LP Di LSB fr RO b. CPOL=1, CPHA=1 Figure 14. SPI/MICROWIRE Serial-Interface Timing 16 MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 a HIGH-Z SCLK a. CPOL = 0, CPHA =0 HIGH-Z b. CPOL =1, CPHA=1 Figure 15. QSPI Serial-interface Timing SCLK CLKR S ssTRB HIGH-Z HIGH-Z r= DOUT HIGH-Z Figure 16. TMS320 Interface Timing 17 MAXIMMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Following the data transfer, the DSP receive shift regis- ter (RSR) contains a 16-bit word consisting of the 12 data bits, MSB first, followed by four trailing Os. Applications Information Power-On Initialization When the +5V power supply is first applied to the MAX191, perform a single conversion to initialize the ADC (the BUSY signal status is undefined at power-on). Disregard the data outputs. Power-Down Mode In some battery-powered systems, it is desirable to power down or remove power from the ADC during inactive periods. To power down the MAX191, drive PD low. In this mode, all internal ADC circuitry is off except the reference, and the ADC consumes less than 50UA max (assuming all signals CS, RD, CLK, and HBEN are static and within 200mV of the supplies). Figure 17 shows a practical way to drive the PD pin. If using inter- MAXIM MAX191 a. INTERNAL- REFERENCE COMPENSATION MODE MAXIM MAX191 1} |> PD OPEN- DRAIN BUFFER b. EXTERNAL-REFERENCE COMPENSATION MODE nal reference compensation, drive PD between Vpp and DGND with a uP I/O pin or other logic device (Figure 17a). For external-reference compensation mode, use the circuit in Figure 17b to drive PD between DGND and the floating voltage of PD. An alternative is to drive PD with three-state logic or a switch, provided the off leakage does not exceed 100nA. Internal Reference The internal 4.096V reference is available at VREF and must be bypassed to AGND with a 4.7yF low-ESR capacitor (less than 1/2Q) in parallel with a 0.1pF capaci- tor, unless internal-reference compensation mode is used (see the Internal Reference Compensation section). This minimizes noise and maintains a low reference impedance at high frequencies. The reference output can be disabled by connecting REFADJ to Vpp when using an external reference. Reference-Compensation Modes Power-down performance can be optimized for a given conversion rate by selecting either internal or external reference compensation. Internal Compensation The connection for internal compensation is shown in Figure 18a. In this mode, the reference stabilizes quick- ly enough so that a conversion typically starts within 35us after the ADC is reactivated (PD pulled high). In this compensation mode, the reference buffer requires longer recovery time from SAR transients, therefore requiring a slower clock (and conversion time). With internal reference compensation, the typical conversion time rises to 25us (Figure 18b). Figure 18c illustrates the typical average supply current vs. conversion rate, Le VREF MAXIM MAX191 0.1 uF i REFADJ = Figure 17. Drive Circuits for PD Pin 18 Figure 18a. Internal-Compensation Mode Circuit MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down VREF 15us 20us 25us Lf al lo 10,000 A 2 S Sa SUPPLY CURRENT (11 3 Qo 10 50 200 tk 5k 20k 100k CONVERSIONS PER SECOND Figure 18b. Low Average-Power Mode Operation (internal Compensation) which can be achieved using power-down between conversions. External Compensation Figure 19a shows the connection for external compensa- tion with reference adjustment. In this mode, an external 4.7uUF capacitor compensates the reference output amplifier, allowing for maximum conversion speed and lowest conversion noise. However, when reactivating the ADC after power-down, the reference takes typically 2ms to fully charge the 4.7uF capacitor, so more time is required before a conversion can start (Figure 19b). Thus, the average current consumed in power-up/power- down operations is higher in external compensation mode than in internal compensation mode. Gain and Offset Adjustment Figure 20 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 22 shows the bipolar I/O transfer function. Code transitions occur halfway between successive integer LSB values. Note that 1LSB = 1.00mV (4.096V/4096) for unipolar operation and 1LSB = 1.00mV ((4.096V/2 - -4.096V/2)/4096) for bipolar operation. Figures 19a and 21a show how to adjust the ADC gain in applications that require full-scale range adjustment. The connection shown in Figure 21a provides +0.5% for +20LSBs of adjustment range and is recommended for applications that use an external reference. On the other hand, Figure 19a is recommended for applica- tions that use the internal reference, because it uses fewer external components. lf both offset and full scale need adjustment, the circuit in Figure 21b is recommended. For single-supply MAXIM Figure 18c. Average Supply Current vs. Conversion Rate, Powering Down Between Conversions ] PD VREF MAAXIAM MAX191 O.1yF | PEFADU Figure 19a. External-Compensation Mode with Internal Reference Adjustment Circuit ADCs, it is virtually impossible to null system negative offset errors. However, the MAX191 input configuration is pseudo-differentialonly the difference in voltage between AIN+ and AIN- will be converted into its digital representation. By applying a small positive voltage to AIN-, the 0 input voltage at AIN+ can be adjusted to above or below AIN- voltage, thus nulling positive or negative system offset errors. RQ and R10 can be removed for applications that require only positive sys- tem errors to be nulled. To trim the offset error of the MAX191, apply 1/2LSB to the analog input and adjust R6 so the digital output code changes between 000 (hex) and 001 (hex). To adjust full scale, apply FS - 1 1/2LSBs and adjust R2 until the output code changes 19 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down OPEN CIRCUIT (FLOAT) PD 1 1 | 1 VRE ' pg! 2ms 200ms I >| ee 12.5us | Figure 19b. Low Average-Power Mode Operation (External Compensation) between FFE (hex) and FFF (hex). Because interaction occurs between adjustments, offset should be adjusted before gain. For an input gain of two, remove R7 and R8. The MAX191 accepts input voltages from AGND to Vpp while operating from a single supply, and Vss to VppD when operating from dual supplies. Figure 22 shows the bipolar input transfer function with AIN- connected to midscale for single-supply operation and connected to GND operating from dual supplies. When operating from a single supply, the MAX191 can be configured for bipolar operation on its pseudo-differential input. Instead of using AIN- as an analog input return, AIN- can be set to a different positive potential voltage above ground (BIP pin is set high). The sampled ana- log input (AIN+) can swing to any positive voltage above and below AIN-, and the ADC performs bipolar conversions with respect to AIN-. When operating from dual supplies, the MAX191 full-scale range is from -VREF/2 to +VREF/2. Digital Bus Noise If the data bus connected to the ADC is active during a conversion, crosstalk from the data pins to the ADC comparator may generate errors. Slow-memory mode avoids this problem by placing the uP in a wait state during the conversion. In ROM mode, if the data bus is active during the conversion, it should be isolated from the ADC using three-state drivers. The ADC generates considerable digital noise in ROM mode when RD or CS go high and the output data dri- vers are disabled after a conversion has started. This noise can cause large errors if it occurs when the SAR latches a comparator decision. To avoid this problem, 20 OUTPUT FULL-SCALE CODE TRANSITION t1..0411 \ 11...110 11. .101 | | | Y | | FS = VREF | Y FS iLsp- 5S. 7096 00...011 4 ] | 00...010 T 00... 001 | oo...o9 L-by 4 4 | 4 5 0 1 2 8 4 FS AIN INPUT VOLTAGE (LSB) FS-LSB Figure 20. Unipolar Transfer Function TO AIN+ Figure 21a. Trim Circuit for Gain (0.5%) RD and CS should be active for less than one clock cycle. If this is not possible, RD or CS should go high at the rising edge of CLK, since the comparator output is always latched on falling edges of CLK. Layout, Grounding, Bypassing Use printed circuit boards for best system performance. MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down R7 MAMXIAA 10k MAX480 as af AIN+ Ot... 114 Ot... 110 MAXIM MAX191 |] po-D11 00... 010 00... 001 00... 000 W1...114 11... 110 11... 101 10...001 10... 000 AIN- SINGLE SUPPLY (aIN- e) 2 DUAL SUPPLY - AIN- =0V > * CONNECT AIN- TO AGND WHEN USING DUAL SUPPLIES Figure 21b. Offset (+10mV) and Gain (41%) Trim Circuit Figure 22. Bipolar Transfer Function Wire-wrap boards are not recommended. Board layout should ensure that digital- and analog-signal lines are separated from each other. Do not run analog and digi- tal (especially clock) lines parallel to one another, or SUPPLIES digital lines underneath the ADC package. Figure 23 shows the recommended system ground connections. Establish a single-point ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND Sn to it. No other digital-system ground should be con- nected to this single-point analog ground. The ground return to the power supply for this star ground should be low impedance and as short as possible for noise- free operation. +5V BV GND High-frequency noise in the VDD power supply may Vpp AGND Vgg DGND } | +5V DGND affect the high-speed comparator in the ADC. Bypass DIGITAL these supplies to the single-point analog ground with dot CIRCUTRY * OPTIONAL Figure 23. Power-Supply Grounding Connection MAXIM 21 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 0.01pF and 10uF bypass capacitors. Minimize capaci- tor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10 resistor can be connected as a lowpass filter to filter out supply noise (Figure 23). Dynamic Performance High-speed sampling capability and throughput make the MAX191 ideal for wideband signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques guarantee the ADC's dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this involves applying a low-distortion sine wave to the ADC input and recording the digital conversion results for a speci- fied time. The data is then analyzed using an FFT algo- rithm, which determines its spectral content. Conversion errors are then seen as spectral elements outside the fundamental input frequency. FFT plots are shown in the Typical Operating Characteristics. ADCs have traditionally been evaluated by specifica- tions such as zero and full-scale error, integral nonlin- earity (INL), and differential nonlinearity (DNL). Such parameters are widely accepted for specifying perfor- mance with DC and slowly varying signals, but are less useful in signal-processing applications where the ADCs impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other A/D output signals, except signal harmonics. Signal-to-Noise + Distortion ratio (SINAD) is the same as the SNR, but includes sig- nal harmonics. 22 The theoretical minimum A/D noise is caused by quan- tization error and is a direct result of the ADCs resolu- tion: SNR = (6.02n + 1.76) dB, where n is the number of bits of resolution. 74dB is the SNR of a perfect 12-bit ADC. By transposing the equation that converts resolution to SNR we can compute the effective resolution or the effective number of bits the ADC provides from the measured SNR: n= (SNR -1.76)/6.02 Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal (in the frequen- cy band above DC and below one-half the sample rate) to the fundamental itself. This expressed as: THD = 20log [ V(Vo2 + Vg2 + V42 + Ve2 +... + Va2) Mi] where V1 is the fundamental RMS amplitude and Ve to Vn are the amplitudes of the 2nd through nth harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the funda- mental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input fre- quency. But if the ADC is exceptionally linear, it can occur at a random peak in the ADCs noise floor. Opto-lsolated A/D Interface Many industrial applications require isolation to prevent excessive current flow where ground disparities exist between the ADC and the rest of the system. In Figure 24, a MAX250 and four 6N136 opto-couplers create an MAXIMALow-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 5V Ty 602117970 9 (SCHOTT) Tt. | Dt 100nF_L+ I 14 Voc I 13 1 be IC2.3 HCPL2630 (QUALITY TECHNOLOGIES) 8 , ' 1k VN I | Q ul Lt "k ! 2 2N3906 Te Our 9 | 10 ? 18 | DouT J I ; IC tucmes | -AVIAXKLAVI OUTPUTS IC; 1k MAX250 4 an |3 ik ; VVV_* IN 12 11 6 | Qe | ; 3 2N3906 16 L|4 SSTFB AIN ! I MAXAXLSVI ' 5 ; IC5 spon LL MAX191 1 1k ! AKA 1 8 Hen [2 4 | 3 2 | 1k 7 20 | _ | 19 | I cs RD IC3 | 22 TTLICMOS ko PAR INPUTS AKA ! ap -2 I 5 6 3 iy 8 23 | clk I | ; 5) vpeF 7 EN GND i 4.7yF OtnFt AGND 8 7 5 6 REFADJ ISOLATION VV ~ BARRIER otwroe Veg DGND oe Figure 24. Isolated Data-Acquisition Circuit MAXIM 23 LOLXVNMAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Chip Topography CLK/SCLK PAR a a la > VREF REFADJ 0.198" AGND (5.0292mm) D7/DOUT D6/SCLKOUT BIP a cc Ee n wn 9 a 0.142" (3.6065mm) SUBSTRATE CONNECTED TO Vpp a r I a Eon a wd Ti ob 3. CONTPOLLING Bhs a MILLIMETER 4, MEET JEDEC IN ABOVE TABLE 5. CIMILIAP TO JEDEC MO-0534E EPA ee 24 Package Information MAXIMA