FUJITSU SEMICONDUCTOR

In addition, A 32-bit accumulator is built in to enable long word processing.

• 16-bit input capture (4 channels)

Detects rising, falling, or both edges.

Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.

• 16-bit reload timer (2 channels)

16-bit reload timer operation (select toggle output or one-shot output)

Event count function selection provided

• Clock timer (main cloc k)

Operates directly from oscillator clock.

Compensates for oscillator deviation

Read/write enabled second/minute/hour register

• 16-bit PPG (3 channels)

Output pins (3) , external trigger input pin (1)

• Delay interrupt

10-bit or 8-bit resolution × 8 channels (input multiplexed)

• UART (2 channels)

Full duplex double buffer type

Internal timer can be selected as clock (16-bit reload timer 0)

Asynchronous : 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps, 62500 bps, 500000 bps

Synchronous : 500 Kbps, 1Mbps, 2Mbps (at fCP = 16 MHz)

Receiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masks

Supports up to 1 Mbps

CAN WAKEUP function (connects RX internally to INT0)

Segment driver and command driver with direct LCD panel (display) drive capability

• Low voltage/Program Looping detect reset *2

Automatic reset when low voltage is detected

Program Looping detection function

• Stepping motor controller (4 channels)

• Input/output ports

Push-pull output and Schmitt trigger input

Programmable in bit units for input/output or peripheral signals.

•Flash memory

Supports automatic programming, Embeded AlgorithmTM, write/erase/erase pause/er ase resume instructions

Minato Electronics flash writer

Boot block configuration

* : When used with evaluation pod MB2145-507, use DIP switch S2 setting. For details see the MB2145-507

*1 : Under development

(TOP VIEW)

(FPT-100P-M06)

78 80 X0A A

Low speed oscillator input pin. If no oscillator is connected, apply

pull-down processing.

83 85

SIN0 UART ch.0 serial data input pin.

73 75 P55 GGeneral purpose output port.

RX0 CAN interface 0 RX input pin.

74 76

General purpose input output port.

SGO Sound generator SG0 output pin.

76 78 P57 GGeneral purpose input output port.

SGA Sound generator SGA output pin.

28 to 31 30 to 33 V0 to V3 LCD controller /driver reference power supply pins.

56, 66 58, 68 DVCC High current output buffer with dedicated power supply input pins

(pin numbers 54-57, 59-62, 64-67, 69-72) .

small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address,

so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example

recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH.

MB90428G (A) FE0000H001900H

• Other than CAN Interface

0AH to

A/D converter

2CHPPG1 control status register lower PCNTL1 R/W 16-bit PPG1 0 0 0 0 0 0 0 0

2DHPPG1 control status register higher PCNTH1 R/W 0 0 0 0 0 0 0 -

3CH (Disabled)

3DHClock division control register 0 CDCR0 R/W Prescaler 0 - - - 0 0 0 0

5CHFrequency data register SGFR R/W XXXXXXXX

5DHAmplitude data register SGAR R/W 0 0 0 0 0 0 0 0

6CHLCDC control register lower LCRL R/W LCD controller/

6DHLCDC control register higher LCRH R/W 0 0 0 0 0 0 0 0

1FF2HROM correction address 2 PADR0 R/W XXXXXXXX

1FF3HROM correction address 3 PADR1 R/W XXXXXXXX

1FF4HROM correction address 4 PADR1 R/W XXXXXXXX

1FF5HROM correction address 5 PADR1 R/W XXXXXXXX

392CHPPG1 duty setting register PDUT1 W XXXXXXXX

395CH- - - XXXXX

395DHSecond data register WTSR R/W - - XXXXXX

395EHMinute data register WTMR R/W - - XXXXXX

395FHHour data register WTHR R/W - - - XXXXX

398BH- - - - - - XX

398CHPWM1 select register 1 PWS11 R/W - - 0 0 0 0 0 0

398DHPWM2 select register 1 PWS21 R/W - 0 0 0 0 0 0 0

398FH (Disabled)

3990HPWM1 compare register 2 PWC12 R/W

controller 2

3991H- - - - - - XX

“-” initial value undetermined (none)

• Write/read symbols :

“R/W” read/write enabled

“R” read only

3998HPWM1 compare register 3 PWC13 R/W

399CHPWM1 select register 3 PWS13 R/W - - 0 0 0 0 0 0

399DHPWM2 select register 3 PWS23 R/W - 0 0 0 0 0 0 0

3EFFH (Disabled)

00004AH00007AHRemote request receiving register RRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00004BH00007BH

00004CH00007CHReceiving overrun register ROVRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

00004DH00007DH

00004EH00007EHReceiving interrupt enable register RIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C0AH003D0AHTransmission RTR register TRTRR (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C0BH003D0BH

003C0CH003D0CHRemote frame receiving wait register RFWTR (R/W) XXXXXXXX XXXXXXXX

003C0DH003D0DH

003C0EH003D0EHTransmission interrupt enable register TIER (R/W) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

003C0FH003D0FH

to P07/PPG1

Peripheral function 

Peripheral function SEG13 SEG12 

Peripheral function 

Peripheral function SGA SGO RX0 TX0

Peripheral function PWM2M1 PWM2P1 PWM1M1 PWM1P1

P87/PWM2M3 General purpose I/O port 

Peripheral function 

INT3 INT2 INT1 INT0 

• Time base timer : 18-bit timer, interval interrupt control circuit

other operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCS

The clock timer provides functions including a clock source for the watchdog timer, a sub clock base oscillator

stabilization wait timer, and an interval timer to generate an interrupt at fix ed intervals . Note that the cloc k timer

uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.

•Block Diagram

This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.

In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set count

value is reloaded and count operation continues. The function can be used as an interval timer by generating

an interrupt request at each underflow event. Also, a toggle wavefor m that inverts at each underflow can be

output from the TOT0/1 pin.

External gate input operation

form indicating that the count is in progress can be output form the TOT0 and TOT1 pins.

The real time clock timer is composed of a real time clock timer control register, sub second data register, second/

MCU oscillation frequency operates on a giv en real time clock timer operation, a 4 MHz frequency is assumed.

The real time clock timer operates as a real world timer and provides real world time information.

•Block diagram

functions, as well as master/slave type communication functions (multi-processor mode : master side only

supported) .

• Supports full bit compare, full bit mask as well as partial bet mask filtering.

Provides two receiving mask registers for either standard frame or expanded frame format.

• CAN WAKE UP function

channel built-in CAN controller.

13. Low voltage/Program Looping Detection Reset Circuit

is generated.

a width of 5 machine cycles.

* : This value assumes an oscillation clock speed of 4 MHz.

During recovery from standby mode the detection period is the maximum inter val plus 20 µs.

This circuit does not operate in modes where CPU operation is stopped.

1. Writing “0” to the LVRC register CL bit

2. Internal reset

3. Main oscillation clock stop

5. Transition to time base timer mode or clock mode