C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.4. XBR1: Port I/O CrossBar Register 1 ..........................................................................................107
Figure 15.5. XBR2: Port I/O CrossBar Register 2 ..........................................................................................108
15.3. General Purpose Port I/O...................................................................................................................109
15.4. Configuring Ports Which are not Pinned Out....................................................................................109
Figure 15.6. P0: Port0 Register .......................................................................................................................109
Figure 15.7. PRT0CF: Port0 Configuration Register......................................................................................109
Figure 15.8. P1: Port1 Register .......................................................................................................................110
Figure 15.9. PRT1CF: Port1 Configuration Register......................................................................................110
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register......................................................................................110
Figure 15.11. P2: Port2 Register .....................................................................................................................111
Figure 15.12. PRT2CF: Port2 Configuration Register....................................................................................111
Figure 15.13. P3: Port3 Register .....................................................................................................................112
Figure 15.14. PRT3CF: Port3 Configuration Register....................................................................................112
Table 15.2. Port I/O DC Electrical Characteristics..........................................................................................112
16. SMBus / I2C Bus................................................................................................................ 113
Figure 16.1. SMBus Block Diagram ...............................................................................................................113
Figure 16.2. Typical SMBus Configuration....................................................................................................114
16.1. Supporting Documents......................................................................................................................114
16.2. Operation...........................................................................................................................................115
Figure 16.3. SMBus Transaction.....................................................................................................................115
16.3. Arbitration .........................................................................................................................................116
16.4. Clock Low Extension ........................................................................................................................116
16.5. Timeouts............................................................................................................................................116
16.6. SMBus Special Function Registers....................................................................................................116
Figure 16.4. SMB0CN: SMBus Control Register ............................................................................................118
Figure 16.5. SMB0CR: SMBus Clock Rate Register......................................................................................119
Figure 16.6. SMB0DAT: SMBus Data Register .............................................................................................120
Figure 16.7. SMB0ADR: SMBus Address Register .......................................................................................120
Figure 16.8. SMB0STA: SMBus Status Register................................................................................... .........121
Table 16.1. SMBus Status Codes ....................................................................................................................122
17. SERIAL PERIPHERAL INTERFACE BUS.................................................................. 123
Figure 17.1. SPI Block Diagram .....................................................................................................................123
Figure 17.2. Typical SPI Interconnection........................................................................................................124
17.1. Signal Descriptions............................................................................................................................124
17.2. Operation...........................................................................................................................................125
Figure 17.3. Full Duplex Operation.................................................................................................................125
17.3. Serial Clock Timing...........................................................................................................................126
Figure 17.4. Data/Clock Timing Diagram.......................................................................................................126
17.4. SPI Special Function Registers..........................................................................................................127
Figure 17.5. SPI0CFG: SPI Configuration Register........................................................................................127
Figure 17.6. SPI0CN: SPI Control Register....................................................................................................128
Figure 17.7. SPI0CKR: SPI Clock Rate Register............................................................................................129
Figure 17.8. SPI0DAT: SPI Data Register......................................................................................................129
18. UART.................................................................................................................................. 130
Figure 18.1. UART Block Diagram ................................................................................................................130
18.1. UART Operational Modes.................................................................................................................131
Table 18.1. UART Modes ...............................................................................................................................131
Figure 18.2. UART Mode 0 Interconnect........................................................................................................131
Figure 18.3. UART Mode 0 Timing Diagram.................................................................................................131
Figure 18.4. UART Mode 1 Timing Diagram.................................................................................................132
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ........................................................................133
Figure 18.6. UART Modes 2 and 3 Timing Diagram......................................................................................134
18.2. Multiprocessor Communications.......................................................................................................135
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram.................................................................135
5 Rev. 1.7