AHM1200AJS3B - Advanced Micro Devices, Inc.

Preliminary Information

Mobile

AMD Athlon 4

Processor Model 6 CPGA Data Sheet

Publication # 24319 Rev: E

Issue Date: November 2001

Featuring:

Preliminary Information

Trademarks

AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD PowerNow!, and 3DNow!

are trademarks of Advanced Micro Devices, Inc.

HyperTransport is a trademark of the HyperTransport Technology Consortium.

MMX is a trademark of Intel Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of

their respective companies.

The contents of this document are provided in connection with Advanced

Micro Devices, Inc. (“AMD”) products. AMD makes no representations or

warranties with respect to the accuracy or completeness of the contents of

this publication and reserves the right to make changes to specifications and

product descriptions at any time without notice. No license, whether express,

implied, arising by estoppel or otherwise, to any intellectual property rights

is granted by this publication. Except as set forth in AMD’s Standard Terms

and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims

any express or implied warranty, relating to its products including, but not

limited to, the implied warranty of merchantability, fitness for a particular

purpose, or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for use

as components in systems intended for surgical implant into the body, or in

other applications intended to support or sustain life, or in any other applica-

tion in which the failure of AMD’s product could create a situation where per-

sonal injury, death, or severe property or environmental damage may occur.

AMD reserves the right to discontinue or make changes to its products at any

time without notice.

Table of Contents iii
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
1.1 Processor Microarchitecture Summary  . . . . . . . . . . . . . . . . . . 2
2 Interface Signals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
2.1 Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Push-Pull (PP) Drivers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6
3 Logic Symbol Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
4 Power Management   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4.1 Power Management States   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FID_Change State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Processor Performance States and the FID_Change 
Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 18
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 Clock Control   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 SYSCLK Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5 Special Cycles  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 CPUID Support  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
6 Thermal Design  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
7 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
7.1 Conventions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Interface Signal Groupings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Soft Voltage Identification (SOFTVID[4:0])  . . . . . . . . . . . . . 35
7.4 Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 35
7.5 VCCA AC and DC Characteristics   . . . . . . . . . . . . . . . . . . . . . 36
7.6 Decoupling   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.7 Valid Voltage and Frequency Combinations . . . . . . . . . . . . . 37
7.8 VCC_CORE AC and DC Characteristics   . . . . . . . . . . . . . . . . 38

iv Table of Contents
Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001
Preliminary Information
7.9 Absolute Ratings   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.10 VCC_CORE Voltage and Current  . . . . . . . . . . . . . . . . . . . . . . 41
7.11 SYSCLK and SYSCLK# AC and DC Characteristics   . . . . . . 42
7.12 AMD Athlon System Bus AC and DC Characteristics   . . . . . 44
7.13 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 46
7.14 Open Drain Test Circuit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.15 Thermal Diode Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . 49
7.16 Reserved Pins DC Characteristics  . . . . . . . . . . . . . . . . . . . . . 52
7.17 FID_Change Induced PLL Lock Time   . . . . . . . . . . . . . . . . . . 52
8 Signal and Power-Up Requirements  . . . . . . . . . . . . . . . . . . . .  53
8.1 Power-Up Requirements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 53
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 56
8.2 Processor Warm Reset Requirements  . . . . . . . . . . . . . . . . . . 56
Mobile AMD Athlon 4 Processor Model 6 and Northbridge
Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9 Mechanical Data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  57
9.1 Introduction   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.2 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.3 Package Dimensions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10 Pin Descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
10.1 Pin Diagram and Pin Name Abbreviations  . . . . . . . . . . . . . . 61
10.2 Pin List   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3 Detailed Pin Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Athlon System Bus Pins  . . . . . . . . . . . . . . . . . . . . . . . . . 78
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKFWDRST Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKIN and RSTCLK (SYSCLK) Pins  . . . . . . . . . . . . . . . . . . . 78
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
COREFB and COREFB# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 78
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FID[3:0] Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INIT# Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 80
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NMI Pin  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table of Contents v
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 81
Scan Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SOFTVID[4:0] and VID[4:0] Pins. . . . . . . . . . . . . . . . . . . . . . . 81
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
THDA and THDC Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VREF_SYS Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ZN and ZP Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11 Ordering Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  85
11.1 Standard Mobile AMD Athlon 4 Processor Model 6 
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A  Conventions, Abbreviations, and References  . . . . . . . . . . . . . . . . . . . .  87
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

vi Table of Contents

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

List of Figures vii
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
List of Figures
Figure 1. Typical Mobile AMD Athlon™ 4 Processor Model 6 System
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Mobile AMD Athlon 4 Processor Model 6 Power Management
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SOFTVID Transition During the AMD Athlon System Bus 
Disconnect for FID_Change  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. AMD Athlon System Bus Disconnect Sequence in the Stop 
Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Exiting the Stop Grant State and Bus Connect Sequence . . . . 21
Figure 7. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Processor Connect State Diagram  . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. VCC_CORE Voltage Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 42
Figure 11. SYSCLK Waveform  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. General ATE Open Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 48
Figure 13. Signal Relationship Requirements During Power-Up 
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Mobile AMD Athlon 4 Processor Model 6 CPGA Package. . . . 59
Figure 15. Mobile AMD Athlon 4 Processor Model 6 Pin Diagram—
Topside View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 16. Mobile AMD Athlon 4 Processor Model 6 Pin Diagram—
Bottomside View  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 17. OPN Example for the Mobile AMD Athlon 4 Processor 
Model 6  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

viii List of Figures

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

List of Tables ix
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
List of Tables
Table 1. FID[4:0] SYSCLK Multiplier Combinations  . . . . . . . . . . . . . . . 25
Table 2. Processor Special Cycle Definition  . . . . . . . . . . . . . . . . . . . . . . 27
Table 3. Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4. Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5. SOFTVID[4:0] DC Characteristics  . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6. FID[3:0] DC Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. Valid Voltage and Frequency Combinations  . . . . . . . . . . . . . . 37
Table 9. VCC_CORE AC and DC Characteristics  . . . . . . . . . . . . . . . . . . 38
Table 10. Absolute Ratings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. SYSCLK and SYSCLK# DC Characteristics  . . . . . . . . . . . . . . . 42
Table 13. SYSCLK and SYSCLK# AC Characteristics  . . . . . . . . . . . . . . . 43
Table 14. AMD Athlon™ System Bus DC Characteristics  . . . . . . . . . . . . 44
Table 15. AMD Athlon System Bus AC Characteristics  . . . . . . . . . . . . . . 45
Table 16. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 46
Table 17. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 49
Table 18. Guidelines for Platform Thermal Protection of the 
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. Reserved Pins (N1, N3, and N5) DC Characteristics  . . . . . . . . 52
Table 20. FID_Change Induced PLL Lock Time  . . . . . . . . . . . . . . . . . . . . 52
Table 21. CPGA Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Dimensions for the Mobile AMD Athlon 4 Processor Model 6
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. SOFTVID[4:0] and VID[4:0] Code to Voltage Definition . . . . . 82
Table 26. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 27. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

xList of Tables

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Revision History xi
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
Revision History
Date Rev Description
November 2001 E ■Revised “Thermal Protection Characterization” on page 50.
November 2001 D
■Added the 1200 MHz speed grade with a new –50 mV transient (both AC and DC)
requirement and a 1.35 V maximum DC voltage. This change effects:
•Table 9, “VCC_CORE AC and DC Characteristics,” on page 38
•Table 11, “VCC_CORE Voltage and Current,” on page 41
•Figure 17, “OPN Example for the Mobile AMD Athlon™ 4 Processor Model 6” on
page 85
■Revised Table 16, “General AC and DC Characteristics,” on page 46 to add FID validity
timing requirement.
■Added “Open Drain Test Circuit” on page 48 and Figure 12, “General ATE Open Drain Test
Circuit” on page 48.
■Added “Thermal Protection Characterization” on page 50 and Table 18, “Guidelines for
Platform Thermal Protection of the Processor,” on page 51.
■Revised notes 7 and 8 of “Power-Up Timing Requirements” on page 54.
■Revised Table 22, “Dimensions for the Mobile AMD Athlon™ 4 Processor Model 6 CPGA
Package,” on page 58.
October 2001 C ■Revised Table 9, “VCC_CORE AC and DC Characteristics,” on page 38, and Figure 9,
“VCC_CORE Voltage Waveform” on page 39.
August 2001 B
■Updated Chapter 1, “Overview” on page 1.
■Updated Figure 13, “Signal Relationship Requirements During Power-Up Sequence” on
page 53 and supporting text in “Power-Up Timing Requirements” on page 54.
■Corrected Table 22, “Dimensions for the Mobile AMD Athlon™ 4 Processor Model 6
CPGA Package,” on page 58 and Figure 14 on page 59.
July 2001 A ■Initial Public Release

xii Revision History

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 1 Overview 1

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

1Overview

The Mobile AMD Athlon™ 4 Processor Model 6 powers the next

generation of high-performance notebook computing platforms,

delivering an unprecedented mobile computing experience.

The mobile AMD Athlon™ 4 processor model 6 provides

extremely high-performance processing power for cutting-edge

software applications, including digital content creation, digital

photo editing, digital video, image compression, video encoding

for streaming over the internet, soft DVD, commercial 3D

modeling, workstation-class Computer-Aided Design (CAD),

commercial desktop publishing, and speech recognition. It also

offers the scalability and “peace-of-mind” reliability that IT

managers and business users require for enterprise computing.

This processor incorporates AMD PowerNow!™ technology, an

advanced power management solution that provides

performance-on-demand while extending battery life.

This processor features a seventh-generation microarchitecture

with an integrated L2 cache that supports the growing

processor and system bandwidth requirements of emerging

software, graphics, I/O, and memory technologies. The

high-speed execution core of the processor includes multiple

x86 instruction decoders, a dual-ported 128-Kbyte split

level-one (L1) cache, a 256-Kbyte L2 integrated cache, three

independent integer pipelines, three address calculation

pipelines, and a fully pipelined, out-of-order, floating-point

engine.

The processor microarchitecture incorporates 3DNow!™

professional technology, a high-performance cache

architecture, and the 200-MHz, 1.6 Gigabyte per second

AMD Athlon system bus. The AMD Athlon system bus

combines the latest technological advances, such as

point-to-point topology, source-synchronous packet-based

transfers, and low-voltage signaling. This combination provides

an extremely powerful, scalable bus available for any AMD

processor-based x86 processor. The AMD Athlon system bus

combines the latest technological advances, such as

point-to-point topology, source-synchronous packet-based

transfers, and low-voltage signaling, to provide a powerful,

scalable bus architecture

2Overview Chapter 1

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

This processor is binary-compatible with existing x86 software

and backwards compatible with applications optimized for

enhanced 3DNow!, MMX™, and SSE instructions. Using a data

format and Single-Instruction Multiple-Data (SIMD) operations

based on the MMX instruction model, the processor can

produce as many as four, 32-bit, single-precision floating-point

results per clock cycle, resulting in peak performance of 4.8

Gflops at 1200 MHz (fully scalable). The 3DNow! professional

technology implemented in the processor includes new integer

multimedia instructions and software-directed data movement

instructions for optimizing such applications as digital content

creation and streaming video for the internet, as well as new

instructions for Digital Signal Processing

(DSP)/communications applications.

1.1 Processor Microarchitecture Summary

The following features summarize the mobile AMD Athlon 4

processor model 6 microarchitecture:

■High performance and power saving modes specifically for

notebook designs with AMD PowerNow! technology

■The industry's first nine-issue, superpipelined, superscalar

x86 processor microarchitecture designed for high clock

frequencies

■Multiple x86 instruction decoders

■Fully pipelined floating-point execution unit that executes

all x87 (floating-point), MMX, SSE, and 3DNow! professional

technology instructions

■Three out-of-order, superscalar, pipelined integer units

■Three out-of-order, superscalar, pipelined address

calculation units

■A 72-entry instruction control unit

■Advanced dynamic branch prediction

■3DNow! professional technology with new instructions to

enable improved integer math calculations for speech or

video encoding and improved data movement for internet

plug-ins and other streaming applications

■A 200-MHz AMD Athlon system bus (scalable beyond 400

MHz) enabling leading-edge system bandwidth for data

movement-intensive applications

■High-performance cache architecture featuring an

integrated 128-Kbyte L1 cache and a 256-Kbyte L2 cache

Chapter 1 Overview 3

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

The mobile AMD Athlon 4 processor model 6 delivers

outstanding system performance in a cost-effective, low-profile

PGA package. Figure 1 shows a typical mobile AMD Athlon 4

processor model 6 system block diagram.

Figure 1. Typical Mobile AMD Athlon™ 4 Processor Model 6 System Block Diagram

SDRAM or DDR

Memory Bus

AGP

PCI Bus

LAN PC Card

ISA or LPC

USB

Dual EIDE

Docking

Controller

Modem / Audio

Programmable

Voltage Regulator

Thermal Monitor

Battery

Super I/O

Embedded Controller

Mobile

AMD Athlon™ 4

Processor Model 6

System Controller

(Northbridge)

Peripheral Bus

Controller

(Southbridge)

AMD Athlon system

bus

AGP Bus

4Overview Chapter 1

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 2 Interface Signals 5

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

2 Interface Signals

2.1 Overview

The AMD Athlon™ system bus architecture is designed to

deliver excellent data movement bandwidth for next-

generation x86 platforms as well as the high-performance

required by enterprise-class application software. The system

bus architecture consists of three high-speed channels (a

unidirectional processor request channel, a unidirectional

probe channel, and a 72-bit bidirectional data channel),

source-synchronous clocking, and a packet-based protocol. In

addition, the system bus supports several control, clock, and

legacy signals. The interface signals use an impedance

controlled push-pull, low-voltage, swing-signaling technology

contained within the Socket A socket.

For more information, see “AMD Athlon™ System Bus Signals”

on page 6, Chapter 10, “Pin Descriptions” on page 61, and the

AMD Athlon™ and AMD Duron™ Processor System Bus

Specification, order# 21902.

2.2 Signaling Technology

The AMD Athlon system bus uses a low-voltage, swing-signaling

technology, that has been enhanced to provide larger noise

margins, reduced ringing, and variable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential receivers that require a reference

voltage (VREF). The reference signal is used by the receivers to

determine if a signal is asserted or deasserted by the source.

Termination resistors are not needed because the driver is

impedance-matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input threshold.

For more information about pins and signals, see Chapter 10,

“Pin Descriptions” on page 61.

6Interface Signals Chapter 2

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

2.3 Push-Pull (PP) Drivers

The mobile AMD Athlon 4 processor model 6 supports

Push-Pull (PP) drivers. The system logic configures the

processor with the configuration parameter called SysPushPull

(1=PP). The impedance of the PP drivers is set to match the

impedance of the motherboard by two external resistors

connected to the ZN and ZP pins.

See “ZN and ZP Pins” on page 83 for more information.

2.4 AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded, point-to-

point interface with the following three point-to-point channels:

■A 13-bit unidirectional output address/command channel

■A 13-bit unidirectional input address/command channel

■A 72-bit bidirectional data channel

For more information, see Chapter 7, “Electrical Data” on page

33 and the AMD Athlon™ and AMD Duron™ Processor System

Bus Specification, order# 21902.

Chapter 3 Logic Symbol Diagram 7

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

3 Logic Symbol Diagram

Figure 2 is the mobile AMD Athlon™ 4 processor model 6 logic

symbol diagram, showing the logical grouping of the input and

output signals.

Figure 2. Logic Symbol Diagram

SDATA[63:0]#

SDATAINCLK[3:0]#

SDATAOUTCLK[3:0]#

Data

SADDIN[14:2]#

SADDINCLK#

Probe/SysCMD

SADDOUT[14:2]#

SADDOUTCLK#

VID[4:0]

FID[3:0]

A20M#

CLKFWDRST

CONNECT

COREFB

COREFB#

FERR

IGNNE#

INIT#

INTR

NMI

PROCRDY

PWROK

RESET#

SFILLVALID#

SMI#

STPCLK#

SYSCLK#SYSCLK

Clock

Voltage

Control

Frequency

Control

Legacy

Request

Mobile

AMD Athlon™ 4

Processor Model 6

SDATAINVALID#

SDATAOUTVALID#

Power

and Initialization

Management Thermal

Diode

THERMDA

THERMDC

FLUSH#

SOFTVID[4:0]

8Logic Symbol Diagram Chapter 3

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 4 Power Management 9

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

4 Power Management

This chapter describes the power management features of the

mobile AMD Athlon™ 4 processor model 6. The power

management features of the processor are compliant with the

ACPI 1.0b and ACPI 2.0 specifications and support

AMD PowerNow!™ technology.

4.1 Power Management States

The mobile AMD Athlon™ 4 processor model 6 has a variety of

operating states that are designed to support different power

management goals. In addition to the standard operating state,

the processor supports low-power Halt and Stop Grant states

and the FID_Change state. These states are used by Advanced

Configuration and Power Interface (ACPI) enabled operating

systems, for processor power management. AMD PowerNow!

software is used to control processor performance states with

operating systems that do not support ACPI 2.0-defined

processor performance state control.

Figure 3 on page 10 shows the power management states of the

processor. The figure includes the ACPI “Cx” naming

convention for these states.

10 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Figure 3. Mobile AMD Athlon™ 4 Processor Model 6 Power Management States

The following sections provide an overview of the power

management states. For more details, refer to the

AMD Athlon™ and AMD Duron™ Processor System Bus

Specification, order# 21902.

Note: In all power management states that the processor is

powered, the system must not stop the system clock

(SYSCLK/SYSCLK#) to the processor.

Working State The Working state is the state in which the processor is

executing instructions.

Halt State When the processor executes the HLT instruction, the processor

enters the Halt state and issues a Halt special cycle to the

AMD Athlon system bus. The processor only enters the low

power state dictated by the CLK_Ctl MSR if the system

Halt

Working

Execute HLT

SMI#, INTR, NMI, INIT#, RESET#

Incoming Probe

Probe Serviced

STPCLK# asserted

STPCLK# deasserted

Stop Grant

Cache Snoopable

Incoming Probe

Probe Serviced

Probe

State

STPCLK# deasserted

(Read PLVL2 register

or throttling)

C3/S1

Stop Grant

Cache Not Snoopable

Sleep

STPCLK# asserted

STPCLK#deasserted

FID_Change

Write to FidVidCtl MSR

SIP Stream and

System Bus Connect

Note: The AMD AthlonTM System Bus is connected during the following states:

1) The Probe state

2) During transitions between the Halt state and the C2 Stop Grant state

3) During transitions between the C2 Stop Grant state and the Halt state

4) C0 Working state

Software transitions

Hardware transitions

Legend

Chapter 4 Power Management 11

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

controller (Northbridge) disconnects the AMD Athlon system

bus in response to the Halt special cycle.

If STPCLK# is asserted, the processor will exit the Halt state

and enter the Stop Grant state. The processor will initiate a

system bus connect, if it is disconnected, then issue a Stop

Grant special cycle. When STPCLK# is deasserted, the

processor will exit the Stop Grant state and re-enter the Halt

state. The processor will issue a Halt special cycle when

re-entering the Halt state.

The Halt state is exited when the processor detects the

assertion of INIT#, INTR, NMI, RESET#, or SMI#. When the

Halt state is exited the processor will initiate an AMD Athlon

system bus connect if it is disconnected.

Stop Grant States The processor enters the Stop Grant state upon recognition of

assertion of STPCLK# input. After entering the Stop Grant

state, the processor issues a Stop Grant special bus cycle on the

AMD Athlon system bus. The processor is not in a low-power

state at this time, because the AMD Athlon system bus is still

connected. After the Northbridge disconnects the AMD Athlon

system bus in response to the Stop Grant special bus cycle, the

processor enters a low-power state dictated by the CLK_Ctl

MSR. If the Northbridge needs to probe the processor during

the Stop Grant state while the system bus is disconnected, it

must first connect the system bus. Connecting the system bus

places the processor into the higher power probe state. After

the Northbridge has completed all probes of the processor, the

Northbridge must disconnect the AMD Athlon system bus

again so that the processor can return to the low-power state.

During the Stop Grant states, the processor latches INIT#,

INTR, NMI, and SMI#, if they are asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor will initiate a connect of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recognized and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized. If RESET# is sampled asserted during the Stop

Grant state, the processor exits the Stop Grant state and the

reset process begins.

12 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

There are two mechanisms for asserting STPCLK#—hardware

and software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This is accomplished by asserting the THERM#

input to the Southbridge. Throttling asserts STPCLK# for a

percentage of a predefined throttling period: STPCLK# is

repetitively asserted and deasserted until THERM# is

deasserted.

Software can force the processor into the Stop Grant state by

accessing ACPI-defined registers typically located in the

Southbridge.

The operating system places the processor into the C2 Stop

Grant state by reading the P_LVL2 register in the Southbridge.

If an ACPI Thermal Zone is defined for the processor, the

operating system can initiate throttling with STPCLK# using

the ACPI defined P_CNT register in the Southbridge. The

Northbridge connects the AMD Athlon system bus, and the

processor enters the Probe state to service cache snoops during

Stop Grant for C2 or throttling.

In C2, probes are allowed, as shown in Figure 3 on page 10.

The operating system places the processor into the C3 Stop

Grant state by reading the P_LVL3 register in the Southbridge.

In C3, the operating system and Northbridge hardware enforce

a policy that prevents the processor from being probed. The

Southbridge will deassert STPCLK# and bring the processor

out of the C3 Stop Grant state if a bus master request, interrupt,

or any other enabled resume event occurs.

The Stop Grant state is also entered for the S1, Powered On

Suspend, system sleep state based on a write to the SLP_TYP

and SLP_EN fields in the ACPI-defined Power Management 1

control register in the Southbridge. During the S1 sleep state,

system software ensures no bus master or probe activity occurs.

The Southbridge deasserts STPCLK# and brings the processor

out of the S1 Stop Grant state when any enabled resume event

occurs.

Chapter 4 Power Management 13

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Probe State The Probe state is entered when the Northbridge connects the

AMD Athlon system bus to probe the processor (for example, to

snoop the processor caches) when the processor is in the Halt or

Stop Grant state. When in the Probe state, the processor

responds to a probe cycle in the same manner as when it is in

the Working state. When the probe has been serviced, the

processor returns to the same state as when it entered the

Probe state (Halt or Stop Grant state). When probe activity is

completed the processor only returns to a low-power state after

the Northbridge disconnects the AMD Athlon system bus again.

FID_Change State The FID_Change State is part of the AMD Athlon system bus

FID_Change Protocol. During the FID_Change state the

Frequency Identification (FID[4:0]) code that determines the

core frequency of the processor and Voltage Identification

(VID[4:0]) driven on the SOFTVID[4:0] pins are transitioned to

change the core frequency and core voltage of the processor.

Note: The FID[3:0] pins of the processor do not transition as part

of the FID_Change protocol.

Processor

Performance States

and the FID_Change

Protocol

The FID_Change protocol is used by AMD PowerNow! software

to transition the processor from one performance state to

another. The FID_Change protocol is also used for ACPI

2.0-compliant processor performance state control.

Processor performance states are combinations of processor

core voltage and core frequency. Processor performance states

are used in mobile systems to optimize the power consumption

of the processor (and therefore battery powered run-time)

based upon processor utilization.

Table 8, “Valid Voltage and Frequency Combinations,” on

page 37 specifies the valid voltage and frequency combinations

supported by the processor based upon the maximum core

frequency and the maximum nominal core voltage supported by

the processor.

The core frequency is determined by a 5-bit Frequency ID (FID)

code. The core voltage is determined by a 5-bit Voltage ID (VID)

code.

■Before PWROK is asserted to the processor, the VID[4:0]

outputs of the processor dictate the core voltage level of the

processor.

14 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

■After PWROK is asserted, the core voltage of the processor

is dictated by the SOFTVID[4:0] outputs. The SOFTVID[4:0]

outputs of the processor are not driven to a deterministic

value until after PWROK is asserted to the processor. The

motherboard therefore must provide a ‘VID Multiplexer’ to

drive the VID[4:0] outputs to the DC/DC converter for the

core voltage of the processor before PWROK is asserted and

drive the SOFTVID[4:0] outputs to the DC to DC converter

after PWROK is asserted.

■The FID[3:0] signals are valid after PWROK is asserted. The

chipset must not sample the FID[3:0] signals until they

become valid.

■After RESET# is deasserted, the FID[3:0] outputs are not

used to transmit FID information for subsequent software

controlled changes in the operating frequency of the

processor.

■Processor performance state transitions are required to

occur as two separate transitions. The order of these

transitions depends on whether the transition is to a higher

or lower performance state. When transitioning from a lower

performance state to a higher performance state the order

of the transitions is:

1. The FID_Change protocol is used to transition to the

higher voltage, while keeping the frequency fixed at

the current setting.

2. The FID_Change protocol is then used to transition to

the higher frequency, while keeping the voltage fixed

at the higher setting.

When transitioning from a high performance state to a

lower performance state the order of the transitions is:

1. The FID_Change protocol is used to transition to the

lower frequency, while keeping the voltage fixed at its

current setting.

2. The FID_Change protocol is then used to transition to

the lower voltage, while keeping the frequency fixed at

the lower setting.

■The processor provides two MSRs to support the

FID_Change protocol: the FidVidCtl MSR and the

FidVidStatus MSR. For a definition of these MSRs and their

use, refer to the Mobile AMD Athlon™ and Mobile

AMD Duron™ Processor BIOS Developer Application Note,

order# 24141.

Chapter 4 Power Management 15

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

FID_Change Protocol Description By Example:

Note: In any FID_Change transition only the core voltage or core

frequency of the processor is transitioned. Two FID_Change

transitions are required to transition the voltage and

frequency to a valid performance state. When the voltage is

being transitioned, the frequency is held constant by

transitioning to the same FID[3:0] as the current FID

reported in the FidVidStatus MSR.

■System software determines that a change in processor

performance state is required.

■System software executes a WRMSR instruction to write to

the FidVidCtl MSR to dictate:

•The new VID[4:0] code that will be driven to the DC/DC

converter from the SOFTVID[4:0] outputs of the

processor that selects the new core voltage level.

•The new FID[4:0] code that will be used by the processor

to dictate its new operating frequency.

•A Stop Grant Timout Count (SGTC)[19:0] value that

determines how many SYSCLK/SYSCLK# 100-MHz clock

periods the processor will remain in the FID_Change

state. This time accounts for the time that it takes for the

PLL of the processor to lock to the new core frequency

and the time that it takes for the core voltage of the

processor to ramp to the new value.

•The FIDCHGRATIO bit must be set to 1.

•The VIDC bit must be set to a 1 if the voltage is going to

be changed.

•The FIDC bit must be set to a 1 if the frequency is going

to be changed.

Writing the SGTC field to a non-zero value initiates the

FID_Change protocol.

■On the instruction boundary that the SGTC field of the

FidVidCtl MSR is written to a non-zero value, the processor

stops code execution and issues a FID_Change special cycle

on the AMD Athlon system bus.

■The FID_Change special cycle has a data encoding of

0007_0002h that is passed on SDATA[31:0].

■SDATA[36:32] contain the new FID[4:0] code during the

FID_Change special cycle. The Northbridge is required to

16 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

capture this FID[4:0] code when the FID_Change special

cycle is run.

■In response to receiving the FID_Change special cycle, the

Northbridge is required to disconnect. The Northbridge will

complete any in-progress bus cycles and then disable its

arbiter before disconnecting the AMD Athlon system bus so

that it will not initiate a AMD Athlon system bus connect

based on bus master or other activity. The Northbridge must

disconnect the AMD Athlon system bus or the system will

hang because the processor is not executing any operating

system or application code and is waiting for the

AMD Athlon system bus to disconnect so that it can

continue with the FID_Change protocol. The Northbridge

initiates an AMD Athlon system bus disconnect in the usual

manner: it deasserts CONNECT.

■The processor allows the disconnect to complete by

deasserting PROCRDY. The Northbridge completes the

disconnect by asserting CLKFWDRST.

■Once the AMD Athlon system bus has been disconnected in

response to a FID_Change special cycle, the Northbridge is

not allowed to initiate a re-connect, the processor is

responsible for the eventual re-connect.

■After the AMD Athlon system bus is disconnected, the

processor enters a low-power state where the clock grid is

ramped down by a value specified in the CLK_Ctl MSR.

■After entering the low-power state, the processor will:

•begin counting down the value that was programmed into

the SGTC field

•drive the new VID[4:0] value on SOFTVID[4:0], causing

its core voltage to transition

•drive the new FID[4:0] value to its PLL, causing the PLL

to lock to the new core frequency.

■When the SGTC count reaches zero, the processor will ramp

its entire clock grid to full frequency (the PLL is already

locked to) and signal that it is ready for the Northbridge to

transmit the new SIP (Serial Initialization Protocol) stream

associated with the new processor core operating frequency.

The processor signals this by pulsing PROCRDY high and

then low.

■The Northbridge responds to this high pulse on PROCRDY

by pulsing CLKFWDRST low and then transferring a SIP

stream as it does after PROCRDY is deasserted after the

Chapter 4 Power Management 17

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

deassertion of RESET#. The difference is that the SIP

stream that the Northbridge transmits to the processor now

corresponds to the FID[4:0] that was transmitted on

SDATA[36:32] during the FID_Change special cycle.

■After the SIP stream is transmitted, the processor initiates

the AMD Athlon system bus connect sequence by asserting

PROCRDY. The Northbridge responds by deasserting

CLKFWDRST. The forward clocks are started and the

processor issues a Connect special cycle.

■The AMD Athlon system bus connection causes the

processor to resume execution of operating system and

application code at the instruction that follows the WRMSR

to the FidVidCtl MSR that started the FID_Change protocol

and processor performance state transition.

■Figure 4 illustrates the processor SOFTVID transition

during the AMD Athlon system bus disconnect in response

to a FID_Change special cycle.

Figure 4. SOFTVID Transition During the AMD Athlon™ System Bus Disconnect for FID_Change

1.4 V

CPUCOREVCC 1.2 V

SOFTVID[4:0] from the

processor VID combination that selects 1.2 V

< 100 µ

µµ

µs

ProcRdy

Connect

ClkFwdRst

VID combination that

selects 1.4 V

The processor core frequency changes and new

SOFTVID[4:0] values are driven after the system

bus interface disconnect occurs and the

processor has entered a low power state. The

duration of the disconnect is dictated by

software programming the FidVidControl MSR in

the processor.

18 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

4.2 Connect and Disconnect Protocol

Significant power savings of the processor only occur if the

processor is disconnected from the system bus by the

Northbridge while in the Halt or Stop Grant state. The

Northbridge can optionally initiate a bus disconnect upon the

receipt of a Halt or Stop Grant special cycle. The option of

disconnecting is controlled by an enable bit in the Northbridge.

If the Northbridge requires the processor to service a probe

after the system bus has been disconnected, it must first

initiate a system bus connect.

Connect Protocol In addition to the legacy STPCLK# signal and the Halt and Stop

Grant special cycles, the AMD Athlon system bus connect

protocol includes the CONNECT, PROCRDY, and CLKFWDRST

signals and a Connect special cycle.

AMD Athlon system bus disconnects are initiated by the

Northbridge in response to the receipt of a Halt, Stop Grant, or

FID_Change special cycle. Reconnect is initiated by the

processor in response to an interrupt for Halt, STPCLK#

deassertion, or completion of a FID_Change transition.

Reconnect is initiated by the Northbridge to probe the

processor.The Northbridge contains BIOS programmable

registers to enable the system bus disconnect in response to

Halt and Stop Grant special cycles. When the Northbridge

receives the Halt or Stop Grant special cycle from the processor

and, if there are no outstanding probes or data movements, the

Northbridge deasserts CONNECT a minimum of eight SYSCLK

periods after the last command sent to the processor. The

processor detects the deassertion of CONNECT on a rising edge

of SYSCLK and deasserts PROCRDY to the Northbridge. In

return, the Northbridge asserts CLKFWDRST in anticipation of

reestablishing a connection at some later point.

Note: The Northbridge must disconnect the processor from the

AMD Athlon system bus before issuing the Stop Grant

special cycle to the PCI bus or passing the Stop Grant special

cycle to the Southbridge for systems that connect to the

Southbridge with HyperTransport™ technology.

This note applies to current chipset implementation—

alternate chipset implementations that do not require this

are possible.

Chapter 4 Power Management 19

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Note: In response to Halt special cycles, the Northbridge passes the

Halt special cycle to the PCI bus or Southbridge

immediately.

The processor can receive an interrupt after it sends a Halt

special cycle, or STPCLK# deassertion after it sends a Stop

Grant special cycle to the Northbridge but before the

disconnect actually occurs. In this case, the processor sends the

Connect special cycle to the Northbridge, rather than

continuing with the disconnect sequence. In response to the

Connect special cycle, the Northbridge cancels the disconnect

request.

The system is required to assert the CONNECT signal before

returning the C-bit for the connect special cycle (assuming

CONNECT has been deasserted).

For more information, see the AMD Athlon™ and AMD Duron™

Processor System Bus Specification, order# 21902 for the

definition of the C-bit and the Connect special cycle.

20 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Figure 5 shows STPCLK# assertion resulting in the processor in

the Stop Grant state and the AMD Athlon system bus

disconnected.

Figure 5. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State

An example of the AMD Athlon system bus disconnect

sequence is as follows:

1. The peripheral controller (Southbridge) asserts STPCLK#

to place the processor in the Stop Grant state.

2. When the processor recognizes STPCLK# asserted, it enters

the Stop Grant state and then issues a Stop Grant special

cycle.

3. When the special cycle is received by the Northbridge, it

deasserts CONNECT, assuming no probes are pending,

initiating a bus disconnect to the processor.

4. The processor responds to the Northbridge by deasserting

PROCRDY.

5. The Northbridge asserts CLKFWDRST to complete the bus

disconnect sequence.

6. After the processor is disconnected from the bus, the

processor enters a low-power state. The Northbridge passes

the Stop Grant special cycle along to the Southbridge.

Stop Grant

STPCLK#

CONNECT

PROCRDY

CLKFWDRST

PCI Bus

AMD Athlon™

System Bus

Chapter 4 Power Management 21

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Figure 6 shows the signal sequence of events that takes the

processor out of the Stop Grant state, connects the processor to

the AMD Athlon system bus, and puts the processor into the

Working state.

Figure 6. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from

the Stop Grant state and connects it to the system bus:

1. The Southbridge deasserts STPCLK#, informing the

processor of a wake event.

2. When the processor recognizes STPCLK# deassertion, it

exits the low-power state and asserts PROCRDY, notifying

the Northbridge to connect to the bus.

3. The Northbridge asserts CONNECT.

4. The Northbridge deasserts CLKFWDRST, synchronizing the

forwarded clocks between the processor and the

Northbridge.

5. The processor issues a Connect special cycle on the system

bus and resumes operating system and application code

execution.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

22 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Connect State

Diagram

Figure 7 and Figure 8 on page 23 describe the Northbridge and

processor connect state diagrams, respectively.

Figure 7. Northbridge Connect State Diagram

Condition

1 A disconnect is requested and probes are still pending.

2 A disconnect is requested and no probes are pending.

3 A Connect special cycle from the processor.

4 No probes are pending.

5 PROCRDY is deasserted.

6 A probe needs service.

7 PROCRDY is asserted.

Three SYSCLK periods after CLKFWDRST is deasserted.

Although reconnected to the system interface, the

Northbridge must not issue any non-NOP SysDC

commands for a minimum of four SYSCLK periods after

deasserting CLKFWDRST.

Action

ADeassert CONNECT eight SYSCLK periods

after last SysDC sent.

B Assert CLKFWDRST.

C Assert CONNECT.

D Deassert CLKFWDRST.

Disconnect

Pending Connect Disconnect

Requested

Reconnect

Pending

Probe

Pending 2

Disconnect

Probe

Pending 1

2/A

4/A

5/B

3/C

7/D,C

6/C 7/D

Chapter 4 Power Management 23

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Figure 8. Processor Connect State Diagram

Condition

1CONNECT is deasserted by the Northbridge (for a

previously sent Halt or Stop Grant special cycle).

2Processor receives a wake-up event and must cancel

the disconnect request.

3 Deassert PROCRDY and slow down internal clocks.

4Processor wake-up event or CONNECT asserted by

Northbridge.

5 CLKFWDRST is deasserted by the Northbridge.

6Forward clocks start three SYSCLK periods after

CLKFWDRST is deasserted.

Action

A CLKFWDRST is asserted by the Northbridge.

B Issue a Connect special cycle.*

CReturn internal clocks to full speed and assert

PROCRDY.

* The Connect special cycle is only issued after a

processor wake-up event (interrupt or STPCLK#

deassertion) occurs. If the AMD Athlon™ processor

system bus is connected so the Northbridge can

probe the processor, a Connect special cycle is not

issued at that time (it is only issued after a

subsequent processor wake-up event).

Connect

Disconnect

Pending

Disconnect

Connect

Pending 1

Connect

Pending 2

3/A

4/C

6/B

2/B

24 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

4.3 Clock Control

The processor implements a Clock Control (CLK_Ctl) MSR

(address C001_001Bh) that determines the internal clock

divisor when the AMD Athlon system bus is disconnected.

Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,

Software, and Debug Developers Guide, order# 21656, for more

details on the CLK_Ctl register.

Refer to the Mobile AMD Athlon™ and Mobile AMD Duron™

Processor BIOS Developer Application Note, order# 24141, for

more details on the CLK_Ctl register.

4.4 SYSCLK Multipliers

The processor provides two mechanisms for communicating

processor core operating frequency information to the

Northbridge. These are the processor FID[3:0] outputs and the

FID_Change special cycle. The FID[3:0] outputs specify the

core frequency of the processor as a multiple of the 100-MHz

input clock (SYSCLK/SYSCLK#) of the processor.

The FID[3:0] signals are valid after PWROK is asserted. The

chipset must not sample the FID[3:0] signals until they become

valid.The FID[3:0] outputs of the processor provide processor

operating frequency information that the Northbridge uses

when creating the SIP stream that the Northbridge sends to the

processor after RESET# is deasserted. The FID[3:0] outputs

always select a 5x SYSCLK multiplier:

FID[3:0] = 0 1 0 0

Software will use the FID_Change protocol to transition the

processor to the desired performance state.

The FID[3:0] outputs are not used as part of the FID_Change

protocol and do not change from their RESET# value during

software-controlled processor core frequency transitions.

The FID_Change special cycle is used to communicate

processor operating frequency information to the Northbridge

during software-controlled processor core voltage and

frequency (performance state) transitions. The FidVidCtl MSR

Chapter 4 Power Management 25

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

allows software to specify a 5-bit FID value during

software-controlled processor performance state transitions.

The additional bit allows transitions to lower SYSCLK

multipliers of 3x to 4x as well as all other SYSCLK multipliers

supported by the processor.

For a description of the FID_Change protocol refer to the

earlier section in this chapter.

Table 1 lists the FID[4:0] SYSCLK multiplier codes for the

processor used by software to dictate the core frequency of the

processor and the 5-bit value driven on SDATA[36:32]# by the

processor during the FID_Change special bus cycle.

Note: Only clock multipliers associated with operating frequencies

specified in the “Electrical Data” chapter are valid for this

processor.

Note: Software distinguishes the speed grade of the processor by

reading the MFID field of the FidVidStatus MSR.

Table 1. FID[4:0] SYSCLK Multiplier Combinations1

FID[4:0]2,3,5 Clock Mode SDATA[36:32]#4

00000 11x 11111

00001 11.5x 11110

00010 12x 11101

00011 12.5x 11100

00100 5x 11011

00101 5.5x 11010

00110 6x 11001

00111 6.5x 11000

Notes:

1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software

is responsible for transitioning the processor to the desired frequency.

2. Value programmed into the FidVidCtl MSR.

3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.

4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA

bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the

motherboard with a digital storage scope.

5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting

is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant

disconnect divisor of 512.

26 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

01000 7x 10111

01001 7.5x 10110

01010 8x 10101

01011 8.5x 10100

01100 9x 10011

01101 9.5x 10010

01110 10x 10001

01111 10.5x 10000

10000 3x 01111

10001 Reserved Reserved

10010 4x 01101

10011 Reserved Reserved

10100 13x 11100

10101 13.5x 11100

10110 14x 11100

10111 Reserved Reserved

11000 15x 11100

11001 Reserved Reserved

11010 16x 11100

11011 16.5x 11100

11100 17x 11100

11101 18x 11100

11110 Reserved Reserved

11111 Reserved Reserved

Table 1. FID[4:0] SYSCLK Multiplier Combinations1

FID[4:0]2,3,5 Clock Mode SDATA[36:32]#4

Notes:

1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software

is responsible for transitioning the processor to the desired frequency.

2. Value programmed into the FidVidCtl MSR.

3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.

4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA

bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the

motherboard with a digital storage scope.

5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting

is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant

disconnect divisor of 512.

Chapter 4 Power Management 27

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

4.5 Special Cycles

In addition to the special cycles documented in the

AMD Athlon™ and AMD Duron™ Processor System Bus

Specification, order# 21902, the processor supports the SMM

Enter, SMM Exit, and FID_Change special cycles.

Table 2 defines the contents of SDATA[31:0] during the special

cycles.

Table 2. Processor Special Cycle Definition

Special Cycle Contents of SDATA[31:0]

SMM Enter 0005_0002h

SMM Exit 0006_0002h

FID_Change*0007_0002h

Note:

* The new FID[4:0] taken from the FID[4:0] field of the FidVidCtl MSR is driven on

SDATA[36:32] during the FID_Change special cycle.

28 Power Management Chapter 4

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 5 CPUID Support 29

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

5 CPUID Support

The mobile AMD Athlon™ 4 processor model 6 version and

feature set recognition can be performed through the use of the

CPUID instruction, that provides complete information about

the processor—vendor, type, name, etc., and its capabilities.

Software can make use of this information to accurately tune

the system for maximum performance and benefit to users.

For information on the use of the CPUID instruction see:

■AMD Athlon™ Processor Recognition Application Note

Addendum, order# 21922

For information on additions to the CPUID instruction

functionality specific to the mobile AMD Athlon™ 4 processor

model 6 see:

■Mobile AMD Athlon™ and Mobile AMD Duron™ Processor

BIOS Developer Application Note, order# 24141

For information about the CPUID features supported by the

mobile AMD Athlon 4 processor model 6, refer to the following

documents:

■AMD Processor Recognition Application Note, order# 20734

■AMD Athlon™ Processor Recognition Application Note

Addendum, order# 21922

■AMD Athlon™ Processors BIOS Developers Application Note,

order# 21656

30 CPUID Support Chapter 5

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 6 Thermal Design 31

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

6 Thermal Design

The Mobile AMD Athlon™ 4 Processor Model 6 provides a

diode that can be used in conjunction with an external

temperature sensor to determine the die temperature of the

processor.

The diode anode (THERMDA) and cathode (THERMDC) are

available as pins on the processor.

Refer to “Thermal Diode Characteristics” on page 49 and

“THDA and THDC Pins” on page 83 for more details.

For information about the usage of this diode and thermal

design, including layout and airflow considerations, see the

Mobile System Thermal Design Guidelines, order# 24383.

Table 3 shows the thermal design power.

Table 3. Thermal Design Power

Frequency

(MHz) Nominal Voltage Thermal Design

Power1,2

850 1.40 V 22 W

900 1.40 V 24 W

950 1.40 V 24 W

1000 1.40 V 25 W

1100 1.40 V 25 W

1200 1.35 V 25 W

Notes:

1. Thermal design power represents the maximum sustained power dissipated while executing

publicly-available software or instruction sequences under normal system operation at

nominal VCC_CORE. Thermal solutions must monitor the temperature of the processor to

prevent the processor from exceeding its maximum die temperature.

2. Specified through characterization for a die temperature of 95°C.

32 Thermal Design Chapter 6

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

Chapter 7 Electrical Data 33
24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet
Preliminary Information
7 Electrical Data
7.1 Conventions
The conventions used in this chapter are as follows:
■Current specified as being sourced by the processor is
negative.
■Current specified as being sunk by the processor is positive.
7.2 Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 4  defines each group and the signals contained in each
group.
Table 4. Interface Signal Groupings
Signal Group Signals Notes
Power VID[4:0], SOFTVID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “Absolute Ratings” on 
page 40, “Soft Voltage 
Identification (SOFTVID[4:0])” on 
page 35, “VCCA AC and DC 
Characteristics” on page 36, 
“VCC_CORE AC and DC 
Characteristics” on page 38, 
“COREFB and COREFB# Pins” on 
page 78, “SOFTVID[4:0] and 
VID[4:0] Pins” on page 81, and 
“VCCA Pin” on page 83.
Frequency FID[3:0]
See “Frequency Identification 
(FID[3:0])” on page 35 and 
“FID[3:0] Pins” on page 79.
System Clocks SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and 
RSTCLK/RSTCLK#), PLLBYPASSCLK, PLLBYPASSCLK#,
See “SYSCLK and SYSCLK# AC and 
DC Characteristics” on page 42, 
“SYSCLK and SYSCLK#” on 
page 83, and “PLL Bypass and Test 
Pins” on page 80.

34 Electrical Data Chapter 7
Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001
Preliminary Information
AMD Athlon™ 
System Bus
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, 
SADDOUTCLK#, SFILLVALID#, SDATAINVALID#, 
SDATAOUTVALID#, SDATA[63:0]#, SDATAINCLK[3:0]#, 
SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT
See “AMD Athlon™ System Bus AC 
and DC Characteristics” on page 
44 and “CLKFWDRST Pin” on 
page 78.
Southbridge RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, 
STPCLK#, FLUSH#
See “General AC and DC 
Characteristics” on page 46, “INTR 
Pin” on page 80, “NMI Pin” on 
page 80, “SMI# Pin” on page 81, 
“INIT# Pin” on page 79, “A20M# 
Pin” on page 78, “FERR Pin” on 
page 79, “IGNNE# Pin” on 
page 79, “STPCLK# Pin” on 
page 83, and “FLUSH# Pin” on 
page 79.
JTAG TMS, TCK, TRST#, TDI, TDO See “General AC and DC 
Characteristics” on page 46.
Test PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2, SCANCLK1, 
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC 
Characteristics” on page 46, “PLL 
Bypass and Test Pins” on page 80, 
“Scan Pins” on page 81, and 
“Analog Pin” on page 78, 
Miscellaneous DBREQ#, DBRDY, PWROK
See “General AC and DC 
Characteristics” on page 46, 
“DBRDY and DBREQ# Pins” on 
page 79, and “PWROK Pin” on 
page 81.
Reserved 
(RSVD) Pins N1, N3, and N5
See “Reserved Pins DC 
Characteristics” on page 52, and 
“RSVD Pins” on page 81.
Thermal THERMDA, THERMDC
See “Thermal Diode 
Characteristics” on page 49 and 
“THDA and THDC Pins” on 
page 83
Table 4. Interface Signal Groupings (continued)
Signal Group Signals Notes

Chapter 7 Electrical Data 35

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

7.3 Soft Voltage Identification (SOFTVID[4:0])

Table 5 shows the SOFTVID[4:0] DC Characteristics. For more

information, see “SOFTVID[4:0] and VID[4:0] Pins” on

page 81.

7.4 Frequency Identification (FID[3:0])

Table 6 shows the FID[3:0] DC characteristics. For more

information, see “FID[3:0] Pins” on page 79.

Table 5. SOFTVID[4:0] DC Characteristics

Parameter Description Min Max

IOL Output Current Low 16 mA

SOFTVID_VOH SOFTVID[4:0] Output High Voltage – 2.625V *

Note:

* The SOFTVID pins must not be pulled above this voltage by an external pullup resistor.

Table 6. FID[3:0] DC Characteristics

Parameter Description Min Max

IOL Output Current Low 16 mA

VOH Output High Voltage – 2.625 V *

Note:

* The FID pins must not be pulled above this voltage by an external pullup resistor.

36 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.5 VCCA AC and DC Characteristics

Table 7 shows the AC and DC characteristics for VCCA. For

more information, see “VCCA Pin” on page 83.

7.6 Decoupling

See the AMD Athlon™ Processor-Based Motherboard Design

Guide, order# 24363, or contact your local AMD office for

information about the decoupling required on the motherboard

for use with the mobile AMD Athlon™ 4 processor model 6.

Table 7. VCCA AC and DC Characteristics

Symbol Parameter Min Nominal Max Units Notes

VVCCA VCCA Pin Voltage 2.25 2.5 2.75 V 1

IVCCA VCCA Pin Current 0 50 mA/GHz 2

Notes:

1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.

2. Measured at 2.5 V.

Chapter 7 Electrical Data 37

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

7.7 Valid Voltage and Frequency Combinations

Table 8 specifies the valid voltage and frequency combinations

that this processor is characterized to operate. The Maximum

Frequency column corresponds to the rated frequency of the

processor. The Maximum FID (MFID) field in the FidVidStatus

MSR is used by software to determine the maximum frequency

of the processor. Each row in the table shows the maximum

frequency allowable at the voltage specified in each column.

“Power Management States” on page 9 describes how

AMD PowerNow!™ software uses this information to

implement processor performance states.

Table 8. Valid Voltage and Frequency Combinations

Maximum Frequency VCC_CORE_NOM Voltage

1.400 V 1.350 V 1.300 V 1.250 V 1.200 V

850 MHz 850 MHz 700 MHz 600 MHz 500 MHz ≤ 500 MHz

900 MHz 900 MHz 700 MHz 600 MHz 500 MHz ≤ 500 MHz

950 MHz 950 MHz 800 MHz 700 MHz 600 MHz ≤ 500 MHz

1000 MHz 1000 MHz 800 MHz 700 MHz 600 MHz ≤ 500 MHz

1100 MHz 1100 MHz 900 MHz 800 MHz 700 MHz ≤ 600 MHz

1200 MHz N/A 1200 MHz 1000 MHz 900 MHz ≤ 800 MHz

Notes:

1. All voltages listed are nominal. See Figure 9 on page 39 for AC and DC transient voltage tolerances.

2. The “≤“ symbol indicates that the BIOS vendor can use any performance state equal to or less than the specified frequency at that

given voltage. For example, “≤ 800 MHz” means that the BIOS may use 800 MHz, 700 MHz, 600 MHz, 500 MHz, 400 MHz, or 300

MHz provided that the chipset and system support the chosen processor operating frequencies.

3. The maximum processor die temperature is 95º C for all voltage and frequency combinations.

38 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.8 VCC_CORE AC and DC Characteristics

Table 9 shows the AC and DC characteristics for VCC_CORE.

For more information, see Table 24, “Cross-Reference by Pin

Location,” on page 70 and Figure 9 on page 39.

Table 9. VCC_CORE AC and DC Characteristics

Symbol Parameter Limit in Working State2Units

VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM1100 mV

VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM1 –50 mV

VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM1 150 mV

VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM1, 3 for

processors with a maximum frequency of 1200 MHz –50 mV

VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM1, 3 for all

other processors –100 mV

tMAX_AC Maximum excursion time for AC transients 10 µs

tMIN_AC Negative excursion time for AC transients 5 µs

Notes:

1. VCC_CORE nominal values are shown in Table 8, “Valid Voltage and Frequency Combinations,” on page 37.

2. All voltage measurements are taken differentially at the COREFB/COREFB# pins.

3. Absolute minimum allowable VCC_CORE voltage, including all transients, is 1.10 V.

Chapter 7 Electrical Data 39

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Figure 9 shows the processor core voltage (VCC_CORE)

waveform response to perturbation. The tMIN_AC (negative AC

transient excursion time) and tMAX_AC (positive AC transient

excursion time) represent the maximum allowable time below

or above the DC tolerance thresholds.

Figure 9. VCC_CORE Voltage Waveform

tmin_AC

VCC_CORE_MAX_AC

tmax_AC

VCC_CORE_MAX_DC

VCC_CORE_NOM

VCC_CORE_MIN_DC

VCC_CORE_MIN_AC

ICORE_MIN

ICORE_MAX

dI /dt

40 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.9 Absolute Ratings

Do not subject the processor to conditions that exceed the

absolute ratings listed in Table 10, as such conditions may

adversely affect long-term reliability or result in functional

damage.

Table 10. Absolute Ratings

Parameter Description Min Max

VCC_CORE Mobile AMD Athlon™ 4 Processor Model 6 core supply –0.5 V VCC_CORE Max + 0.5 V

VCCA Mobile AMD Athlon 4 Processor Model 6 PLL supply –0.5 V VCCA Max + 0.5 V

VPIN Voltage on any signal pin –0.5 V VCC_CORE Max + 0.5 V

TSTORAGE Storage temperature of processor –40ºC 100ºC

Chapter 7 Electrical Data 41

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

7.10 VCC_CORE Voltage and Current

Table 11 shows the voltage and current of the processor during

normal and reduced power states.

Table 11. VCC_CORE Voltage and Current

Frequency

(MHz) Voltage Maximum ICC (Power

Supply Current) Die Temperature Notes

850

1.40 V

15.71 A

95°C

900 17.14 A

950 17.14 A

1000 17.90 A

1100 17.90 A

1200 1.35 V 18.50 A

Halt/Stop Grant C2

1.20 V

2.00 A 1, 2, 3

Stop Grant C2 1.07 A 50°C1, 2, 3, 4

Stop Grant C3/S1 0.80 A 1, 2, 3, 4

Notes:

1. See also Figure 3, “Mobile AMD Athlon™ 4 Processor Model 6 Power Management States” on page 10.

2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner

of the process, and are not representative of the typical Stop Grant current that is currently about one–third of the

maximum specified current.

3. These currents occur when the AMD Athlon system bus is disconnected and a low power ratio of 1/512 is applied to

the core clock grid of the processor. A low power ratio of 1/512 is dictated by a value of 6007_9263h programmed into

the Clock Control (CLK_Ctl) MSR,.

4. The Stop Grant current consumption is characterized and not tested.

42 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.11 SYSCLK and SYSCLK# AC and DC Characteristics

Table 12 shows the DC characteristics of the SYSCLK and

SYSCLK# differential clocks. The SYSCLK signal represents

CLKIN and RSTCLK tied together while the SYSCLK# signal

represents CLKIN# and RSTCLK# tied together.

Figure 10 shows the DC characteristics of the SYSCLK and

SYSCLK# signals.

Figure 10. SYSCLK and SYSCLK# Differential Clock Signals

Table 12. SYSCLK and SYSCLK# DC Characteristics

Symbol Description Min Max Units

VThreshold-DC Crossing before transition is detected (DC) 400 mV

VThreshold-AC Crossing before transition is detected (AC) 450 mV

ILEAK_P Leakage current through P-channel pullup to VCC_CORE –250 µA

ILEAK_N Leakage current through N-channel pulldown to VSS (Ground) 250 µA

VCROSS Differential signal crossover VCC_CORE/2

±100 mV

CPIN Capacitance * 4 12 pF

Note:

* The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.

SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.

VCROSS VThreshold-DC = 400 mV VThreshold-AC = 450 mV

Chapter 7 Electrical Data 43

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

Table 13 shows the mobile AMD Athlon 4 processor model 6

SYSCLK/SYSCLK# differential clock AC characteristics.

Figure 11 shows a sample waveform.

Figure 11. SYSCLK Waveform

Table 13. SYSCLK and SYSCLK# AC Characteristics

Symbol Description Min Max Units Notes

Clock Frequency 50 100 MHz

Duty Cycle 30% 70% –

t1Period 10 ns 1, 2

t2High Time 1.8 ns

t3Low Time 1.8 ns

t4Fall Time 2 ns

t5Rise Time 2 ns

Period Stability ± 300 ps

Notes:

1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track

the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load, must be less than 500 kHz.

2. Circuitry driving the SYSCLK and SYSCLK# inputs may purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock

generators). In no cases can the period violate the minimum specification above. SYSCLK and SYSCLK# inputs may vary from

100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz.

VCROSS

VThreshold-AC

44 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.12 AMD Athlon™ System Bus AC and DC Characteristics

Table 14 shows the DC characteristics of the AMD Athlon

system bus.

Table 14. AMD Athlon™ System Bus DC Characteristics

Symbol Parameter Condition Min Max Units Notes

VREF DC Input Reference Voltage (0.5 x VCC_CORE)

–50

(0.5 x VCC_CORE)

+50 mV 1

IVREF_LEAK_P VREF Tristate Leakage Pullup VIN=VREFNominal –100 µA

IVREF_LEAK_N

VREF Tristate Leakage

Pulldown VIN=VREFNominal +100 µA

VIH Input High Voltage VREF + 200 VCC_CORE + 500 mV

VIL Input Low Voltage –500 VREF – 200 mV

VOH Output High Voltage IOUT = –200 µA0.85*VCC_CORE VCC_CORE+500 mV 2

VOL Output Low Voltage IOUT = 1 mA –500 400 mV 2

ILEAK_P Tristate Leakage Pullup VIN= VSS

(Ground) –250 µA

ILEAK_N Tristate Leakage Pulldown VIN= VCC_CORE

Nominal +250 µA

CIN Input Pin Capacitance 4 12 pF

Notes:

1. VREF

– VREF is nominally set by a (1%) resistor divider from VCC_CORE.

– The suggested divider resistor values are 100 ohms over 100 ohms to produce a divisor of 0.50.

– Example: VCC_CORE = 1.4 V, VREF = 750 mV (1.4 x 0.50).

– Peak-to-Peak AC noise on VREF (AC) should not exceed 2% of VREF (DC).

2. Specified at T = 95°C and VCC_CORE.

Chapter 7 Electrical Data 45

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

The AC characteristics of the AMD Athlon system bus are

shown in Table 15. The parameters are grouped based on the

source or destination of the signals involved.

Table 15. AMD Athlon™ System Bus AC Characteristics

Group Symbol Parameter Min Max Units Notes

All Signals TRISE Output Rise Slew Rate 1 3 V/ns 1

TFALL Output Fall Slew Rate 1 3 V/ns 1

Forward

Clocks

TSKEW-SAMEEDGE Output skew with respect to

the same clock edge –385ps2

TSKEW-DIFFEDGE Output skew with respect to a

different clock edge –770ps2

TSU Input Data Setup Time 300 ps 3

THD Input Data Hold Time 300 ps 3

CIN Capacitance on input Clocks 4 12 pF

COUT Capacitance on output Clocks 4 12 pF

Sync

TVAL RSTCLK to Output Valid 250 2000 ps 4, 5

TSU Setup to RSTCLK 500 ps 4, 6

THD Hold from RSTCLK 1000 ps 4, 6

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its

forward clock, as measured at the package, with respect to the same clock edge.

TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of

RSTCLK.

46 Electrical Data Chapter 7

Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet 24319E — November 2001

Preliminary Information

7.13 General AC and DC Characteristics

Table 16 shows the mobile AMD Athlon 4 processor model 6 AC

and DC characteristics of the Southbridge, JTAG, test, and

miscellaneous pins.

Table 16. General AC and DC Characteristics

Symbol Parameter Description Condition Min Max Units Notes

VIH Input High Voltage (VCC_CORE/2) +

200mV VCC_CORE Max V 1, 2

VIL Input Low Voltage –300 350 mV 1, 2

VOH Output High Voltage VCC_CORE – 400 VCC_CORE +

300 mV

VOL Output Low Voltage –300 400 mV

ILEAK_P Tristate Leakage Pullup VIN= VSS (Ground) –250 µA

ILEAK_N Tristate Leakage Pulldown VIN= VCC_CORE

Nominal 250 µA

IOH Output High Current –16 mA 3

IOL Output Low Current 16 mA 3

TSU Sync Input Setup Time 2.0 ns 4, 5

THD Sync Input Hold Time 0.0 ps 4, 5

TDELAY Output Delay with respect to

RSTCLK 0.0 6.1 ns 5

Notes:

1. Characterized across DC supply voltage range.

2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.

3. IOL and IOH are measured at VOL maximum and VOH minimum, respectively.

4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

5. These are aggregate numbers.

6. Edge rates indicate the range over which inputs were characterized.

7. In asynchronous operation, the signal must persist for this time to enable capture.

8. This value assumes RSTCLK frequency is 10 ns ==> TBIT = 2*fRST.

9. The approximate value for standard case in normal mode operation.

10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.

11. Reassertions of the signal within this time are not guaranteed to be seen by the core.

12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power–Up Timing Requirements,“ for more

information.

Chapter 7 Electrical Data 47

24319E—November 2001 Mobile AMD Athlon™ 4 Processor Model 6 CPGA Data Sheet

Preliminary Information

TBIT Input Time to Acquire 20.0 ns 7, 8

TRPT Input Time to Reacquire 40.0 ns 9–13

TRISE Signal Rise Time 1.0 3.0 V/ns 6

TFALL Signal Fall Time 1.0 3.0 V/ns 6

CPIN Pin Capacitance 4 12 pF

TVALID Time to data valid 100 ns 14

Table 16. General AC and DC Characteristics (continued)