AUIRFIZ34N
HEXFET® Power MOSFET
PD - 97778
04/20/12
AUTOMOTIVE GRADE
TO-220AB Full-Pak
AUIRFIZ34N
GDS
Gate Drain Source
S
D
G
Features
lAdvanced Planar Technology
lLow On-Resistance
lIsolated Package
lHigh Voltage Isolation = 2.5KVRMS
lSink to Lead Creepage Distantce = 4.8mm
l175°C Operating Temperature
lFully Avalanche Rated
lLead-Free, RoHS Compliant
lAutomotive Qualified*
Description
Specifically designed for Automotive applications,
this cellular design of HEXFET® Power MOSFETs
utilizes the latest processing techniques to achieve
low on-resistance per silicon area. This benefit
combined with the fast switching speed and
ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for
use in Automotive and a wide variety of other
applications.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in
the specifications is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Ambient temperature (TA) is 25°C, unless otherwise specified.
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HEXFET® is a registered trademark of International Rectifier.
*Qualification standards can be found at http://www.irf.com/
Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°C Continuous Drain Current, V
GS
@ 10V A
I
DM
Pulsed Drain Current
ch
P
D
@T
C
= 25°C Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
E
AS
Single Pulse Avalanche Energy (Thermally Limited)
dh
mJ
I
AR
Avalanche Current
ch
A
E
AR
Repetitive Avalanche Energy
c
mJ
dv/dt Peak Diode Recovery dv/dt
eh
V/ns
T
J
Operating Junction and
T
STG
Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case )
Mounting Torque, 6-32 or M3 screw
Thermal Resistance
Parameter Typ. Max. Units
R
JC
Junction-to-Case
i
–– 4.1 °C/W
R
JA
Junction-to-Ambient ––– 65
-55 to + 175
300
10 lbf
y
in (1.1N
y
m)
37
0.24
± 20
Max.
21
15
100
5.0
3.7
110
16
V
(BR)DSS
55V
R
DS(on)
max. 40m
I
D
21A
AUIRFIZ34N
2www.irf.com
S
D
G
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 610µH
RG = 25, IAS = 16A. (See Figure 12)
ISD 16A, di/dt 420A/µs, VDD V(BR)DSS,
TJ 175°C.
Pulse width 300µs; duty cycle 2%.
t=60s, =60Hz
Uses IRFZ34N data and test conditions.
R is measured at Tj at approximately 90°C.
S
D
G
Static Electrical Characteristics @ T
J
= 2C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DS S Drain-to-Source Breakdown Voltage 55 ––– ––– V
V(BR)DSS /TJ Breakdown Voltage Temp. Coefficient ––– 0.052 ––– VC
RDS(on) Static Drain-to-Source On-Resistance –– ––– 40
m
VGS(th) Gate Threshold Voltage 2.0 –– 4.0 V
gfs Forward Transconductance 6.5 ––– ––– S
IDSS Drain-to-Source Leakage Current ––– ––– 25 μA
––– –– 250
IGSS Gate-to-Source Forward Leakage –– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100
Dynamic Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
QgTotal Gate Charge ––– ––– 34
Qgs Gate-to-Source Charge ––– ––– 68 nC
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 14
td(on) Turn-On Delay Time ––– 7.0 –––
trRise Time –49–
td(off) Turn-Off Delay Time 31 –– ns
tfFall Time 40
LDInternal Drain Inductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LSInternal Source Inductance ––– 7.5 ––– from package
and center of die contact
Ciss Input Capacitance ––– 700 –––
Coss Output Capacitance ––– 240 ––– pF
Crss Reverse Transfer Capacitance ––– 100 –––
C Drain to Sink Capacitance ––– 12 –––
Diode Characteristics
Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 21
(Body Diode) A
I
SM
Pulsed Source Current ––– ––– 100
(Body Diode)
c
V
SD
Diode Forward Voltage –– –– 1.6 V
t
rr
Reverse Recovery Time 57 86 ns
Q
rr
Reverse Recovery Charge ––– 130 200 nC
t
on
Forward Turn-On Time
Intrins ic turn-on time is negligible (turn-on is dominated by LS+LD)
ƒ = 1.0MHz, See Fig. 5
h
VGS = 20V
VGS = -20V
MOSFET s ymbol
integral reverse
p-n junction diode.
VDS = 25V, ID = 16A
h
ID = 16A
VDS = 44V
Conditions
RD = 1.8, See Fig. 10
fh
VGS = 0V
T
J
= 25°C, I
S
= 11A, V
GS
= 0V
f
T
J
= 25°C, I
F
= 16A
di/dt = 100A/μs
fh
Conditions
VGS = 0V, ID = 250μA
Reference to 25°C, ID = 1mA
h
VGS = 10V, ID = 11A
f
VDS = VGS , ID = 250μA
VDS = 55V, VGS = 0V
VDS = 44V, VGS = 0V, TJ = 15C
ƒ = 1.0MHz
Conditions
VGS = 10V, See Fig. 6&13
fh
VDD = 28V
ID = 16A
RG = 18
VDS = 25V
AUIRFIZ34N
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Qualification standards can be found at International Rectifiers web site: http//www.irf.com/
Exceptions to AEC-Q101 requirements are noted in the qualification report.
Qualification Information
TO-220 Fullpak N/A
Qualification Level
Automotive
(per AEC-Q101)
Comments: This part number(s) passed Automotive qualification.
IR’s Industrial and Consumer qualification level is granted by
extension of the higher Automotive level.
Charged Device Model Class C5 (+/- 2000V)
††
AEC-Q101-005
Moisture Sensitivity Level
RoHS Compliant Yes
ESD
Machine Model Class M2 (+/- 200V)
††
AEC-Q101-002
Human Body Model Class H1A (+/- 500V)
††
AEC-Q101-001
AUIRFIZ34N
4www.irf.com
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
45678910
T = 25°C
J
GS
V , Gate-to-Source Voltage (V)
D
I , Drain-to-Source Current (A)
A
V = 25V
20μs PULSE WIDTH
T = 175°C
J
DS
0.0
0.4
0.8
1.2
1.6
2.0
2.4
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
V = 10V
GS
A
I = 26A
D
1
10
100
1000
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
20μs PULSE WIDTH
T = 25°C
C
A
4.5V
1
10
100
1000
0.1 1 10 100
I , Drain-to-Source Current (A)
D
V , Drain-to-Source Voltage (V)
DS
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
A
4.5V
20μs PULSE WIDTH
T = 17C
C
TJTJ
AUIRFIZ34N
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Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
200
400
600
800
1000
1200
1 10 100
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
4
8
12
16
20
0 10203040
Q , Total Gate Charge (nC)
G
V , Gate-to-Source Voltage (V)
GS
A
FOR TEST CIRCUIT
SEE FIGURE 13
V = 44V
V = 28V
DS
DS
I = 16A
D
1
10
100
1000
0.4 0.8 1.2 1.6 2.0
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
A
T = 175°C
J
1
10
100
1000
1 10 100
V , Drain-to-Source Voltage (V)
DS
I , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10μs
100μs
1ms
10ms
A
T = 25°C
T = 175°C
Single Pulse
C
J
ce
stics
AUIRFIZ34N
6www.irf.com
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width µs
Duty Factor 
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
5
10
15
20
25
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
AUIRFIZ34N
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3F
50K
.2F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
0
50
100
150
200
250
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
A
Starting T , Junction Temperature (°C)
V = 25V
I
TOP 6.5A
11A
BOTTOM 16A
DD
D
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01
R
G
+
-
tp
VDS
IAS
VDD
V(BR)DSS
AUIRFIZ34N
8www.irf.com
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Circuit Layout Considerations
 Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
*
AUIRFIZ34N
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TO-220AB Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
TO-220AB Full-Pak Part Marking Information
AUFIZ34N
YWWA
XX or XX
Date Code
Y= Year
WW= Work Week
A= Automotive, LeadFree
Part Number
IR Logo
Lot Code
AUIRFIZ34N
10 www.irf.com
Ordering Information
Base part
number
Package Type Standard Pack Complete Part Number
Form
Quantity
AUIRFIZ34N
TO-220 Fullpak
Tube
50
AUIRFIZ34N
AUIRFIZ34N
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reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or services without notice. Part numbers designated with the
“AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance
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of order acknowledgment.
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IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to support
this warranty. Except where mandated by government requirements, testing of all parameters of each product is not
necessarily performed.
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