ICs for Communications PPP and HDLC Synchronous Serial Controller with 2 Channels PASSAT PEB 20525 Version 1.1 PEF 20525 Version 1.1 Preliminary Data Sheet 09.99 DS 2 * PEB 20525, PEF 20525 Revision History: Current Version: 09.99 Previous Version: 07.99 Page (in previous Version) Page (in current Version) 2-24, 2-25, 2-30 2-23, 2-24, Corrected RESET polarity to active low 2-29 3-42, 5-188 3-41,5-193 revised description of transmit data underrun (XDU) handling 5-108 5-109 bit field coding of "GMODE:IPC(1:0)" changed (equal to ESCC2) 5-108 5-109 bit field "GMODE:DMODE(1:0)" reduced to "GMODE:EDMA" 5-108 5-110 bits "SHAPERPD" and "BYPASS" reduced to bit "DSHP" - - HDLC "Non-Automode" renamed to "Address Mode 2" 5-123 5-128 Corrected reset value of register STARH to 10H - 6-215 Added description of external DMA support Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ABM (R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape (R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC (R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT (R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE (R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT (R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. * * ACE TM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUT TM are trademarks of Infineon Technologies AG. Edition 09.99 Published by Infineon Technologies AG i. Gr., SC, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG i.Gr. 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PEB 20525 PEF 20525 Preface The PASSAT is a Protocol Controller for a wide range of data communication and telecommunication applications. This document provides complete reference information on hardware and software related issues as well as on general operation. Organization of this Document This Preliminary Data Sheet is divided into 9 chapters. It is organized as follows: * Chapter 1, Introduction Gives a general description of the product, lists the key features, and presents some typical applications. * Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapters 3 Functional Description These chapters provide detailed descriptions of all PASSAT internal function blocks. * Chapter 4, Detailed Protocol Descriptions Gives a detailed description of all protocols supported by the serial communication controllers SCCs. * Chapter 5, Detailed Register Description Gives a detailed description of all PASSAT on chip registers. * Chapter 6, Programming Provides programming help for PASSAT initialization procedure and operation. * Chapter 7, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces. * Chapter 8, Test Modes Gives a detailed description of the JTAG boundary scan unit. * Chapter 9, Package Outline Preliminary Data Sheet 3 09.99 PEB 20525 PEF 20525 Table of Contents Page Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.4.1 1.4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 System Integration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Serial Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Differences between PASSAT and the HSCX/ESCC Family . . . . . . . . . 1-22 Enhancements to the HSCX Serial Core . . . . . . . . . . . . . . . . . . . . . . . 1-22 Simplifications to the HSCX Serial Core . . . . . . . . . . . . . . . . . . . . . . . 1-22 2 2.1 2.2 2.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Pin Diagram P-LFBGA-80-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Pin Diagram P-TQFP-100-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 3 3.1 3.2 3.2.1 3.2.2 3.2.2.1 3.2.2.2 3.2.2.3 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4 3.2.3.5 3.2.3.6 3.2.3.7 3.2.3.8 3.2.3.9 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 Serial Communication Controller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 Protocol Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 SCC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 SCC FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Clock Mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 Clock Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 Clock Mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Clock Mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 Clock Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 Clock Mode 5a (Time Slot Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 Clock Mode 5b (Octet Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 Clock Mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63 Clock Mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64 Baud Rate Generator (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Clock Recovery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 SCC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68 SCC Serial Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 Serial Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 Serial Bus Collisions and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69 Serial Bus Access Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70 Serial Bus Configuration Timing Modes . . . . . . . . . . . . . . . . . . . . . . . 3-71 Functions Of Signal RTS in HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . 3-71 Preliminary Data Sheet 4 09.99 PEB 20525 PEF 20525 Table of Contents Page 3.2.13 3.2.13.1 3.2.13.2 3.2.13.3 3.2.14 3.2.14.1 3.2.14.2 3.2.15 3.3 3.4 3.5 3.6 3.6.1 3.6.2 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72 FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72 Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 Modem Control Signals (RTS, CTS, CD) . . . . . . . . . . . . . . . . . . . . . . 3-74 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . 3-75 Local Loop Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76 External DMA Controller Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 General Purpose Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79 GPP Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79 GPP Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79 4 4.1 4.1.0.1 4.1.0.2 4.1.0.3 4.1.0.4 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.2 4.2.1 4.2.2 4.2.3 4.3 4.4 4.4.1 4.4.2 4.4.3 Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 HDLC/SDLC Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81 Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 HDLC Receive Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82 Receive Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85 HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85 Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87 One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87 CRC Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87 Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88 Point-to-Point Protocol (PPP) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89 Bit Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89 Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89 Data Transparency in PPP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92 Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . 4-92 Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93 Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98 Signaling System #7 (SS7) Operation . . . . . . . . . . . . . . . . . . . . . . . . 4-100 5 5.1 5.2 5.2.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108 Preliminary Data Sheet 5 09.99 PEB 20525 PEF 20525 Table of Contents Page 5.2.2 5.2.3 5.2.4 Channel Specific SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-125 Channel Specific DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-201 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-208 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-211 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-211 Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-211 Data Transmission (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . 6-211 Data Reception (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-213 External DMA Supported Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-215 Data Transmission (With External DMA Support) . . . . . . . . . . . . . . . 6-215 Data Reception (With External DMA Support) . . . . . . . . . . . . . . . . . . 6-218 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.1.1 7.7.1.2 7.7.1.3 7.7.2 7.7.2.1 7.7.2.2 7.7.2.3 7.7.2.4 7.7.2.5 7.7.2.6 7.7.2.7 7.7.3 7.7.4 Electrical Characteristics (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . 7-222 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-222 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-222 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-223 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-224 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-225 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-225 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-226 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-226 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . 7-226 Siemens/Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 7-227 Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229 PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-232 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-236 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . 7-237 Clock Mode 4 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 7-238 Clock Mode 4 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 7-239 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-241 8 8.1 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-242 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-242 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-247 Preliminary Data Sheet 6 09.99 PEB 20525 PEF 20525 List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 1-6 Figure 2-1 Figure 2-2 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Page Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 System Integration With External DMA Controller . . . . . . . . . . . . . . . 1-19 Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Pin Configuration P-LFBGA-80-2 Package . . . . . . . . . . . . . . . . . . . . 2-23 Pin Configuration P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . 2-24 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . 3-43 XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . 3-43 Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 Selecting one time-slot of programmable delay and width . . . . . . . . 3-54 Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . 3-56 Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58 Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . 3-59 Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . 3-61 Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62 Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63 Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . 3-67 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . 3-67 DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . 3-68 Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72 FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75 SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 HDLC Receive Data Processing in 16 bit Automode. . . . . . . . . . . . . 4-83 HDLC Receive Data Processing in 8 bit Automode. . . . . . . . . . . . . . 4-83 HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . 4-83 HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . 4-84 Preliminary Data Sheet 7 09.99 PEB 20525 PEF 20525 List of Figures Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 8-1 Page HDLC Receive Data Processing in Address Mode 1. . . . . . . . . . . . . 4-84 HDLC Receive Data Processing in Address Mode 0. . . . . . . . . . . . . 4-84 SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . 4-86 PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . 4-91 Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 4-94 Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96 Transmission/Reception of I-Frames and Flow Control . . . . . . . . . . . 4-97 Flow Control: Reception of S-Commands and Protocol Errors . . . . . 4-97 No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . 4-100 Data Transmission (without error), Data Transmission (with error) . 4-100 Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . 6-212 Interrupt Driven Data Reception (Flow Diagram) . . . . . . . . . . . . . . . 6-214 DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . 6-216 Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . 6-217 DMA Receive (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . 6-219 Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . 6-220 Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . 6-221 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . 7-225 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . 7-226 Siemens/Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7-227 Siemens/Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7-227 Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229 Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-232 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-236 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . 7-237 Clock Mode 4 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-238 Clock Mode 4 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-239 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-241 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . 8-242 Preliminary Data Sheet 8 09.99 PEB 20525 PEF 20525 List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 4-1 Table 4-2 Table 4-3 Table 5-1 Table 6-1 Table 6-2 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 8-1 Table 8-2 Page Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 External DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 Test Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 Overview of Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Clock Modes of the SCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 BRRL/BRRH Register and Bit-Fields . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Data Bus Access 16-bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3-77 Data Bus Access 16-bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . . 3-77 Protocol Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80 Address Comparison Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103 Status Information after RME interupt . . . . . . . . . . . . . . . . . . . . . . 6-213 DMA Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-215 Thermal Package Characteristics P-TQFP-100-3 . . . . . . . . . . . . . 7-223 Thermal Package Characteristics P-LFBGA-80-2 . . . . . . . . . . . . . 7-223 Capacitances TA = 25 xC; VDD3 = 3.3 V 0.3 V, VSS = 0 V . . . . . . . . . . . . . . . 7-225 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . 7-226 Siemens/Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 7-228 Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-230 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-233 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-235 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-236 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . 7-237 Clock Mode 4 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-238 Clock Mode 4 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-239 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-241 Boundary Scan Sequence of PASSAT . . . . . . . . . . . . . . . . . . . . . 8-243 Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-246 Preliminary Data Sheet 9 09.99 PEB 20525 PEF 20525 List of Registers Register 5-1 Register 5-2 Register 5-3 Register 5-4 Register 5-5 Register 5-6 Register 5-7 Register 5-8 Register 5-9 Register 5-10 Register 5-11 Register 5-12 Register 5-13 Register 5-14 Register 5-15 Register 5-16 Register 5-17 Register 5-18 Register 5-19 Register 5-20 Register 5-21 Register 5-22 Register 5-23 Register 5-24 Register 5-25 Register 5-26 Register 5-27 Register 5-28 Register 5-29 Register 5-30 Register 5-31 Register 5-32 Register 5-33 Register 5-34 Register 5-35 Register 5-36 Register 5-37 Register 5-38 Register 5-39 Register 5-40 Register 5-41 Register 5-42 Page GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSTAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDIRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDATL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPISL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPISH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DISR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMDRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR0H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PREAMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Data Sheet 10 5-108 5-109 5-112 5-114 5-114 5-116 5-116 5-118 5-118 5-120 5-120 5-122 5-123 5-124 5-125 5-125 5-128 5-128 5-132 5-132 5-136 5-136 5-139 5-139 5-144 5-144 5-149 5-149 5-153 5-154 5-154 5-155 5-155 5-157 5-157 5-158 5-158 5-160 5-160 5-161 5-161 5-163 09.99 PEB 20525 PEF 20525 List of Registers Register 5-43 Register 5-44 Register 5-45 Register 5-46 Register 5-47 Register 5-48 Register 5-49 Register 5-50 Register 5-51 Register 5-52 Register 5-53 Register 5-54 Register 5-55 Register 5-56 Register 5-57 Register 5-58 Register 5-59 Register 5-60 Register 5-61 Register 5-62 Register 5-63 Register 5-64 Register 5-65 Register 5-66 Register 5-67 Register 5-68 Register 5-69 Register 5-70 Register 5-71 Register 5-72 Register 5-73 Register 5-74 Register 5-75 Register 5-76 Register 5-77 Register 5-78 Register 5-79 Register 5-80 Register 5-81 Register 5-82 Register 5-83 Register 5-84 Page RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAL2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLCRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLCRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMBSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMBSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Data Sheet 11 5-163 5-164 5-164 5-166 5-166 5-167 5-167 5-169 5-169 5-170 5-170 5-172 5-172 5-174 5-174 5-175 5-175 5-178 5-178 5-180 5-180 5-181 5-181 5-183 5-183 5-184 5-184 5-186 5-186 5-188 5-188 5-189 5-194 5-194 5-195 5-197 5-202 5-202 5-204 5-204 5-206 5-206 09.99 PEB 20525 PEF 20525 List of Registers Register 5-85 Register 5-86 Register 5-87 Register 5-88 Page VER0 VER1 VER2 VER3 Preliminary Data Sheet ........................................... ........................................... ........................................... ........................................... 12 5-208 5-208 5-209 5-209 09.99 PEB 20525 PEF 20525 Introduction 1 Introduction The PASSAT is a Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications. A generic 8- or 16-bit multiplexed/demultiplexed slave interface provides fast device access with low bus utilization and easy software handshaking (in the P-LFBGA-80-2 package only an 8-bit data bus is provided). DMA handshake control signals allow connection to an external DMA controller. Large on-chip FIFOs of 64 byte capacity per port and direction in combination with enhanced threshold control mechanisms allow decoupling of traffic requirements on host bus and serial interfaces with little exception probabilities such as data underuns or overflows. Each of the two Serial Communication Controllers (SCC) contains an independent Baud Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC and BISYNC). Data rates of up to 2 Mbit/s (DPLL assisted modes) and 12.5 Mbit/s (HDLC, PPP, bit transparent) are supported. The channels can also handle a large set of layer-2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel specific timers are provided to support protocol functions. 1) The serial channels are also called 'ports' or 'cores' depending on the context. Preliminary Data Sheet 1-13 09.99 PPP and HDLC Synchronous Serial Controller with 2 Channels PASSAT Version 1.1 1.1 PEB 20525 PEF 20525 CMOS Features Serial communication controllers (SCCs) * Two independent channels * Full duplex data rates on each channel of up to 12.5 Mbit/s sync - 2 Mbit/s with DPLL * 64 Bytes deep receive FIFO per SCC * 64 Bytes deep transmit FIFO per SCC P-TQFP-100-3 * Serial Interface * * * * * * On-chip clock generation or external clock sources On-chip DPLLs for clock recovery Baud rate generator Clock gating signals Clock gapping capability Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1) * NRZ, NRZI, FM and Manchester data encoding P-LFBGA-80-2 * Optional data flow control using modem control lines (RTS, CTS, CD) * Support of bus configuration by collision detection and resolution Bit Processor Functions * HDLC/SDLC Protocol Modes - Automatic flag detection and transmission - Shared opening and closing flag - Generation of interframe-time fill '1's or flags - Detection of receive line status - Zero bit insertion and deletion Type Package PEB 20525, PEF 20525 P-TQFP-100-3 P-LFBGA-80-2 Preliminary Data Sheet 1-14 09.99 PEB 20525 PEF 20525 Introduction * * * * - CRC generation and checking (CRC-CCITT or CRC-32) - Transparent CRC option per channel and/or per frame - Programmable Preamble (8 bit) with selectable repetition rate - Error detection (abort, long frame, CRC error, short frames) Bit Synchronous PPP Mode - Bit oriented transmission of HDLC frame (flag, data, CRC, flag) - Zero bit insertion/deletion - 15 consecutive '1' bits abort sequence Octet Synchronous PPP Mode - Octet oriented transmission of HDLC frame (flag, data, CRC, flag) - Programmable character map of 32 hard-wired characters (00H-1FH) - Four programmable characters for additional mapping - Insertion/deletion of control-escape character (7DH) for mapped characters Extended Transparent Mode - Fully bit transparent (no framing, no bit manipulation) - Octet-aligned transmission and reception Protocol and Mode Independent - Data bit inversion - Data overflow and underrun detection - Timer Protocol Support * Address Recognition Modes - No address recognition (Address Mode 0) - 8-bit (high byte) address recognition (Address Mode 1) - 8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode 2) * HDLC Automode - 8-bit or 16-bit address generation/recognition - Support of LAPB/LAPD - Automatic handling of S- and I-frames - Automatic processing of control byte(s) - Modulo-8 or modulo-128 operation - Programmable time-out and retry conditions - SDLC Normal Response Mode (NRM) operation for slave * Signaling System #7 (SS7) support - Detection of FISUs, MSUs and LSSUs - Unchanged Fill-In Signaling Units (FISUs) optionally not forwarded - Automatic generation of FISUs in transmit direction (incl. sequence number) - Counting of errored signaling units * Optional DTACK/READY controlled cycles Preliminary Data Sheet 1-15 09.99 PEB 20525 PEF 20525 Introduction Microprocessor Interface * * * * * * 8-bit bus interface (P-LFBGA-80-2 package) 8/16-bit bus interface (P-TQFP-100-3 package) Multiplexed and De-multiplexed address/data bus Intel/Motorola style Asynchronous interface Maskable interrupts for each channel General Purpose Port (GPP) Pins (up to 3 in P-LFBGA-80-2, up to 7 in P-TQFP-1003 package) General * * * * * 3.3V power supply with 5V tolerant inputs Low power consumption Power safe features P-TQFP-100-3 Package (Thermal Resistance: RJA = 42 K/W) Small P-LFBGA-80-2 Package (Thermal Resistance: RJA = 51 K/W) Preliminary Data Sheet 1-16 09.99 PEB 20525 PEF 20525 Introduction 1.2 Logic Symbol * TEST VSS VDD3 TCK TMS TDI TDO TRST JTAG Test Interface A(7:0) ALE 1) TxDA RxDA RTSA/TxCLKO A/OSRA Serial CTSA/CxDA/TCGA Channel A CDA/FSCA/RCG A/OST A TxCLK A RxCLKA D(15:8) 3) Microprocessor Interface D(7:0) RD 1) WR 1) BHE 1) 3) LDS 2) UDS 2) 3) R/W 2) DTACK CS INT/INT PASSAT PEB 20525 PEF 20525 TxDB RxDB RTSB/TxCLKO B/OSRB Serial CTSB/CxDB/TCGB Channel B CDB/FSCB/RCG B/OST B TxCLK B RxCLKB XTAL1 XTAL2 GPn DRTB DRRB DACKB DRTA DRRA DACKA CLK RESET 1) Intel bus mode Motorola bus mode 3) 16-bit mode (TQFP-100 package only) 2) Figure 1-1 External DMA Interface General Purpose Port Logic Symbol Preliminary Data Sheet 1-17 09.99 PEB 20525 PEF 20525 Introduction 1.3 Typical Applications PASSAT devices can be used in LAN-WAN inter-networking applications such as Routers, Switches and Trunk cards and support the common V.35, ISDN BRI (S/T) and RFC1662 standards. Its new features provide powerful hardware and software interfaces to develop high performance systems. 1.3.1 System Integration Example T ransceiver, Fram er PASSAT PEB 20525 PEF 20525 ... C PU ... ... ... S ystem B us R AM B a nk Figure 1-2 System Integration Preliminary Data Sheet 1-18 09.99 PEB 20525 PEF 20525 Introduction Transceiver, Framer PASSAT PEB 20525 PEF 20525 ... CPU ... ... ... System Bus RAM Bank Figure 1-3 DMA Controller System Integration With External DMA Controller Preliminary Data Sheet 1-19 09.99 PEB 20525 PEF 20525 Introduction 1.3.2 Serial Configuration Examples PASSAT supports a variety of serial configurations at Layer-1 and Layer-2 level. The outstanding variety of clock modes supporting a large number of combinations of external and internal clock sources allows easy integration in application environments. serial transmission optional modem control signals Layer-2 LAPD/B or SS7 Protocol Support ... ... ... Figure 1-4 TxD PASSAT PEB 20525 PEF 20525 ... PASSAT PEB 20525 PEF 20525 RxD ... ... TxD ... RxD ... Point-to-Point Configuration Preliminary Data Sheet 1-20 09.99 PEB 20525 PEF 20525 Introduction ... PASSAT PEB 20525 PEF 20525 TxD ... ... Master RxD Layer-1 collision detection or Layer-2 SDLC-NRM operation ... ... CxD TxD RxD TxD RxD TxD ... ... PASSAT PEB 20525 PEF 20525 PASSAT PEB 20525 PEF 20525 ... ... CxD Slave n ... PASSAT PEB 20525 PEF 20525 ... ... Figure 1-5 CxD Slave 2 ... ... Slave 1 ... ... RxD ... Point-to-Multipoint Bus Configuration Layer-1 collision detection ... CxD TxD RxD RxD PASSAT PEB 20525 PEF 20525 ... ... ... CxD TxD Master n PASSAT PEB 20525 PEF 20525 ... ... TxD ... ... PASSAT PEB 20525 PEF 20525 ... Figure 1-6 CxD Master 2 ... Master 1 ... ... RxD ... Multimaster Bus Configuration Preliminary Data Sheet 1-21 09.99 PEB 20525 PEF 20525 Introduction 1.4 Differences between PASSAT and the HSCX/ESCC Family This chapter is useful for all being familiar with the HSCX/ESCC family. 1.4.1 Enhancements to the HSCX Serial Core The PASSAT SCC cores contain the core logic of the HSCX as the heart of the device. Some enhancements are incorporated in the SCCs. These are: * * * * * * Octet-and Bit Synchronous PPP protocol support as in RFC-1662 Signaling System #7 (SS7) support 4-kByte packet length byte counter Enhanced address filtering (16-bit maskable) Enhanced time slot assigner Support of high data rates (12.5 Mbit/s) 1.4.2 Simplifications to the HSCX Serial Core The following features of the HSCX core have been removed: * Extended transparent mode 0 (this mode provided octet buffered data reception without usage of FIFOs; PASSAT supports octet buffered reception via appropriate threshold configurations for the SCC receive FIFOs) Preliminary Data Sheet 1-22 09.99 PEB 20525 PEF 20525 Pin Descriptions 2 Pin Descriptions 2.1 Pin Diagram P-LFBGA-80-2 (top view) * P-LFBGA-80-2 R D# VSS R /W # B M/ A LE A 0/ B LE #/ U DS # A3 A5 A7 V DD J R EA D Y# D TA CK # TM S C S# V DD A2 A4 VSS R ES E T# IN T/ IN T# H V DD W R# C LK D S#/ B HE #/ LDS # A1 V DD A6 VSS R TS A# G D2 VSS D1 VSS VSS TxDA TxCLK A R xC LK A V DD F VSS D3 V DD D0 XTA L2 C DA / FSC A / R CGA #/ OSTA C TS A#/ C xD A / TC GA #/ OSR A R xD A E D6 D4 TE S T1 D5 TxDB XTA L1 VSSA V DD A D D7 D RR B / GP1 D AC K B # GP2 C TE S T2 Figure 2-1 D RTB / GP0 V DD V DD VSS TC K C TS B#/ C xD B / TC GB #/ OSR B TR S T# V DD B A VSS V DD D AC K A # VSS R xD B R xC LK B C DB / FSC B / R CGB #/ OSTB D RTA D RR A V DD R TS B# VSS TxCLK B VSS TD I TD O 9 8 7 6 5 4 3 2 1 Pin Configuration P-LFBGA-80-2 Package Preliminary Data Sheet 2-23 09.99 PEB 20525 PEF 20525 Pin Descriptions 2.2 Pin Diagram P-TQFP-100-3 (top view) * 55 60 65 70 50 80 45 85 40 90 35 95 25 20 15 10 1 100 5 30 VSS V DD VSS V DD TM S R /W # D S#/B H E #/LD S # C S# B M/A LE VSS V DD A 0/B LE#/U DS # A1 A2 A3 V DD VSS W IDT H A4 A5 A6 A7 VSS V DD GP6 TD O TC K V DD VSS C TS B#/C xDB /TC G B #/O S RB VSSA XTA L2 XTA L1 V DD A C TS A#/C xDA /TC G A #/O S RA C DA /FSC A /RC G A #/O S TA R xD A R xC LK A TxDA V DD VSS TxCLK A R TS A# R ES E T# IN T/INT# V DD VSS G P 10 GP9 GP8 V DD VSS D 12 D 13 D 14 D 15 V DD VSS D RTA D AC K A # D RR A D RR B /G P 1 D RTB /G P 0 D AC K B #/G P 2 R TS B# R xD B V DD VSS R xC LK B TxDB TxCLK B C DB /FSC B /RC G B #/O S TB V DD TR S T# TD I 75 D 11 D 10 D9 D8 VSS V DD TE S T2 TE S T1 D7 D6 D5 D4 VSS V DD D3 D2 D1 D0 VSS V DD C LK R EA D Y#/D TA CK # W R# R D# VSS P-TQFP-100-3 Figure 2-2 Pin Configuration P-TQFP-100-3 Package Preliminary Data Sheet 2-24 09.99 PEB 20525 PEF 20525 Pin Descriptions 2.3 Pin Definitions and Functions Table 2-1 Microprocessor Bus Interface Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 C8 D9 D6 D8 E8 F9 F7 E6 81 80 79 78 75 74 73 72 67 66 65 64 61 60 59 58 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I/O Data Bus The data bus lines are bi-directional tri-state lines which interface with the system's data bus. The PASSAT in the P-LFBGA-80-2 package does not support 16-bit bus modes. J2 G3 J3 H4 J4 H5 G5 29 30 31 32 36 37 38 A7 A6 A5 A4 A3 A2 A1 I I I I I I I Address Bus These pins connect to the system's address bus to select one of the internal registers for read or write. Preliminary Data Sheet 2-25 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-1 Microprocessor Bus Interface Pin No. PLFBGA80-2 P-TQFP100-3 J5 39 J6 42 Symbol In (I) Function Out (O) A0 I Address Line A0 (8-bit modes) In Motorola and in Intel 8-bit mode this signal represents the least significant address line. BLE I Byte Low Enable (16-bit Intel bus mode) This signal indicates a data transfer on the lower byte of the data bus (D7..D0). Together with signal BHE the type of bus access is determined (byte or word access at even or odd address). UDS I Upper Data Strobe (16-bit Motorola bus mode) This active low strobe signal serves to control read/write operations. Together with signal LDS the type of bus access is determined. BM I Bus Mode - BM = static '1' for operation in Motorola bus mode (de-multiplexed). - BM = static '0' for operation in Intel bus mode with de-multiplexed address and data buses. - Pin BM/ALE has the function of an Address Latch Enable (ALE) for operation in Intel bus mode with a multiplexed address/data bus. A falling edge on this pin selects Intel multiplexed bus mode. ALE I Address Latch Enable (mux'ed Intel bus) The address is latched by the PASSAT with the falling edge of ALE. The address input pins A(7:0) must be externally connected to the data bus pins D(7:0). For operation of the 8-bit PASSAT (P-LFBGA-802 package) in a 16-bit environment, A(7:0) should be connected to address/data lines AD(8:1) of the external bus. D(7:0) interface to AD(7:0) of the external bus. Preliminary Data Sheet 2-26 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-1 Microprocessor Bus Interface Pin No. PLFBGA80-2 P-TQFP100-3 G6 44 Symbol In (I) Function Out (O) DS I Data Strobe (8-bit Motorola bus mode only) This active low strobe signal serves to control read/write operations. BHE I Bus High Enable (16-bit Intel bus mode only) This signal indicates a data transfer on the upper byte of the data bus (D15..D8). In 8-bit Intel bus mode this signal has no function. LDS I Lower Data Strobe (16-bit Motorola bus mode) This active low strobe signal serves to control read/write operations. Together with signal UDS the type of bus access is determined (byte or word access at even or odd address). In 8-bit Intel bus mode, a pull-up resistor to VDD3 is recommended on this pin. J9 52 RD I Read Strobe (Intel bus mode only) This signal indicates a read operation. The bus is able to accept data on lines D(7:0) / D(15:0) during an active RD signal. In Motorola bus mode, a pull-up resistor to VDD3 is recommended on this pin. J7 45 R/W I Read/Write Enable (Motorola bus mode) This signal distinguishes between read and write operation. As an input it must be valid during data strobe (DS). In Intel bus mode, a pull-up resistor to VDD3 is recommended on this pin. H7 43 CS I Chip Select A low signal selects PASSAT for read/write operations. Preliminary Data Sheet 2-27 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-1 Microprocessor Bus Interface Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 G8 53 WR I Write Strobe (Intel bus mode only) This signal indicates a write operation. Valid data is present data on lines D(7:0) / D(15:0) during an active WR signal. In Motorola bus mode, a pull-up resistor to VDD3 is recommended on this pin. - 33 WIDTH I Width Of Bus Interface A low signal on this input selects the 8-bit bus interface mode. A high signal on this input selects the 16-bit bus interface mode. In this case word transfer to/from the internal registers is enabled. Byte transfers are implemented by using BLE and BHE (Intel bus mode) or LDS and UDS (Motorola bus mode) In P-LFBGA-80-2 package this signal is not available, since only 8 bit bus width is supported. G7 55 CLK I Clock The system clock for PASSAT is provided through this pin. H1 20 INT/INT O o/d Preliminary Data Sheet Interrupt Request The INT/INT goes active when one or more of the bits in registers ISR0..ISR2 are set to '1'. A read to these registers clears the interrupt. The INT/ INT line is inactive when all interrupt status bits are reset. Interrupt sources can be unmasked in registers IMR0..IMR2 by setting the corresponding bits to '0'. 2-28 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-1 Microprocessor Bus Interface Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 H9 54 READY O DTACK O Ready (Intel bus mode) Data Transfer Acknowledge (Motorola mode) During a slave access (register read/write) this signal (output) indicates, that the PASSAT is ready for data transfer. The signal remains active until the data strobe (DS in Motorola bus mode, RD/WR in Intel bus mode) and/or the chip select (CS) go inactive. This line is tri-state when unused. A pull-up resistor to VDD3 is recommended if this function is not used. H2 19 RESET Reset With this active low signal the on-chip registers and state machines are forced to reset state. During Reset all pins are in a high impedance state. Preliminary Data Sheet I 2-29 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-2 External DMA Interface Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 A9 84 DRTA O DMA Request Transmitter Channel A The transmitter on a this channel requests a DMA transfer by activating the DRTA line. The request remains active as long as the Transmit FIFO requires data transfers. The amount of data bytes to be transferred from the system memory to the serial channel (= Byte Count) must be written first to the XBCL, XBCH registers. Always blocks of data (n x 32 bytes + rest ; n=0,1,...) are transferred till the Byte Count is reached. DRTA is deactivated with the beginning of the last write cycle. A8 86 DRRA O DMA Request Receiver Channel A The receiver on this serial channel requests a DMA transfer by activating the DRRA line. The request remains active as long as the Receive FIFO requires data transfers, thus always blocks of data are transferred. DRRA is deactivated immediately following the falling edge of the last read cycle. B7 85 DACKA I Preliminary Data Sheet DMA Acknowledge Channel A A low signal on this pin informs the PASSAT that the requested DMA cycle controlled via DRTA or DRRA of this channel is in progress, i.e. the DMA controller has achieved bus mastership from the CPU and will start data transfer cycles (either write or read). In conjunction with a read or write operation this input serves as Access Enable (similar to CS) to the respective FIFOs. If DACKA is active, the input to pins A(7:0) and CS is ignored and the FIFOs are implicitly selected. If not used, a pull-up resistor to VDD is required for this pin. 2-30 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-2 External DMA Interface Pin No. PLFBGA80-2 P-TQFP100-3 D5 88 C7 C6 87 89 Symbol In (I) Function Out (O) DRTB O DMA Request Transmitter Channel B (corresponding to channel A) GP0 I/O General Purpose Pin #0 If DMA support is not enabled, this pin serves as a general pupose input/output pin. After reset this pin serves as a general purpose input. A pull-up resistor to VDD3 is recommended. DRRB O DMA Request Receiver Channel B (corresponding to channel A) GP1 I/O General Purpose Pin #1 If DMA support is not enabled, this pin serves as a general pupose input/output pin. After reset this pin serves as a general purpose input. A pull-up resistor to VDD3 is recommended. DACKB I DMA Acknowledge Channel B (corresponding to channel A) GP2 General Purpose Pin #2 If DMA support is not enabled, this pin serves as a general pupose input/output pin. A pull-up resistor to VDD3 is recommended if this pin is not used. Preliminary Data Sheet I/O 2-31 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-3 Serial Port Pins Pin No. PLFBGA80-2 P-TQFP100-3 F3 17 Symbol In (I) Function Out (O) TxCLK A I/O Transmit Clock Channel A The function of this pin depends on the selected clock mode and the value of bit 'TOE' (CCR0L register, refer to Table 3-2 "Clock Modes of the SCCs" on page 3-45). If programmed as Input (CCR0L.TOE='0'), either - the transmit clock for the channel (clock mode 0a, 2a, 4, 5b, 6a), or - a transmit strobe signal for the channel (clock mode 1) can be provided to this pin. If programmed as Output (CCR0L.TOE='1'), this pin supplies either - the transmit clock from the baud rate generator (clock mode 0b, 2b, 3b, 6b, 7b), or - the transmit clock from the DPLL circuit (clock mode 3a, 7a), or - an active-low control signal marking the programmed transmit time-slot in clock mode 5a. F2 13 RxCLK A Preliminary Data Sheet I Receive Clock Channel A The function of this pin depends on the selected clock mode (refer to Table 3-2 "Clock Modes of the SCCs" on page 3-45). A signal provided on pin RxCLKA may supply - the receive clock (clock mode 0, 4, 5b), or - the receive and transmit clock (clock mode 1, 5a), or - the clock input for the baud rate generator (clock mode 2, 3). 2-32 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-3 Serial Port Pins (cont'd) Pin No. PLFBGA80-2 P-TQFP100-3 E3 11 Symbol In (I) Function Out (O) CDA I Carrier Detect Channel A The function of this pin depends on the selected clock mode. It can supply - either a modem control or a general purpose input (clock modes 0, 2, 3, 6, 7). If auto-start is programmed, it functions as a receiver enable signal. - or a receive strobe signal (clock mode 1). Polarity of CDA can be set to 'active low' with bit ICD in register CCR1H. Additionally, an interrupt may be issued if a state transition occurs at the CDA pin (programmable feature). FSCA I Frame Sync Clock Channel A (cm 5a) When the SCC is in the time-slot oriented clock mode 5a, this pin functions as the Frame Synchronization Clock input. RCGA I Receive Clock Gating Channel A (cm 4) In clock mode 4 this pin is used as Receive Clock Gating signal. If no clock gating function is required, a pull-up resistor to VDD3 is recommended. OSTA I Octet Sync Transmit Channel A (cm 5b) When the SCC is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), a synchronization pulse on this input pin aligns transmit octets. Preliminary Data Sheet 2-33 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-3 Serial Port Pins (cont'd) Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 G1 18 RTSA O Request to Send Channel A The function of this pin depends on the settings of bits RTS, FRTS in register CCR1H . In bus configuration, RTS can be programmed to: - go low during the actual transmission of a frame shifted by one clock period, excluding collision bits. - go low during reception of a data frame. - stay always high (RTS disabled). E2 10 CTSA I Clear to Send Channel A A low on the CTSA input enables the transmitter. Additionally, an interrupt may be issued if a state transition occurs at the CTSA pin (programmable feature). If no 'Clear To Send' function is required, a pulldown resistor to VSS is recommended. CxDA I Collision Data Channel A In a bus configuration, the external serial bus must be connected to the corresponding CxDA pin for collision detection. A collision is detected whenever a logical '1' is driven on the open drain TxDA output but a logical '0' is detected via CxDA input. TCGA I Transmit Clock Gating Channel A (cm 4) In clock mode 4 these pins are used as Transmit Clock Gating signals. If no clock gating function is required, a pull-up resistor to VDD3 is recommended. OSRA I Octet Sync Receive Channel A (cm 5b) (clock mode 5b) When the SCC is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), received octets are aligned to this synchronization pulse input. Preliminary Data Sheet 2-34 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-3 Serial Port Pins (cont'd) Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 F4 14 TxDA O o/d Transmit Data Channel A Transmit data is shifted out via this pin. It can be configured as push/pull or open drain output characteristic via bit 'ODS' in register CCR1L. E1 12 RxDA I Receive Data Channel A Serial data is received on this pin. A4 96 TxCLK B I/O Transmit Clock Channel B (corresponding to channel A) B4 94 RxCLK B I Receive Clock Channel B (corresponding to channel A) B3 97 CDB FSCB RCGB OSTB I I I I Carrier Detect Channel B Frame Sync Clock Channel B (cm 5a) Receive Clock Gating Channel B (cm 4) Octet Sync Transmit Channel B (cm 5b) (corresponding to channel A) A6 90 RTSB O Request to Send Channel B (corresponding to channel A) C1 5 CTSB CxDB TCGB OSRB I I I I Clear to Send Channel B Collision Data Channel B Transmit Clock Gating Channel B (cm 4) Octet Sync Receive Channel B (cm 5b) (corresponding to channel A) D4 95 TxDB O o/d Transmit Data Channel B (corresponding to channel A) Preliminary Data Sheet 2-35 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-3 Serial Port Pins (cont'd) Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 B5 91 RxDB I Receive Data Channel B (corresponding to channel A) D3 E4 8 7 XTAL1 XTAL2 I O Crystal Connection If the internal oscillator is used for clock generation (clock modes 0b, 6, 7) the external crystal has to be connected to these pins. The internal oscillator should be powered up (GMODE:OSCPD = '0') and the signal shaper may be activated (GMODE:DSHP = '0'). Moreover, XTAL1 may be used as input for a common clock source to both SCCs, provided by an external clock generator (oscillator). In this case the oscillator unit may be powered down and it is recommended to bypass the shaper of the internal oscillator unit by setting bit 'DSHP' to '1'. A pull-down resistor to VSS is recommended for pin XTAL1 if not used. Table 2-4 General Purpose Pins Pin No. PLFBGA80-2 P-TQFP100-3 - 23 24 25 26 Symbol In (I) Function Out (O) GP10 GP9 GP8 GP6 Preliminary Data Sheet I/O General Purpose Pins These pins serve as general purpose input/output pins. 2-36 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-5 Test Interface Pins Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 B2 99 TRST I JTAG Reset Pin (internal pull-up) For proper device operation, a reset for the boundary scan controller must be supplied to this active low pin. If the boundary scan of the PASSAT is not used, this pin can be connected to VSS to keep it in reset state. C2 2 TCK I JTAG Test Clock (internal pull-up) If the boundary scan of the PASSAT is not used, this pin may remain unconnected. A2 100 TDI I JTAG Test Data Input (internal pull-up) If the boundary scan of the PASSAT is not used, this pin may remain unconnected. A1 1 TDO O JTAG Test Data Output H8 46 TMS I JTAG Test Mode Select (internal pull-up) If the boundary scan of the PASSAT is not used, this pin may remain unconnected. D7 68 TEST1 I Test Input 1 When connected to VDD3 the PASSAT works in a vendor specific test mode. This pin must be connected to VSS. C9 69 TEST2 I Test Input 2 When connected to VDD3 the PASSAT works in a vendor specific test mode. This pin must be connected to VSS. Preliminary Data Sheet 2-37 09.99 PEB 20525 PEF 20525 Pin Descriptions Table 2-6 Power Pins Pin No. Symbol In (I) Function Out (O) PLFBGA80-2 P-TQFP100-3 A7, B1, B8, C4, C5, E7, F1, G4, G9, H6, J1 3, 15, VDD3 21, 27, 35, 40, 47, 49, 56, 62, 70, 76, 82, 92, 98 - Digital Supply Voltage 3.3 V 0.3 V All pins must be connected to the same voltage potential. A3, A5, B6, B9, C3, E9, F5, F6, F8, G2, H3, J8 4, 16, VSS 22, 28, 34, 41, 48, 50, 51, 57, 63, 71, 77, 83, 93 - Digital Ground (0 V) All pins must be connected to the same voltage potential. D1 9 VDDA - Analog Supply Voltage 3.3 V 0.3 V This pin supplies the on-chip oscillator of the PASSAT. It can be directly connected to V DD3. D2 6 VSSA - Analog Ground (0 V) This pin supplies the ground level to the on-chip oscillator of the PASSAT. It can be directly connected to VSS. - -- N.C. - Not Connected Preliminary Data Sheet 2-38 09.99 PEB 20525 PEF 20525 Functional Overview 3 Functional Overview The functional blocks of PASSAT can be divided into two major domains: - the microprocessor interface of PASSAT provides access to internal on-chip and to the system portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally these FIFOs can be accessed by an external 4-channel DMA controller. - the Serial Communication Controller (SCC) is capable of processing bit-synchronous (HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully transparent data traffic. Data exchange between the serial communication controller and the microprocessor interface is performed using FIFOs, decoupling these two clocking domains. 3.1 Block Diagram Figure 3-1 Block Diagram 5 JTAG Test Interface Serial Channel A L A P C o n tro l T ra n sm it F IF O (3 2 B yte ) T ra n s m it F IF O (3 2 B yte ) R e ce ive F IF O (3 2 B yte ) R e c e ive F IF O (3 2 B yte ) T ra n s m it P ro to co l M a c h in e TSA D e c o d e r/ C o llisio n D e te ctio n D PLL M ic ro p ro c e s s o r In te rfa c e 26 R e c e ive P ro to co l M a c h in e 7 BRG C lo c k C o n tro l O s cilla to r Serial Channel B T ra n sm it F IF O (3 2 B yte ) R e ce ive F IF O (3 2 B yte ) 7 External DMA Interface 6 Preliminary Data Sheet 3-39 09.99 PEB 20525 PEF 20525 Functional Overview 3.2 Serial Communication Controller (SCC) 3.2.1 Protocol Modes Overview The SCC is a multi-protocol communication controller. The core logic provides different protocol modes which are listed below: * HDLC Modes - HDLC Transparent Operation (Address Mode 0) - HDLC Address Recognition (Address Mode 1, Address Mode 2 8/16-bit) - Full-Duplex LAPB/LAPD Operation (Automode 8/16-bit) - Half-Duplex SDLC-NRM Operation (Automode 8-bit) - Signaling System #7 (SS7) Operation * Point-to-Point Protocol (PPP) Modes - Bit Synchronous PPP - Octet Synchronous PPP * Extended Transparent Mode A detailed description of these protocol modes is given in Chapter 4, starting on page 480. 3.2.2 SCC FIFOs Each SCC provides its own transmit and receive FIFOs to handle internal arbitration and microcontroller latencies. 3.2.2.1 SCC Transmit FIFO The SCC transmit FIFO is divided into two parts of 32 bytes each ('transmit pools'). The interface between the two parts provides clock synchronization between the system clock domain and the protocol logic working with the serial transmit clock. Preliminary Data Sheet 3-40 09.99 PEB 20525 PEF 20525 Functional Overview 3 2 b y te S h a d o w p a rt (n o t a c c e s s a b le b y C P U ) T ra n s m it P ro to c o l M a c h in e M ic ro p ro c e s s o r/D M A In te rfa c e Figure 3-2 3 2 b y te T ra n s m it P o o l (a c c e s s a b le b y C P U ) SCC Transmit FIFO The 32 bytes system clocked FIFO part is accessable by the CPU/DMA controller; it accepts transmit data even if the SCC is in power-down condition (register CCR0H bit PU='0'). The only exception is a transmit data underrun (XDU) event. In case of an XDU event (e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer another byte to the protocol logic. This XDU blocking mechanism prevents unexpected serial data. The blocking condition must be cleared by reading the interrupt status register ISR1 after the XDU interrupt was generated. Thus, the XDU interrupt indication should not be masked in register IMR1. Transfer of data to the 32 byte shadow part only takes place if the SCC is in power-up condition and an appropriate transmit clock is provided depending on the selected clock mode. Serial data transmission will start as soon as at least one byte is transferred into the shadow FIFO and transmission is enabled depending on the selected clock mode (CTS signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive). 3.2.2.2 SCC Receive FIFO The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between the two parts provides clock synchronization between the system clock domain and the protocol logic working with the serial receive clock. Preliminary Data Sheet 3-41 09.99 PEB 20525 PEF 20525 Functional Overview 3 2 b yte R e c e iv e P o o l (a c c e s s a b le b y C P U ) R ec eive P rotocol M achine M icroprocessor/D M A Inte rfac e Figure 3-3 3 2 b yte S h a d o w p a rt (n o t a c c e s s a b le b y C P U ) SCC Receive FIFO New receive data is announced to the CPU with an interrupt latest when the FIFO fill level reaches a chosen threshold level (selected with bitfield 'RFTH(1..0)' in register "CCR3H" on page 5-149). Default value for this threshold level is 32 bytes. If the SCC receive FIFO is completely filled, further incoming data is ignored and a receive data overflow condition ('RDO') is detected. As soon as the receive FIFO provides empty space, receive data is accepted again after a frame end or frame abort sequence. The automatically generated receive status byte (RSTA) will contain an 'RDO' indication in this case and the next incoming frame will be received in a normal way. Therefore no further CPU intervention is necessary to recover the SCC from an 'RDO' condition. A "frame" with 'RDO' status might be a mixture of a frame partly received before the 'RDO' event occured and the rest of this frame received after the receive FIFO again accepted data and the frame was still incoming. A quite arbitrary series of data or complete frames might get lost in case of an 'RDO' event. Every frame which is completely discarded because of an 'RDO' condition generates an 'RFO' interrupt. The SCC receive FIFO can be cleared by command 'RRES' in register CMDRH. Note that clearing the receive FIFO during operation might delete a frame end / block end indication. A frame which was already partly transferred cannot be "closed" in this case. A new frame received after receiver reset command will be appended to this "open" frame. Preliminary Data Sheet 3-42 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.2.3 SCC FIFO Access Figure 3-4 and Figure 3-5 illustrate byte interpretation for Intel and Motorola 16-bit accesses to the transmit and receive FIFOs. X F IF O R F IF O . B yte. 32 . B yte. 32 . . . . . . . B yte . . B yte . . B yte . . B yte . . B yte . 5 4 3 2 1 D (1 5:8) Figure 3-4 D (7 :0 ) 5 4 3 2 1 D (1 5:8) D (7 :0 ) XFIFO/RFIFO Word Access (Intel Mode) X F IF O R F IF O . B yte. 32 . B yte. 32 . . . . . . . B yte . . B yte . . B yte . . B yte . . B yte . D (1 5:8) Figure 3-5 . . . . . . . B yte . . B yte . . B yte . . B yte . . B yte . . . . . . . . B yte . . B yte . . B yte . . B yte . . B yte . 5 4 3 2 1 D (7 :0 ) D (1 5:8) 5 4 3 2 1 D (7 :0 ) XFIFO/RFIFO Word Access (Motorola Mode) Preliminary Data Sheet 3-43 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3 Clocking System The PASSAT includes an internal Oscillator (OSC) as well as two independent Baud Rate Generators (BRG) and two Digital Phase Locked Loop (DPLL) circuits. The transmit and receive clock can be generated either * externally, and supplied directly via the RxCLK and/or TxCLK pins (called external clock modes) * internally, by selecting - the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG) - the internal DPLL, recovering the receive (and optionally transmit) clock from the receive data stream. (called internal clock modes) There are a total of 14 different clocking modes programmable via bit field 'CM' in register CCR0L, providing a wide variety of clock generation and clock pin functions, as shown in Table 3-2. The transmit clock pins (TxCLK) may also be configured as output clock and control signals in certain clock modes if enabled via bit 'TOE' in register CCR0L. The clocking source for the DPLL's is always the internal channel specific BRG; the scaling factor (divider) of the BRG can be programmed through BRRL and BRRH registers. There are two channel specific internal operational clocks in the SCC: One operational clock (= transmit clock) for the transmitter part and one operational clock (= receive clock) for the receiver part of the protocol logic. Note: The internal timers always run using the internal transmit clock. Table 3-1 Overview of Clock Modes Clock Type Receive Clock Transmit Clock Preliminary Data Sheet Source Generation Clock Mode RxCLK Pins Externally 0, 1, 4, 5 OSC, DPLL, BRG, Internally TxCLK Pins, RxCLK Pins Externally OSC, DPLL, BRG/BCR, BRG Internally 2, 3a, 6, 7a 3b, 7b 0a, 2a, 4, 6a 1,5 3a, 7a 2b, 6b 0b, 3b, 7b 3-44 09.99 PEB 20525 PEF 20525 Functional Overview The internal structure of each SCC channel consists of 3 clocking domains, transmit, receive, and system. These three function blocks are clocked with internal transmit frequency fTRM, internal receive frequency fREC and system frequency fSYS, respectively (system frequency fSYS only supplies the SCC receive and transmit FIFO part facing the microprocessor interface). The internal FIFO interfaces are used to transfer data between the different clock domains. The clocks fTRM and fREC are internal clocks only and need not be identical to external clock inputs e.g. fTRM and TxCLK input pin. The features of the different clock modes are summarized in Table 3-2. Table 3-2 Clock Modes of the SCCs Channel Configuration Clock Sources Control Sources Clock Mode CCR0L: CM(2..0) CCR0L: to SSEL BRG to DPLL to REC to TRM CD 0a 0b 1 2a 2b 3a 3b 4 5a 0 1 X 0 1 0 1 X 0 - OSC - RxCLK RxCLK RxCLK RxCLK - - - - - BRG BRG BRG - - - RxCLK RxCLK RxCLK DPLL DPLL DPLL BRG RxCLK RxCLK TxCLK BRG RxCLK TxCLK BRG/16 DPLL BRG TxCLK RxCLK CD CD - CD CD CD CD - - 5b 1 - - RxCLK TxCLK - 6a 6b 7a 7b 0 1 0 1 OSC OSC OSC OSC BRG BRG BRG - DPLL DPLL DPLL BRG TxCLK BRG/16 DPLL BRG CD CD CD CD Preliminary Data Sheet 3-45 R- Strobe - - - - - - - - FSC - BRG - - BRG/16 DPLL BRG TS-Control FrameX- Strobe Sync Tx - - CD - - - - RCG (TSAR/ PCMRX) (TSAR/ PCMRX) - - - - Rx Output via TxCLK (if CCR0L: TOE = `1') - - TxCLK - - - - TCG (TSAX/ PCMTX) (TSAX/ PCMTX) - - - - - - - - - - - - FSC OST OSR - - - - - - - - - - BRG/16 DPLL BRG 09.99 PEB 20525 PEF 20525 Functional Overview Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) is enabled which allows connection of an external crystal to pins XTAL1-XTAL2. The output signal of the OSC can be used for one serial channel, or for both serial channels (independent baud rate generators and DPLLs). Moreover, XTAL1 alone can be used as input for an externally generated clock. The first two columns of Table 3-2 list all possible clock modes configured via bit field 'CM' and bit 'SSEL' in register CCR0L. For example, clock mode 6b is choosen by writing a '6' to register CCR0L.CM(2:0) and by setting bit CCR0L.SSEL equal to '1'. The following 4 columns (grouped as 'Clock Sources') specify the source of the internal clocks. Columns REC and TRM correspond to the domain clock frequencies fREC and fTRM . The columns grouped as 'Control Sources' cover additional clock mode dependent control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or synchronization signals (clock mode 5). The last column describes the function of signal TxCLK which in some clock modes can be enabled as output signal monitoring the effective transmit clock or providing a time slot control signal (clock mode 5). The following is an example of how to read Table 3-2: For clock mode 6b (row '6b') the TRM clock (column 'TRM') is supplied by the baudrate generator (BRG) output divided by 16 (source BRG/16). The BRG (column 'BRG') is derived from the internal oscillator which is supplied by pin XTAL1 and XTAL2. The REC clock (column 'REC') is supplied by the internal DPLL which itself is supplied by the baud rate generator (column 'DPLL') again. Note: The REC clock is DPLL clock divided by 16. If enabled by bit 'TOE' in register CCR0L the resulting transmit clock can be monitored via pin TxCLK (last column, row '6b'). Preliminary Data Sheet 3-46 09.99 PEB 20525 PEF 20525 Functional Overview The clocking concept is illustrated in a block diagram manner in the following figure: Additional control signals are not illustrated (please refer to the detailed clock mode descriptions below). TxCLK RxCLK CRYSTAL XTAL2 XTAL1 or RxD TTL Oscillator 0b 6a/b 7a/b 2a/b 3a/b BRG settings controlled by: register CCR0, bit field 'CM' selects the clock mode number 16:1 3a 7a 0b 3b 7b 2b 6b 1 5a 0a 2a 6a 4 5b fTRM Transmitter Figure 3-6 fR x C L K f TxCLK f RxCLK fB R G / 1 6 f BRG fBRG f TxCLK f RxCLK f BRG/16 f BRG f DPLL fDPLL f DPLL DPLL register CCR0, bit 'SSEL' selects the additional a/b option 0a/b 1 5a/b 4 2a/b 3 b 7b 3a 6a/b 7a fR E C Receiver Clock Supply Overview Preliminary Data Sheet 3-47 09.99 PEB 20525 PEF 20525 Functional Overview Clock Modes 3.2.3.1 Clock Mode 0 (0a/0b) Separate, externally generated receive and transmit clocks are supplied to the SCC via their respective pins. The transmit clock may be directly supplied by pin TxCLK (clock mode 0a) or generated by the internal baud rate generator from the clock supplied at pin XTAL1 (clock mode 0b). In clock mode 0b the resulting transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. XTAL2 XTAL1 clock mode 0a clock supply RxCLK 1 CTS , CxD, TCG CD, F S C , R C G 2 TxCLK RTS Ctrl. RxD Ctrl. TxD clock mode 0b XTAL2 XTAL1 or clock supply OSC RxCLK 1 CTS , CxD, TCG f BRG = f OSC /k CD, F S C , R C G TxCLK M K=(n+1)/2 Ctrl. Ctrl. Figure 3-7 (tx clock monitor output) RTS RxD TxD Clock Mode 0a/0b Configuration Preliminary Data Sheet 3-48 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.2 Clock Mode 1 Externally generated RxCLK is supplied to both the receiver and transmitter. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK pin. These strobe signals work on a per bit basis. This operating mode can be used in time division multiplex applications or for adjusting disparate transmit and receive data rates. Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte synchronization (byte alignment). This means that the strobe signal needs to be detected once only to transmit or receive a complete byte. X T A L2 X T A L1 c loc k m od e 1 c lo c k s u pp ly R xC L K 1 C TS , C xD , T C G CD , F S C , R C G T xC L K V SS (e n a b le s tra n s m it) re c eive s tro b e tran s m it s trob e RTS C trl. R xD C trl. T xD R xD CD (rx stro b e) R xC LK T xC LK (tx stro b e) T xD N o te : In e xten de d tra ns p aren t m o de the s tro be s ign als ne ed to be de te c ted o nc e o nly to tran s m it o r re c eive a c om p lete b yte . T h us b yte align m en t is pro v ide d in th is m od e. Figure 3-8 Clock Mode 1 Configuration Preliminary Data Sheet 3-49 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.3 Clock Mode 2 (2a/2b) The BRG is driven by an external clock (RxCLK pin) and delivers a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies the internal receive clock. Depending on the programming of register CCR0L bit 'SSEL', the transmit clock will be either an external input clock signal provided at pin TxCLK in clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the latter case, the transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. XTAL2 XTAL1 clock mode 2a clock supply RxCLK BRG 1 CTS , CxD, TCG CD, F S C , R C G DPLL 2 TxCLK RTS Ctrl. RxD Ctrl. TxD XTAL2 XTAL1 clock mode 2b clock supply RxCLK BRG 1 CTS , CxD, TCG DPLL 16:1 CD, F S C , R C G TxCLK (tx clock monitor output) RTS Ctrl. RxD Ctrl. Figure 3-9 TxD Clock Mode 2a/2b Configuration Preliminary Data Sheet 3-50 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.4 Clock Mode 3 (3a/3b) The BRG is fed with an externally generated clock via pin RxCLK. Depending on the value of bit 'SSEL' in register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or delivers directly the receive and transmit clock (clock mode 3b). In the first case the DPLL output clock is used as receive and transmit clock. XTAL2 XTAL1 clock mode 3a clock supply RxCLK BRG 1 CTS , CxD, TCG CD, F S C , R C G DPLL TxCLK (tx clock monitor output) RTS Ctrl. RxD Ctrl. TxD XTAL2 XTAL1 clock mode 3b clock supply RxCLK BRG 1 CTS , CxD, TCG CD, F S C , R C G TxCLK (tx clock monitor output) RTS Ctrl. RxD Ctrl. TxD Figure 3-10 Clock Mode 3a/3b Configuration Preliminary Data Sheet 3-51 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.5 Clock Mode 4 Separate, externally generated receive and transmit clocks are supplied via pins RxCLK and TxCLK. In addition separate receive and transmit clock gating signals are supplied via pins RCG and TCG. These gating signals work on a per bit basis. X TA L2 X TA L1 clo ck m ode 4 c loc k su pply R xC L K 1 C T S , C xD , TC G tra ns m it c lo ck gate s igna l C D , FS C , RCG rec eive c lo ck gate s igna l 2 T xC L K RTS C trl. R xD C trl. T xD T xC L K 1 c lo ck d e lay TCG T xD R x CL K RCG RxD Figure 3-11 Clock Mode 4 Configuration Preliminary Data Sheet 3-52 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.6 Clock Mode 5a (Time Slot Mode) This operation mode has been designed for application in time-slot oriented PCM systems. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clock are common for each channel and must be supplied externally via pin RxCLK. The SCC receives and transmits only during fixed time-slots. Either one time-slot - of programmable width (1 ... 512 bit, via TTSA and RTSA registers), and - of programmable location with respect to the frame synchronization signal (via pin FSC) or up to 32 time-slots - of constant width (8 bits), and - of programmable location with respect to the frame synchronization signal (via pin FSC) can be selected. The time-slot locations can be programmed independently for receive and transmit direction via TTSA/RTSA and PCMTX/PCMRX registers. Depending on the value programmed via those registers, the receive/transmit time-slot starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame synchronization signal. Figure 3-12 shows how to select a time-slot of programmable width and location and Figure 3-13 shows how to select one or more time-slots of 8-bit width. If bit 'TOE' in register CCR0L is set, the selected transmit time-slot(s) is(are) indicated at an output status signal via pin TxCLK, which is driven to `low' during the active transmit window. Bit 'TSCM' in register CCR1H determines whether the internal offset counters are continuously running even if no synchronization pulse is detected at FSC signal or stopping at their maximum value. In the continuous case the repetition rate of offset counter operation is 1024 transmit or receive clocks respectively. An FSC pulse detected earlier resets the counters and starts operation again. In the non-continuous case the time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an FSC pulse is detected. Preliminary Data Sheet 3-53 09.99 PEB 20525 PEF 20525 Functional Overview T T S A 0 ..3 : T ra n sm it T im e S lo t A ss ig n m e n t R e g iste r 7 TTSA3 0 7 TTSA2 0 T CC 7 0 TTSA1 0 7 TTSA0 T T SN 0 T CS T EPC M = '0': T PC M M ask Disab led FSC R xC L K a c tive tim e slo t T S d e la y (tra n sm it): 1 + T T S N *8 + T C S (1 ...1 0 2 4 ) T S w id th (tra n sm it): TCC (1 ...5 1 2 clo c k s) T S d e la y (re c e ive ): 1 + R T S N *8 + R C S (1 ...1 0 2 4 ) T S w id th (re c e ive ): RCC (1 ..5 1 2 ) R T S A 0 ..3 : R e ce ive T im e S lo t A s sig n m e n t R e g is te r 7 RTSA3 0 7 RTSA2 0 RC C 7 0 RTSA1 0 7 RTSA0 RT SN 0 RC S RE PCM = '0 ': RPC M M ask Disab led Figure 3-12 Selecting one time-slot of programmable delay and width Preliminary Data Sheet 3-54 09.99 PEB 20525 PEF 20525 Functional Overview Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame itself to achieve synchronization (at least for the 2nd and subsequent PCM frames): DELAY = PCM frame length = 1 + xTSN*8 + xCS. xTSN and xCS have to be set appropriately. Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected. PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7. Note: In extended transparent mode the width xCC of the selected time-slot has to be n x 8 bit because of character synchronization (byte alignment). In all other modes the width can be used to define windows down to a minimum length of one bit. Preliminary Data Sheet 3-55 09.99 PEB 20525 PEF 20525 Functional Overview TTSA0..3: Transmit Time Slot Assignment Register 7 TTSA3 0 7 TTSA2 0 TCC 7 1 TTSA1 0 7 TTSA0 0 TCS TTSN TEPCM = '1': TPCM Mask Enabled PCMTX0..3: Transmit PCM Mask Register 31 PCMTX3 24 23 PCMTX2 17 16 15 PCMTX1 8 7 1 PCMTX0 3 0 1 FSC ... RxCLK active time slot TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17 8 bit TS delay (transmit): 1 + TTSN*8 + TCS (1..1024) TS delay (receive): 1 + RTSN*8 + RCS (1..1024) RTSA0..3: Receive Time Slot Assignment Register 7 RTSA3 0 7 RTSA2 RCC 0 7 1 Figure 3-13 PCMRX3 24 23 PCMRX2 0 7 RTSA0 0 RCS RTSN REPCM = '1': TPCM Mask Enabled PCMRX0..3: Receive PCM Mask Register 31 RTSA1 16 15 PCMRX1 8 7 PCMRX0 0 Selecting one or more time-slots of 8-bit width The common transmit and receive clock is supplied at pin RxCLK and the common frame synchronisation signal at pin FSC. The "strobe signals" for active time slots are generated internally by the time slot assigner block (TSA) independent in transmit and receive direction. When the transmit and receive PCM masks are enabled, bit fields 'TCC' and 'RCC' are ignored because of the constant 8-bit time slot width. Preliminary Data Sheet 3-56 09.99 PEB 20525 PEF 20525 Functional Overview X TA L2 X TA L1 clo ck m od e 5a c lo c k s u p p ly R xC LK 1 C T S , C xD , TC G CD , FS C, RCG Tim e S lot A ssign er (TS A ) TxC LK tim e slo t in d ic a to r s ig n a l R TS C trl. R xD C trl. n 0 1 TxD 2 ... n 0 R xC LK FSC T S d elay TS w idth in te rn a l tx stro b e T xC L K T S -C o n tro l T xD TS de la y TS w idth in te rn a l rx s tro b e RxD Figure 3-14 Clock Mode 5a Configuration Note: The transmit time slot delay and width is programmable via bit fields 'TTSN', 'TCS' and 'TCC' in registers TTSA0..TTSA3. The receive time slot delay and width is programmable via bit fields 'RTSN', 'RCS' and 'RCC' in registers RTSA0..RTSA3. Preliminary Data Sheet 3-57 09.99 PEB 20525 PEF 20525 Functional Overview The following figures provide a more detailed description of the TSA internal counter operation and exceptional cases: clock mode 5a bit TSCM='0' (continuous mode) FSC RxCLK, TxCLK ... load offset ocnt: load offset ocnt: ocnt := 1024 - TSdelay ocnt := 1024 ocnt := N, ocnt := 1024 - TSdelay N < TSdelay ocnt := 0 load duration dcnt: Mode TEPCM/REPCM = '0' dcnt := 0 dcnt := TSwidth - 1 active time slot Mode TEPCM/REPCM = '1' dcnt := 0 dcnt := 255 active time slots according PCMTX/PCMRX TSdelay = 1 + xTSN*8 + xCS (1...1024) Exceptions: a) FSC pulse period > 1024: The offset counter ocnt will automaically restart after 1024 clock cycles and will be restarted again by the late FSC pulse! FSC TSdelay + 1024 clock cycles ocnt start ocnt restart ocnt restart b) FSC pulse period < (TSdelay + TSwidth), i.e. FSC pulse detected while duration counter still active: The offset counter ocnt will automaically restart, but duration counter dcnt continues operation (transmit/receive in active time slots) FSC < 1024 clock cycles ocnt start ocnt restart dcnt start Figure 3-15 Clock Mode 5a "Continuous Mode" Preliminary Data Sheet 3-58 09.99 PEB 20525 PEF 20525 Functional Overview Each frame sync pulse starts the internal offset counter with (1024 - TSdelay) whereas TSdelay is the configured value defining the start position. Whenever the offset counter reaches its maximum value 1024, it triggers the duration counter to start operation. If continuous mode is selected (bit CCR1H.TSCM='0') the offset counter continues starting with value 0 until another frame sync puls is detected or again the maximum value 1024 is reached. Once the duration counter is triggered it runs out independently from the offset counter, i.e. an active time slot period may overlap with the next frame beginning (frame sync event, refer to exception b) in Figure 3-15). c lo c k m o d e 5 a b it T S C M = '1 ' (n o n c o n tin u o u s m o d e ) A d ifferen t b eh avior to c lock m o de 5a c on tino us m o de is give n o nly in ca se o f E xce ptio n a ). E x c e p tio n s : a ) F S C pu ls e pe riod > 1 02 4 : T h e o ffs et c o un te r o c nt w ill s top on its m ax im um v a lue 1 02 4 , w h ic h trigg ers th e d ura tion c o u nte r d c nt a nd w ill b e re s tarte d a ga in by th e 'la te' F S C p uls e ! FSC T S de la y + 1 0 24 c loc k c yc le s o c nt s ta rt o c nt := T S de la y - 1 o c nt s to p o c nt s ta rt Figure 3-16 Clock Mode 5a "Non Continuous Mode" If non-continuous mode is selected (bit CCR1H.TSCM='1') the offset counter is stopped on its maximum value 1024 until another frame sync puls is detected. This allows frame sync periods greater than 1024 clock cycles, but the accesible part is limited by the range of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM mask is selected. Preliminary Data Sheet 3-59 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.7 Clock Mode 5b (Octet Sync Mode) This operation mode has been designed for applications using Octet Synchronous PPP. It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported, i.e. bits TTSA1.TEPCM and RTSA1.REPCM must be set to '1'. Clock mode 5b provides octet alignment to time slots if Octet Synchronous PPP protocol mode or extended transparent mode is selected. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clocks are separate and must be supplied at pins RxCLK and TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of programmable location with respect to the octet synchronization signals (via pins OSR and OST) The time-slot locations can be programmed independently for receive and transmit direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 / PCMRX0..PCMRX3. Figure 3-17 shows how to select one or more octet wide time-slots. Bit 'TSCM' in register CCR1H determines whether the internal counters are continuously running even if no synchronization pulse is detected at OST/OSR signals or stopping at their maximum value. In the continuous case the repetition rate of operation is 1024 transmit or receive clocks respectively. An OST/OSR pulse detected earlier resets the corresponding offset counter and starts operation again. In the non-continuous case the transmit/receive time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an OST/ OSR pulse is detected. Preliminary Data Sheet 3-60 09.99 PEB 20525 PEF 20525 Functional Overview T T S A 0 ..3 : T ra n sm it T im e S lo t A s sig nm en t R e g iste r 7 TTSA3 0 7 TTSA2 0 TCC 7 1 TTSA1 0 7 TTSA0 0 TTSN TCS T E PC M = '1': T P C M M ask En ab led P C M T X 0 ..3 : T ra n sm it P C M M a sk R e g is te r 31 P C M T X3 24 23 P C M T X2 17 16 15 P C M T X1 8 7 1 OSR OST R xC LK T xC L K P CM TX0 3 0 1 ... a c tive tim e slo t TS0 TS1 TS2 TS3 TS4 TS5 T S 16 T S 17 8 bit T S de la y (tra n sm it): 1 + T T S N *8 + T C S (1 ...1 0 2 4 ) T S d e la y (re c e ive ): 1 + R T S N *8 + R C S (1 ...1 0 2 4 ) R T S A 0 ..3 : R e c e ive T im e S lo t A ss ig n m e nt R e g ister 7 RTSA3 0 7 RTSA2 0 RCC 7 1 P CM RX3 24 23 P CM RX2 0 7 RTSA0 0 RCS R T SN R EP CM = '1': T P CM M ask En ab led P C M R X 0 ..3 : R e c e ive P C M M a sk R e g is ter 31 RTSA1 16 15 P CM RX1 8 7 P CM RX0 0 Figure 3-17 Selecting one or more octet wide time-slots The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for active time slots are generated internally by the time slot assigner blocks (TSA) independent in transmit and receive direction. Bit fields 'TCC' and 'RCC' are ignored because of the constant 8-bit time slot width. Preliminary Data Sheet 3-61 09.99 PEB 20525 PEF 20525 Functional Overview X TA L 2 X TA L 1 c lo c k m o d e 5 b clo ck su pply R xC LK 1 C TS , C xD , TC G , O S T Tim e S lo t A ss ign e r (R T S A ) C D , FS C , R C G , O S R TxC LK R TS Tim e Slot A s sig ne r (T TS A ) C trl. R xD C trl. n 0 1 2 TxD 2 ... n 0 RxCLK T xC LK O SR O ST T S de la y TS w id th internal tx s tro be T xD TS d elay TS w id th internal rx stro be RxD Figure 3-18 Clock Mode 5b Configuration Note: The transmit time slot delay and width is programmable via bit fields 'TTSN', 'TCS' and 'TCC' in registers TTSA0..TTSA3. The receive time slot delay and width is programmable via bit fields 'RTSN', 'RCS' and 'RCC' in registers RTSA0..RTSA3. Preliminary Data Sheet 3-62 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.8 Clock Mode 6 (6a/6b) This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator and delivers a reference clock for the DPLL which is 16 times the resulting DPLL output frequency which in turn supplies the internal receive clock. Depending on the programming of register CCR0L bit 'SSEL', the transmit clock will be either an external input clock signal provided at pin TxCLK in clock mode 6a or the clock delivered by the BRG divided by 16 in clock mode 6b. In the latter case, the transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. clock mode 6a XTAL2 XTAL1 or OSC RxCLK V SS C T S, CxD, TCG BRG clock supply C D, FSC, RCG TxCLK DPLL 1 RTS Ctrl. RxD Ctrl. TxD clock mode 6b XTAL2 XTAL1 or OSC RxCLK V SS C T S, CxD, TCG BRG C D, FSC, RCG DPLL TxCLK 16:1 (tx clock monitor output) RTS Ctrl. RxD Ctrl. TxD Figure 3-19 Clock Mode 6a/6b Configuration Preliminary Data Sheet 3-63 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.3.9 Clock Mode 7 (7a/7b) This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator. Depending on the value of bit 'SSEL' in register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and transmit data. clock mode 7a XTAL2 XTAL1 or OSC RxCLK CTS, CxD, TCG BRG V SS C D, FSC, RCG TxCLK DPLL (tx clock monitor output) RTS Ctrl. RxD Ctrl. TxD clock mode 7b XTAL2 XTAL1 or OSC RxCLK CTS, CxD, TCG V SS C D, FSC, RCG BRG TxCLK (tx clock monitor output) RTS Ctrl. RxD Ctrl. Figure 3-20 TxD Clock Mode 7a/7b Configuration Preliminary Data Sheet 3-64 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.4 Baud Rate Generator (BRG) Each serial channel provides a baud rate generator (BRG) whose division factor is controlled by registers BRRL and BRRH. Whether the BRG is in the clocking path or not depends on the selected clock mode. Table 3-3 BRRL/BRRH Register and Bit-Fields Register Bit-Fields Offset Pos. Name Default Description BRRL 38H/88H 5..0 BRN 0 Baud Rate Factor N BRRH 39H/89H 11..8 range N = 0..63 BRM 0 Baud Rate Factor M, range M = 0..15 The clock division factor k is calculated by: k = (N + 1) x 2M f B RG = f i n k 3.2.5 Clock Recovery (DPLL) The SCC offers the advantage of recovering the received clock from the received data by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock information via a separate serial clock line. For this purpose, the DPLL is supplied with a `reference clock' from the BRG which is 16 times the expected data clock rate (clock mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG by a constant factor of 16 (clock mode 2b, 6b; bit 'SSEL' in register CCR0L set) or also directly from the DPLL (clock mode 3a, 7a). The main task of the DPLL is to derive a receive clock and to adjust its phase to the incoming data stream in order to enable optimal bit sampling. The mechanism for clock recovery depends on the selected data encoding (see "Data Encoding" on page 3-71). The following functions have been implemented to facilitate a fast and reliable synchronization: Preliminary Data Sheet 3-65 09.99 PEB 20525 PEF 20525 Functional Overview Interference Rejection and Spike Filtering Two or more edges in the same directional data stream within a time period of 16 reference clocks are considered to be interference and consequently no additional clock adjustment is performed. Phase Adjustment (PA) Referring to Figure 3-21, Figure 3-22 and Figure 3-23, in the case where an edge appears in the data stream within the PA fields of the time window, the phase will be adjusted by 1/16 of the data. Phase Shift (PS) (NRZ, NRZI only) Referring to Figure 3-21 in the case where an edge appears in the data stream within the PS field of the time window, a second sampling of the bit is forced and the phase is shifted by 180 degrees. Note: Edges in all other parts of the time window will be ignored. This operation facilitates a fast and reliable synchronization for most common applications. Above all, it implies a very fast synchronization because of the phase shift feature: one edge on the received data stream is enough for the DPLL to synchronize, thereby eliminating the need for synchronization patterns, sometimes called preambles. However, in case of extremely high jitter of the incoming data stream the reliability of the clock recovery cannot be guaranteed. The SCC offers the option to disable the Phase Shift function for NRZ and NRZI encodings by setting bit 'PSD' in register CCR0L to '1'. In this case, the PA fields are extended as shown in Figure 3-22. Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach the optimal sampling position. To ensure correct data sampling, preambles should precede the data information. Figure 3-21, Figure 3-22 and Figure 3-23 explain the DPLL algorithms used for the different data encodings. Preliminary Data Sheet 3-66 09.99 PEB 20525 PEF 20525 Functional Overview Bit Cell DPLL Count Correction 0 1 0 2 3 4 5 6 7 +PA 8 9 10 11 12 13 14 15 PS -PA 0 DPLL Output ITD01806 Figure 3-21 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) Bit Cell DPLL Count 0 Correction 0 1 2 3 4 5 6 +PA 7 8 9 10 11 12 13 14 15 -PA 0 DPLL Output ITD04820 Figure 3-22 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) Preliminary Data Sheet 3-67 09.99 PEB 20525 PEF 20525 Functional Overview Bit Cell (FM Coding) Bit Cell (Manchester Coding) DPLL Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 Correction 0 +PA - ignore - -PA 0 +PA - ignore - Transmit Clock Receive Clock ITD01807 Figure 3-23 DPLL Algorithm for FM0, FM1 and Manchester Encoding To supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the DPLL. 3.2.6 SCC Timer Operation Each SCC provides a general purpose timer e.g. to support protocol functions. In all operating modes the timer is clocked by the effective transmit clock. In clock mode 5 (time-slot oriented mode) the clock source for the timer can be optionally switched to the frame sync clock (input pin FSC) by setting bit 'SRC' in register TIMR3. The timer is controlled by the CPU via access to registers CMDRL and TIMR0..TIMR3. The timer can be started any time by setting bit 'STI' in register CMDRL. After the timer has expired it generates a timer interrupt ('TIN'). With bit field 'CNT(2..0)' in register TIMR3 the number of automatic timer restarts can be programmed. If the maximum value '111' is entered, a timer interrupt is generated periodically, with the time period determined by bit field 'TVALUE' (registers TIMR0..TIMR3). The timer can be stopped any time by setting bit 'TRES' in register CMDRL to '1'. In HDLC Automode the timer is used internally for autonomous protocol functions (refer to the chapter "Automode" on page 4-81). If this operating mode is selected, bit 'TMD' in register TIMR3 must be set to '1'. Preliminary Data Sheet 3-68 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.7 SCC Serial Bus Configuration Mode Beside the point-to-point configuration, the SCC effectively supports point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods. In a pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves), or in a multimaster configuration, data transmission can be initiated by each station over a common transmit line (bus). In case more than one station attempts to transmit data simultaneously (collision), the bus has to be assigned to only one station. A collision-resolution procedure is implemented in the SCC. Bus assignment is based on a priority mechanism with rotating priorities. This allows each station a bus access within a predetermined maximum time delay (deterministic CSMA/CD), no matter how many transmitters are connected to the serial bus. Prerequisites for bus operation are: * NRZ encoding * `OR'ing of data from every transmitter on the bus (this can be realized as a wired-OR, using the TxD open drain capability) * Feedback of bus information (CxD input). The bus configuration is selected via bitfield SC(2:0) in register CCR0H. Note: Central clock supply for each station is not necessary if both the receive and transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the phase shift between the individual transmit clocks. The bus configuration mode operates independently of the clock mode, e.g. also together with clock mode 1 (receive and transmit strobe operation). 3.2.8 Serial Bus Access Procedure The idle state of the bus is identified by eight or more consecutive `1's. When a device starts transmission of a frame, the bus is recognized to be busy by the other devices at the moment the first `zero' is transmitted (e.g. first `zero' of the opening flag in HDLC mode). After the frame has been transmitted, the bus becomes available again (idle). Note: If the bus is occupied by other transmitters and/or there is no transmit request in the SCC, logical `1' will be continuously transmitted on TxD. 3.2.9 Serial Bus Collisions and Recovery During the transmission, the data transmitted on TxD is compared with the data on CxD. In case of a mismatch (`1' sent and `0' detected, or vice versa) data transmission is immediately aborted, and idle (logical `1') is transmitted. Preliminary Data Sheet 3-69 09.99 PEB 20525 PEF 20525 Functional Overview HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is generated. Since a `zero' (`low') on the bus prevails over a `1' (high impedance) if a wired-OR connection is implemented, and since the address fields of the HDLC frames sent by different stations normally differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. The frame of the transmitter with the highest temporary priority (determined by the address field) is not affected and is transmitted successfully. All other stations cease transmission immediately and return to bus monitoring state. Note: If a wired-OR connection has been realized by an external pull-up resistor without decoupling, the data output (TxD) can be used as an open drain output and connected directly to the CxD input. For correct identification as to which frame is aborted and thus has to be repeated after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to be unique, i.e. SCC transmit FIFO should not contain data of more than one frame. For this purpose new data may be provided to the transmit FIFO only after 'ALLS' interrupt status is detected. 3.2.10 Serial Bus Access Priority Scheme To ensure that all competing stations are given a fair access to the transmission medium, a two-stage bus access priority scheme is supported by PASSAT: Once a station has successfully completed the transmission of a frame, it is given a lower level of priority. This priority mechanism is based on the requirement that a station may attempt transmitting only when a determined number of consecutive `1's are detected on the bus. Normally, a transmission can start when eight consecutive `1's on the bus are detected (through pin CxD). When an HDLC frame has been successfully transmitted, the internal priority class is decreased. Thus, in order for the same station to be able to transmit another frame, ten consecutive `1's on the bus must be detected. This guarantees that the transmission requests of other stations are satisfied before the same station is allowed a second bus access. When ten consecutive `1's have been detected, transmission is allowed again and the priority class (of all stations) is increased (to eight `1's). Inside a priority class, the order of transmission (individual priority) is based on the HDLC address, as explained in the preceding paragraph. Thus, when a collision occurs, it is always the station transmitting the only `zero' (i.e. all other stations transmit a `one') in a bit position of the address field that wins, all other stations cease transmission immediately. Preliminary Data Sheet 3-70 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.11 Serial Bus Configuration Timing Modes If a bus configuration has been selected, the SCC provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. * Timing mode 1 (CCR0H:SC(2:0) = `001') Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated 1/2 a clock period later at the CxD pin with the falling clock edge. * Timing mode 2 (CCR0H:SC(2:0) = `011') Data is output with the falling clock edge and evaluated with the next falling clock edge. Thus one complete clock period is available between data output and collision detection. 3.2.12 Functions Of Signal RTS in HDLC Mode In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC bits) to be active when data (frame or character) is being transmitted. This signal is delayed by one clock period with respect to the data output TxD, and marks all data bits that could be transmitted without collision (see Figure 3-24). In this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. Collision TxD CxD RTS ITT00242 Figure 3-24 Request-to-Send in Bus Operation Note: For details on the functions of the RTS pin refer to "Modem Control Signals (RTS, CTS, CD)" on page 3-74. 3.2.13 Data Encoding The SCC supports the following coding schemes for serial data: - - - - Non-Return-To-Zero (NRZ) Non-Return-To-Zero-Inverted (NRZI) FM0 (also known as Bi-Phase Space) FM1 (also known as Bi-Phase Mark) Preliminary Data Sheet 3-71 09.99 PEB 20525 PEF 20525 Functional Overview - Manchester (also known as Bi-Phase) The desired line coding scheme can be selected via bit field 'SC(2:0)' in register CCR0H. 3.2.13.1 NRZ and NRZI Encoding NRZ: The signal level corresponds to the value of the data bit. By programming bit 'DIV' (CCR1L register), the SCC may invert the transmission and reception of data. NRZI: A logical `0' is indicated by a transition and a logical `1' by no transition at the beginning of the bit cell. Transmit/ Receive Clock NRZ NRZI 0 Figure 3-25 1 1 0 0 1 0 ITD05313 NRZ and NRZI Data Encoding 3.2.13.2 FM0 and FM1 Encoding FM0: An edge occurs at the beginning of every bit cell. A logical `0' has an additional edge in the center of the bit cell, whereas a logical `1' has none. The transmit clock precedes the receive clock by 90. FM1: An edge occurs at the beginning of every bit cell. A logical `1' has an additional edge in the center of the bit cell, a logical `0' has none. The transmit clock precedes the receive clock by 90. Preliminary Data Sheet 3-72 09.99 PEB 20525 PEF 20525 Functional Overview Transmit Clock Receive Clock FM0 FM1 1 1 0 0 1 0 ITD01809 Figure 3-26 FM0 and FM1 Data Encoding 3.2.13.3 Manchester Encoding Manchester: In the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. At the center of the bit cell this level is inverted. The transmit clock precedes the receive clock by 90. The bit cell is shifted by 180 in comparison with FM coding. Transmit Clock Receive Clock Manchester 1 1 0 0 1 0 ITD01810 Figure 3-27 Manchester Data Encoding Preliminary Data Sheet 3-73 09.99 PEB 20525 PEF 20525 Functional Overview 3.2.14 Modem Control Signals (RTS, CTS, CD) 3.2.14.1 RTS/CTS Handshaking The SCC provides two pins (RTS, CTS) per serial channel supporting the standard request-to-send modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical `0' on the request-to-send output (RTS). It is also possible to control the RTS output by software. After having received the permission to transmit (CTS) the SCC starts data transmission. In the case where permission to transmit is withdrawn in the course of transmission, the frame is aborted and IDLE is sent. After transmission is enabled again by re-activation of CTS, and if the beginning of the frame is still available in the SCC, the frame will be re-transmitted (self-recovery). However, if the permission to transmit is withdrawn after the data available in the shadow part of the SCC transmit FIFO has been completely transmitted and the pool is released, the transmitter and the SCC transmit FIFO are reset, the RTS output is deactivated and an interrupt (XMR) is generated. Note: For correct identification as to which frame is aborted and thus has to be repeated after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to be unique, i.e. SCC transmit FIFO should not contain data of more than one frame, which could happen if transmission of a new frame is started by providing new data to the transmitter too early. For this purpose the 'All Sent' interrupt (ISR1.ALLS) has to be waited for before providing new transmit data. Note: In the case where permission to transmit is not required, the CTS input can be connected directly to VSS and/or bit 'FCTS' (register CCR1H) may be set to '1'. Additionally, any transition on the CTS input pin, sampled with the transmit clock, will generate an interrupt indicated via register ISR1, if this function is enabled by setting the 'CSC' bit in register IMR1 to '0'. Preliminary Data Sheet 3-74 09.99 PEB 20525 PEF 20525 Functional Overview ~ ~ TxCLK ~ ~ TxD ~ ~ RTS ~ ~ CTS Sampling ITT00244 Figure 3-28 RTS/CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), in HDLC mode the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR1L register. This is only available if the serial channel is operating in a bus configuration mode in clock mode 0 or 1. * If SOC1, SOC0 bits are set to `11', the RTS output is active (= low) during the reception of a frame. * If SOC1, SOC0 bits are set to `10', the RTS output function is disabled and the RTS pin remains always high. 3.2.14.2 Carrier Detect (CD) Receiver Control Similar to the RTS/CTS control for the transmitter, the SCC supports the carrier detect modem control function for the serial receiver if the Carrier Detect Auto Start (CAS) function is programmed by setting the 'CAS' bit in register CCR1H. This function is always available in clock modes 0, 2, 3, 6, 7 via the CD pin. In clock mode 1 the CD function is not supported. See Table 3-2 for an overview. If the CAS function is selected, the receiver is enabled and data reception is started when the CD input is detected to be high. If CD input is set to `low', reception of the current character (byte) is still completed. 3.2.15 Local Loop Test Mode To provide fast and efficient testing, the SCC can be operated in a test mode by setting the 'TLP' bit in register CCR2L. The on-chip serial data input and output signals (TxD, Preliminary Data Sheet 3-75 09.99 PEB 20525 PEF 20525 Functional Overview RxD) are connected, generating a local loopback. As a result, the user can perform a self-test of the SCC. T L P = '0 ' RxD S C C re c e iv e lo g ic T L P = '1 ' T L P O = '0 ' S C C tra n s m it lo g ic TxD I D L E '1 ' T L P O = '1 ' Figure 3-29 SCC Test Loop Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L. Note: A sufficient clock mode must be used for test loop operation such that receiver and transmitter operate with the same frequencies depending on the clock supply (e.g. clock mode 2b or 6b). 3.3 Microprocessor Interface The communication between the CPU and PASSAT is done via a set of directly accessible registers. The interface may be configured as Intel or Motorola type (refer to description of pin 'BM') with a selectable data bus width of 8 or 16 bit (refer to description of pin 'WIDTH'). Note: For the PASSAT in P-LFBGA-80-2 package only an 8-bit wide bus interface is supported. The CPU transfers data to/from PASSAT (via 64 byte deep FIFOs per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is selected, access to the lower/upper part of the data bus is determined by signals BHE/ BLE as shown in Table 3-4 (Intel mode) or by the upper and lower data strobe signals UDS/LDS as shown in Table 3-5 (Motorola mode). Preliminary Data Sheet 3-76 09.99 PEB 20525 PEF 20525 Functional Overview Table 3-4 Data Bus Access 16-bit Intel Mode BHE BLE Register Access Data Pins Used 0 0 Word access (16 bit) D(15:0) 0 1 Byte access (8 bit), odd address D(15:8) 1 0 Byte access (8 bit), even address D(7:0) 1 1 no data transfer - Table 3-5 Data Bus Access 16-bit Motorola Mode UDS LDS Register Access Data Pins Used 0 0 Word access (16 bit) D(15:0) 0 1 Byte access (8 bit), even address D(15:8) 1 0 Byte access (8 bit), odd address D(7:0) 1 1 no data transfer - Each of the two serial channels of PASSAT is controlled via an identical, but completely independent register set (Channel A and B). Global functions that are common to or independent from the two serial channels are located in global registers. 3.4 External DMA Controller Support The PASSAT comprises a 4-channel DMA interface for fast and effective data transfers using an external DMA controller. For both serial channels, a separate DMA Request output for Transmit (DRT) and Receive direction (DRR) as well as a DMA Acknowledgement input (DACK) is provided. The PASSAT activates the DRR/DRT line as long as data transfers are needed from/to the specific FIFO (level triggered demand transfer mode of DMA controller). It is the responsibility of the DMA controller to perform the correct amount of bus cycles. Either read cycles will be performed if the DMA transfer has been requested from the receiver, or write cycles if DMA has been requested from the transmitter. If the DMA controller provides a DMA acknowledge signal (DACK pin, input to the PASSAT), each bus cycle implicitly selects the top of the specific FIFO and neither address (via A0..A7) nor chip select need to be supplied (I/O to Memory transfers). If no DACK signal is provided, normal read/write operations (providing addresses) must be performed (Memory to Memory transfers). The PASSAT deactivates the DRR/DRT line immediately after the last read/write cycle of the data transfer has started. Preliminary Data Sheet 3-77 09.99 PEB 20525 PEF 20525 Functional Overview 3.5 Interrupt Architecture For certain events in PASSAT an interrupt can be generated, requesting the CPU to read status information from PASSAT. The interrupt line INT/INT is asserted with the output characteristics programmed in bit field 'IPC(1..0)' in register "GMODE" on page 5-109 (open drain/push pull, active low/high). Since only one interrupt request output is provided, the cause of an interrupt must be determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1, ISR2, DISR, GPISL/GPISH). GSTAR GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0 GPIS GPIM DISR Channel B Channel A DIMR ISR2 (ch A) IMR2 (ch A) ISR1 (ch A) IMR1 (ch A) ISR0 (ch A) IMR0 (ch A) Figure 3-30 Interrupt Status Registers Each interrupt indication of registers ISR0, ISR1, ISR2, DISR and GPISL/GPISH can be selectively unmasked by resetting the corresponding bit in the corresponding mask registers IMR0, IMR1, IMR2, DIMR and GPIML/GPIMH. Use of these registers depends on the selected serial mode. If bit 'VIS' in register CCR0L is set to '1', masked interrupt status bits are visible in the interrupt status registers ISR0..ISR2. Interrupts masked in registers IMR0..IMR2 will not generate an interrupt though. A read access to the interrupt status registers clears the bits. A global interrupt mask bit (bit 'GIM' in register GMODE) suppresses interrupt generation at all. To enable the interrupt system after reset, this bit must be set to '0'. Preliminary Data Sheet 3-78 09.99 PEB 20525 PEF 20525 Functional Overview The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel related interrupts and general purpose port interrupts. 3.6 General Purpose Port Pins 3.6.1 GPP Functional Description General purpose port pins are provided on pins GP6, GP8, GP9 and GP10 in P-TQFP100-3 package (not provided in P-LFBGA-80-2 package). If external DMA support is not enabled, pins GP0...GP2 are available as general purpose pins (in both P-TQFP-100-3 and P-LFBGA-80-2 package). Every pin is separately programmable via the General Purpose Port Direction registers GPDIRL/GPDIRH to operate as an output (bit GPnDIR='0') or as an input (bit GPnDIR='1', reset value). If defined as output, the state of the pin is directly controlled via the General Purpose Port Data registers GPDATL/GPDATH. Read access to these registers delivers the current state of all GPP pins (input and output signals). If defined as input, the state of the pin is monitored. The signal state of the corresponding GP pins is sampled with a rising edge of CLK and is readable via registers GPDATL/ GPDATH. 3.6.2 GPP Interrupt Indication The GPP block generates interrupts for transitions on each input signal. All changes may be indicated via interrupt (optional). To enable interrupt generation, the corresponding interrupt mask bit in registers GPIML/GPIMH must be reset to '0'. Bit PI in the gloabl interrupt status register (GSTAR) is set to '1' if an interrupt was generated by any one or more of the the general purpose port pins. The GPP pin causing the interrupt can be located by reading the GPISL/GPISH registers. Preliminary Data Sheet 3-79 09.99 PEB 20525 PEF 20525 Detailed Protocol Description 4 Detailed Protocol Description The following Table 4-1 provides an overview of all supported protocol modes and . The desired protocol mode is selected via bit fields in the channel configuration registers CCR2L and CCR3L. Table 4-1 Protocol Mode Overview Protocol Mode Register CCR2L - Bit Field: CCR3L MDS ADM PPPM ESS7 '00' '0' HDLC Automode (LAP D / LAP B / SDLC-NRM) 16 bit '00' '1' 8 bit '00' '0' HDLC Address Mode 2 16 bit '01' '1' 8 bit '01' '0' HDLC Address Mode 1 '10' '1' HDLC Address Mode 0 '10' '0' Signaling System #7 (SS7) Operation '10' '0' '00' '1' Bit Synchronous PPP Mode '10' '0' '11' '0' Octet Synchronous PPP Mode Extended Transparent Mode1) 1) '01' '11' '1' '00' '0' Extended transparent mode is a fully bit-transparent transmission/reception mode. All modes are discussed in details in this chapter. 4.1 HDLC/SDLC Protocol Modes The HDLC controller of each serial channel (SCC) can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be performed in a very flexible way satisfying almost any application specific requirements. There are 4 different HDLC operating modes which can be selected via register CCR2L. The following table provides an overview of the different address comparison mechanisms in HDLC operating modes: Preliminary Data Sheet 4-80 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Table 4-2 Mode Address Comparison Overview Address Field 16 bit Address Mode 2 Auto Mode Address Mode 1 Address Mode 0 4.1.0.1 8 bit 8 bit None Recognized Address Bytes for a Match: High Address Byte Low Address Byte FEH / FCH (1111 11 C/R 02) and RAL1 FEH / FCH (1111 11 C/R 02) and RAL2 RAH1 and RAL1 RAH2 and RAL2 RAL1 don't care RAL2 don't care FEH / FCH (1111 11 C/R 02) don't care RAH1 don't care RAH2 don't care don't care don't care Automode Characteristics: Window size 1, random message length, address recognition. The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC protocol. The HDLC control field, I-field data of the frames and an additional status byte are temporarily stored in the SCC receive FIFO. Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte address recognition. If a 2-byte address field is selected, the high address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the setting of the CRI bit in RAH1, and will be excluded from the address comparison. Similarly, two comparison values can be programmed in special registers (RAL1, RAL2) for the low address byte. A valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. Thus, the SCC can be called (addressed) with 6 different address combinations, however, only the logical connection identified through the address combination RAH1/RAL1 will be processed in the auto-mode, all others in the non auto-mode. HDLC frames with address fields that do not match any of the address combinations, are ignored by the SCC. Preliminary Data Sheet 4-81 09.99 PEB 20525 PEF 20525 Detailed Protocol Description In the case of a 1-byte address, only RAL1 and RAL2 will be used as comparison values. According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as COMMAND and the value in RAL2 as RESPONSE. The address bytes can be masked to allow selective broadcast frame recognition. For further information see "Receive Address Handling" on page 4-85. 4.1.0.2 Address Mode 2 Characteristics: address recognition, arbitrary window size. All frames with valid addresses (address recognition identical to auto-mode) are forwarded directly to the RFIFO. The HDLC control field, I-field data and an additional status byte are temporarily stored in the SCC receive FIFO. In address mode 2, all frames with a valid address are treated similarly. The address bytes can be masked to allow selective broadcast frame recognition. 4.1.0.3 Address Mode 1 Characteristics: address recognition high byte. Only the high byte of a 2-byte address field will be compared. The address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values RAH1 and RAH2. The whole frame excluding the first address byte will be stored in the SCC receive FIFO. The address bytes can be masked to allow selective broadcast frame recognition. 4.1.0.4 Address Mode 0 Characteristics: no address recognitio No address recognition is performed and each complete frame will be stored in the SCC receive FIFO. 4.1.1 HDLC Receive Data Processing The following figures give an overview about the management of the received frames in the different HDLC operating modes. The graphics show the actual HDLC frame and how PASSAT interprets the incoming octets. Below that it is shown which octets are stored in the RFIFO and will thus be transferred into memory. Preliminary Data Sheet 4-82 09.99 PEB 20525 PEF 20525 Detailed Protocol Description 16 bit ADDR Automode 16 bit FLAG (high) (low) CRC16 CTRL I-field (data) RSTA option 1) Figure 4-1 option 2) RAH1,2 RAL1,2 (address compare) RSTA HDLC Receive Data Processing in 16 bit Automode 8 bit ADDR FLAG Automode 8 bit FLAG to RFIFO registers involved (low) CRC16 CTRL /32 I-field (data) FLAG RSTA to RFIFO opt. 1) registers involved Figure 4-2 option 2) RAL1,2 (address compare) RSTA HDLC Receive Data Processing in 8 bit Automode 16 bit ADDR Address Mode 2 16 bit /32 FLAG (high) (low) /32 CRC16 data FLAG RSTA to RFIFO option 1) registers involved Figure 4-3 option 2) RSTA RAH1,2 RAL1,2 (address compare) HDLC Receive Data Processing in Address Mode 2 (16 bit) Preliminary Data Sheet 4-83 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Address Mode 2 8 bit 8 bit ADDR FLAG CRC16 (low) /32 data FLAG RSTA to RFIFO opt. 1) registers involved Figure 4-4 option 2) RSTA RAL1,2 (address compare) HDLC Receive Data Processing in Address Mode 2 (8 bit) 8 bit ADDR Address Mode 1 16 bit ADDR FLAG CRC16 data FLAG RSTA to RFIFO opt. 1) registers involved Figure 4-5 option 2) RSTA RAH1,2 (address compare) HDLC Receive Data Processing in Address Mode 1 CRC16 Address Mode 0 /32 FLAG /32 data FLAG RSTA to RFIFO option 2) registers involved Figure 4-6 RSTA HDLC Receive Data Processing in Address Mode 0 option 1) The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H) option 2) The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in register CCR3H) Preliminary Data Sheet 4-84 09.99 PEB 20525 PEF 20525 Detailed Protocol Description 4.1.2 Receive Address Handling The Receive Address Low/High Bytes (registers RAL1/RAH1 and RAL2/RAH2) can be masked on a per bit basis by setting the corresponding bits in the mask registers AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address recognition. Masked bit positions always match in comparison of the received frame address with the respective address fields in the Receive Address Low/High registers. This feature is applicable to all HDLC protocol modes with address recognition (auto mode, address mode 2 and address mode 1). It is disabled if all bits of mask bit fields AMRAL1/AMRAH1 and AMRAL2/AMRAH2 are set to `zero' (which is the reset value). Detection of the fixed group address FEH or FCH, if applicable to the selected operating mode, remains unchanged. As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit address field of received frames can be pushed to the receive data buffer (first one/two bytes of the frame). This function is especially useful in conjunction with the extended broadcast address recognition. It is enabled by setting control bit 'RADD' in register CCR3H. 4.1.3 HDLC Transmit Data Processing Two different types of frames can be transmitted: - I-frames and - transparent frames as shown below. Preliminary Data Sheet 4-85 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Frames with automatic 8 or 16 bit Address and Control Byte Generation (Automode): 8 bit ADDR 16 bitADDR FLAG CRC16 CTRL /32 data FLAG XFIFO XAD1 XAD2 internally generated option 2) registers involved Frames without automatic Address and Control Byte Generation (Address Mode 2/1/0): CRC16 FLAG /32 data FLAG XFIFO option 2) option 2) Generation of the 16 or 32 bit CRC field can optionally be disabled by setting bit 'XCRC' in register CCR2H, in which case the CRC must be calculated and written into the last 2 or 4 bytes of the transmit FIFO, to immediately proceed closing flag. Figure 4-7 SCC Transmit Data Flow (HDLC Modes) For transmission of I-frames (selected via transmit command 'XIF' in register CMDRL), the address and control fields are generated autonomously by the SCC and the data in the corresponding transmit data buffer is entered into the information field of the frame. This is possible only if the SCC is operated in Automode. For (address-) transparent frames, the address and the control fields have to be entered in the transmit data buffer by software. This is possible in all operating modes and used also in auto-mode for sending U-frames. If bit 'XCRC' in register CCR2H is set, the CRC checksum will not be generated internally. The checksum has to be provided via the transmit data buffer as the last two or four bytes by software. The transmitted frame will be closed automatically only with a (closing) flag. Preliminary Data Sheet 4-86 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Note: The SCC does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense according the HDLC protocol or not. 4.1.4 Shared Flags If the `Shared Flag' feature is enabled by setting bit 'SFLG' in register CCR1L the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one already available in the SCC transmit FIFO. In receive direction the SCC always expects and handles 'Shared Flags'. 'Shared Zeroes' of consecutive flags are also supported. 4.1.5 One Bit Insertion Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC protocol, the SCC offers a feature of inserting/deleting a 'one' after seven consecutive `zeros' into the transmit/receive data stream, if the serial channel is operating in bus configuration mode. This method is useful if clock recovery is performed by DPLL. Since only NRZ data encoding is supported in a bus configuration, there are possibly long sequences without edges in the receive data stream in case of successive `0's received, and the DPLL may lose synchronization. Enabling the one bit insertion feature by setting bit 'OIN' in register CCR2H, it is guaranteed that at least after - 5 consecutive `1's a `0' will appear (bit stuffing), and after - 7 consecutive `0's a `1' will appear (one insertion) and thus a correct function of the DPLL is ensured. Note: As with the bit stuffing, the `one insertion' is fully transparent to the user, but it is not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary systems using circuits that also implement this function, such as the PEB 20542 and PEB 20532. 4.1.6 Preamble Transmission If enabled via bit 'EPT' in register CCR2H, a programmable 8-bit pattern is transmitted with a selectable number of repetitions after Interframe Timefill transmission is stopped and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed in register PREAMB and the repetition time in bit field 'PRE' of register CCR2H. Note: Zero Bit Insertion is disabled during preamble transmission. 4.1.7 CRC Generation and Checking In HDLC/SDLC mode, error protection is done by CRC generation and checking. Preliminary Data Sheet 4-87 09.99 PEB 20525 PEF 20525 Detailed Protocol Description In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at the end of each frame consists of two bytes of CRC checksum. If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm, enabled via bit 'C32' in register CCR1L. In this case the Frame Check Sequence consists of four bytes. Optionally the internal handling of received and transmitted CRC checksum can be influenced via control bits 'RCRC', 'DRCRC' in register CCR3H and 'XCRC' in register CCR2H. Receive direction: If not disabled by setting bit 'DRCRC' (register CCR3H), the received CRC checksum is always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame, immediately preceding a closing flag. If bit 'RCRC' is set, the received CRC checksum is treated as data and will be forwarded to the RFIFO, where it precedes the frame status byte. Nevertheless the received CRC checksum is additionally checked for correctness. If CRC checking is disabled with bit CCR3H:DRCRC, the limits for `Valid Frame' check are modified accordingly (refer to description of the Receive Status Byte, RSTA:VFR). Transmit direction: If bit 'XCRC' is set, the CRC checksum is not generated internally. The checksum has to be provided via the transmit data buffer by software. The transmitted frame will only be closed automatically with a (closing) flag. Note: The SCC does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense or not according the HDLC protocol. 4.1.8 Receive Length Check Feature The SCC offers the possibility to supervise the maximum length of received frames and to terminate data reception in the case that this length is exceeded. This feature is controlled via the special Receive Length Check Registers RLCRL/ RLCRH. The function is enabled by setting bit 'RCE' (Receive Length Check Enable) and the maximum frame length to be checked is programmed via bit field 'RL'. The maximum receive length can be determined as a multiple of 32-byte blocks as follows: MAX_LENGTH = (RL + 1) x 32 , where RL is the value written to bit field 'RL'. Thus, the maximum length of receive frames can be programmed between 32 and 65536 bytes. All frames exceeding this length are treated as if they had been aborted by the remote station, i.e. the CPU is informed via - an 'RME' interrupt generated by the SCC, and - the receive abort indication 'RAB' in the Receive Status Byte (RSTA). Preliminary Data Sheet 4-88 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Additionally an optional 'FLEX' interrupt is generated prior to 'RME', indicating that the maximum receive frame length was exceeded. Receive operation continues with the beginning of the next receive frame. 4.2 Point-to-Point Protocol (PPP) Modes PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC, synchronous HDLC, and octet synchronous. The PASSAT supports bit and octet synchronous HDLC PPP for use over dial-up connections. The octet synchronous mode of PPP protocol (RFC 1662) supports PPP over SONET applications. The synchronous HDLC PPP modes are submodes of the HDLC mode. The appropriate PPP mode is selected via bit field 'PPPM' in register CCR2L. The PPP-support hardware allows software to perform segmentation and reassembly of PPP payloads, and allows PASSAT to perform the synchronous HDLC PPP protocol conversions as required for the network interface. 4.2.1 Bit Synchronous PPP The PASSAT transmits a data block, inserts HDLC Header (Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Zero-bit stuffing algorithm is also performed. No character mapping is performed. The bit-synchronous PPP mode differs from the HDLC mode (address mode 0) only in the abort sequence: HDLC requires at least 7 consecutive '1' bits as abort sequence, whereas PPP requires at least 15 '1' bits. For receive operation PASSAT monitors the incoming data stream for the Opening Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data and are processed as normal HDLC packet including checking of CRC. 4.2.2 Octet Synchronous PPP The PASSAT transmits a data block, inserts HDLC Header (Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Beside this standard HDLC operation, zero-bit stuffing is not performed, but character mapping is performed. For receive operation PASSAT monitors the incoming data stream for the Opening Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data and are processed as normal HDLC packet including checking of CRC. Received mapped characters are unmapped. 4.2.3 Data Transparency in PPP Mode When transporting bit-files (as opposed to text files), or compressed files, the characters could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the Preliminary Data Sheet 4-89 09.99 PEB 20525 PEF 20525 Detailed Protocol Description MODEM would not pass through. PASSAT maintains an Async Control Character Map (ACCM) for characters 00-1F Hex. Whenever there is a mapped character in the data stream, the transmitter precedes that character with a control-escape character of 7DH. After the control-escape, the character itself is transmitted with bit 5 inverted. character e.g. 13H is mapped to 7DH, 33H). At the receive end, a 7DH character is discarded and the following character is modified by inverting bit 5 (e.g. if 7DH, 33H is received, the 7DH is discarded and the 33H is changed to 13H the original character). The 32 lookup octet values (00H-1FH) are stored within the on-chip registers ACCM0..3. In addition to the ACCM, 4 user programmable characters (especially outside the range 00-1F Hex) can also be mapped using the control-escape sequence described above. These characters are specified in registers UDAC0..3. The receiver discards all characters which are received unmapped, but expected to be mapped because of ACCM0..3 and UDAC0..3 register contents. If this occurs within an HDLC frame, the unexpected characters are discarded before forwarded to the receive CRC checking unit. 7DH (control-escape) and 7EH (flag) octets in the data stream are mapped in general. The sequence of mapping control logic is: 1. 7DH and 7EH octets, 2. ACCM0..3, 3. UDAC0..3. This mechanism is applied to octet synchronous HDLC PPP mode. Preliminary Data Sheet 4-90 09.99 PEB 20525 PEF 20525 Detailed Protocol Description * A C C M 0..3 : A s yn c C o ntrol C hara cter M ap R e gister ACCM3 ACCM2 7 0 1F 1E ... 15 0 ... 0 0 ACCM1 3 7 0 14 13 12 0 1 0 AC CM0 7 0 7 0 11 ... 00 0 ... 0 U D A C 0..3: U se r D e fin ed A sync C ontrol C hara cter M ap R e gister 7 UDAC 3 0 7 0 UDAC 2 7E h 7 UDAC 1 7E h d a ta in tra n sm it F IF O : 0 7 U DAC0 7E h 13H 20H 01H 02H 20H 0 20h H D LC fra m in g : 7EH 13H 01H 02H 7EH PPP m a p p in g : 7EH 7D H 33H 7D H 00H 01H 02H 7EH s eria l line re ce ive d c h a ra c te r: 7E H 7D H 33H 7D H 00H 01H 02H 7EH PPP u n m a p p in g : 7EH 7EH d a ta in re ce ive F IF O : 13H 20H 01H 02H 13H 20H 01H 02H N o te : C R C g ene ratio n/ch ec k ing is as s um ed to be dis ab le d in this e xa m ple; a cc ording the P P P m ap ping/ un m app in g, C R C ch arac ters are tre ated as 'd ata' ch arac te rs be in g m a pp ed/un m app ed if n ec es s ary . Figure 4-8 PPP Mapping/Unmapping Example Preliminary Data Sheet 4-91 09.99 PEB 20525 PEF 20525 Detailed Protocol Description 4.3 Extended Transparent Mode Characteristics: fully transparent When programmed in the extended transparent mode via the CCR2L register (bits MDS1, MDS0, ADM = `111'), the SCC performs fully transparent data transmission and reception without HDLC framing, i.e. without * FLAG insertion and deletion * CRC generation and checking * bit stuffing. This feature can be profitably used e.g. for: * user specific protocol variations * line state monitoring, or * test purposes, in particular for monitoring or intentionally generating HDLC protocol rule violations (e.g. wrong CRC) Character or octet boundary synchronization can be achieved by using clock mode 5 or clock mode 1 with an external receive strobe input to pin CD. Setting invokes this out-of-band flow control for the receiver. When the shadow part of the receive FIFO has reached a set threshold of 28 bytes, the signal is forced inactive (high). When the shadow part of the receive FIFO is empty, the is re-asserted (low). Note that the data is immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as long as there is space available). So when the shadow receive FIFO reaches the 28 bytes threshold, there is 4 more byte storage available before overflow can occur. This allows sufficient time for the far end transmitter to react to the change in the signal and stop sending more data. A transmit data underrun condition in the XFIFO is indicated with an 'XDU' interrupt. Nevertheless, transmission continues inserting SYN characters into the data stream until new data is available in the transmit FIFO. Inserted SYN characters are not part of the frame and thus not used for CRC calculation. 4.4 Procedural Support (Layer-2 Functions) When operating in the auto mode, the SCC offers a high degree of protocol support. In addition to address recognition, the SCC autonomously processes all (numbered) S- and I-frames (window size 1 only) with either normal or extended control field format (modulo-8 or modulo-128 sequence numbers - selectable via register CCR2H bit 'MCS'). The following functions will be performed: - updating of transmit and receive counter - evaluation of transmit and receive counter - processing of S commands Preliminary Data Sheet 4-92 09.99 PEB 20525 PEF 20525 Detailed Protocol Description - - - - - - flow control with RR/RNR generation of responses recognition of protocol errors transmission of S commands, if acknowledgement is not received continuous status query of remote station after RNR has been received programmable timer/repeater functions. In addition, all unnumbered frames are forwarded directly to the processor. The logical link can be initialized by software at any time (Reset HDLC Receiver by RRES command in register CMDRH). Additional logical connections can be operated in parallel by software. 4.4.1 Full-Duplex LAPB/LAPD Operation Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured to function as a combined (primary/secondary) station, where they autonomously perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol. Reception of Frames: The logical processing of received S-frames is performed by the SCC without interrupting the host. The host is merely informed by interrupt of status changes in the remote station (receiver ready / receiver not ready) and protocol errors (unacceptable N(R), or S-frame with I-field). I-frames are also processed autonomously and checked for protocol errors. The I-frame will not be accepted in the case of sequence errors (no interrupt is forwarded to the host), but is immediately confirmed by an S-response. If the host sets the SCC into a `receive not ready' status, an I-frame will not be accepted (no interrupt) and an RNR response is transmitted. U-frames are always stored in the RFIFO and forwarded directly to the host. The logical sequence and the reception of a frame in auto mode is illustrated in Figure 4-9. Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the SCC checks only the least significant bit of the receive and transmit counter regardless of the selected modulo count. Preliminary Data Sheet 4-93 09.99 PEB 20525 PEF 20525 Detailed Protocol Description 1 Rec.Activ RR,REJ,SREJ Y RNR Y CRC Error or Abort ? N Y Y CRC Error or Abort ? N Y Prot. Error ? I Frame N Y Set RAB Set RRNR Int :RME 1 1 Aborted ? CRC Error ? Set CRCE Int : PCE RESET RRNR N N Y N Int : PCE Aborted ? Set RAB Prot. Error ? U Frame Y N Prot. Error ? Int : PCE N N CRC Error ? Y 1 N N Wait for Acknowledge ? Set CRCE Wait for Acknowledge ? Y Y N(R)=V(S)+1 ? N(R)=V(S)+1 ? N Y Response f=1 ? Y RESET Wait for Acknowledge V(S) = V(S) +1 RESET Wait for Acknowledge N Y V(S) = V(S) +1 N Data Overflow ? RESET Wait for Acknowledge Y Int : ALLS Set RDO Int :XMR Int : ALLS Int : ALLS N N Rec. Ready ? Int :RME Y N Command with p=1 ? Y Rec.Ready ? N(S)=V(R)+1 ? Y N Data Overflow ? Y Y Trm RR Response f=p N Trm RNR Response f=p Set RDO Int :RME N Int :RME V (R) =V(R)+1 Trm RR Response f=p ITD00230 1 Figure 4-9 Processing of Received Frames in Auto Mode Preliminary Data Sheet 4-94 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Transmission of Frames: The SCC autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit I-frames. After the frame has been transmitted, the timer is self-started, the XFIFO is inhibited, and the SCC waits for the arrival of a positive acknowledgement. This acknowledgement can be provided by means of an S- or I-frame. If no positive acknowledgement is received during time t1, the SCC transmits an Scommand (p = `1'), which must be answered by an S-response (f = `1'). If the S-response is not received, the process is performed n1 times (in HDLC known as N2, refer to register TIMR3). Upon the arrival of an acknowledgement or after the completion of this poll procedure the XFIFO is enabled and an interrupt is generated. Interrupts may be triggered by the following: * message has been positively acknowledged (ALLS interrupt) * message must be repeated (XMR interrupt) * response has not been received (TIN interrupt). In automode, only when the ALLS interrupt has been issued data of a new frame may be provided to the XFIFO! Upon arrival of an RNR frame, the software timer is started and the status of the remote station is polled periodically after expiration of t1, until the status `receive ready' has been detected. The user is informed via the appropriate interrupt. If no response is received after n1 times, a TIN interrupt, and t1 clock periods thereafter an ALLS interrupt is generated and the process is terminated. Note: The internal timer mode should only be used in the auto mode. Transparent frames can be transmitted in all operating modes. Preliminary Data Sheet 4-95 09.99 PEB 20525 PEF 20525 Detailed Protocol Description T Proc. Inactiv Rec. RNR CMDR ; STI Set RRNR Trm RR/RNR Command p=1 1 Trm I Frame Set wait for Acknowledge Load n1 Load t 1 T Proc. Activ t 1 Run Out n1 = 0 ? 2 Rec. I Frame Y Rec.RR RRNR Set ? N Response with f=1 ? Y 2 N Rec.RNR Y Load n1 N Load t 1 n1 = 7 Wait for Acknowledge ? Y ? Wait for Acknowledge ? N Y N N Y n1 = n1-1 Int : TIN Load t 1 Rec.Ready Y N N (R) = V (S)+1 ? ? Y Trm RR Command, p=1 N Trm RNR Command, p=1 1 2 1 2 ITD00231 11.06.1996 B/R Figure 4-10 Timer Procedure/Poll Cycle Preliminary Data Sheet 4-96 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Examples The interaction between SCC and the host during transmission and reception of I-frames is illustrated in the following two figures. The flow control with RR/RNR of I-frames during transmission/reception is illustrated in Figure 4-11. Both, the sequence of the poll cycle and protocol errors are shown in Figure 4-12. I (0.0) ALLS I (0.0) RR(1) WFA Transmit I Frame RNR(0) RSC(RNR) RNR t1 I (0.1) RME WFA RR(1) Reception RR(0)p=1 I Frame RNR(0)f=1 XMR t1 I (1.1) ALLS Transmit I Frame Confirm with I Frame I (1.2) ALLS WFA RR(0)p=1 RR(0)f=1 RSC(RR) RR(2) RME WFA = Wait For Acknowledge (see Status Register) Figure 4-11 Transmission/Reception of I-Frames and Flow Control Poll Cycle RNR WFA I (0.0) RNR(0) XRNR TIN t1 RRp=1 t1 RRp=1 t1 RR(0)p=1 ALLS RR(0)f=1 RR RR(0)p=1 Protocol Error I (0.0) RR(0)f=1 RME I (0.0) RR(0) RR(1) WFA ALLS PCE RR(0)p=1 RR(1) RR(2) WFA = Wait For Acknowledge (see Status Register) Figure 4-12 Flow Control: Reception of S-Commands and Protocol Errors Preliminary Data Sheet 4-97 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Protocol Error Handling: Depending on the error type, erroneous frames are handled according to Table 4-3. Table 4-3 Error Handling Frame Type Error Type Generated Response Generated Interrupt Rec. Status I CRC error Aborted Unexpected N(S) Unexpected N(R) - - S-frame - RME RME - PCE CRC error Abort - - S CRC error Aborted Unexpected N(R) With I-field - - - - - - PCE PCE - - - - Note: The station variables ( V(S), V(R) ) are not changed. 4.4.2 Half-Duplex SDLC-NRM Operation The LAP controllers of the two serial channels can be configured to function in a halfduplex Normal Response Mode (NRM), where they operate as a slave (secondary) station, by setting the NRM bit in the CCR2L register of the corresponding channel. In contrast to the full-duplex LAP B/LAP D operation, where the combined (primary + secondary) station transmits both commands and responses and may transmit data at any time, the NRM mode allows only responses to be transmitted and the secondary station may transmit only when instructed to do so by the master (primary) station. The SCC gets the permission to transmit from the primary station via an S-, or Iframe with the poll bit (p) set. The NRM mode can be profitably used in a point-to-multipoint configuration with a fixed master-slave relationship, which guarantees the absence of collisions on the common transmit line. It is the responsibility of the master station to poll the slaves periodically and to handle error situations. Prerequisite for NRM operation is: - auto mode with 8-bit address field selected Register CCR2L bit fields 'MDS1', 'MDS0', 'ADM' = `000' - Register TIMR3 bit 'TMD' = `0' - same transmit and receive addresses, since only responses can be transmitted, i.e. Register XAD1 = XAD2 and register RAL1 = RAL2 (address of secondary). Preliminary Data Sheet 4-98 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Note: The broadcast address may be programmed in register RAL2 if broadcasting is required. In this case registers RAL1 and RAL2 are not equal. The primary station has to operate in transparent HDLC mode. Reception of Frames: The reception of frames functions similarly to the LAPB/LAPD operation (see "FullDuplex LAPB/LAPD Operation" on page 4-93). Transmission of Frames: The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station via an S-, or I-frame with the poll bit set. The SCC can be told to send an I-frame issuing the transmit command 'XIF' in register CMDRL. The transmission of the frame, however, will not be initiated by the SCC until reception of either an * RR, or * I-frame with poll bit set (p = `1'). After the frame has been transmitted (with the final bit set), the host has to wait for an ALLS or XMR interrupt. A secondary does not poll the primary for acknowledgements, thus timer supervision must be done by the primary station. Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an interrupt is forwarded to the host, either the - message has been positively acknowledged (ALLS interrupt), or the - message must be repeated (XMR interrupt). Additionally, the on-chip timer can be used under host control to provide timer recovery of the secondary if no acknowledgements are received at all. Note: A secondary will transmit transparent frames only if the permission to send is given by receiving an S-frame or I-frame with poll bit set (p = `1'). Examples: A few examples of SCC/host interaction in the case of normal response mode (NRM) mode are shown in Figure 4-13 and Figure 4-14. Preliminary Data Sheet 4-99 09.99 PEB 20525 PEF 20525 Detailed Protocol Description XIF RR(0)p=1 I (0,0)p=1 RME I(0,1)f=1 RR(0)f=1 I (1,1)p=1 ALLS RR(2)f=1 ITD00237 Primary Secondary ITD01800 Figure 4-13 No Data to Send: Data Reception/Transmission XIF XIF RR(0)p=1 RR(0)p=1 I (0,0)f=1 I (0,0)f=1 t RR(0)p=1 RR(1)p=0 ALLS XMR RR(0)f=1 ITD00238 ITD01801 Figure 4-14 4.4.3 Data Transmission (without error), Data Transmission (with error) Signaling System #7 (SS7) Operation The PASSAT supports the signaling system #7 (SS7) which is described in ITU-Q.703. SS7 support must be activated by setting bit 'ESS7' in register CCR3L. Preliminary Data Sheet 4-100 09.99 PEB 20525 PEF 20525 Detailed Protocol Description Receive The SS7 protocol is supported by the following hardware features in receive direction: * Recognition of Signaling Unit type * Discard of repeatedly received FISUs and LSSUs if content is unchanged (optional) * Check if the length of the received signaling unit is at least six octets (including the opening flag) * Check if the signal information field of a received signaling unit consists of more than 272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current signaling unit will be aborted. * Counting and processing of errored signaling units In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed automatically. By examining the length indicator of a received Signal Unit (SU) PASSAT decides whether a FISU has been received. Consecutively received FISUs will be compared and optionally not stored in the RFIFO, if the content is equal to the previous one. The same applies to Link Status Signaling Units (LSSUs), if enabled with bit CCR3L.CSF. The different types of Signaling Units as Message Signaling Unit (MSU), Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated in the RSTA byte (bit field 'SU'), which is automatically added to the RFIFO with each received Signaling Unit. The complete Signaling Unit except start and end flags is stored in the receive FIFO. The functions of bits CCR3H.RCRC and CCR3H.RADD are also valid in SS7 mode, with bit 'RADD' related to BSN (backward sequence number) and FSN (forward sequence number). Errored signaling units are counted and processed according to ITU-T Q.703. The SU counter and errored-SU counter are reset by setting CMDRH.RSUC to '1'. The error threshold can be selected to be 64 (default) or 32 by clearing/setting bit CCR3L.SUET. If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not masked by bit IMR1.SUEX. Transmit In transmit direction, following features are supported: * single or repetitive transmission of signaling units * automatic generation of Fill-In Signaling Units (FISU) Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been transmitted completely, PASSAT optionally starts sending of Fill In Signaling Units (FISUs) containing the forward sequence number (FSN) and the backward sequence number (BSN) of the previously transmitted signaling unit. Setting bit CCR3L.AFX to '1' causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has been initiated, the current FISU is completed and the new SU is sent. After this, Preliminary Data Sheet 4-101 09.99 PEB 20525 PEF 20525 Detailed Protocol Description transmission of FISUs continues. The internally generated FISUs contain FSN and BSN of the last transmitted signaling unit written to XFIFO. Using CMDRL.XREP='1', the contents of XFIFO (1..32 bytes) can be sent continuously. This cyclic transmission can be stopped with the CMDRL.XRES command. Preliminary Data Sheet 4-102 09.99 PEB 20525 PEF 20525 Register Description 5 Register Description 5.1 Register Overview The PASSAT global registers are used to configure and control the Serial Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation. All registers are 8-bit organized registers, but grouped and optimized for 16 bit access. 16 bit access (P-TQFP-100-3 package) is supported to even addresses only. Table 5-1 provides an overview about all on-chip registers: Table 5-1 Register Overview Offset Register Ch A Ch B read write Res Meaning Val Page Global registers: 00H GCMDR 00H Global Command Register 5-108 01H GMODE 0FH Global Mode Register 5-109 02H Reserved 03H GSTAR 00H Global Status Register 5-112 04H GPDIRL 07H GPP Direction Register (Low Byte) 5-114 05H GPDIRH FFH GPP Direction Register (High Byte) 5-114 06H GPDATL - GPP Data Register (Low Byte) 5-116 07H GPDATH - GPP Data Register (High Byte) 5-116 08H GPIML 07H GPP Interrupt Mask Register (Low Byte) 5-118 09H GPIMH FFH GPP Interrupt Mask Register (High Byte) 5-118 0AH GPISL 00H GPP Interrupt Status Register (Low Byte) 5-120 0BH GPISH 00H GPP Interrupt Status Register (High Byte) 5-120 0CH DCMDR 0DH Reserved 0EH 0FH 00H DMA Command Register 5-122 DISR 00H DMA Interrupt Status Register 5-123 DIMR 77H DMA Interrupt Mask Register 5-124 - Receive/Transmit FIFO (Low Byte) 5-125 - Receive/Transmit FIFO (High Byte) 5-125 Channel specific registers: 10H 60H 11H 61H RFIFO Preliminary Data Sheet XFIFO 5-103 09.99 PEB 20525 PEF 20525 Register Description Table 5-1 Register Overview (cont'd) Offset Register Ch A Ch B read write Res Meaning Val Page 12H 62H STARL 00H Status Register (Low Byte) 5-128 13H 63H STARH 10H Status Register (High Byte) 5-128 14H 64H CMDRL 00H Command Register (Low Byte) 5-132 15H 65H CMDRH 00H Command Register (High Byte) 5-132 16H 66H CCR0L 00H Channel Configuration Register 0 (Low Byte) 5-136 17H 67H CCR0H 00H Channel Configuration Register 0 (High Byte) 5-136 18H 68H CCR1L 00H Channel Configuration Register 1 (Low Byte) 5-139 19H 69H CCR1H 00H Channel Configuration Register 1 (High Byte) 5-139 1AH 6AH CCR2L 00H Channel Configuration Register 2 (Low Byte) 5-144 1BH 6BH CCR2H 00H Channel Configuration Register 2 (High Byte) 5-144 1CH 6CH CCR3L 00H Channel Configuration Register 3 (Low Byte) 5-149 1DH 6DH CCR3H 00H Channel Configuration Register 3 (High Byte) 5-149 1EH 6EH PREAMB 00H Preamble Register 5-153 1FH 6FH Reserved 20H 70H ACCM0 00H PPP ASYNC Control Character Map 0 5-154 21H 71H ACCM1 00H PPP ASYNC Control Character Map 1 5-154 22H 72H ACCM2 00H PPP ASYNC Control Character Map2 5-155 23H 73H ACCM3 00H PPP ASYNC Control Character Map 3 5-155 24H 74H UDAC0 7EH User Defined PPP ASYNC Control Character Map 0 5-157 25H 75H UDAC1 7EH User Defined PPP ASYNC Control Character Map 1 5-157 26H 76H UDAC2 7EH User Defined PPP ASYNC Control Character Map 2 5-158 Preliminary Data Sheet 5-104 09.99 PEB 20525 PEF 20525 Register Description Table 5-1 Register Overview (cont'd) Offset Register Ch A Ch B read write Res Meaning Val Page 27H 77H UDAC3 7EH User Defined PPP ASYNC Control Character Map 3 5-158 28H 78H TTSA0 00H Transmit Time Slot Assignment Register 0 5-160 29H 79H TTSA1 00H Transmit Time Slot Assignment Register 1 5-160 2AH 7AH TTSA2 00H Transmit Time Slot Assignment Register 2 5-161 2BH 7BH TTSA3 00H Transmit Time Slot Assignment Register 3 5-161 2CH 7CH RTSA0 00H Receive Time Slot Assignment Register 0 5-163 2DH 7DH RTSA1 00H Receive Time Slot Assignment Register 1 5-163 2EH 7EH RTSA2 00H Receive Time Slot Assignment Register 2 5-164 2FH 7FH RTSA3 00H Receive Time Slot Assignment Register 3 5-164 30H 80H PCMTX0 00H PCM Mask Transmit Direction Register 0 5-166 31H 81H PCMTX1 00H PCM Mask Transmit Direction Register 1 5-166 32H 82H PCMTX2 00H PCM Mask Transmit Direction Register 2 5-167 33H 83H PCMTX3 00H PCM Mask Transmit Direction Register 3 5-167 34H 84H PCMRX0 00H PCM Mask Receive Direction Register 0 5-169 35H 85H PCMRX1 00H PCM Mask Receive Direction Register 1 5-169 36H 86H PCMRX2 00H PCM Mask Receive Direction Register 2 5-170 37H 87H PCMRX3 00H PCM Mask Receive Direction Register 3 5-170 38H 88H BRRL 00H Baud Rate Register (Low Byte) 5-172 39H 89H BRRH 00H Baud Rate Register (High Byte) 5-172 3AH 8AH TIMR0 00H Timer Register 0 5-174 3BH 8BH TIMR1 00H Timer Register 1 5-174 3CH 8CH TIMR2 00H Timer Register 2 5-175 3DH 8DH TIMR3 00H Timer Register 3 5-175 3EH 8EH XAD1 00H Transmit Address 1 Register 5-178 3FH 8FH XAD2 00H Transmit Address 2 Register 5-178 40H 90H RAL1 00H Receive Address 1 Low Register 5-180 41H 91H RAH1 00H Receive Address 1 High Register 5-180 42H 92H RAL2 00H Receive Address 2 Low Register 5-181 43H 93H RAH2 00H Receive Address 2 High Register 5-181 Preliminary Data Sheet 5-105 09.99 PEB 20525 PEF 20525 Register Description Table 5-1 Register Overview (cont'd) Offset Register Ch A Ch B read write Res Meaning Val Page 44H 94H AMRAL1 00H Mask Receive Address 1 Low Register 5-183 45H 95H AMRAH1 00H Mask Receive Address 1 High Register 5-183 46H 95H AMRAL2 00H Mask Receive Address 2 Low Register 5-184 47H 96H AMRAH2 00H Mask Receive Address 2 High Register 5-184 48H 98H RLCRL 00H Receive Length Check Register (Low Byte) 5-186 49H 99H RLCRH 00H Receive Length Check Register (High Byte) 5-186 4AH 9AH Reserved ... 4FH 9FH 50H A0H ISR0 00H Interrupt Status Register 0 5-188 51H A1H ISR1 00H Interrupt Status Register 1 5-188 52H A2H ISR2 00H Interrupt Status Register 2 5-189 53H A3H Reserved 54H A4H IMR0 FFH Interrupt Mask Register 0 5-194 55H A5H IMR1 FFH Interrupt Mask Register 1 5-194 56H A6H IMR2 03H Interrupt Mask Register 2 5-195 57H A7H Reserved 58H A8H RSTA 00H Receive Status Byte 5-197 59H A9H ... 5FH Reserved AFH Channel specific DMA registers: B0H CAH Reserved ... B7H D1H B8H D2H XBCL 00H Transmit Byte Count (Low Byte) 5-202 B9H D3H XBCH 00H Transmit Byte Count (High Byte) 5-202 BAH D4H Preliminary Data Sheet 5-106 09.99 PEB 20525 PEF 20525 Register Description Table 5-1 Register Overview (cont'd) Offset Register Ch A Ch B read write Res Meaning Val Page Reserved ... C3H DDH C4H DEH RMBSL 00H Receive Maximum Buffer Size (Low Byte) 5-204 C5H DFH RMBSH 00H Receive Maximum Buffer Size (High Byte) 5-204 C6H E0H RBCL 00H Receive Byte Count (Low Byte) 5-206 C7H E1H RBCH 00H Receive Byte Count (High Byte) 5-206 C8H E2H Reserved C9H E3H Reserved Miscellaneous: E4H ... Reserved EBH ECH VER0 03H Version Register 0 5-208 EDH VER1 F0H Version Register 1 5-208 EEH VER2 05H Version Register 2 5-209 EFH VER3 10H Version Register 3 5-209 Preliminary Data Sheet 5-107 09.99 PEB 20525 PEF 20525 Register Description 5.2 Detailed Register Description 5.2.1 Global Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), offset address and usual handling; * a table containing the bit information (name of bit positions); * a section containing the detailed description of each bit. Register 5-1 GCMDR Global Command Register CPU Accessibility: read/write Reset Value: 00H Offset Address: 00H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 0 0 SWR Global Command Bits 0 SWR 0 0 0 0 Software Reset Command Self clearing command bit: bit='0' No software reset command is issued. bit='1' Causes PASSAT to perform a complete reset identical to hardware reset. Preliminary Data Sheet 5-108 09.99 PEB 20525 PEF 20525 Register Description (GMODE) Register 5-2 GMODE Global Mode Register CPU Accessibility: read/write Reset Value: 0FH Offset Address: 01H typical usage: written by CPU evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 DSHP GIM DMA and Global Interrupt Control 0 EDMA EDMA IPC(1:0) OSCPD Reserved Enable External DMA Support This bit field controls the DMA operation mode: IPC(1:0) EDMA='0' The external DMA controller support functions are disabled. PASSAT is operated in standard register access controlled mode. EDMA='1' External DMA controller support functions are enabled. Interrupt-Port Configuration These bits control the function of interrupt output pin INT/INT: IPC(1:0) Output Function: '00' Open Drain active low '01' Push/Pull active low '10' Reserved. '11' Push/Pull active high Preliminary Data Sheet 5-109 09.99 PEB 20525 PEF 20525 Register Description (GMODE) OSCPD Oscillator Power Down Setting this bit to '0' enables the internal oscillator. For power saving purposes (escpecially if clock modes are used which do not need the internal oscillator) this bit may remain set to '1'. OSCPD='0' The internal oscillator is active. OSCPD='1' The internal oscillator is in power down mode. Note: After reset this bit is set to '1', i.e. the oscillator is in power down mode! Reserved Reserved Bit The reset value of this bit is '1'. It should be set to '0' during configuration in any case. Note: This bit is a redundant control bit for the shaper in the oscillator unit. In later revisions of PASSAT the shaper will be controlled with bit 'DSHP' only! DSHP Disable Shaper This bit has to be set to '0' if the shaping function in the oscillator unit is desired. The shaper amplifies the oscillator signal and improves the slope of the clock edges. DSHP='0' Shaper is enabled. Recommended setting if a crystal is connected to pins XTAL1/XTAL2. DSHP='1' Shaper is disabled (bypassed). Recommended setting if - a TTL level clock signal is supplied to pin XTAL1 - the oscillator unit is unused Note: (1) After reset this bit is set to '1', i.e. the shaper is disabled! (2) For correct operation the reserved bit 2 must be set to '0' (in later revisions the shaper will be controlled with bit 'DSHP' only)! Preliminary Data Sheet 5-110 09.99 PEB 20525 PEF 20525 Register Description (GMODE) GIM Global Interrupt Mask This bits disables all interrupt indications via pin INT/INT. Internal operation (interrupt generation, interrupt status register update,...) is not affected. If set, pin INT/INT immediately changes or remains in inactive state. GIM='0' Global interrupt mask is cleared. Pin INT/INT is controlled by the internal interrupt control logic and activated as long as at least one unmasked interrupt indication is pending (not yet confirmed by read access to corresponding interrupt status register). GIM='1' Global interrupt mask is set. Pin INT/INT remains inactive. Note: After reset this bit is set to '1', i.e. all interrupts are disabled! Preliminary Data Sheet 5-111 09.99 PEB 20525 PEF 20525 Register Description (GSTAR) Register 5-3 GSTAR Global Status Register CPU Accessibility: read/write Reset Value: 00H Offset Address: 03H typical usage: written by PASSAT evaluated by CPU Bit 7 6 5 4 3 2 1 0 ISB1 ISB0 Global Interrupt Status Information GPI GPI DMI ISA2 ISA1 ISA0 ISB2 General Purpose Port Indication (-) This bit indicates, that a GPP port interrupt indication is pending: DMI GPI='0' No general purpose port interrupt indication is pending. GPI='1' General purpose port interrupt indication is pending. The source for this interrupt can be further determined by reading registers GPISL/GPISH (refer to page 5-120). DMA Interrupt Indication (-) This bit indicates, that a DMA interrupt indication is pending: DMI='0' No DMA interrupt indication is pending. DMI='1' DMA interrupt indication is pending. The source for this interrupt (channel A/B, receive/transmit) can be further determined by reading register DISR (refer to page 5123). Preliminary Data Sheet 5-112 09.99 PEB 20525 PEF 20525 Register Description (GSTAR) ISA2 Channel A Interrupt Status Register 2 ISA1 Channel A Interrupt Status Register 1 ISA0 Channel A Interrupt Status Register 0 ISB2 Channel B Interrupt Status Register 2 ISB1 Channel B Interrupt Status Register 1 ISB0 Channel B Interrupt Status Register 0 These bits indicate, that an interrupt indication is pending in the corresponding interrupt status register(s) ISR0/ISR1/ISR2 of the serial communication controller (SCC): bit='0' No interrupt indication is pending. bit='1' An interrupt indication is pending. Preliminary Data Sheet 5-113 09.99 PEB 20525 PEF 20525 Register Description (GPDIRL) Register 5-4 GPDIRL GPP Direction Register (Low Byte) CPU Accessibility: read/write Reset Value: 07H Offset Address: 04H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 GP10DIR GP9DIR GP8DIR 2 1 0 GP2DIR GP1DIR GP0DIR GPP I/O Direction Control 0 0 Register 5-5 0 0 0 GPDIRH GPP Direction Register (High Byte) CPU Accessibility: read/write Reset Value: FFH Offset Address: 05H typical usage: written by CPU evaluated by PASSAT Bit 7 6 5 4 3 GPP I/O Direction Control 1 GP6DIR Preliminary Data Sheet 1 1 5-114 1 09.99 PEB 20525 PEF 20525 Register Description (GPDIRH) GPnDIR GPP Pin n Direction Control (-) This bit selects between input and output function of the corresponding GPP pin: bit = '0' output bit = '1' input (reset value) Preliminary Data Sheet 5-115 09.99 PEB 20525 PEF 20525 Register Description (GPDATL) Register 5-6 GPDATL GPP Data Register (Low Byte) CPU Accessibility: read/write Reset Value: - Offset Address: 06H typical usage: written by CPU(outputs) and PASSAT(inputs), evaluated by PASSAT(outputs) and CPU(inputs) Bit 7 6 5 4 3 2 1 0 GPP Data I/O - - Register 5-7 - - - GP10DAT GP9DAT GP8DAT GPDATH GPP Data Register (High Byte) CPU Accessibility: read/write Reset Value: - Offset Address: 07H typical usage: written by CPU(outputs) and PASSAT(inputs), evaluated by PASSAT(outputs) and CPU(inputs) Bit 7 6 5 4 3 2 1 0 GPP Data I/O - GP6DAT Preliminary Data Sheet - - 5-116 - GP2DAT GP1DAT GP0DAT 09.99 PEB 20525 PEF 20525 Register Description (GPDATH) GPnDAT GPP Pin n Data I/O Value (-) This bit indicates the value of the corresponding GPP pin: bit = '0' If direction is input: input level is 'low'; if direction is output: output level is 'low'. bit = '1' If direction is input: input level is 'high'; if direction is output: output level is 'high'. Preliminary Data Sheet 5-117 09.99 PEB 20525 PEF 20525 Register Description (GPIML) Register 5-8 GPIML GPP Interrupt Mask Register (Low Byte) CPU Accessibility: read/write Reset Value: 07H Offset Address: 08H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 GP10IM GP9IM GP8IM 2 1 0 GP2IM GP1IM GP0IM GPP Interrupt Mask Bits 0 Register 5-9 0 0 0 0 GPIMH GPP Interrupt Mask Register (High Byte) CPU Accessibility: read/write Reset Value: FFH Offset Address: 09H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 GPP Interrupt Mask Bits 1 GP6IM Preliminary Data Sheet 1 1 5-118 1 09.99 PEB 20525 PEF 20525 Register Description (GPIMH) GPnIM GPP Pin n Interrupt Mask (-) This bit controls the interrupt mask of the corresponding GPP pin: bit = '0' Interrupt generation is enabled. An interrupt is generated on any state transition of the corresponding port pin (inputs). bit = '1' Interrupt generation is disabled (reset value). Preliminary Data Sheet 5-119 09.99 PEB 20525 PEF 20525 Register Description (GPISL) Register 5-10 GPISL GPP Interrupt Status Register (Low Byte) CPU Accessibility: read/write Reset Value: 00H Offset Address: 0AH typical usage: written by PASSAT, read and evaluated by CPU Bit 7 6 5 4 3 2 1 0 GP10I GP9I GP8I 2 1 0 GP2I GP1I GP0I GPP Interrupt Status Bits 0 Register 5-11 0 0 0 0 GPISH GPP Interrupt Status Register (High Byte) CPU Accessibility: read/write Reset Value: 00H Offset Address: 0BH typical usage: written by PASSAT, read and evaluated by CPU Bit 7 6 5 4 3 GPP Interrupt Status Bits 0 GP6I Preliminary Data Sheet 0 0 5-120 0 09.99 PEB 20525 PEF 20525 Register Description (GPISH) GPnI GPP Pin n Interrupt Indiction (-) This bit indicates if an interrupt event occured on the corresponding GPP pin: bit = '0' No interrupt indication is pending at this pin (no state transition has occured). bit = '1' An interrupt indication is pending (a state transition occured). The interrupt indication is cleared after read access. Preliminary Data Sheet 5-121 09.99 PEB 20525 PEF 20525 Register Description (DCMDR) Register 5-12 DCMDR DMA Command Register CPU Accessibility: read/write Reset Value: 00H Offset Address: 0CH typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 RDRA 0 DMA Controller Reset Command Bits RDTB 0 RDRB 0 RDTB Reset DMA Transmit Channel B RDRB Reset DMA Receive Channel B RDTA Reset DMA Transmit Channel A RDRA Reset DMA Receive Channel A RDTA 0 Self-clearing command bit. These bits bring the external DMA support logic to the reset state: bit='0' No reset is performed. bit='1' Reset is performed. Preliminary Data Sheet 5-122 09.99 PEB 20525 PEF 20525 Register Description (DISR) Register 5-13 DISR DMA Interrupt Status Register CPU Accessibility: read/write Reset Value: 00H Offset Address: 0EH typical usage: written by PASSAT, evaluated by CPU Bit 7 6 5 4 3 2 1 0 RBFA RDTEA TDTEA DMA Interrupt Status Register 0 RBFB RDTEB TDTEB RBFB Receive Buffer Full Channel B RBFA Receive Buffer Full Channel A 0 If a receive buffer size is defined in registers RMBSL/RMBSH and during reception the end of the receive buffer is reached this interrupt is generated indicating that the receive buffer is full. If the external DMA controller supports length protection for receive buffers itself this interrupt is obsolete. In that case, the receive buffer length check can be disabled by settin bit RMBSH:DRMBS to '1'. RDTEB Receive DMA Transfer End Channel B RDTEA Receive DMA Transfer End Channel A This bit set to '1' indicates that a DMA transfer of receive data is finished and the receive data is completely moved to the corresponding receive buffer in host memory. TDTEB Transmit DMA Transfer End Channel B TDTEA Transmit DMA Transfer End Channel A This bit set to '1' indicates that the data is completely moved from the transmit buffer to the on-chip transmit FIFO, i.e. the transmit byte count programmed in registers XBCL/XBCH is reached. Preliminary Data Sheet 5-123 09.99 PEB 20525 PEF 20525 Register Description (DIMR) Register 5-14 DIMR DMA Interrupt Mask Register CPU Accessibility: read/write Reset Value: 77H Offset Address: 0FH typical usage: Bit 7 6 5 4 3 2 1 0 DMA Interrupt Mask Register 0 MRBFB MRDTEB MTDTEB 0 MRBFA MRDTEA MTDTEA MRBFB Mask Receive Buffer Full Interrupt Channel B MRBFA Mask Receive Buffer Full Interrupt Channel A MRDTEB Mask Receive DMA Transfer End Interrupt Channel B MRDTEA Mask Receive DMA Transfer End Interrupt Channel A MTDTEB Mask Transmit DMA Transfer End Interrupt Channel B MTDTEA Mask Transmit DMA Transfer End Interrupt Channel A If a bit in this interrupt mask register is set to '1', the corresponding interrupt is not generated and not indicated in the corresponding bit position in the DISR register. After reset all interrupts are masked. Preliminary Data Sheet 5-124 09.99 PEB 20525 PEF 20525 Register Description (FIFOL) 5.2.2 Channel Specific SCC Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), channel specific offset addresses and usual handling; * a table containing the bit information (name of bit positions); * a section containing the detailed description of each bit. Register 5-15 FIFOL Receive/Transmit FIFO (Low Byte) CPU Accessibility: read/write Reset Value: Channel A Channel B Offset Address: 10H 60H typical usage: XFIFO: written by CPU, evaluated by PASSAT RFIFO: written by PASSAT, evaluated by CPU Bit 7 6 5 4 3 2 1 0 1 0 RFIFO/XFIFO Access Low Byte FIFO(7:0) Register 5-16 FIFOH Receive/Transmit FIFO (High Byte) CPU Accessibility: read/write Reset Value: Channel A Channel B Offset Address: 11H 61H typical usage: XFIFO: written by CPU, evaluated by PASSAT RFIFO: written by PASSAT, evaluated by CPU Bit 7 6 5 4 3 2 RFIFO/XFIFO Access High Byte FIFO(15:8) Preliminary Data Sheet 5-125 09.99 PEB 20525 PEF 20525 Register Description (FIFOH) Receive FIFO (RFIFO) Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal 'WIDTH'. Note: The 'WIDTH' signal is available for the P-TQFP-100-3 package only. With the PLFBGA-80-2 package only 8-bit accesses are supported. The size of the accessible part of RFIFO is determined by programming the RFIFO threshold level in bit field CCR3H.RFTH(1:0). The threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. * Interrupt Controlled Data Transfer (GMODE.EDMA='0') Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF or an RME interrupt (see ISR0 register). The address provided during an RFIFO read access is not incremental; it is always 10H for channel A or 60H for channel B. RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is reached. The message is not yet complete. A fix number of bytes, dependent from the threshold level, has to be read. RME Interrupt: The message is completely received. The number of valid bytes is determined by reading the RBCL, RBCH registers. The content of the RFIFO is released by issuing the "Receive Message Complete" command (CMDRH.RMC). * DMA Controlled Data Transfer (GMODE.EDMA='1') If DMA operation is enabled, the PASSAT autonomously requests data transfer by asserting the DRR line to the external DMA controller. The DRR line remains active until the beginning of the last receive data byte/word transfer. For a detailed decription of the external DMA interface operation refer to "External DMA Controller Support" on page 377. Transmit FIFO (XFIFO) Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal 'WIDTH'. Note: The 'WIDTH' signal is available for the P-TQFP-100-3 package only. With the PLFBGA-80-2 package only 8-bit accesses are supported. * Interrupt Controlled Data Transfer (GMODE.EDMA='0') Following an XPR (or an ALLS) interrupt, up to 32 bytes/16 words of new transmit data can be written into the XFIFO. Transmit data can be released for transmission with an XTF command. The address provided during an XFIFO write access is not incremental; it is always 10H for channel A or 60H for channel B. Preliminary Data Sheet 5-126 09.99 PEB 20525 PEF 20525 Register Description (FIFOH) * DMA Controlled Data Transfer (GMODE.EDMA='1') If DMA operation is enabled, the PASSAT autonomously requests data transfer to the XFIFO by asserting the DRT line to the external DMA controller. The DRT line remains active until the beginning of the last transmit data byte/word transfer. For a detailed decription of the external DMA interface operation refer to "External DMA Controller Support" on page 3-77. Preliminary Data Sheet 5-127 09.99 PEB 20525 PEF 20525 Register Description (STARL) Register 5-17 STARL Status Register (Low Byte) CPU Accessibility: read only Reset Value: 00H Channel A Channel B Offset Address: 12H 62H typical usage: updated by PASSAT read and evaluated by CPU Bit 7 6 5 4 3 Command Status XREPE Register 5-18 1 0 Transmitter Status 0 0 2 CEC 0 XDOV XFW CTS 3 2 1 0 STARH Status Register (High Byte) CPU Accessibility: read only Reset Value: 10H Channel A Channel B Offset Address: 13H 63H typical usage: updated by PASSAT read and evaluated by CPU Bit 7 6 5 4 Receiver Status 0 Preliminary Data Sheet 0 CD Automode Status RLI 5-128 DPLA WFA XRNR RRNR 09.99 PEB 20525 PEF 20525 Register Description (STARH) XREPE CEC Transmit Repetition Executing XREPE='0' No transmit repetition command is in execution. XREPE='1' A XREP command (register CMDRL) is currently in execution. Command Executing CEC='0' No command is currently in execution. The command registers CMDRL/CMDRH can be written by CPU. CEC='1' A command (written previously to registers CMDRL/ CMDRH) is currently in execution. No further command can be written to registers CMDRL/CMDRH by CPU. Note: CEC will be active at most 2.5 receive or transmit clock cycles (depending on whether a receiver or transmitter related command is executed). CEC will stay active if the SCC is in power-down mode or if no serial clock, needed for command execution, is available. XDOV XFW Transmit FIFO Data Overflow XDOV='0' Less than or equal to 32 bytes have been written to the XFIFO. XDOV='1' More than 32 bytes have been written to the XFIFO. This bit is reset by: - a transmitter reset command 'XRES' - or when all bytes in the accessible half of the XFIFO have been moved into the inaccessible half. Transmit FIFO Write Enable XFW='0' The XFIFO is not able to accept further transmit data. XFW='1' Transmit data can be written to the XFIFO. Preliminary Data Sheet 5-129 09.99 PEB 20525 PEF 20525 Register Description (STARH) CTS CTS (Clear To Send) Input Signal State CTS='0' CTS input signal is inactive (high level) CTS='1' CTS input signal is active (low level) Note: A transmit clock must be provided in order to detect the signal state of the CTS input pin. Optionally this input can be programmed to generate an interrupt on signal level changes. CD CD (Carrier Detect) Input Signal State CD='0' CD input signal is low. CD='1' CD input signal is high. Note: A receive clock must be provided in order to detect the signal state of the CD input pin. Optionally this input can be programmed to generate an interrupt on signal level changes. RLI Receive Line Inactive This bit indicates that neither flags as interframe time fill nor data are being received via the receive line. RLI='0' Receive line is active, no constant high level is detected. RLI='1' Receive line is inactive, i.e. more than 7 consecutive '1' are detected on the line. Note: A receive clock must be provided in order to detect the receive line state. DPLA DPLL Asynchronous This bit is only valid if the receive clock is recovered by the DPLL and FM0, FM1 or Manchester data encoding is selected. It is set when the DPLL has lost synchronization. In this case reception is disabled (receive abort condition) until synchronization has been regained. In addition transmission is interrupted in all cases where transmit clock is derived from the DPLL (clock mode 3a, 7a). Interruption of transmission is performed the same way as on deactivation of the CTS signal. DPLA='0' DPLL is synchronized. DPLA='1' DPLL is asynchronous (re-synchronization process is started automatically). Preliminary Data Sheet 5-130 09.99 PEB 20525 PEF 20525 Register Description (STARH) WFA Wait For Acknowledgement This status bit is significant in Automode only. It indicates whether the Automode state machine expects an acknowledging I- or S-Frame for a previously sent I-Frame. XRNR WFA='0' No acknowledge I/S-Frame is expected. WFA='1' The Automode state machine is waiting for an achnowledging S- or I-Frame. Transmit RNR Status This status bit is significant in Automode only. It indicates the receiver status of the local station (SCC). RRNR XRNR='0' The receiver is ready and will automatically answer pollframes with a S-Frame with 'receiver-ready' indication. XRNR='1' The receiver is NOT ready and will automatically answer poll-frames with a S-Frame with a 'receiver-not-ready' indication. Received RNR (Receiver Not Ready) Status This status bit is significant in Automode only. It indicates the receiver status of the remote station. RRNR='0' The remote station receiver is ready. RRNR='1' The remote receiver is NOT ready. (A 'receiver-not-ready' indication was received from the remote station) Preliminary Data Sheet 5-131 09.99 PEB 20525 PEF 20525 Register Description (CMDRL) Register 5-19 CMDRL Command Register (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 14H 64H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 Timer STI Register 5-20 3 2 0 XREP 0 2 1 0 0 0 RRES Transmitter Commands TRES XIF XRES XF XME CMDRH Command Register (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 15H 65H typical usage: written by CPU, evaluated by PASSAT Bit 1 7 6 5 4 3 Receiver Commands RMC RNR Preliminary Data Sheet 0 0 5-132 RSUC 09.99 PEB 20525 PEF 20525 Register Description (CMDRH) STI Start Timer Command Self-clearing command bit: HDLC Automode: In HDLC Automode the timer is used internally for the autonomous protocol support functions. The timer is started automatically by the SCC when an I-Frame is sent out and needs to be acknowledged. If the 'STI' command is issued by software: STI='1' An S-Frame with poll bit set is sent out and the internal timer is started expecting an acknowledge from the remote station via an I- or S-Frame. The timer is stopped after receiving an acknowledge otherwise the timer expires generating a timer interrupt. Note: In HDLC Automode, bit 'TMD' in register TIMR3 must be set to '1' All protocol modes except HDLC Automode: In these modes the timer is operating as a general purpose timer. STI='1' This commands starts timer operation. The timer can be stopped by setting bit 'TRES'. Note: Bit 'TMD' in register TIMR3 must be cleared for proper operation TRES Timer Reset Self-clearing command bit. This bit deactivates timer operation: XIF TRES='0' Timer operation enabled. TRES='1' Timer operation stopped. Transmit I-Frame Self-clearing command bit. This command bit is significant in HDLC Automode only. XIF='1' Preliminary Data Sheet Initiates the transmission of an I-frame in auto-mode. Additional to the opening flag, the address and control fields of the frame are added by PASSAT. 5-133 09.99 PEB 20525 PEF 20525 Register Description (CMDRH) XRES Transmitter Reset Command Self-clearing command bit: XRES='1' XF The SCC transmit FIFO is cleared and the transmitter protocol engines are reset to their initial state. A transmitter reset command is recommended after all changes in protocol mode configurations (e.g. switching between sub-modes of HDLC). Transmit Frame This self-clearing command bit is significant in interrupt driven operation only (GMODE.EDMA='0'). XF='1' After having written up to 32 bytes to the XFIFO, this command initiates transmission. In packet oriented protocols like HDLC/PPP the opening flag is automatically added by PASSAT. If the end of the packet is part of the transmit data, bit 'XME' should be set in addition. DMA Mode After having written the length of the data block to be transmitted to registers XBCL and XBCH, this command initiates the data transfer from host memory to PASSAT by DMA. Transmission on the serial side starts as soon as 32 bytes are transferred to the XFIFO or the transmit byte counter value is reached. XME Transmit Message End Self-clearing command bit: XME='1' XREP Indicates that the data block written last to the XFIFO contains the end of the packet. This bit should always be set in conjunction with a transmit command ('XF' or 'XIF'). Transmission Repeat Command Self-clearing command bit: XREP='1' Preliminary Data Sheet If bit 'XREP' is set together with bit 'XME' and 'XF', PASSAT repeatedly transmits the contents of the XFIFO (1..32 bytes). The cyclic transmission can be stopped with the 'XRES' command. 5-134 09.99 PEB 20525 PEF 20525 Register Description (CMDRH) RMC Receive Message Complete Self-clearing command bit: RMC='1' RNR With this bit the CPU indicates to PASSAT that the current receive data has been fetched out of the RFIFO. Thus the corresponding space in the RFIFO can be released and re-used by PASSAT for further incoming data. Receiver Not Ready Command NON self-clearing command bit: This command bit is significant in HDLC Automode only. RSUC RNR='0' Forces the receiver to enter its 'receiver-ready' state. The receiver acknowledges received poll or I-Frames with a 'receiver-ready' indication. RNR='1' Forces the receiver to enter its 'receiver-not-ready' state. The receiver acknowledges received poll or I-Frames with a 'receiver-not-ready' indication. Reset Signaling Unit Counter Self-clearing command bit: This command bit is significant if HDLC SS7 mode is selected. RSUC='1' RRES The Signaling System #7 (SS7) unit counter is reset. Receiver Reset Command Self-clearing command bit: RRES='1' Preliminary Data Sheet The SCC receive FIFO is cleared and the receiver protocol engines are reset to their initial state. The SCC receive FIFO accepts new receive data from the protocol engine immediately after receiver reset procedure. It is recommended to disable data reception before issuing a receiver reset command by setting bit CCR3L.RAC = '0' and enabling data reception afterwards. A 'receiver reset' command is recommended after all changes in protocol mode configurations. 5-135 09.99 PEB 20525 PEF 20525 Register Description (CCR0L) Register 5-21 CCR0L Channel Configuration Register 0 (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 16H 66H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 misc. VIS Register 5-22 PSD 2 1 0 Clock Mode Selection 0 TOE SSEL CM(2:0) CCR0H Channel Configuration Register 0 (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 17H 67H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 Power Line Coding PU SC(2:0) Preliminary Data Sheet 4 5-136 3 2 1 0 0 0 0 0 09.99 PEB 20525 PEF 20525 Register Description (CCR0H) PU Power Up PU='0' The SCC is in 'power-down' mode. The protocol engines are switched off (standby) and no operation is performed. This may be used to save power when SCC is not in use. Note: The SCC transmit FIFO accepts transmit data even in 'power-down' mode. PU='1' SC(2:0) The SCC is in 'power-up' mode. Serial Port Configuration This bit field selects the line coding of the serial port. Note, that special operation modes and settings may require or exclude operation in special line coding modes. Refer to the 'prerequisites' in the dedicated mode descriptions. SC = '000' NRZ data encoding SC = '001' Bus configuration, timing mode 1 (NRZ data encoding) SC = '010' NRZI data encoding SC = '011' Bus configuration, timing mode 2 (NRZ data encoding) SC = '100' FM0 data encoding SC = '101' FM1 data encoding SC = '110' Manchester data encoding SC = '111' Reserved Note: If bus configuration mode is selected, only NRZ data encoding is supported. VIS Masked Interrupts Visible VIS='0' Masked interrupt status bits are not displayed in the interrupt status registers (ISR0..ISR2). VIS='1' Masked interrupt status bits are visible and automatically cleared after interrupt status register (ISR0..ISR2) read access. Note: Interrupts masked in registers IMR0..IMR2 will not generate an interrupt. Preliminary Data Sheet 5-137 09.99 PEB 20525 PEF 20525 Register Description (CCR0H) PSD DPLL Phase Shift Disable This option is only applicable in the case of NRZ or NRZI line encoding is selected. TOE PSD='0' Normal DPLL operation. PSD='1' The phase shift function of the DPLL is disabled. The windows for phase adjustment are extended. Transmit Clock Out Enable For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock can be monitored on pin TxCLK as an output signal. In clock mode 5, a time slot control signal marking the active transmit time slot is output on pin TxCLK. Bit 'TOE' is invalid for all other clock modes. SSEL TOE='0' TxCLK pin is input. TOE='1' TxCLK pin is switched to output function if applicable for the selected clock mode. Clock Source Select Distinguishes between the 'a' and 'b' option of clock modes 0, 2, 3, 5, 6 and 7. CM(2:0) SSEL='0' Option 'a' is selected. SSEL='1' Option 'b' is selected. Clock Mode This bit field selects one of main clock modes 0..7. For a detailed description of the clock modes refer to Chapter 3.2.3 CM = '000' clock mode 0 CM = '001' clock mode 1 CM = '010' clock mode 2 CM = '011' clock mode 3 CM = '100' clock mode 4 CM = '101' clock mode 5 (time-slot oriented clocking modes) CM = '110' clock mode 6 CM = '111' clock mode 7 Preliminary Data Sheet 5-138 09.99 PEB 20525 PEF 20525 Register Description (CCR1L) Register 5-23 CCR1L Channel Configuration Register 1 (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 18H 68H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 SFLG DIV ODS 0 misc. CRL Register 5-24 SOC(1:0) C32 CCR1H Channel Configuration Register 1 (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 19H 69H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 FRTS FCTS CAS TSCM misc. 0 ICD Preliminary Data Sheet 0 RTS 5-139 09.99 PEB 20525 PEF 20525 Register Description (CCR1H) CRL CRC Reset Value This bit defines the initial value of the internal transmit/receive CRC generators: C32 CRL='0' Initial value is 0xFFFFH (16 bit CRC), 0xFFFFFFFFH (32 bit CRC). This is the default value for most HDLC/PPP applications. CRL='1' Initial value is 0x0000H (16 bit CRC), 0x00000000H (32 bit CRC). CRC 32 Select This bit enables 32-bit CRC operation for transmit and receive. C32='0' 16-bit CRC-CCITT generation/checking. C32='1' 32-bit CRC generation/checking. Note: The internal 'valid frame' criteria is updated depending on the selected number of CRC-bytes. SOC(1:0) Serial Output Control This bit field selects the RTS signal output function. (This bit field is only valid in bus configuration modes selected via bit field SC(2:0) in register CCR0H). SFLG SOC = '0X' RTS ouput signal is active during transmission of a frame (active low). SOC = '10' RTS ouput signal is always inactive (high). SOC = '11' RTS ouput signal is active during reception of a frame (active low). Shared Flags Transmission This bit enables 'shared flag transmission' in HDLC protocol mode. If another transmit frame begin is stored in the SCC transmit FIFO, the closing flag of the preceding frame becomes the opening flag of the next frame (shared flags): SFLG = '0' Shared flag transmission disabled. SFLG = '1' Shared flag transmission enabled. Note: The receiver always supports shared flags and shared zeros of consecutive flags. Preliminary Data Sheet 5-140 09.99 PEB 20525 PEF 20525 Register Description (CCR1H) DIV Data Inversion This bit is only valid if NRZ data encoding is selected via bit field SC(2:0) in register CCR0H. ODS DIV='0' No Data Inversion. DIV='1' Data is transmitted/received inverted (on a per bit basis). In HDLC and HDLC Synchronous PPP modes the continuous '1' idle sequence is NOT inverted. Interframe time fill flag transmission is inverted. Output Driver Select The transmit data output pin TxD can be configured as push/pull or open drain output chracteristic. ICD RTS ODS='0' TxD pin is open drain output. ODS='1' TxD pin is push/pull output. Invert Carrier Detect Pin Polarity ICD='0' Carrier Detect (CD) input pin is active high. ICD='1' Carrier Detect (CD) input pin is active low. Request To Send Pin Control The request to send pin RTS can be controlled by PASSAT as an output autonomously or via setting/clearing bit 'RTS'. This bit is not valid in clock mode 4. RTS='0' Pin RTS (output) pin is controlled by PASSAT autonomously. RTS is activated during transmission. In bus configuration mode the functionality depends on bit field 'SOC' setting. RTS='1' Pin RTS can be controlled by software. The output level of this pin depends on bit 'FRTS'. Note: For RTS pin control a transmit clock is necessary. Preliminary Data Sheet 5-141 09.99 PEB 20525 PEF 20525 Register Description (CCR1H) FRTS Flow Control (using signal RTS) Bit 'FRTS' together with bit 'RTS' determine the function of signal RTS: RTS, FRTS 0, 0 Pin RTS is controlled by PASSAT autonomously. RTS is activated (low) as soon as transmit data is available within the SCC transmit FIFO. 0, 1 Pin RTS is controlled by PASSAT autonomously supporting bi-directional data flow control. RTS is activated (low) if the shadow part of the SCC receive FIFO is empty and de-activated (high) when the SCC receive FIFO fill level reaches its receive FIFO threshold. 1, 0 Forces pin RTS to active state (low). 1, 1 Forces pin RTS to inactive state (high). Note: For RTS pin control a transmit clock is necessary. FCTS Flow Control (using signal CTS) This bit controls the function of pin CTS. CAS FCTS = '0' The transmitter is stopped if CTS input signal is inactive (high) and enabled if active (low). FCTS = '1' The transmitter is enabled, disregarding CTS input signal. Carrier Detect Auto Start CAS = '0' The CD pin is used as general input. In clock mode 1, 4 and 5, clock mode specific control signals must be provided at this pin (receive strobe, receive gating RCG, frame sync clock FSC). A pull-up/down resistor is recommended if unused. CAS = '1' The CD pin enables/disables the receiver for data reception. (Polarity of CD pin can be configured via bit 'ICD'.) Note: (1) In clock mode 1, 4 and 5 this bit must be set to '0'.(3) A receive clock must be provided in order to detect the signal state of the CD input pin. Preliminary Data Sheet 5-142 09.99 PEB 20525 PEF 20525 Register Description (CCR1H) TSCM Time Slot Control Mode This bit controls internal counter operation in time slot oriented clock mode 5: TSCM='0' The internal counter keeps running, restarting with zero after being expired. TSCM='1' The internal counter stops at its maximum value and restarts with the next frame sync pulse again. Preliminary Data Sheet 5-143 09.99 PEB 20525 PEF 20525 Register Description (CCR2L) Register 5-25 CCR2L Channel Configuration Register 2 (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 1AH 6AH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 TLPO TLP misc. MDS1 Register 5-26 MDS0 ADM NRM PPPM(1:0) CCR2H Channel Configuration Register 2 (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 1BH 6BH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 ITF 0 OIN XCRC misc. MCS EPT Preliminary Data Sheet NPRE(1:0) 5-144 09.99 PEB 20525 PEF 20525 Register Description (CCR2H) MDS(1:0) Mode Select This bit field selects the HDLC protocol sub-mode including the 'extended transparent mode'. MDS = '00' Automode. MDS = '01' Address Mode 2. MDS = '10' Address Mode 0/1. (Option '0' or '1' is selected via bit 'ADM'.) MDS = '11' Extended transparent mode (bit transparent transmission/ reception). Note: 'MDS(1:0)' must be set to '10' if any PPP mode is enabled via bit field 'PPPM' or if SS7 is enabled via bit 'ESS7' in register CCR3L. ADM Address Mode Select The meaning of this bit depends on the selected protocol sub-mode: Automode, Address Mode 2: Determines the address field length of an HDLC frame. ADM = '0' 8-bit address field. ADM = '1' 16-bit address field. Address Mode 0/1: Determines whether address mode 0 or 1 is selected. ADM = '0' Address Mode 0 (no address recognition). ADM = '1' Address Mode 1 (high byte address recognition). Extended Transparent Mode: ADM = '1' NRM recommended setting Normal Response Mode This bit is valid in HDLC Automode operation only and determines the function of the Automode LAP-Controller: NRM = '0' Full-duplex LAP-B / LAP-D operation. NRM = '1' Half-duplex normal response mode (NRM) operation. Preliminary Data Sheet 5-145 09.99 PEB 20525 PEF 20525 Register Description (CCR2H) PPPM(1:0) PPP Mode Select This bit field enables and selects the HDLC PPP protocol modes: PPPM = '00' No PPP protocol operation. The HDLC sub-mode is determined by bit field 'MDS'. PPPM = '01' Octet synchronous PPP protocol operation. PPPM = '10' Reserved PPPM = '11' Bit synchronous PPP protocol operation. Note: 'Address Mode 0' must be selected by setting bit field 'MDS(1:0)' to '10' and bit 'ADM' to '0' if any PPP mode is enabled. TLPO Test Loop Out Function This bit is only valid if test loop is enabled and controls whether test loop transmit data is driven on pin TxD: TLP TLPO = '0' Test loop transmit data is driven to TxD pin. TLPO = '1' Test loop transmit data is NOT driven to TxD pin. TxD pin is idle '1'. Depending on the selected output characteristic the pin is high impedance (bit CCR1L.ODS ='0') or driving high (CCR1L.ODS ='1'). Test Loop This bit controls the internal test loop between transmit and receive data signals. The test loop is closed at the far end of serial transmit and receive line just before the respective TxD and RxD pins: TLP = '0' Test loop disabled. TLP = '1' Test loop enabled. The software is responsible to select a clock mode which allows correct reception of transmit data depending on the external clock supply. Transmit data is sent out via pin TxD if not disabled with bit 'TLPO'. The receive input pin RxD is internally disconnected during test loop operation. Preliminary Data Sheet 5-146 09.99 PEB 20525 PEF 20525 Register Description (CCR2H) MCS Modulo Count Select This bit is valid in HDLC Automode operation only and determines the control field format: EPT MCS = '0' Basic operation, one byte control field (modulo 8 counter operation). MCS = '1' Extended operation, two bytes control field (modulo 128 counter operation). Enable Preamble Transmission This bit enables preamble transmission. The preamble is started after interframe time fill (ITF) transmission is stopped because a new frame is ready to be transmitted. The preamble pattern consists of 8 bits defined in register PREAMB, which is sent repetitively. The number of repetitions is determined by bit field 'PRE(1:0)': EPT='0' Preamble transmission is disabled. EPT='1' Preamble transmission is enabled. Note: Preamble operation does NOT influence HDLC shared flag transmission if enabled. NPRE(1:0) Number of Preamble Repetitions This bit field determines the number of preambles transmitted: NPRE = '00' 1 preamble. NPRE = '01' 2 preambles. NPRE = '10' 4 preambles. NPRE = '11' 8 preambles. ITF Interframe Time Fill This bit selects the idle state of the transmit pin TxD: ITF='0' Continuous logical '1' is sent during idle phase. ITF='1' Continuous flag sequences are sent ('01111110' flag pattern). Note: It is recommended to clear bit 'ITF' in bus configuration modes, i.e. continuous '1's are sent as idle sequence and data encoding is NRZ. Preliminary Data Sheet 5-147 09.99 PEB 20525 PEF 20525 Register Description (CCR2H) OIN One Insertion In HDLC mode a one-insertion mechanism similar to the zero-insertion can be activated: XCRC OIN='0' The '1' insertion mechanism is disabled. OIN='1' In transmit direction a logical '1' is inserted to the serial data stream after 7 consecutive zeros. In receive direction a '1' is deleted from the receive data stream after receiving 7 consecutive zeros. This enables clock information to be recovered from the receive data stream by means of a DPLL, even in the case of NRZ data encoding, because a transition at bit cell boundary occurs at least every 7 bits. Transmit CRC Checking Mode XCRC='0' The transmit checksum (2 or 4 bytes) is generated and appended to the transmit data automatically. XCRC='1' The transmit checksum is not generated automatically. The checksum is expected to be provided by software as the last 2 or 4 bytes in the transmit data buffer. Preliminary Data Sheet 5-148 09.99 PEB 20525 PEF 20525 Register Description (CCR3L) Register 5-27 CCR3L Channel Configuration Register 3 (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 1CH 6CH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 RAC 0 0 ESS7 1 0 misc. ELC AFX Register 5-28 CSF SUET CCR3H Channel Configuration Register 3 (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 1DH 6DH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 0 0 misc. 0 DRCRC Preliminary Data Sheet RCRC RADD 5-149 RFTH(1:0) 09.99 PEB 20525 PEF 20525 Register Description (CCR3H) ELC Enable Length Check This bit is only valid in HDLC SS7 mode: If the number of received octets exceeds 272 + 7 within one Signaling Unit, reception is aborted and bit RSTA.RAB is set. AFX ELC='0' Length Check disabled. ELC='1' Length Check enabled. Automatic FISU Transmission This bit is only valid in HDLC SS7 mode: After the contents of the transmit FIFO (XFIFO) has been transmitted completely, FISUs are transmited automatically. These FISUs contain the FSN and BSN of the last transmitted Signaling Unit (provided in XFIFO). CSF AFX='0' Automatic FISU transmission disabled. AFX='1' Automatic FISU transmission enabled. Compare Status Field This bit is only valid in HDLC SS7 mode: If the status fields of consecutive LSSUs are equal, only the first will be stored and every following is ignored SUET CSF='0' Compare is disabled, all received LSSUs are stored in the receive FIFO. CSF='1' Compare is enabled, only the first one of consecutive equal LSSUs is stored in the receive FIFO. Signalling Unit Counter Threshold This bit is only valid in HDLC SS7 mode: Defines the number of signaling units received in error that will cause an error rate high indication (ISR1.SUEX). SUET='0' threshold is 64 errored signaling units. SUET='1' threshold is 32 errored signaling units. Preliminary Data Sheet 5-150 09.99 PEB 20525 PEF 20525 Register Description (CCR3H) RAC Receiver active Switches the receiver between operational/inoperational states: ESS7 RAC='0' Receiver inactive, receive line is ignored. RAC='1' Receiver active. Enable SS7 Mode This bit is only valid in HDLC mode only. ESS7='0' Disable signaling system #7 (SS7) support. ESS7='1' Enable signaling system #7 (SS7) support. Note: If SS7 mode is enabled, 'Address Mode 0' must be selected by setting bit field CCR2L:MDS(1:0) to '10' and bit CCR2L:ADM to '0'. DRCRC RCRC Disable Receive CRC Checking DRCRC='0' The receiver expects a 16 or 32 bit CRC within a HDLC frame. CRC processing depends on the setting of bit 'RCRC'. Frames shorter than expected are marked 'invalid' or are discarded (refer to RSTA description). DRCRC='1' The receiver does not expect any CRC within a HDLC frame. The criteria for 'valid frame' indication is updated accordingly (refer to RSTA description). Bit 'RCRC' is ignored. Receive CRC Checking Mode RCRC='0' The received checksum is evaluated, but NOT forwarded to the receive FIFO. RCRC='1' The received checksum (2 or 4 bytes) is evaluated and forwarded to the receive FIFO as data. Preliminary Data Sheet 5-151 09.99 PEB 20525 PEF 20525 Register Description (CCR3H) RADD Receive Address Forward to RFIFO This bit is only valid - if an HDLC sub-mode with address field support is selected (Automode, Address Mode 2, Address Mode 1) - in SS7 mode RFTH(1:0) RADD='0' The received HDLC address field (either 8 or 16 bit, depending on bit 'ADM') is evaluated, but NOT forwarded to the receive FIFO. In SS7 mode, the signaling unit fields 'FSN' and 'BSN' are NOT forwarded to the receive FIFO. RADD='1' The received HDLC address field (either 8 or 16 bit, depending on bit 'ADM') is evaluated and forwarded to the receive FIFO. In SS7 mode, the signaling unit fields 'FSN' and 'BSN' are forwarded to the receive FIFO. Receive FIFO Threshold This bit field defines the level up to which the SCC receive FIFO is filled with valid data before an 'RPF' interrupt is generated. (In case of a 'frame end' condition the PASSAT notifies the CPU immediately, disregarding this threshold.) RFTH(1:0) Threshold level in number of data bytes. '00' 32 byte '01' 16 byte '10' 4 byte '11' 2 byte Preliminary Data Sheet 5-152 09.99 PEB 20525 PEF 20525 Register Description (PREAMB) Register 5-29 PREAMB Preamble Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 1EH 6EH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 Preamble Pattern PRE(7:0) PRE(7:0) Preamble This bit field determines the preamble pattern which is send out during preamble transmission. Note: In HDLC-mode, zero-bit insertion is disabled during preamble transmission. Preliminary Data Sheet 5-153 09.99 PEB 20525 PEF 20525 Register Description (ACCM0) Register 5-30 ACCM0 PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 20H 70H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 02 01 00 2 1 0 09 08 ASYNC Character Control Map 07..00 07 Register 5-31 06 05 04 03 ACCM1 PPP ASYNC Control Character Map 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 21H 71H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 ASYNC Character Control Map 0F..08 0F Preliminary Data Sheet 0E 0D 0C 5-154 0B 0A 09.99 PEB 20525 PEF 20525 Register Description (ACCM2) Register 5-32 ACCM2 PPP ASYNC Control Character Map2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 22H 72H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 12 11 10 2 1 0 19 18 ASYNC Character Control Map 17..10 17 Register 5-33 16 15 14 13 ACCM3 PPP ASYNC Control Character Map 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 23H 73H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 ASYNC Character Control Map 1F..18 1F Preliminary Data Sheet 1E 1D 1C 5-155 1B 1A 09.99 PEB 20525 PEF 20525 Register Description (ACCM3) ACCM ASYNC Character Control Map This bit field is valid in HDLC octet-synchronous PPP mode only: Each bit selects the corresponding character (indicated as hex value 1FH..00H in the register description table) as control character which has to be mapped into the transmit data stream. Preliminary Data Sheet 5-156 09.99 PEB 20525 PEF 20525 Register Description (UDAC0) Register 5-34 UDAC0 User Defined PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value: 7EH Channel A Channel B Offset Address: 24H 74H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 ASYNC Character 0 AC0 Register 5-35 UDAC1 User Defined PPP ASYNC Control Character Map 1 CPU Accessibility: read/write Reset Value: 7EH Channel A Channel B Offset Address: 25H 75H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 ASYNC Character 1 AC1 Preliminary Data Sheet 5-157 09.99 PEB 20525 PEF 20525 Register Description (UDAC2) Register 5-36 UDAC2 User Defined PPP ASYNC Control Character Map 2 CPU Accessibility: read/write Reset Value: 7EH Channel A Channel B Offset Address: 26H 76H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 ASYNC Character 2 AC2 Register 5-37 UDAC3 User Defined PPP ASYNC Control Character Map 3 CPU Accessibility: read/write Reset Value: 7EH Channel A Channel B Offset Address: 27H 77H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 ASYNC Character 3 AC3 Preliminary Data Sheet 5-158 09.99 PEB 20525 PEF 20525 Register Description (UDAC3) AC3..0 User Defined ASYNC Character Control Map This bit field is valid in HDLC octet-synchronous PPP mode only: These bit fields define user determined characters as control characters which have to be mapped into the transmit data stream. In register ACCM only characters 00H..1FH can be selected as control characters. Register UDAC allows to specify any four characters in the range 00H..FFH . The default value is a 7EH flag which must be always mapped. Thus no additional character is mapped if 7EH 's are programed to bit fields AC3...0 (reset value). (7EH is mapped automatically, even if not defined via a AC bit field.) Preliminary Data Sheet 5-159 09.99 PEB 20525 PEF 20525 Register Description (TTSA0) Register 5-38 TTSA0 Transmit Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 28H 78H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 Tx Clock Shift 0 Register 5-39 0 0 0 0 TCS(2:0) TTSA1 Transmit Time Slot Assignment Register 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 29H 79H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 Tx Time Slot Number TEPCM Preliminary Data Sheet TTSN(6:0) 5-160 09.99 PEB 20525 PEF 20525 Register Description (TTSA2) Register 5-40 TTSA2 Transmit Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2AH 7AH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 0 0 TCC8 Transmit Channel Capacity TCC(7:0) Register 5-41 TTSA3 Transmit Time Slot Assignment Register 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2BH 7BH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Transmit Channel Capacity 0 Preliminary Data Sheet 0 0 0 5-161 0 09.99 PEB 20525 PEF 20525 Register Description (TTSA3) The following register bit fields allow flexible assignment of bit- or octet-aligned transmit time-slots to the serial channel. For more detailed information refer to chapters "Clock Mode 5a (Time Slot Mode)" on page 3-53 and "Clock Mode 5b (Octet Sync Mode)" on page 3-60. TCS(2:0) Transmit Clock Shift This bit field determines the transmit clock shift. TEPCM Enable PCM Mask Transmit This bit selects the additional Transmit PCM Mask (refer to register PCMTX0..PCMTX3): TTSN(6:0) TEPCM='0' Standard time-slot configuration. TEPCM='1' The time-slot width is constant 8 bit, bit fields 'TTSN' and 'TCS' determine the offset of the PCM mask and 'TCC' is ignored. Each time-slot selected via register PCMTX0..PCMTX3 is an active transmit timeslot. Transmit Time Slot Number This bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): Offset = 1+TTSN*8 + TCS (1..1024 clocks) TCC(8:0) Transmit Channel Capacity This bit field determines the transmit time-slot width in standard time-slot configuration (bit TEPCM='0'): Number of bits = TCC + 1, (1..512 bits/time-slot) Preliminary Data Sheet 5-162 09.99 PEB 20525 PEF 20525 Register Description (RTSA0) Register 5-42 RTSA0 Receive Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2CH 7CH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 Rx Clock Shift 0 Register 5-43 0 0 0 0 RCS(2:0) RTSA1 Receive Time Slot Assignment Register 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2DH 7DH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 Rx Time Slot Number REPCM Preliminary Data Sheet RTSN(6:0) 5-163 09.99 PEB 20525 PEF 20525 Register Description (RTSA2) Register 5-44 RTSA2 Receive Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2EH 7EH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 0 0 RCC8 Receive Channel Capacity RCC(7:0) Register 5-45 RTSA3 Receive Time Slot Assignment Register 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 2FH 7FH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Receive Channel Capacity 0 Preliminary Data Sheet 0 0 0 5-164 0 09.99 PEB 20525 PEF 20525 Register Description (RTSA3) The following register bit fields allow flexible assignment of bit- or octet-aligned receive time-slots to the serial channel. For more detailed information refer to chapters "Clock Mode 5a (Time Slot Mode)" on page 3-53 and "Clock Mode 5b (Octet Sync Mode)" on page 3-60. RCS(2:0) Receive Clock Shift This bit field determines the receive clock shift. REPCM Enable PCM Mask Receive This bit selects the additional Receive PCM Mask (refer to register PCMRX0..PCMRX3): RTSN(6:0) REPCM='0' Standard time-slot configuration. REPCM='1' The time-slot width is constant 8 bit, bit fields 'RTSN' and 'RCS' determine the offset of the PCM mask and 'RCC' is ignored. Each time-slot selected via register PCMRX0..PCMRX3 is an active receive timeslot. Receive Time Slot Number This bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): Offset = 1+RTSN*8 + RCS (1..1024 clocks) RCC(8:0) Receive Channel Capacity This bit field determines the receive time-slot width in standard time-slot configuration (bit REPCM='0'): Number of bits = RCC + 1, (1..512 bits/time-slot) Preliminary Data Sheet 5-165 09.99 PEB 20525 PEF 20525 Register Description (PCMTX0) Register 5-46 PCMTX0 PCM Mask Transmit Direction Register 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 30H 80H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 T01 T00 1 0 T09 T08 PCM Mask for Transmit Direction T07 Register 5-47 T06 T05 T04 T03 T02 PCMTX1 PCM Mask Transmit Direction Register 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 31H 81H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 PCM Mask for Transmit Direction T15 T14 Preliminary Data Sheet T13 T12 5-166 T11 T10 09.99 PEB 20525 PEF 20525 Register Description (PCMTX2) Register 5-48 PCMTX2 PCM Mask Transmit Direction Register 2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 32H 82H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 T17 T16 9 8 T25 T24 PCM Mask for Transmit Direction T23 Register 5-49 T22 T21 T20 T19 T18 PCMTX3 PCM Mask Transmit Direction Register 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 33H 83H typical usage: written by CPU; read and evaluated by PASSAT Bit 15 14 13 12 11 10 PCM Mask for Transmit Direction T31 T30 Preliminary Data Sheet T29 T28 5-167 T27 T26 09.99 PEB 20525 PEF 20525 Register Description (PCMTX3) PCMTX PCM Mask for Transmit Direction This bit field is valid in HDLC clock mode 5 only and the PCM mask must be enabled via bit 'TEPCM' in register TTSA1. Each bit selects one of 32 (8-bit) transmit time-slots. The offset of timeslot zero to the frame sync pulse can be programmed via register TTSA1 bit field 'TTSN'. Preliminary Data Sheet 5-168 09.99 PEB 20525 PEF 20525 Register Description (PCMRX0) Register 5-50 PCMRX0 PCM Mask Receive Direction Register 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 34H 84H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 T01 T00 9 8 T09 T08 PCM Mask for Receive Direction T07 Register 5-51 T06 T05 T04 T03 T02 PCMRX1 PCM Mask Receive Direction Register 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 35H 85H typical usage: written by CPU; read and evaluated by PASSAT Bit 15 14 13 12 11 10 PCM Mask for Receive Direction T15 T14 Preliminary Data Sheet T13 T12 5-169 T11 T10 09.99 PEB 20525 PEF 20525 Register Description (PCMRX2) Register 5-52 PCMRX2 PCM Mask Receive Direction Register 2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 36H 86H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 T17 T16 9 8 T25 T24 PCM Mask for Receive Direction T23 Register 5-53 T22 T21 T20 T19 T18 PCMRX3 PCM Mask Receive Direction Register 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 37H 87H typical usage: written by CPU; read and evaluated by PASSAT Bit 15 14 13 12 11 10 PCM Mask for Receive Direction T31 T30 Preliminary Data Sheet T29 T28 5-170 T27 T26 09.99 PEB 20525 PEF 20525 Register Description (PCMRX3) PCMRX PCM Mask for Receive Direction This bit field is valid in HDLC clock mode 5 only and the PCM mask must be enabled via bit 'REPCM' in register RTSA1. Each bit selects one of 32 (8-bit) receive time-slots. The offset of timeslot zero to the frame sync pulse can be programmed via register RTSA1 bit field 'RTSN'. Preliminary Data Sheet 5-171 09.99 PEB 20525 PEF 20525 Register Description (BRRL) Register 5-54 BRRL Baud Rate Register (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 38H 88H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Baud Rate Generator Factor N 0 Register 5-55 0 BRN(5:0) BRRH Baud Rate Register (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 39H 89H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Baud Rate Generator Factor M 0 Preliminary Data Sheet 0 0 0 5-172 BRM(3:0) 09.99 PEB 20525 PEF 20525 Register Description (BRRH) BRM(3:0) Baud Rate Factor 'M' BRN(5:0) Baud Rate Factor 'N' These bit fields determine the division factor of the internal baud rate generator. The baud rate generator input clock and the usage of baud rate generator output depends on the selected clock mode. The division factor k is calculated by: k = (N + 1) x 2M with M=0..15 and N=0..63. f B RG = f i n k Preliminary Data Sheet 5-173 09.99 PEB 20525 PEF 20525 Register Description (TIMR0) Register 5-56 TIMR0 Timer Register 0 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3AH 8AH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Timer Value TVALUE(7:0) Register 5-57 TIMR1 Timer Register 1 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3BH 8BH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Timer Value TVALUE(15:0) Preliminary Data Sheet 5-174 09.99 PEB 20525 PEF 20525 Register Description (TIMR2) Register 5-58 TIMR2 Timer Register 2 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3CH 8CH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Timer Value TVALUE(23:16) Register 5-59 TIMR3 Timer Register 3 CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3DH 8DH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Timer Configuration SRC Preliminary Data Sheet 0 0 TMD 5-175 0 CNT(2:0) 09.99 PEB 20525 PEF 20525 Register Description (TIMR3) SRC Clock Source (valid in clock mode 5 only) This bit selects the clock source of the internal timer: TMD SRC = '0' The timer is clocked by the effective transmit clock. SRC = '1' The timer is clocked by the frame-sync synchronization signal supplied via the FSC pin in clock mode 5. Timer Mode This bit must be set to '1' if HDLC Automode operation is selected. In all other protocol modes it must remain '0': CNT(2:0) TMD='0' The timer is controlled by the CPU via access to registers CMDRL and TIMR0..TIMR3. The timer can be started any time by setting bit 'STI' in register CMDRL. After the timer has expired it generates a timer interrupt. The timer can be stopped any time by setting bit 'TRES' in register CMDRL to '1'. TMD='1' The timer is used by the PASSAT for protocol specific time-out and retry transactions in HDLC Automode. Counter The meaning of this bit field depends on the selected protocol mode. In HDLC Automode, with bit TMD='1': * Retry Counter (in HDLC protocol known as 'N2'): Bit field 'CNT' indicates the number of S-Command frames (with poll bit set) which are transmitted autonomously by PASSAT after every expiration of the time out period 't' (determined by 'TVALUE'), in case an I-Frame gets not acknowledged by the opposite station. The maximum value is 6 S-command frames. If 'CNT' is set to '7', the number of S-commands is unlimited in case of no acknowledgement. In all other modes, with bit TMD='0': * Restart Counter : Bit field 'CNT' indicates the number of automatic restarts which are performed by PASSAT after every expiration of the time-out period 't', in case the timer is not stopped by setting bit 'TRES' in register CMDRL to '1'. The maximum value is 6 restarts. If 'CNT' is set to '7', a timer interrupt is generated periodically with time period 't' determined by bit field 'TVALUE'. Preliminary Data Sheet 5-176 09.99 PEB 20525 PEF 20525 Register Description (TIMR3) TVALUE (23:0) Timer Expiration Value This bit field determines the timer expiration period 't': t = ( TVALUE + 1 ) CP ('CP' is the clock period, depending on bit 'SRC'.) Preliminary Data Sheet 5-177 09.99 PEB 20525 PEF 20525 Register Description (XAD1) Register 5-60 XAD1 Transmit Address 1 Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3EH 8EH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 0 XAD1_0 1 0 Transmit Address (high) XAD1 (high byte) or XAD1 (COMMAND) Register 5-61 XAD2 Transmit Address 2 Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 3FH 8FH typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 Transmit Address (low) XAD2 (low byte) or XAD2 (RESPONSE) Preliminary Data Sheet 5-178 09.99 PEB 20525 PEF 20525 Register Description (XAD2) XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address field handling only (Automode, Address Mode 1, Non-Automode). They can be programmed with one individual address byte which is inserted automatically into the address field (8 or 16 bit) of a HDLC transmit frame. The function depends on the selected protocol mode and address field size (bit 'ADM' in register CCR2L). XAD1 Transmit Address 1 - 2-byte address field: Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit 1 must be set to '0'. According to the ISDN LAP-D protocol, bit 1 is interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is manipulated automatically by PASSAT according to the setting of bit 'CRI' in register RAH1. The following is the C/R value (on bit 1), when: - transmitting COMMANDs: '1' (if 'CRI'='1') ; '0' (if 'CRI'='0') - transmitting RESPONSEs: '0' (if 'CRI'='1') ; '1' (if 'CRI'='0') (In ISDN LAP-D, the high byte is known as 'SAPI'.) In accordance with the HDLC protocol, bit 'XAD1_0' should be set to '0', to indicate that the address field contains (at least) one more byte. - 1-byte address field: According to the X.25 LAP-B protocol, XAD1 is the address of a 'COMMAND' frame. XAD2 Transmit Address 2 - 2-byte address field: Bit field XAD2 constitutes the low byte of the 2-byte address field. (In ISDN LAP-D, the low byte is known as 'TEI'.) - 1-byte address field: According to the X.25 LAP-B protocol, XAD2 is the address of a 'RESPONSE' frame. Preliminary Data Sheet 5-179 09.99 PEB 20525 PEF 20525 Register Description (RAL1) Register 5-62 RAL1 Receive Address 1 Low Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 40H 90H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 1 0 CRI RAH1_0 Receive Address 1 (low) RAL1 RAL1 Register 5-63 RAH1 Receive Address 1 High Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 41H 91H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 Receive Address 1 (high) RAH1 or RAH1 Preliminary Data Sheet 5-180 09.99 PEB 20525 PEF 20525 Register Description (RAL2) Register 5-64 RAL2 Receive Address 2 Low Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 42H 92H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Receive Address 2 (low) RAL2 Register 5-65 RAH2 Receive Address 2 High Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 43H 93H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Receive Address 2 (high) RAH2 Preliminary Data Sheet 5-181 09.99 PEB 20525 PEF 20525 Register Description (RAH2) In operating modes that provide address recognition, the high/low byte of the received address is compared with the individually programmable values in register RAH2/ RAL2/RAH1/RAL1. This addresses can be masked on a per bit basis by setting the corresponding bits in registers AMRAL1/AMRAH1/AMRAL2/AMRAH2 to allow extended broadcast address recognition. This feature is applicable to all HDLC sub-modes with address recognition. RAH1 Receive Address 1 Byte High In HDLC Automode bit '1' is reserved for 'CRI' (Command Response Interpretation). In all other modes RAH1 is an 8 bit address. CRI Command/Response Interpretation The setting of this bit effects the meaning of the 'C/R' bit in the receive status byte (RSTA). This status bit 'C/R' should be interpreted after reception as follows: '0' (if 'CRI'='1') ; '1' (if 'CRI'='0') : COMMAND received '1' (if 'CRI'='1') ; '0' (if 'CRI'='0') : RESPONSE received Note: If 1-byte address field is selected in HDLC Automode, RAH1 must be set to 0x00H. RAL1 Receive Address 1 Byte Low The general function and its meaning depends on the selected HDLC operating mode: * Automode / Address Mode 2 (16-bit address) RAL1 can be programmed with the value of the first individual low address byte. * Automode / Address Mode 2 (8-bit address) According to X.25 LAP-B protocol, the address in RAL1 is considered as the address of a 'COMMAND' frame. RAH2 Receive Address 2 Byte High RAL2 Receive Address 2 Byte Low Value of the second individually programmable high/low address byte. If a 1-byte address field is selected, RAL2 is considered as the address of a 'RESPONSE' frame according to X.25 LAP-B protocol. Preliminary Data Sheet 5-182 09.99 PEB 20525 PEF 20525 Register Description (AMRAL1) Register 5-66 AMRAL1 Mask Receive Address 1 Low Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 44H 94H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Receive Mask Address 1 (low) AMRAL1 Register 5-67 AMRAH1 Mask Receive Address 1 High Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 45H 95H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Receive Mask Address 1 (high) AMRAH1 Preliminary Data Sheet 5-183 09.99 PEB 20525 PEF 20525 Register Description (AMRAL2) Register 5-68 AMRAL2 Mask Receive Address 2 Low Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 46H 96H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 Receive Mask Address 2 (low) AMRAL2 Register 5-69 AMRAH2 Mask Receive Address 2 High Register CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 47H 97H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Receive Mask Address 2 (high) AMRAH2 Preliminary Data Sheet 5-184 09.99 PEB 20525 PEF 20525 Register Description (AMRAH2) AMRAH2 Receive Mask Address 2 Byte High AMRAL2 Receive Mask Address 2 Byte Low AMRAH1 Receive Mask Address 1 Byte High AMRAL1 Receive Mask Address 1 Byte Low Setting a bit in this registers to '1' masks the corresponding bit in registers RAH2/RAL2/RAH1/RAL1. A masked bit position always matches when comparing the received frame address with registers RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism. bit = '0' The dedicated bit position is NOT masked. This bit position in the received address must match with the corresponding bit position in registers RAH2/RAL2/RAH1/ RAL1 to accept the frame. bit = '1' The dedicated bit position is masked. This bit position in the received address NEED NOT match with the corresponding bit position in registers RAH2/RAL2/RAH1/ RAL1 to accept the frame. Preliminary Data Sheet 5-185 09.99 PEB 20525 PEF 20525 Register Description (RLCRL) Register 5-70 RLCRL Receive Length Check Register (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 48H 98H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 1 0 Receive Length Limit RL(7:0) Register 5-71 RLCRH Receive Length Check Register (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 49H 99H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 Receive Length Check Control RCE Preliminary Data Sheet 0 0 2 Receive Length Limit 0 5-186 0 RL(10:8) 09.99 PEB 20525 PEF 20525 Register Description (RLCRH) RCE Receive Length Check Enable This bit is valid in HDLC mode only and enables/disables the receive length check function: RCE = '0' No receive length check on received HDLC frames is performed. RCE = '1' The receive length check is enabled. All bytes of a HDLC frame which are transferred to the receive FIFO (depending on the selected protocol sub-mode and receive CRC handling) are counted and checked against the maximum length check limit which is programmed in bit field 'RL'. A frame exceeding the maximum length is treated as if it were aborted on the receive line ('RME' interrupt and bit 'RAB' (receive abort) set in the RSTA byte). In addition a 'FLEX' interrupt is generated prior to 'RME', if enabled. Note: The Receive Status Byte (RSTA) is part of the frame length checking. RL(10:0) Receive Length Check Limit This bit-field defines the receive length check limit (32..65536 bytes) if checking is enabled via bit 'RCE': RL(10:0) The receive length limit is calculated by: Limit = ( RL + 1 ) 32 Preliminary Data Sheet 5-187 09.99 PEB 20525 PEF 20525 Register Description (ISR0) Register 5-72 ISR0 Interrupt Status Register 0 CPU Accessibility: read only Reset Value: 00H Channel A Channel B Offset Address: 50H A0H typical usage: updated by PASSAT read and evaluated by CPU Bit 7 6 5 4 3 2 1 0 RPF RME RFS FLEX 3 2 1 0 ALLS XDU SUEX 0 ISR0 RDO Register 5-73 RFO PCE RSC ISR1 Interrupt Status Register 1 CPU Accessibility: read only Reset Value: 00H Channel A Channel B Offset Address: 51H A1H typical usage: updated by PASSAT read and evaluated by CPU Bit 7 6 5 4 ISR1 TIN CSC Preliminary Data Sheet XMR XPR 5-188 09.99 PEB 20525 PEF 20525 Register Description (ISR2) Register 5-74 ISR2 Interrupt Status Register 2 CPU Accessibility: read only Reset Value: 00H Channel A Channel B Offset Address: 52H A2H typical usage: updated by PASSAT read and evaluated by CPU Bit 7 6 5 4 3 2 1 0 0 0 PLLA CDSC ISR2 0 Preliminary Data Sheet 0 0 0 5-189 09.99 PEB 20525 PEF 20525 Register Description (ISR2) RDO Receive Data Overflow Interrupt This bit is set to '1', if receive data of the current frame got lost because of a SCC receive FIFO full condition. However the rest of the frame is received and discarded as long as the receive FIFO remains full and is stored as soon as FIFO space is available again. The receive status byte (RSTA) of such a frame contains an 'RDO' indication. In DMA operation the 'RDO' indication is also set in the receive byte count register RBCH. RFO Receive FIFO Overflow Interrupt This bit is set to '1', if the SCC receive FIFO is full and a complete frame must be discarded. This interrupt can be used for statistical purposes, indicating that the host was not able to service the SCC receive FIFO quickly enough, e.g. due to high bus latency. PCE Protocol Error Interrupt This bit is valid in HDLC Automode only. It is set to '1', if the receiver has detected a protocol error, i.e. one of the following events occured: * an S- or I-frame was received with wrong N(R) counter value; * an S-frame containing an Information field was received. RSC Receive Status Change Interrupt This bit is valid in HDLC Automode only. It is set to '1', if a status change of the remote station receiver has been detected by receiving a S-frame with receiver ready (RR) or receiver not ready (RNR) indication. Because only a status change is indicated via this interrupt, the current status can be evaluated by reading bit 'RRNR' in status register STARH. RPF Receive Pool Full Interrupt This bit is set to '1' if the RFIFO threshold level, set with bit field 'RFTH(1:0)' in register CCR3H, is reached. Default threshold level is 32 data bytes. Preliminary Data Sheet 5-190 09.99 PEB 20525 PEF 20525 Register Description (ISR2) RME Receive Message End Interrupt This bit set to '1' indicates that the reception of one message is completed, i.e. either - one message which fits into RFIFO not exceeding the receive FIFO threshold, or - the last part of a message, all in all exceeding the receive FIFO threshold is stored in the RFIFO. The complete message length can be determined by reading the RBCL/ RBCH registers. The number of bytes stored in RFIFO is given by the 5, 4, 2 or 1 least significant bits of register RBCL, depending on the selected RFIFO threshold (bit field 'RFTH(1:0)' in register CCR3H). Additional frame status information is available in the RSTA byte, stored in the RFIFO as the last byte of each frame. RFS Receive Frame Start Interrupt This bit is set to '1', if the beginning of a valid frame is detected by the receiver. A valid frame start is detected either if a valid address field is recognized (in all operating modes with address recognition) or if a start flag is recognized (in all operating modes with no address recognition). FLEX Frame Length Exceeded Interrupt This bit is set to '1', if the frame length check feature is enabled and the current received frame is aborted because the programmed frame length limit was exceeded (refer to registers RLCRL/RLCRH for detailed description). TIN Timer Interrupt This bit is set to '1', if the internal timer was activated and has expired (refer also to description of timer registers TIMR0..TIMR3). CSC CTS Status Change This bit is set to '1', if a transition occurs on signal CTS. The current state of signal CTS is monitored by status bit 'CTS' in status register STARL. Preliminary Data Sheet 5-191 09.99 PEB 20525 PEF 20525 Register Description (ISR2) XMR Transmit Message Repeat This bit is set to '1', if transmission of the last frame has to be repeated (by software), because * the SCC has received a negative acknowledge to an I-frame (in HDLC Automode operation); * a collision occured after at least 31 bytes of data have been completely sent out, i.e. automatic re-transmission cannot be performed by the SCC; * CTS signal was deasserted after at least 31 bytes of data have been completely sent out. Note: For easy recovery from a collision event (in bus configuration only), the SCC transmit FIFO should not contain more than one complete frame. This can be achieved by using the 'ALLS' interrupt to control the corresponding transmit channel forwarding a new frame on all sent (ALLS) event only. XPR Transmit Pool Ready Interrupt This bit is set to '1', if a transmitter reset command was executed successfully (command bit 'XRES' in register CMDRL) and whenever the XFIFO is able to accept new transmit data again. An 'XPR' interrupt is not generated, if no sufficient transmit clock is available (depending on the selected clock mode). ALLS ALL Sent Interrupt This bit is set to '1': * if the last bit of the current HDLC frame is sent out via pin TxD and no further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO is empty (Address Mode 2/1/0); * if an I-frame is sent out completely via pin TxD and either a valid acknowledge S-frame has been received or a time-out condition occured because no valid acknowledge S-frame has been received in time (Automode). Preliminary Data Sheet 5-192 09.99 PEB 20525 PEF 20525 Register Description (ISR2) XDU Transmit Data Underrun Interrupt This bit is set to '1', if the current frame was terminated by the SCC with an abort sequence, because neither a 'frame end' indication was detected in the FIFO (to complete the current frame) nor more data is available in the SCC transmit FIFO. Note: The transmitter is stopped if this condition occurs. The XDU condition MUST be cleared by reading register ISR1, thus bit 'XDU' should not be masked via register IMR1. SUEX Signalling Unit Counter Exceeded Interrupt This bit is set to '1', if 256 correct or incorrect SU's have been received and the internal counter is reset to 0. PLLA DPLL Asynchronous Interrupt This bit is only valid, if the receive clock is derived from the internal DPLL and FM0, FM1 or Manchester data encoding is selected (depending on the selected clock mode and data encoding mode). It is set to '1' if the DPLL has lost synchronization. Reception is disabled until synchronization has been regained again. If the transmitter is supplied with a clock derived from the DPLL, transmission is also interrupted. CDSC Carrier Detect Status Change Interrupt This bit is set to '1', if a state transition has been detected at signal CD. Because only a state transition is indicated via this interrupt, the current status can be evaluated by reading bit 'CD' in status register STARH. Preliminary Data Sheet 5-193 09.99 PEB 20525 PEF 20525 Register Description (IMR0) Register 5-75 IMR0 Interrupt Mask Register 0 CPU Accessibility: read/write Reset Value: FFH Channel A Channel B Offset Address: 54H A4H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 RPF RME RFS FLEX 3 2 1 0 ALLS XDU SUEX 1 IMR0 RDO Register 5-76 RFO PCE RSC IMR1 Interrupt Mask Register 1 CPU Accessibility: read/write Reset Value: FFH Channel A Channel B Offset Address: 55H A5H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 IMR1 TIN CSC Preliminary Data Sheet XMR XPR 5-194 09.99 PEB 20525 PEF 20525 Register Description (IMR2) Register 5-77 IMR2 Interrupt Mask Register 2 CPU Accessibility: read/write Reset Value: 03H Channel A Channel B Offset Address: 56H A6H typical usage: written by CPU; read and evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 0 0 PLLA CDSC IMR2 0 Preliminary Data Sheet 0 0 0 5-195 09.99 PEB 20525 PEF 20525 Register Description (IMR2) (IM) Interrupt Mask Bits Each SCC interrupt event can generate an interrupt signal indication via pin INT/INT. Each bit position of registers IMR0..IMR2 is a mask for the corresponding interrupt event in the interrupt status registers ISR0..ISR2. Masked interrupt events never generate an interrupt indication via pin INT/INT. bit = '0' The corresponding interrupt event is NOT masked and will generate an interrupt indication via pin INT/INT. bit = '1' The corresponding interrupt event is masked and will NEITHER generate an interrupt vector NOR an interrupt indication via pin INT/INT. Moreover, masked interrupt events are: * not displayed in the interrupt status registers ISR0..ISR2 if bit 'VIS' in register CCR0L is programmed to '0'. * displayed in interrupt status registers ISR0..ISR2 if bit 'VIS' in register CCR0L is programmed to '1'. Note: After RESET, all interrupt events are masked. For detailed interrupt event description refer to the corresponding bit position in registers ISR0..ISR2. Preliminary Data Sheet 5-196 09.99 PEB 20525 PEF 20525 Register Description (RSTA) Register 5-78 RSTA Receive Status Byte CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: 58H A8H typical usage: written by PASSAT to RFIFO; read from RFIFO and evaluated by CPU Bit 7 6 5 4 3 2 1 0 C/R LA Receive Status Byte VFR RDO CRCOK RAB HA(1:0)/ SU(1:0) The Receive Status Byte 'RSTA' contains comprehensive status information about the last received frame (HDLC/PPP). The SCC attaches this status byte to the receive data and thus it should be read from the RFIFO. In HDLC/PPP modes the RSTA value can optionally be read from this register address. In extended transparent mode this status field does not apply. Preliminary Data Sheet 5-197 09.99 PEB 20525 PEF 20525 Register Description (RSTA) VFR Valid Frame Determines whether a valid frame has been received. VFR='0' The received frame is invalid. An invalid frame is either a frame which is not an integer number of 8 bits (n * 8 bits) in length (e.g. 25 bits), or a frame which is too short, taking into account the operation mode selected via CCR2L (MDS1, MDS0, ADM) and the selected CRC algorithm (CCR1L:C32) as follows: for CCR3H:DRCRC = '0' (CRC reception enabled): * automode / address mode 2 (16-bit address) 4 bytes (CRC-CCITT) or 6 (CRC-32) * automode / address mode 2 (8-bit address) 3 bytes (CRC-CCITT) or 5 (CRC-32) * address mode 1: 3 bytes (CRC-CCITT) or 5 (CRC-32) * address mode 0: 2 bytes (CRC-CCITT) or 4 (CRC-32) for CCR3H:DRCRC = '1' (CRC reception disabled): * automode / address mode 2 (16-bit address): 2 bytes * automode / address mode 2 (8-bit address): 1 byte * address mode 1: 1 byte * address mode 0: 1 byte Note: Shorter frames are not reported at all. VFR='1' RDO The received frame is valid. Receive Data Overflow RDO='0' No receive data overflow has occurred. RDO='1' A data overflow has occurred during reception of the frame. Additionally, an interrupt can be generated (refer to ISR0:RDO/IMR0:RDO). Preliminary Data Sheet 5-198 09.99 PEB 20525 PEF 20525 Register Description (RSTA) CRCOK CRC Compare/Check CRCOK='0' CRC check failed, received frame contains errors. CRCOK='1' CRC check OK; the received frame does not contain CRC errors. Preliminary Data Sheet 5-199 09.99 PEB 20525 PEF 20525 Register Description (RSTA) C/R Command/Response Significant only if 2-byte address mode has been selected. Value of the C/R bit (bit 1 of high address byte) in the received frame. The interpretation depends on the setting of the 'CRI' bit in the RAH1 register (See "RAH1" on page 180.). LA Low Byte Address Compare Significant in automode and address mode 2 only. The low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two addresses (RAL1, RAL2). LA='0' RAL2 has been recognized. LA='1' RAL1 has been recognized. According to the X.25 LAPB protocol, RAL1 is interpreted as the address of a COMMAND frame and RAL2 is interpreted as the address of a RESPONSE frame. Preliminary Data Sheet 5-200 09.99 PEB 20525 PEF 20525 Register Description (RSTA) 5.2.3 Channel Specific DMA Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), channel specific offset address and usual handling; * a table containing the bit information (name of bit positions); * a section containing the detailed description of each bit. Preliminary Data Sheet 5-201 09.99 PEB 20525 PEF 20525 Register Description (XBCL) Register 5-79 XBCL Transmit Byte Count (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: B8H D2H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 2 1 0 XBC(7:0) Register 5-80 XBCH Transmit Byte Count (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: B9H D3H typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 XME XF XIF 0 Preliminary Data Sheet 5-202 3 XBC(11:8) 09.99 PEB 20525 PEF 20525 Register Description (XBCH) XBC (11:0) Transmit Byte Count This register is used in DMA Mode only, to program the length (1...4096 bytes) of the next frame to be transmitted. The length of the block in number of bytes is: Length = XBC + 1 This allows the PASSAT to request the correct amount of DMA cycles after an 'XF' or' XIF' command. XME Transmit Message End Command Only valid in external DMA controller mode. This bit is identical to 'XME' command bit (refer to register "CMDRL" on page 5-132). XF Transmit Frame Command Only valid in external DMA controller mode. This bit is identical to 'XF' command bit (refer to register "CMDRL" on page 5-132). XIF Transmit I-Frame Command Only valid in external DMA controller mode. This bit is identical to 'XIF' command bit (refer to register "CMDRL" on page 5-132). Preliminary Data Sheet 5-203 09.99 PEB 20525 PEF 20525 Register Description (RMBSL) Register 5-81 RMBSL Receive Maximum Buffer Size (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: C4H DEH typical usage: written by CPU, evaluated by PASSAT Bit 7 6 5 4 3 2 1 0 9 8 Receive Maximum Buffer Size RMBS(7:0) Register 5-82 RMBSH Receive Maximum Buffer Size (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: C5H DFH typical usage: written by CPU, evaluated by PASSAT Bit 15 14 13 12 11 10 Receive Maximum Buffer Size RE DRMBS Preliminary Data Sheet 0 0 5-204 RMBS(11:8) 09.99 PEB 20525 PEF 20525 Register Description (RMBSH) RE Receive DMA Enable Only valid if external DMA controller support is enabled. Self-clearing command bit: DRMBS RE='0' The DMA controller is not set up to forward receive data into a buffer in memory. RE='1' Setting this bit to '1' enables the DMA support logic to request the external DMA controller to transfer receive data when available in RFIFO. Disable Receive Maximum Buffer Size (RMBS) Check Only valid if external DMA controller support is enabled. DRMBS='0' Evaluation of bit field RMBS(11:0) is enabled. DRMBS='1' Evaluation of bit field RMBS(11:0) is disabled. RMBS(11:0) Receive Maximum Buffer Size Only valid if external DMA controller support is enabled. The size of the receive buffer in host memory can be set up in this bit field to ensure that request for DMA transfers are inhibited when the maximum buffer size is reached. An RBF interrupt is generated (if unmasked) to inform the CPU. If the external DMA controller supports this function, it can be disabled by setting bit 'DRMBS' to '1'. Preliminary Data Sheet 5-205 09.99 PEB 20525 PEF 20525 Register Description (RBCL) Register 5-83 RBCL Receive Byte Count (Low Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: C6H E0H typical usage: written by PASSAT, evaluated by CPU Bit 7 6 5 4 3 2 1 0 2 1 0 RBC(7:0) Register 5-84 RBCH Receive Byte Count (High Byte) CPU Accessibility: read/write Reset Value: 00H Channel A Channel B Offset Address: C7H E1H typical usage: written by PASSAT, evaluated by CPU Bit 7 6 5 4 RDO 0 0 0 Preliminary Data Sheet 5-206 3 RBC(11:8) 09.99 PEB 20525 PEF 20525 Register Description (RBCH) RBC(11:0) Receive Byte Count This bit field determines the receive byte count (1..4095) of the currently received frame/block. RDO RDO Indication Only valid in DMA controller mode. This bit is identical to the 'RDO' status bit belonging to this frame (see description of register "RSTA" on page 5-197). Preliminary Data Sheet 5-207 09.99 PEB 20525 PEF 20525 Register Description (VER0) 5.2.4 Miscellaneous Registers Register 5-85 VER0 Version Register 0 CPU Accessibility: read/write Reset Value: 83H Offset Address: ECH typical usage: evaluated by CPU Bit 7 6 5 4 3 2 1 Manufacturer Code 0 Fix '1' VER(7:0) Register 5-86 VER1 Version Register 1 CPU Accessibility: read/write Reset Value: F0H Offset Address: EDH typical usage: evaluated by CPU Bit 7 6 5 4 3 Device Code (bits 3 .. 0) 2 1 0 Manufacturer Code VER(15:8) Preliminary Data Sheet 5-208 09.99 PEB 20525 PEF 20525 Register Description (VER2) Register 5-87 VER2 Version Register 2 CPU Accessibility: read/write Reset Value: 05H Offset Address: EEH typical usage: evaluated by CPU Bit 7 6 5 4 3 2 1 0 2 1 0 Device Code (bits 11 .. 4) VER(23:16) Register 5-88 VER3 Version Register 3 CPU Accessibility: read/write Reset Value: 10H Offset Address: EFH typical usage: evaluated by CPU Bit 7 6 5 4 3 Version Number Device Code (bits 15 .. 12) VER(31:24) Preliminary Data Sheet 5-209 09.99 PEB 20525 PEF 20525 Register Description (VER3) VER(31:0) Version Register Identical to 32 bit boundary scan ID string. The 32 bit string consists of the bit fields: VER(31:28) 1H Version Number VER(27:12) 005FH Device Code VER(11:0) 083H Manufacturer Code (LSB fixed to '1') Preliminary Data Sheet 5-210 09.99 PEB 20525 PEF 20525 Programming 6 Programming 6.1 Initialization After Reset the CPU has to write a minimum set of registers and an optional set depending on the required features and operating modes. First, the following initialization steps must be taken: * Select serial protocol mode (refer to Table 4-1 "Protocol Mode Overview" on page 480), * Select encoding of the serial data (refer to Chapter 3.2.13 "Data Encoding" on page 3-71), * Program the output characteristics of - pin TxD (selected with bit 'ODS' in "Channel Configuration Register 1 (Low Byte)" on page 5-139) and - interrupt pin INT/INT (selected with bit field 'IPC(1:0)' in "Global Mode Register" on page 5-109), * Choose a clock mode (refer to Table 3-1 "Overview of Clock Modes" on page 3-44). * Power-up the oscillator unit (with or without shaper) by re-setting bit GMODE:OSCPD to '0', if appropriate (GMODE:DSHP='0' enables the shaper). The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the PASSAT between power-up and power-down mode. This has no influence upon the contents of the registers, i.e. the internal state remains stored. In power-down mode however, all internal clocks are disabled, no interrupts from the corresponding channel are forwarded to the CPU. This state can be used as a standby mode, when the channel is (temporarily) not used, thus substantially reducing power consumption. The PASSAT should usually be initialized in Power-Down mode. The need for programming further registers depends on the selected features (serial mode, clock mode specific features, operating mode, address mode, user demands). 6.2 Interrupt Mode 6.2.1 Data Transmission (Interrupt Driven) In transmit direction 2 x 32 byte FIFO buffers (transmit pools) are provided for each channel. After checking the XFIFO status by polling the Transmit FIFO Write Enable bit (bit 'XFW' in STARL register) or after a Transmit Pool Ready ('XPR') interrupt, up to 32 bytes may be entered by the CPU into the XFIFO. The transmission of a packet can be started by issuing an 'XF' or 'XIF' command via the CMDRL register. If enabled, a specified number of preambles (refer to registers CCR2H and PREAMB) are sent out optionally before transmission of the current packet starts. Preliminary Data Sheet 6-211 09.99 PEB 20525 PEF 20525 Programming If the transmit command does not include an end of message indication (CMDRL.XME), PASSAT will repeatedly request for the next data block by means of an 'XPR' interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the CPU. This process will be repeated until the CPU indicates the end of message per 'XME' command, after which packet transmission is finished correctly by appending the CRC and closing flag sequence. Consecutive packets may be transmitted as back-to-back packets and may even share a flag (enabled via CCR1L.SFLG), if service of XFIFO is quick enough. In case no more data is available in the XFIFO prior to the arrival of the end-of-message indiction ('XME'), the transmission of the packet is terminated with an abort sequence and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet may also be aborted per software at any time (CMDRL.XRES). The data transmission sequence, from the CPU's point of view, is outlined in Figure 6-1. A c tion ta ke n by CP U ST AR T In terru p t in dication to C P U R e set T ra n sm itte r (C M D R L .XR E S ) A c tion ta ke n b y th e S C C 'X P R ' In te rrup t T ra nsm it se ria l d ata a nd a pp e nd tra ile r T ra nsm it se ria l d ata XF IF O R EAD Y Issu e C om m an d C M D R L.XF or C M D R L.XIF No W rite D ata to XF IF O (u p to 32 byte s) Issu e C om m an d C M D R L.XF +.X M E or C M D R L.XIF +.X M E E n d of M es sag e ? Yes Figure 6-1 Interrupt Driven Data Transmission (Flow Diagram) Preliminary Data Sheet 6-212 09.99 PEB 20525 PEF 20525 Programming 6.2.2 Data Reception (Interrupt Driven) Also 2 x 32 byte FIFO buffers (receive pools) are provided for each channel in receive direction. There are different interrupt indications concerned with the reception of data: * 'RPF' (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited with the receive FIFO threshold in register CCR3H, bit field 'RFTH(1..0)'; default is 32 bytes) can be read from RFIFO and the received message is not yet complete. * 'RME' (Receive Message End) interrupt, indicating that the reception of one message is completed, i.e. either - one message which fits into RFIFO not exceeding the receive FIFO threshold, or - the last part of a message, all in all exceeding the receive FIFO threshold is stored in the RFIFO. In addition to the message end ('RME') interrupt the following information about the received packet is stored by PASSAT in special registers and/or RFIFO: Table 6-1 Status Information after RME interupt Status Information Location Length of received message registers RBCH, RBCL CRC result (good/bad) RSTA register (or last byte of received data) Valid frame (yes/no) RSTA register (or last byte of received data) ABORT sequence recognized (yes/no) RSTA register (or last byte of received data) Data overflow (yes/no) RSTA register (or last byte of received data) Results from address comparison (with automatic address handling) RSTA register (or last byte of received data) Type of frame (COMMAND/RESPONSE) RSTA register (or last byte of received data) (with automatic address handling) Type of Signaling Unit (in SS7 mode) RSTA register (or last byte of received data) Note: After the received data has been read from the RFIFO, this must be explicitly acknowledged by the CPU issuing an 'RMC' (Receive Message Complete) command. The CPU has to handle the 'RPF' interrupt before the complete 2 x 32byte FIFO is filled up with receive data which would cause a "Receive Data Overflow" condition. The data reception sequence, from the CPU's point of view, is outlined in Figure 6-2. Preliminary Data Sheet 6-213 09.99 PEB 20525 PEF 20525 Programming A c tion tak en by CPU STAR T In terru pt in dic atio n to C P U R es et R e ceive r (C M D R H .R R E S ) A c tiva te R e ce ive r (C C R 3L .R A C ) W AIT F OR IN TER R U PT 'R P F ' In terru pt 'R M E '/'TC D ' In terru pt R ea d re giste rs R BC L, RB C H (R c B yte C ou n t) R ea d [3 2] 1) b yte s from R FIF O R ea d [R B C L % 3 2] 1) , 2) b yte s from R FIF O R elea se R F IFO (C M D R H .R M C ) 1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field RFTH(1:0) in register . 2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register (depending on the selected receive threshold RFTH(1:0)). Figure 6-2 Interrupt Driven Data Reception (Flow Diagram) Preliminary Data Sheet 6-214 09.99 PEB 20525 PEF 20525 Programming 6.3 External DMA Supported Mode The following table provides a definition of terms used in this chapter to describe the operation with external DMA controller support. Table 6-2 DMA Terminology Packet A "Packet" is a connected block of data bytes. If a receive status byte (RSTA) is attached to data bytes, it is also considered as part of the packet. Buffer A "Buffer" is a limited space in memory that is reserved for DMA reception/transmission. PASSAT can optionally keep track of predefined (receive) buffer limits and notify the CPU with an appropriate interrupt if this functionality is not provided by the external DMA controller. A packet can go into one single buffer, or it can go fragmented into multiple buffers. Block A "Block" is the amount of data that is transfered from the memory to the XFIFO (transmit DMA transfer) or from the RFIFO to the memory. The block size is 32 bytes by default. It can be lowered with the receive FIFO threshold in register CCR3H, bit field 'RFTH(1..0)'. Bus Cycle A "Bus Cycle" corresponds to a single byte/word transfer. Multiple bus cycles make up a block transfer. DMA Transfer A "DMA Transfer" is the movement of complete buffers and/or packets between the XFIFO/RFIFO and the memory by the external DMA controller. 6.3.1 Data Transmission (With External DMA Support) Any packet transmission is prepared by initializing the external DMA controller with the transmit buffer start address and writing the packet size in number of bytes to registers XBCL/XBCH. Now there are two possible scenarios: * If the prepared transmit buffer in memory contains a complete packet, the start command for DMA transmission is issued by setting bits 'XF' and 'XME' in register XBCH to '1'. The DMA support logic will request the external DMA controller to transfer data into the XFIFO . After the last byte has been transmitted, the protocol machine appends the trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit DMA Transfer End (TDTE) interrupt is generated (refer to Figure 6-3). * If a transmit packet is distributed over more than one transmit buffer in memory, the 'XF' command (without setting the 'XME' bit) forces PASSAT to request data transfers from the external DMA controller from this buffer. A Transmit DMA Transfer End Preliminary Data Sheet 6-215 09.99 PEB 20525 PEF 20525 Programming (TDTE) interrupt is generated whenever a block of <XBC> bytes is completely transferred. For the last buffer, containing the end of the transmit packet, the 'XF' command is issued together with bit 'XME' set (refer to Figure 6-4). After transmission is complete, the optional generation of the ALLS interrupt indicates that all transmit data has been sent on pin TxD. Note: In HDLC Automode, the 'XF' command may be replaced by the 'XIF' command in the same register, when transmission of an I-frame is desired. CPU / MEMORY PASSAT Packet n: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') DMA transfer of <XBC> transmit data bytes XBC TFIFO ... TFIFO TFIFO TDTE interrupt ALLS interrupt (optional) Packet (n+1): (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') XBC ... Figure 6-3 DMA Transmit (Single Buffer per Packet) Preliminary Data Sheet 6-216 09.99 PEB 20525 PEF 20525 Programming PASSAT CPU / MEMORY Packet n, Buffer 0: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF') DMA transfer of <XBC> transmit data bytes XBC TFIFO ... TFIFO TFIFO TDTE interrupt Packet n, Buffer 1: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF') DMA transfer of <XBC> transmit data bytes XBC TFIFO ... TFIFO TFIFO TDTE interrupt Packet n, Buffer m: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') DMA transfer of <XBC> transmit data bytes XBC TFIFO ... TFIFO TFIFO TDTE interrupt ALLS interrupt (optional) Figure 6-4 Fragmented DMA Transmission (Multiple Buffers per Packet) Preliminary Data Sheet 6-217 09.99 PEB 20525 PEF 20525 Programming 6.3.2 Data Reception (With External DMA Support) The receive DMA support logic is able to limit its requesting for data transfers to a byte count programmed in register RMBSL/RMBSH. If the external DMA controller is capable of handling maximum receive buffer sizes itself, this feature can be disabled by setting bit RMBSH:DRMBS to '1'. If a new packet is received by the SCC, the DMA support logic will request the external DMA controller to move receive data out of the RFIFO. Now there are two possible scenarios: * If the maximum buffer size programmed in register RMBSL/RMBSH has been transferred (only if RMBSH:DRMBS = '0'), PASSAT stops requesting for data transfers and a Receive Buffer Full (RBF) interrupt is generated. The CPU now updates the receive buffer base address in the external DMA controller and releases the receive DMA control logic by setting the 'RE' bit in register RMBSH. Optionally the maximum buffer size value can be updated with the same register write access. * If the end of a received packet/block is part of the curent DMA transfer, PASSAT generates a Receive DMA Transfer End (RDTE) interrupt and stops operation. The CPU now reads the received byte count from registers RBCL/RBCH. The receive DMA support logic will not continue requesting for data transfer until it is set up again with the 'RE' command in register RMBSH. If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size RMBS is chosen to be larger than the expected receive packets, each buffer will contain the whole packet (see Figure 6-5). In this case (or if RMBSH:DRMBS = '1') a Receive Buffer Full (RBF) interrupt will never occur, simplifying the software. To ensure that no packets exceeding the maximum buffer size are forwarded from the SCC to the RFIFO, the receive packet length should be limited with registers RLCRL/RLCRH. Preliminary Data Sheet 6-218 09.99 PEB 20525 PEF 20525 Programming PASSAT CPU / MEMORY Packet 0: (prepare external DMA controller with receive buffer start address) (set max. receive buffer size and issue 'RE' command) DMA transfer of all receive data bytes RMBS RFIFO ... RFIFO RFIFO RDTE interrupt (read RBC register) RBC Packet 1: (prepare external DMA controller with receive buffer start address) ... Figure 6-5 DMA Receive (Single Buffer per Packet) Figure 6-6 shows an example for fragmented reception of a packet larger than the prepared receive buffers in memory. In this case the length of the received packet is 199 bytes, each of the buffers in host memory is 128 bytes deep: Preliminary Data Sheet 6-219 09.99 PEB 20525 PEF 20525 Programming 199 Bytes Payload Packet ... Receive Buffers in Memory 1 32 32 32 32 32 7 ... 1 128 2nd packet fragment 128 1st packet fragment Figure 6-6 32 Fragmented Reception per DMA (Example) After the external DMA controller is initialized with the base address of receive buffer #1 and the maximum buffer size RMBS is written to PASSAT, simultaneously activated with the 'RE' command, requesting of DMA transfer from the RFIFO to the receive buffer takes place in blocks of 32 bytes (unless changed with bit field 'RFTH' in register CCR3H). After four 32-byte-blocks have been transferred, the first receive buffer is filled up completely with receive data. The PASSAT indicates this by generating the RBF interrupt. Now the CPU has to provide the base address of the second receive buffer to the external DMA controller and issue the 'RE' command to PASSAT again. This allows the external DMA controller to continue data transfers into the second receive buffer. After another two 32-byte-blocks have been transferred, the DMA request for the remaining 7 bytes (including the RSTA byte) is generated to the external DMA controller, follwed by the generation of the RDTE interrupt. Now the DMA transfer is completed and software has to read the number of received bytes from the Receive Byte Count registers RBCL/ RBCH. The following figure (Figure 6-7) gives the sequence of actions from both, the PASSAT and the CPU for this example (fragmented reception of 199 bytes into two receive buffers): Preliminary Data Sheet 6-220 09.99 PEB 20525 PEF 20525 Programming PASSAT CPU / MEMORY Packet 1, Fragment 1: (prepare external DMA controller with receive buffer start address) (set max. receive buffer size to 128 bytes and issue 'RE' command) RMBS 32 DMA transfer of 128 receive data bytes 32 RFIFO 32 RFIFO 32 RFIFO RFIFO RBF interrupt Packet 1, Fragment 2: (prepare external DMA controller with receive buffer start address) (issue 'RE' command) RMBS 32 DMA transfer of 71 receive data bytes 32 RFIFO 7 RFIFO RFIFO RDTE interrupt (read RBC register) RBC Packet 2, Fragment 1: (prepare external DMA controller with receive buffer start address) ... Figure 6-7 Fragmented Reception Sequence (Example) Preliminary Data Sheet 6-221 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7 Electrical Characteristics (Preliminary) All electrical characteristics given in this chapter are preliminary and subject to change. 7.1 Absolute Maximum Ratings Parameter Symbol Ambient temperature under bias PEB PEF Storage temperature IC supply voltage Voltage on any signal pin with respect to ground ESD robustness1) HBM: 1.5 k, 100 pF 1) Limit Values Unit TA TA Tstg VDD3 VS 0 to 70 - 40 to 85 C C - 65 to 125 C - 0.3 to 3.6 V - 0.3 to 5.5 V VESD,HBM 2500 V According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Operating Range Parameter Symbol Ambient temperature PEB TA PEF TA Junction temperature Supply voltage Ground TJ VDD3 VSS Limit Values Unit Test Condition min. max. 0 -40 70 85 C C 0 125 C 3.0 3.6 V 0 0 V Note: In the operating range, the functions given in the circuit description are fulfilled. Preliminary Data Sheet 7-222 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.3 Table 7-1 Thermal Package Characteristics Thermal Package Characteristics P-TQFP-100-3 Parameter Symbol Value Unit Thermal Package Resistance Junction to Ambient Airflow: Ambient Temperature: without airflow TA=-40C JA(0,-40) 45.7 K/W without airflow TA=+25C JA(0,25) 41.5 K/W airflow 1 m/s (~200 lfpm) TA=+25C JA(1,25) 39.6 K/W airflow 2 m/s (~400 lfpm) TA=+25C JA(2,25) 38.8 K/W airflow 3 m/s (~600 lfpm) TA=+25C JA(3,25) 38.4 K/W Table 7-2 Thermal Package Characteristics P-LFBGA-80-2 Parameter Symbol Value Unit Thermal Package Resistance Junction to Ambient Airflow: Ambient Temperature: without airflow TA=-40C JA(0,-40) 56.1 K/W without airflow TA=+25C JA(0,25) 50.6 K/W airflow 1 m/s (~200 lfpm) TA=+25C JA(1,25) 48.2 K/W airflow 2 m/s (~400 lfpm) TA=+25C JA(2,25) 47.2 K/W airflow 3 m/s (~600 lfpm) TA=+25C JA(3,25) 46.6 K/W Preliminary Data Sheet 7-223 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.4 DC Characteristics Parameter Symbol Input low voltage Input high voltage Output low voltage Output high voltage Power supply current operational (average) VIL VIH VOL Limit Values Unit Notes min. max. - 0.4 0.8 V 2.0 5.5 V 0.45 V 2.4 VOH ICC (AV) V tbd mA IOL = 7 mA 1) IOL = 2 mA 2) IOH = - 1.0 mA VDD = 3.3 V, TA = 25 C, CLK = 20 MHz, XTAL = 20 MHz, inputs at VSS/VDD, no output loads power down (no clocks) Power dissipation ICC (PD) tbd P 100 VDD = 3.3 V, TA = 25 C mW VDD = 3.3 V, TA = 25 C, mA CLK = 20 MHz, XTAL = 20 MHz, inputs at VSS/VDD, no output loads Input leakage current IIL tbd A VDD = 3.3 V, GND = 0 V; inputs at VSS/VDD, no output loads Output leakage current IOZ tbd A VDD = 3.3 V, GND = 0 V; VOUT = 0 V, VDDP + 0.4 1) Apply to the next pins: tbd. 2) Apply to all the I/O and O pins that do not appear in the list in note 1), except tbd. The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Preliminary Data Sheet 7-224 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.5 AC Characteristics Interface Pins TA = 0 to + 70 C; VDD3 = 3.3 V 0.3 V Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0". The AC testing input/output waveforms are shown below. 2.4 2.0 2.0 Device Under Test Test Points 0.8 0.8 C Load = 50 pF 0.45 ITS09800 Figure 7-1 7.6 Input/Output Waveform for AC Tests Capacitances Interface Pins Table 7-3 Capacitances TA = 25 C; VDD3 = 3.3 V 0.3 V, VSS = 0 V Parameter Input capacitance Output capacitance I/O-capacitance Preliminary Data Sheet Symbol CIN COUT CIO Limit Values Unit min. max. tbd tbd pF tbd tbd pF tbd tbd pF 7-225 Test Condition 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7 Timing Diagrams 7.7.1 Microprocessor Interface Timing 7.7.1.1 Microprocessor Interface Clock Timing 1 2 3 C LK Figure 7-2 Microprocessor Interface Clock Timing Table 7-4 Microprocessor Interface Clock Timing No. Parameter Limit Values min. 1 CLK clock period max. 30 CLK frequency Unit ns 33 MHz 2 CLK high time 11 ns 3 CLK low time 11 ns Preliminary Data Sheet 7-226 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.1.2 Siemens/Intel Bus Interface Timing * A (7 :0 ) B H E 1) 4 5 6 7 CS 8 17 RD 16 IN T 2) 10 11a 11 D (7 :0 ) D (1 5 :8 ) 1) 14a 14 15 15a D TAC K Figure 7-3 Siemens/Intel Read Cycle Timing * A (7 :0 ) B H E 1) 4 5 6 7 CS 9 17 WR 12 13 D (7 :0 ) D (1 5 :8 ) 1) 14a 14 15 15a D TAC K Figure 7-4 Siemens/Intel Write Cycle Timing (1) Signals BHE and D(15:8) only available in 16-bit Intel bus mode (2) Interrupt signal shown is push-pull, active high. Same timings apply to push-pull, active low interrupt signal. In case of open-drain output the timing depends on external components. Preliminary Data Sheet 7-227 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) Table 7-5 Siemens/Intel Bus Interface Timing No. Parameter Limit Values min. Unit max. 4 active address to active RD/WR setup time 10 ns 5 inactive RD/WR to inactive address hold time 0 ns 6 active CS to active RD/WR setup time 0 ns 7 inactive RD/WR to inactive CS hold time 0 ns 8 RD active pulse width tbd ns 9 WR active pulse width 30 ns 10 active RD to valid data delay 11 inactive RD to invalid data hold time 15 5 11a inactive RD to data high impedance delay ns ns 15 ns 12 valid data to inactive WR setup time 15 ns 13 inactive WR to invalid data hold time 5 ns 14 active RD/WR to active DTACK delay 14a active CS to driven DTACK delay 15 inactive RD/WR to inactive DTACK delay 15a inactive CS to DTACK high impedance delay 16 inactive RD to inactive INT/INT delay 17 RD/WR inactive pulse width Preliminary Data Sheet tbd 7-228 10 ns tbd ns 10 ns tbd ns 1 TCLK ns 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.1.3 Motorola Bus Interface Timing * A (7 :0 ) A (7 :1 ) 1) 40 41 CS 42 R /W 43 44 45 46 55 DS L D S , U D S 1) 54 IN T 2) 48 49a 49 D (7 :0 ) D (1 5 :8 ) 1) 52a 52 53 53a DTACK Figure 7-5 Motorola Read Cycle Timing * A (7 :0 ) A (7 :1 ) 1) 40 41 CS 42 43 44 45 R /W 47 55 DS L D S , U D S 1) 50 51 D (7 :0 ) D (1 5 :8 ) 1) 52a 52 53 53a D TAC K Figure 7-6 Motorola Write Cycle Timing (1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode (2) Interrupt signal shown is push-pull, active high. Same timings apply to push-pull, active low interrupt signal. In case of open-drain output the timing depends on external components. Preliminary Data Sheet 7-229 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) Table 7-6 Motorola Bus Interface Timing No. Parameter Limit Values min. Unit max. 40 active address to active DS setup time 10 ns 41 inactive DS to inactive address hold time 0 ns 42 active CS to active DS setup time 0 ns 43 inactive DS to inactive CS hold time 0 ns 44 active R/W to active DS setup time 0 ns 45 inactive DS to inactive R/W hold time 0 ns 46 DS active pulse width (read access) tbd ns 47 DS active pulse width (write access) 30 ns 48 active DS (read) to valid data delay 49 inactive DS (read) to invalid data hold time 15 5 49a inactive DS (read) to data high impedance delay ns ns 15 ns 50 valid data to inactive DS (write) setup time 15 ns 51 inactive DS (write) to invalid data hold time 5 ns 52 active DS to active DTACK delay 10 ns tbd ns 10 ns 53a inactive CS to DTACK high impedance delay tbd ns 54 inactive DS (read) to inactive INT/INT delay 1 TCLK 55 DS inactive pulse width 52a active CS to driving DTACK delay 53 inactive DS to inactive DTACK delay Preliminary Data Sheet tbd 7-230 ns 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2 PCM Serial Interface Timing 7.7.2.1 Clock Input Timing 81,84,87 82,85,88 RxCLK TxCLK XTAL1 Figure 7-7 Clock Input Timing Table 7-7 Clock Input Timing 83,86,89 No. Parameter Limit Values min. Unit max. 81 RxCLK clock period tbd ns 82 RxCLK high time tbd ns 83 RxCLK low time tbd ns 84 TxCLK clock period tbd ns 85 TxCLK high time tbd ns 86 TxCLK low time tbd ns 87 XTAL1 clock period (internal oscillator used) tbd ns XTAL1 clock period (TTL clock signal supplied) tbd ns XTAL1 high time (internal oscillator used) tbd ns XTAL1 high time (TTL clock signal supplied) tbd ns XTAL1 low time (internal oscillator used) tbd ns XTAL1 low time (TTL clock signal supplied) tbd ns 88 89 Preliminary Data Sheet 7-231 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.2 Receive Cycle Timing 90 Receive Clock (Note 1) 91 92 91 92 RxD (Note 2) 91 92 RxD (Note 3) 93 94 CD (Note 4) Figure 7-8 Receive Cycle Timing Note: 1. Whichever supplies the receive clock depending on the selected clock mode: externally clocked via RxCLK or XTAL1 or internally clocked via DPLL or BRG. (No edge relation can be measured if the internal receive clock is derived from the external clock source by devision stages (BRG) or DPLL) 2. NRZ, NRZI and Manchester data encoding 3. FM0 and FM1 data encoding 4. If Carrier Detect auto start feature enabled (not for clock modes 1 and 5) Preliminary Data Sheet 7-232 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) Table 7-8 Receive Cycle Timing No. Parameter Limit Values min. Receive data rates 90 Clock period Unit max. externally clocked (HDLC) 16 Mbit/s internally clocked (DPLL modes) 2 Mbit/s internally clocked (non DPLL modes) 2 Mbit/s externally clocked tbd ns internally clocked (DPLL modes) tbd ns internally clocked (non DPLL modes) tbd ns 91 RxD to RxCLK setup time tbd ns 92 RxD to RxCLK hold time tbd ns 93 CD to RxCLK rising edge setup time tbd ns 94 CD to RxCLK falling edge hold time tbd ns Preliminary Data Sheet 7-233 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.3 Transmit Cycle Timing 100 Transmit Clock (Note1) 101 TxD (Note2,5) 102 102 TxD (Note3) 103 103 TxCLK (Note4) 104 105 CxD CTS 106 106 RTS (Note5) Figure 7-9 Transmit Cycle Timing Note: 1. Whichever supplies the transmit clock depending on the selected clock mode: externally clocked via TxCLK, RxCLK or XTAL1 or internally clocked via DPLL or BRG. (No edge relation can be measured if the internal transmit clock is derived from the external clock source by devision stages (BRG) or DPLL) 2. NRZ, NRZI and Manchester data encoding 3. FM0 and FM1 data encoding 4. If TxCLK output feature is enabled (only in some clock modes) 5. The timing is valid for non bus configuration modes and bus configuration mode 1. In bus configuration mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e. driven by the falling TxCLK edge. Preliminary Data Sheet 7-234 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) Table 7-9 Transmit Cycle Timing No. Parameter Limit Values min. Transmit data rates 100 Clock period Unit max. externally clocked 16 Mbit/s internally clocked (DPLL modes) 2 Mbit/s internally clocked (non DPLL modes) 2 Mbit/s externally clocked tbd ns internally clocked (DPLL modes) tbd ns internally clocked (non DPLL modes) tbd ns 101 TxD to TxCLK delay (NRZ, NRZI encoding) tbd ns 102 TxD to TxCLK delay (FM0, FM1, Manchester encoding) tbd ns 103 TxD to TxCLK(out) delay (output function enabled) tbd tbd ns 104 CxD to TxCLK setup time, CTS to TxCLK setup time tbd ns 105 CxD to TxCLK hold time, CTS to TxCLK hold time tbd ns 106 RTS to TxCLK delay (not bus configuration mode) RTS to TxCLK delay (bus configuration mode) Preliminary Data Sheet 7-235 tbd ns tbd ns 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.4 Clock Mode 1 Strobe Timing RxCLK 110 111 CD (RxStrobe) RxD (Note1) valid 112 113 TxCLK (TxStrobe) 114 115 TxD (Note1,3) 114 115 TxD (Note2,3) Figure 7-10 Clock Mode 1 Strobe Timing Note: 1. No bus configuration mode and bus configuration mode 1 2. Bus configuration mode 2 3. TxD Idle is either active high or high impedance if 'open drain' output type is selected. Table 7-10 Clock Mode 1 Strobe Timing No. Parameter Limit Values min. Unit max. 110 Receive strobe to RxCLK setup tbd ns 111 Receive strobe to RxCLK hold tbd ns 112 Transmit strobe to RxCLK setup tbd ns 113 Transmit strobe to RxCLK hold tbd ns 114 TxD to RxCLK delay tbd ns 115 TxD to RxCLK high impedance delay tbd ns Preliminary Data Sheet 7-236 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.5 Clock Mode 5 Frame Synchronisation Timing RxCLK 130 131 CD (FSC) 132 132 TxCLK Note1 132 132 TxCLK Note2 Figure 7-11 Clock Mode 5 Frame Synchronisation Timing Note: 1. Normal operation and bus configuration mode 1 2. Bus configuration mode 2 Table 7-11 Clock Mode 5 Frame Synchronisation Timing No. Parameter Limit Values min. Unit max. 130 Sync pulse to RxCLK setup time tbd ns 131 Sync pulse to RxCLK hold time tbd ns 132 TxCLKout to RxCLK delay (time slot monitor) tbd Preliminary Data Sheet 7-237 tbd ns 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.6 Clock Mode 4 Receive Cycle Timing 141 RxCLK 140 RCG 142 RxD 143 Figure 7-12 Clock Mode 4 Receive Timing Table 7-12 Clock Mode 4 Receive Timing No. Parameter Limit Values min. Unit max. 140 RCG setup time tbd ns 141 RCG hold time tbd ns 142 RxD setup time tbd ns 143 RxD hold time tbd ns Preliminary Data Sheet 7-238 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.2.7 Clock Mode 4 Transmit Cycle Timing 14 6 T xC L K 1 45 14 7 TCG 14 9 T xD Figure 7-13 Clock Mode 4 Transmit Timing Table 7-13 Clock Mode 4 Transmit Timing No. Parameter Limit Values min. Unit max. 145 TCG setup time tbd ns 146 TCG hold time tbd ns 147 TxCLK to TxD delay tbd ns 149 TxD to TCG active delay 1 TTxCLK + tbd (ns) Note: TTxCLK is the TxCLK signal time period. Timing 149 results from a constant functional one clock offset + signal delay. Preliminary Data Sheet 7-239 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.3 Reset Timing power-on VDD3 151 CLK 150 RST Figure 7-14 Reset Timing Table 7-14 Reset Timing No. Parameter Limit Values min. Unit max. 150 RESET pulse width tbd ns 150 Number of CLK cycles during RESET active tbd CLK cycles Note: RESET may be asynchronous to CLK when asserted or deasserted. RESET may be asserted during power-up or asserted after power-up. Nevertheless deassertion must be clean. Preliminary Data Sheet 7-240 09.99 PEB 20525 PEF 20525 Electrical Characteristics (Preliminary) 7.7.4 JTAG-Boundary Scan Timing TRST 160 161 162 TCK 163 164 TMS 165 166 TDI 167 TDO Figure 7-15 JTAG-Boundary Scan Timing Table 7-15 JTAG-Boundary Scan Timing No. Parameter Limit Values Unit min. max. 160 TCK period tbd 161 TCK high time tbd ns 162 TCK low time tbd ns 163 TMS setup time tbd ns 164 TMS hold time tbd ns 165 TDI setup time tbd ns 166 TDI hold time tbd ns 167 TDO valid delay tbd ns Preliminary Data Sheet 7-241 ns 09.99 PEB 20525 PEF 20525 Test Modes 8 Test Modes 8.1 JTAG Boundary Scan Interface In the PASSAT a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 8-1 gives an overview about the TAP controller. Test Access Port (TAP) Pins CLOCK CLOCK TRST Reset TMS Test Control TDI Data in TDO TAP Controller - Finite State Machine - Instruction Register (3 bit) - Test Signal Generator Enable 6 ID Data out SS Data out Data out Figure 8-1 Control Bus 1 2 Boundary Scan (n bit) BS Data IN Clock Generation Identification Scan (32 bit) TCK . . . . . . n Block Diagram of Test Access Port and Boundary Scan Unit If no boundary scan operation is planned TRST has to be connected with VSS. TMS, TCK and TDI do not need to be connected since pull-up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put these unused inputs to defined levels, using pull-up resistors. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock Preliminary Data Sheet 8-242 09.99 PEB 20525 PEF 20525 Test Modes signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant '1' on TMS leads to normal operation of the chip. Table 8-1 Boundary Scan Sequence of PASSAT TDI -> Seq. No. Pin Number of Boundary Scan Cells Constant Value In, Out, Enable 1 2 00 2 1 0 3 3 100 4 2 00 5 1 0 6 1 0 7 1 0 8 3 001 9 3 011 10 3 111 11 3 000 12 1 0 13 3 100 14 1 0 15 2 00 16 2 11 17 2 00 18 2 00 19 2 00 20 2 00 21 2 00 22 2 00 23 1 0 24 2 00 25 2 00 26 2 00 Preliminary Data Sheet I/O 8-243 09.99 PEB 20525 PEF 20525 Test Modes Seq. No. Pin Number of Boundary Scan Cells Constant Value In, Out, Enable 27 2 00 28 2 00 29 2 00 30 2 00 31 2 00 32 1 0 33 3 000 34 3 000 35 3 000 36 2 00 37 2 00 38 2 00 39 2 00 40 2 00 41 2 00 42 2 00 43 2 00 44 3 000 45 3 000 46 1 0 47 1 0 48 3 000 49 3 0 50 3 000 51 3 000 52 1 0 53 3 000 54 3 000 55 3 000 56 3 000 Preliminary Data Sheet I/O 8-244 09.99 PEB 20525 PEF 20525 Test Modes Seq. No. Pin I/O Number of Boundary Scan Cells Constant Value In, Out, Enable 57 3 000 58 3 000 59 3 000 60 3 000 61 3 000 62 3 000 63 3 000 64 3 000 65 2 00 66 1 0 67 1 0 68 3 000 69 2 00 70 1 0 71 1 0 72 1 0 73 1 0 74 1 0 -> TDO An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that some functional output and input pins of PASSAT are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of PASSAT contains a total of n = 158 scan cells. The right column of Table 8-1 gives the initialization values of the cells. The desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via TDI (LSB first); see Table 8-2. EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external Preliminary Data Sheet 8-245 09.99 PEB 20525 PEF 20525 Test Modes Table 8-2 Boundary Scan Test Modes Instruction (Bit 2 ... 0) Test Mode 000 001 010 011 111 others EXTEST (external testing) INTEST (internal testing) SAMPLE/PRELOAD (snap-shot testing) IDCODE (reading ID code) BYPASS (bypass operation) handled like BYPASS interconnection line, whereas all output pins are held at constant values (`0' or `1', according to Table 8-1). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip, i.e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1', according to Table 8-1). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle. Note: In capture IR-state the code `001' is automatically loaded into the instruction register, i.e. if INTEST is wanted the shift IR-state does not need to be passed. SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. TDI -> 0001 0000 0000 0101 1111 0000 1000 001 1 -> TDO Note: Since in test logic reset state the code `011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state which is reached by TMS = 0, 1, 0, 0. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. Preliminary Data Sheet 8-246 09.99 PEB 20525 PEF 20525 Package Outlines 9 Package Outlines GPA09236 P-LFBGA-80-2 (Low-Profile Fine-Pitch Ball Grid Array) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Preliminary Data Sheet 9-247 09.99 PEB 20525 PEF 20525 Package Outlines GPP09189 P-TQFP-100-3 (Plastic Thin Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Preliminary Data Sheet 9-248 09.99