PEF20525V1.3 - Infineon Technologies

ICs for Communications

PPP and HDLC Synchronous Seri al Controller wi th 2 Channels

PASSAT

PEB 20525 Ver sion 1.1

PEF 20525 Ver sion 1.1

Preliminary Data Sheet 09.99 DS 2

•

For

uestions on technolo

gy,

deliver

and pri ces pleas e contac t the Infineon Technolo

ies Offices

in Germ an

or the Infineon T echnolo

ies Companies and R epresentatives worldwide:

see our webpa

e at http://w ww.infineon.com

•

PEB 20525, PEF 20525

Revision History: Current Version: 09.99

Previous Version: 07.99

(

in previ ous

Version

)

(

in current

Version

)

Sub

ects

(

or chan

es since last revision

)

2-24

2-25

2-30 2-23

2-24

2-29 Corrected RESET polarit

to active low

3-42

5-188 3-41

5-193 revised description of transmit data underrun

(

XDU

)

handlin

5-108 5-109 bit field codin

of "GMOD E :IPC

(

1:0

)

" chan

(

ual to ESCC2

)

5-108 5-109 bit field "G M OD E:DMODE

(

1:0

)

" reduced to "GMODE:EDMA"

5-108 5-110 bits "SHAPERPD" and "BYPASS" reduced to bit "DSHP"

- - HDLC "Non-Automode" renamed to "Address Mode 2"

5-123 5-128 Corrected reset value of re

ister STARH to 10H

- 6-215 Added description of external DMA support

Edition 09.99

Published by Infineon Technol ogies AG i. Gr .,

SC,

B al an s tr a ß e 73,

81541 München

ies AG i.Gr. 1999.

All Ri

hts Re se rved .

Attention please!

As f ar as patents or other ri

hts of third parties are concerned

liabilit

is onl

assumed for components

not for

applications

pr ocesses and circuits implemen ted within c omponents or assemblies.

The information describes the t

pe of component and shall not be considered as ass ured characteristics.

Term s of deliver

and ri

hts to chan

e desi

n reserved.

Due to technical re

uirements components ma

contain dan

erous substances. For information on the t

pes in

uestion p lease contact

our nearest Infineon Technolo

ies Office.

Infineon Technolo

ies AG is an approved CECC manufac turer.

Packing

Pl ease use the rec

clin

operators known to

ou. We can al so help

ou –

et in touch w ith

our nearest sales

office. B

re eme n t we will take pac kin

material back

if it is sorted. You must bear the costs of transport.

For pa ckin

m ateria l that is r etur ned to us unsor ted o r whic h we are n ot obl i

ed to accept

we shall have to invoice

ou for an

costs i ncurred.

Components used in life-support devices or systems must be express ly a u thorized for such purpose!

Cri t ical c ompo nen ts 1 of the Infineon Technolo

ies AG

onl

be used i n li f e-sup por t d ev ices or s

stems2 with

the express wri tten approv al of the I nfineon Technolo

ies AG.

1 A critical c omponent is a component used in a life-support device or s

stem whose failure can reasonabl

exp ec te d to c aus e t he fa i lure of t hat li f e-sup por t dev ice or s

stem

or to affect its safet

or effectiveness of that

device or s

stem.

2 Lif e supp o rt device s or s

stems are intended

(

)

to be implanted in the human bod

(

)

to support and/or

maintain and sustain human life. If the

fail

it is reasonable to assume t hat the health of the user ma

be en-

dan

ered.

ABM®

AOP®

ARCOFI®

ARCOFI®-BA

ARCOFI®-SP

iTape®

EPIC®-1

EPI C ®-S

ELIC®

FALC®54

FALC®56

FALC®-E1

FALC®-LH

IDE C®

IOM ®

IOM®-1

IOM ®-2

IPAT®-2

ISAC®-P

ISAC®-S

ISAC®-S TE

ISAC®-P TE

ITAC®

IWE®

MUSAC®-A

OC TA T ®-P

QUAT®-S

SICAT®

SICOFI®

SICOFI®-2

SICOFI®-4

SLICOFI® are re

istered t rademarks of Infineon Techno lo

ies AG.

ACE™

ASM™

ASP™

POTSWIRE™

QuadFALC™

SCOUT™ are tr ademarks of Infineon Technolo

ies AG.

PEB 20525

PEF 20525

Preliminary Data Sheet 3 09.99

Preface

The PASSAT is a Protocol Controller for a wide range of data communication and

telecommunication applications. This document provides complete reference

information on hardware and software related issues as well as on general operation.

Organization of this Docum ent

T his Prelimina ry Data Sheet is divided into 9 chapters . It is organized as follows:

• Chapter 1, Intr oduction

Gives a general description of the produ ct, lists t he key featu res, and pres ents som e

typical application s.

• Chapter 2, Pin Description

Lists pi n l ocat io ns wi th associated sig nals , cate gorizes signal s ac cording to fun ction,

and describes si gnal s.

• Chapters 3 Functional Description

These chapters pro vide detailed descriptions of all PASSAT internal function blocks.

• Chapter 4, Detailed Protocol Descriptions

Gives a detailed description of all protocols supported by the serial communication

controllers SCCs.

• Chapter 5, Detailed Register Description

Gives a detailed descrip tion of all PASSAT on chip registers.

• Chapter 6, Pr ogra mming

Provides programming help for PASSAT initialization procedure and operation.

• Chapter 7, Electrical Characteristics

Gives a detailed description of all electrical DC and AC characteristics and provides

timing diagrams and values for all interfaces.

• Chapter 8, Test Modes

Gives a detailed description of the JTAG boundary scan unit.

• Chapter 9, Package Outline

PEB 20525
PEF 20525
Table of Contents Page
Preliminary Data Sheet 4 09.99
Preface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Intr oduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
3 Typical Applica tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
3.1 Syste m In tegration  Example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
3.2 Serial Configuration Examples   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
4 Differences between PASSAT and the HSCX/ESCC Family  . . . . . . . . . 1-22
4.1 En hancements to the HSCX Serial Core . . . . . . . . . . . . . . . . . . . . . . . 1-22
4.2 Simplifications to the HSCX Serial Core  . . . . . . . . . . . . . . . . . . . . . . . 1-22
Pin Descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
1 Pin Diagram P-LFBGA-80-2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2 Pin Di agr am P-TQFP-100- 3   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
3 Pin Definitions and Functi ons  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 25
Functional Overview   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
1 Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
2 Serial Co mmunication Controller (SCC)  . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
2.1 Pr otocol  Modes  Overvi ew  . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 40
2.2 SCC FIFOs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
2.2.1 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
2.2.2 SCC Receive FIFO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
2.2.3 SCC FIFO Access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
2.3 Clocking System  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
2.3.1 Clock Mode 0 (0a/0b )   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
2.3.2 Clock Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
2.3.3 Clock Mode 2 (2a/2b )   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
2.3.4 Clock Mode 3 (3a/3b )   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
2.3.5 Clock Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
2.3.6 Clock Mode 5a (Time Slot Mode)  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
2.3.7 Clock Mode 5b (Octet Sync Mode)  . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
2.3.8 Clock Mode 6 (6a/6b )   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
2.3.9 Clock Mode 7 (7a/7b )   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
2.4 Ba ud Rate G enera tor (BRG)  .  . . . . . . .  . . . . . . .  . . . . . . . . . . . . . . . . . 3-65
2.5 Clock Recov ery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
2.6 SCC Timer Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
2.7 SCC Serial Bus Configuration Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
2.8 Serial Bus Access Procedure  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
2.9 Se rial Bus Col lisions and Recovery . . . . . . . . . . . . . . . . . . . . . . . .  . . . 3-69
2 .10 Serial Bus Access Priority Scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
2.11 Serial Bus Configu ration Timing  Modes    . . . . . . . . . . . . . . . . . . . .  . . . 3-71
2.12 Functions Of Signal RTS  i n HDLC Mod e . . . . . . . . . . . . . . . . . . . . . . . 3- 71

PEB 20525
PEF 20525
Table of Contents Page
Preliminary Data Sheet 5 09.99
2.13 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
2.13.1 NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
2.13.2 FM0 and FM1 Encoding   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72
2.13.3 Manchester Encoding  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
2.14 M odem Control Signals (RTS, CTS, CD )    . . . . . . . . . . . . . . . . . .  . . . . 3-74
2.14.1 RTS/CTS Handshak ing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 74
2.14.2 Carrier Detect (CD) Receiver Control  . . . . . . . . . . . . . . . . . . . . . . . 3-75
2.15 Local Loop T est Mode . . . . . . . .  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . 3-75
3 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
4 External DMA Controll er Support   . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 3- 77
5 Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
6 General Purpose Port Pins  . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . 3-79
6.1 GPP Funct ional  Description . . . . . . . . .  . .  . . . . . . . . . . . . . . . . . . . . . . 3-79
6.2 GPP Interrupt Indication   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79
Detailed Protocol Description   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
1 HDLC/SDLC Protocol Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
1.0.1 Automode   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
1.0.2 Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
1.0.3 Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
1.0.4 Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
1.1 HDLC Receive Data Processing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
1.2 Receive Address Handling   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
1.3 HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85
1.4 Shared Flags  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
1.5 One Bit In sertion  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
1.6 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
1.7 CRC Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
1.8 Receive Length Chec k Featu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
2 Point-to-Point Proto col (PPP) Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
2.1 Bit Synchronous PPP   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
2.2 Octet  Synchronous PPP  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
2.3 Data Transparency in  PPP Mod e  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89
3 Extended  Transparent  Mode  . . . .  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 4- 92
4 Procedural  Support (Layer-2  Functions)   .  . . . . . . . . . . . . . . . . . . . . . . . . 4- 92
4.1 Fu ll-Duplex  LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-93
4.2 Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-98
4.3 Signaling System #7 (SS7) Ope ration . . . . . . . . . . . . . . . . . . . . . . . . 4-100
Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
1 Register Overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
2 Detailed Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108
2.1 Gl obal Re gisters  . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-108

PEB 20525
PEF 20525
Table of Contents Page
Preliminary Data Sheet 6 09.99
2.2 Channel Specific SCC Registers .  . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-125
2.3 Channel Specific DMA Register s .  . . . . . . . . . . . .  . . . . . . . . . . . . . . . 5-201
2.4 Mi scel laneous Registers   . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .  . . 5-208
Programming  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-211
1 Initialization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-211
2 Interrupt Mode  . . . . . . . . . . . . . . . .  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 6- 211
2.1 Data Transmission (Interrupt Driven)  . . . . . . . . . . . . . . . . . . . . . . . . . 6-211
2.2 Data Reception (Interrupt Driven)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-213
3 External DMA Supported Mode  .  . . . . . . .  . . . . . . .  . . . . . . . . . . . . . . . . 6- 215
3.1 Dat a Tran smission (W i th Externa l DMA Support)  . . . . . . . . . . . . .  . . 6-215
3.2 Data Reception (With External DMA Support) . . . . . . . . . . . . . . . . . . 6-218
Electrical Characteristics (Preliminary) . . . . . . . . . . . . . . . . . . . . . . . 7-222
1 Abso lute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-222
2 Operating Range    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .  . . 7-222
3 Thermal Package Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-223
4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-224
5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-225
6 Capacitances  . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 7-225
7 Timing Dia grams  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-226
7.1 Micro proc essor Interface Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-226
7.1.1 Microprocessor Interface Clock Timing  . . . . . . . . . . . . . . . . . . . . . 7-226
7.1.2 Sie mens/Intel Bus Interface Timin g . . . . . . . . . . . . . . . . . . . . . . . . 7-227
7.1.3 Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229
7.2 PCM Serial Inte rface Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-231
7.2.1 Clock Input Timing . . . . . . .  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 7-231
7.2.2 Receive Cycle Timin g  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-232
7.2.3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234
7.2.4 C lock Mode  1 Strobe Timing  . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 7-236
7.2.5 Clock Mode  5 Frame Synchronisati on Timin g . . . . . . .  . . . . . . . . . 7-237
7.2.6 Clock Mode 4 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 7-238
7.2.7 Clock Mode 4 Transmit Cyc le Timing  . . . . . . . . . . . . . . . . . . . . . . 7-239
7.3 Reset Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240
7.4 JTAG-Boundary Scan Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-241
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-242
1 JTAG Boundary Scan Interfac e . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 8-242
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-247

PEB 20525
PEF 20525
List of Figures Page
Preliminary Data Sheet 7  09.99
Figure 1-1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Figure 1-2 Syste m In tegration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Figu re  1 - 3 Sys tem Integ ratio n W ith Exte rn a l DM A  Controller. . . . . . . . . . .  . . . . 1-19
Figure 1-4 Point-to-Point Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Figure 1-5 Point-to-Multipoint Bus Configuration  . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Figure 1-6 Multimaster Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Figure 2-1 Pin Configuration P-LFBGA-80-2 Package . . . . . . . . . . . . . . . . . . . . 2-23
Figure 2-2 Pin Configurat ion P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . 2-24
Figure 3-1 Block  Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Figure 3-2 SCC Transmit FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Figure 3-3 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
Figure 3-4 XFIFO/RFIFO Word Access (Intel Mode)  . . . . . . . . . . . . . . . . . . . . . 3-43
Figure 3-5 XFIFO/RFIFO Word Access (Motorola Mode). . . . . . . . . . . . . . . . . . 3-43
Figure 3-6 Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Figure 3-7 Clock Mode 0a/0b Configur ation . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3- 48
Figure 3-8 Clock Mode 1 Configuration.  . . . . . . . . . . . . . . .  . . . . . . .  . . . . . . . . . 3-49
Figure 3-9 Clock Mode 2a/2b Configur ation . . . . . . . . . . . .  . . . . . . . . . . . . . . . . 3- 50
Figure 3-10 Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
Figure 3-11 Clock Mode 4 Configuration.  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . 3- 52
Figure 3-12 Selec ting one time-slot  of programm able  delay and width  . . . . . . . . 3- 54
Figure 3-13 Selecting one or more time-slots of 8-bit widt h . . . . . . . . . . . . . . . . . 3-56
Figure 3-14 Clock Mode 5a Configuration.  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 3- 57
Figure 3-15 Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . .  . . . 3- 58
Figure 3-16 Clock Mode 5a "Non Continuous Mo de" . . . . . . . . . . . . . . . . . . . . . . 3-59
Figure 3-17 Selecting one or more octet wide time-slots  . . . . . . . . . . . . . . . . . . . 3-61
Figure 3-18 Clock Mode 5b Configuration.  . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . 3- 62
Figure 3-19 Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
Figure 3-20 Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
Figure 3-21 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shi ft Enabled) . . 3- 67
Figure 3-22 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shi ft Disabled) . . 3-67
Figure 3-23 DPLL Algorithm for FM0, FM1 and Manchester Encoding  . . . . . . . . 3-68
Figure 3-24 Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71
Figure 3-25 NRZ and N RZ I Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 3-72
Figure 3-26 FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 73
Figure 3-27 Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
Figure 3-28 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Figure 3-29 SCC Test Loop  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
Figure 3-30 Interrupt Status Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
Figure 4-1 HDLC Receive Data Processing in 16 bit Automode. . . . . . . . . . . . . 4-83
Fig ure 4-2 HDLC Receive Data Processing in 8 bit Automode. . . . . . . . . . . . . . 4-83
Figure 4-3 HDLC  R eceive D ata Processing i n Address  Mode 2 (16 bit). . . . . . . 4-83
Figure 4-4 HDLC  R eceive D ata Processing i n Address  Mode 2 (8 bit). . . . . . . . 4-84

PEB 20525
PEF 20525
List of Figures Page
Preliminary Data Sheet 8  09.99
Figure 4-5 HDLC  R eceive D ata Processing i n Address  Mode 1. . . . . . . . . . .  . . 4- 84
Figure 4-6 HDLC  R eceive D ata Processing i n Address  Mode 0. . . . . . . . . . .  . . 4- 84
Figure 4-7 SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . 4-86
Figure 4-8 PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . 4-91
Figure 4-9 Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 4-94
Figure 4-1 0 Tim er Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
Figure 4-11 Transm issi on/ R eceptio n of I-Frames and Flow  Control. . . . . . . . . . . 4- 97
Figure 4-12 Flow Control: Reception of S-Comm ands and Protocol Errors . . . . . 4- 97
Figure 4-13 No Dat a to Send: Data Reception /Transm is sion . . . . . . .  . . . . . . .  . 4-100
Figure 4-14 Data Tran smiss ion (wit hout error), Data Tran smiss ion (with erro r) . 4- 100
Figure 6-1 Interr upt Drive n Data Transmissi on (Flow  Diagram ) . . . . . . . . . . . . 6-212
Figure 6-2 Interrupt Driven Data Reception (Flo w Diagram). . . . . . . . . . . . . . . 6-214
Figure 6-3 DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . 6-216
Figure 6-4 Fragm ent ed D MA Transmiss ion (Mult iple Buffers per Packet) . . . . 6-217
Figure 6-5 DMA Re ceive (Single Buffer per Packet). . . . . . . . . . . . . . . . . . . . . 6-219
Figure 6-6 Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . 6-220
Figure 6-7 Fragm ent ed R eceptio n Sequence (Ex ample) . . . . . . . . . . . . . . . . . 6- 221
Figure 7-1 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . 7-225
Figure 7-2 Micro proc essor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . 7-226
Figure 7-3 Siem ens/ I ntel Read Cycle  Timing . . . . . . . . . . . . . . . . . . . . . . .  . . . 7-227
Figure 7-4 Siemens/Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7-227
Figure 7-5 Mot oro la Read Cycl e Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229
Figure 7-6 Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-229
Figure 7-7 Clock Input Timing      .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 231
Figure 7-8 Receive Cyc le  Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-232
Figure 7-9 Transmit Cycle  Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-234
Figure 7-10 Clock Mode 1 Strobe Timing . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . 7- 236
Figure 7-11 Clock Mode 5 Frame Synchr oni sat ion Timin g . . . . . . . . . . . . . . . . . 7-237
Figure 7-12 Clock Mode 4 Receive Timing  . . . . . . . . . . . . . .  . . . . . . . . . . . . . . 7-238
Figure 7-13 Clock Mode 4 Trans mit Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-239
Figure 7-14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-240
Figure 7-15 JTAG-Bound ary Scan Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7- 241
Figure 8-1 Block  Diagra m of Test Access Port and Boundary Scan  Unit . . . . . 8- 242

PEB 20525
PEF 20525
List of Table s Page
Preliminary Data Sheet 9  09.99
Table 2-1 Micro proc essor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-25
Table 2-2 External DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-30
Table 2-3 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-32
Table 2-4 General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-36
Table 2-5 Test Interface Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-37
Table 2-6 Power Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   2-38
Table 3-1 Overview of Cloc k Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   3-44
Table 3-2 Clock  Modes of the SCCs . . . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . . . .   3-45
Table 3-3 BRRL/ BR RH Regi ster and Bit-Fields. . . . . . . .  . . . . . . .  . . . . . . .  . .   3-65
Table 3-4 Data Bus Access 16 -bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . .   3-77
Table 3-5 Data Bus Access 16 -bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . .   3-77
Table 4-1 Protocol  Mode Over vi ew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   4-80
Table 4-2 Address Comparison Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .   4-81
Table 4-3 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   4-98
Table 5-1 Register Overview   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-103
Table 6-1 Status Information after RME interupt . . . . . . . . . . . . . . . . . . . . . .   6-213
Table 6-2 DMA Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   6-215
Table 7-1 Thermal Package Chara cteristics  P-TQFP-100-3 . . . . . . . . . . . . .   7-223
Table 7-2 Thermal Package Characteristics P-LFBGA-80-2. . . . . . . . . . . . .   7-223
Table 7-3 Capacitances
TA = 25 ×C; VDD3 = 3.3 V ± 0.3 V, VSS = 0 V . . . . . . . . . . . . . . .   7-225
Table 7-4 Micro proc essor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . .   7-226
Table 7-5 Siemens/Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . .   7-228
Table 7-6 Motorola Bus Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .   7-230
Table 7-7 Clock  Input Timing . . . . . . . . . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . . .   7- 231
Table 7-8 Receive Cyc le Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   7-233
Table 7-9 Transmit Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   7-235
Table 7-10 Clock Mode 1 Strobe Timing . . . . . . . . .  . . . . . . . . . . . . . . . . . . . .   7-236
Table 7-11 Clock Mode 5 Frame Synchr oni sat ion Timing . . . . . . . . . . . . . . .  .   7-237
Table 7-12 Clock Mode 4 Receive Timing . . . . . . .  . . . . . . .  . . . . . . . . . . . . . .   7-238
Table 7-13 Clock Mode 4 Trans mit Timing  . . . . . . . . . . . . . .  . . . . . . . . . . . . .   7-239
Table 7-14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   7-240
Table 7-15 JTAG-B oundary Scan Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . .   7-241
Table 8-1 Boundary Scan Sequence of PASSAT . . . . . . . . . . . . . . . . . . . . .   8-243
Table 8-2 Boundar y Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   8-246

PEB 20525
PEF 20525
List of Re gisters Page
Prelimi nary Dat a Sheet 10  09.99
Register 5-1 GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-108
Register 5-2 GMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-109
Register 5-3 GSTAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-112
Register 5-4 GPDIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-114
Register 5-5 GPDIRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-114
Register 5-6 GPDATL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-116
Register 5-7 GPDATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-116
Register 5-8 GPIML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-118
Register 5-9 GPIMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-118
Register 5-10 GPISL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-120
Register 5-11 GPISH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-120
Register 5-12 DCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-122
Register 5-13 DISR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-123
Register 5-14 DIMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-124
Register 5-15 FIFOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-125
Register 5-16 FIFOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-125
Register 5-17 STARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-128
Register 5-18 STARH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-128
Register 5-19 CMDRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-132
Register 5-20 CMDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-132
Register 5-21 CCR0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-136
Register 5-22 CCR0H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-136
Register 5-23 CCR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-139
Register 5-24 CCR1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-139
Register 5-25 CCR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-144
Register 5-26 CCR2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-144
Register 5-27 CCR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-149
Register 5-28 CCR3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-149
Register 5-29 PREAMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-153
Register 5-30 ACCM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-154
Register 5-31 ACCM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-154
Register 5-32 ACCM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-155
Register 5-33 ACCM3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-155
Register 5-34 UDAC0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-157
Register 5-35 UDAC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-157
Register 5-36 UDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-158
Register 5-37 UDAC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-158
Register 5-38 TTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-160
Register 5-39 TTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-160
Register 5-40 TTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-161
Register 5-41 TTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-161
Register 5-42 RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-163

PEB 20525
PEF 20525
List of Re gisters Page
Prelimi nary Dat a Sheet 11  09.99
Register 5-43 RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-163
Register 5-44 RTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-164
Register 5-45 RTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-164
Register 5-46 PCMTX0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-166
Register 5-47 PCMTX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-166
Register 5-48 PCMTX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-167
Register 5-49 PCMTX3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-167
Register 5-50 PCMRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-169
Register 5-51 PCMRX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-169
Register 5-52 PCMRX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-170
Register 5-53 PCMRX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-170
Register 5-54 BRRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-172
Register 5-55 BRRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-172
Register 5-56 TIMR0  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-174
Register 5-57 TIMR1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-174
Register 5-58 TIMR2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-175
Register 5-59 TIMR3  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-175
Register 5-60 XAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-178
Register 5-61 XAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-178
Register 5-62 RAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-180
Register 5-63 RAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-180
Register 5-64 RAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-181
Register 5-65 RAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-181
Register 5-66 AMRAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-183
Register 5-67 AMRAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-183
Register 5-68 AMRAL2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-184
Register 5-69 AMRAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-184
Register 5-70 RLCRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-186
Register 5-71 RLCRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-186
Register 5-72 ISR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-188
Register 5-73 ISR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-188
Register 5-74 ISR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-189
Register 5-75 IMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-194
Register 5-76 IMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-194
Register 5-77 IMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-195
Register 5-78 RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-197
Register 5-79 XBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-202
Register 5-80 XBCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-202
Register 5-81 RMBSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-204
Register 5-82 RMBSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-204
Register 5-83 RBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-206
Register 5-84 RBCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   5-206

PEB 20525

PEF 20525

List of Re gisters Page

Prelimi nary Dat a Sheet 12 09.99

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-13 09.99

1 Introduction

The PASSAT is a Serial Communication Controller with two independent serial

channels1). The serial channels are derived from updated protocol logic of the ESCC and

DSCC4 device family providing a large set of protocol support and variety in serial

interface configuration. This allows easy integration to different environments and

applications.

A generic 8- or 16-bit multiplexed/demultiplexed slave interface provides fast device

access with low bus utilization and easy software handshaking (in the P-LFBGA-80-2

package only an 8-bit data bus is provided). DMA handshake control signals allow

connection to an external DMA controller .

Large on-chip FIFOs of 64 byte capacity per port and direction in combination with

enhanced threshold control mechanisms allow decoupling of traffic requirements on host

bus and serial interfaces with little exception probabilities such as data underuns or

overflows.

Each of the two Serial Communication Controllers (SCC) contains an independent Baud

Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC

and BISYNC). Data rates of up to 2 Mbit/s (DPLL assisted modes) and 12.5 Mbit/s

(HDLC, PPP, bit transpare nt) are supported. The channels c an also hand le a large set

of layer-2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel

specific timers are provided to support protocol functions.

1) The serial channels are also called ’ports’ or ’cores’ depending on the context.

PPP and HDLC Synchronous Serial Contro ller with 2

Channels

PASSAT

PEB 20525

PEF 20525

Preliminar

Data Sheet 1-14 09.99

Version 1.1 CMOS

Type Package

PEB 20525, PEF 20525 P-TQFP-100-3

P-LFBGA-80-2

1.1 Features

Serial communication controllers (SCCs)

• Two independe nt channels

• Full duplex data rates on each channel of up to

12.5 Mbit /s sy nc - 2 M bi t/s wit h DPLL

• 64 Bytes deep receive FIFO p er SCC

• 64 Bytes deep tr ansm it FIFO per SCC

Serial Interface

• On-chip clock generati on or external clock sources

• On-chip DPLLs for clock recovery

• Baud rate generator

• Clock gating signals

• Clock gapping capa bility

• Programmabl e t ime- slot capability for connecti on t o

TDM interfaces (e.g. T1, E1)

• NRZ, NRZI, FM and Manchester data encod ing

• Optional data flow control using modem control lines (RTS, CTS, CD)

• Support of bus configuration by collision detection and resolution

Bit Processor Functions

•HDLC/SDLC Protocol Modes

– Automatic flag detection and transmission

– Shared opening and closing flag

– Generation of interframe-time fill ’1’s or flags

– Detect ion of receiv e line status

– Zero bit insertion and deletion

•

P-TQFP-100-3

P-LFBGA-80-2

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-15 09.99

– CRC g enera tion and checking (CRC-CCITT or CRC-32)

– Transpa rent CRC option per channel and/or per frame

– Progra mmabl e Preambl e (8 bit) with selectabl e repetition rate

– Error detection (abort, long frame, CRC error, short frames)

•Bit Synchronous PPP Mode

– Bit orien ted transmission of HDLC frame (flag, data, CRC, flag )

– Zero bit insertio n/deleti on

– 15 consecut i ve ’1’ bits abort sequence

•Octet Synchronous PPP Mo d e

– Octe t o riente d tra n sm is s io n of HDLC frame (flag , d at a , CRC, flag)

– Progra mmabl e char act er map of 32 hard-wired char act ers (00H-1FH)

– Four programmable characters for additional mapping

– Insertion/deletion of control-es cape char act er (7DH) for mapped char acters

•Extended Transpar ent Mode

– Fully bit transparent (no framing, no bit manipulation)

– Octet-aligned transmission and reception

• Protocol and Mode Independent

– Data bit inversion

– Data overflow and underrun detection

–Timer

Protocol Support

• Address Recognit ion Modes

– No address rec ogni tion (Address Mode 0)

– 8-bit (high byte) address recognition (Addr ess Mode 1)

– 8-bit (low byte) or 16-bit (high and low byte) address recognition ( Address Mode 2)

• HDLC Automode

– 8-bit or 16-bit address gener at ion/r ecognit ion

– Support of LAPB/LAPD

– Autom atic hand ling of S- and I-frames

– Automatic processing of control byte(s)

– Modulo- 8 or modu lo-128 oper ation

– Progra mmabl e time -out and retry con ditions

– SDLC Normal Response Mode (NRM) operation for slave

• Signaling System #7 (SS7) support

– Detectio n of FISUs, MSUs and LSSUs

– Unch anged Fi ll-In Signaling Uni ts (FISUs) opti onally not forwarded

– Autom atic gene ration of FISUs in transmit direction (incl. sequence num ber)

– Counting of errored signaling units

• Optional DTACK/READY controlled cycles

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-16 09.99

Micr oprocess or Interface

• 8-bit bus inter face (P-LFBGA- 80-2 package)

• 8/16-bit bus interface (P-TQFP-100-3 package)

• Multiplexed and De-mul tiplexed addr ess/ dat a bus

• Intel/Motorola style

• Asynchronous in ter fa ce

• Maskable inte rrupts for each channel

General Purpose Port (GPP) Pins (up to 3 in P-LFBGA-80-2, up to 7 in P-TQFP-100-

3 package)

General

• 3.3V pow er supply with 5V tolera nt inputs

• Low pow er consum ption

• Power safe features

• P-TQFP-100-3 Package (Thermal Resistance: RJA = 42 K/W)

• Small P-LFBGA-80-2 Pack age (Therm al Resist ance: RJA = 51 K/W )

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-17 09.99

1.2 Logic Symbol

•

Figure 1-1 Logic Symbol

VSS

VDD3

TEST

TCK

TMS

TDI

TDO

TRST

JTAG Test

Interface

TxD

RxD

RTS

/TxCLKO

/OSR

CTS

/CxD

/TCG

/FSC

/RCG

/OST

TxCLK

RxCLK

Serial

Channel A

PASSAT

PEB 20525

PEF 20525

XTAL1

XTAL2

TxD

RxD

RTS

/TxCLKO

/OSR

CTS

/CxD

/TCG

/FSC

/RCG

/OST

TxCLK

RxCLK

Serial

Channel B

DRT

DRR

DACK

DRT

DRR

DACK

External DMA

Interface

Intel b u s m o de

Motorola bus mode

A(7:0)

Microprocessor

Interface

D(15:8)

ALE

LDS

UDS

2) 3)

INT/INT

CLK

RESET

DTACK

BHE

1) 3)

R/W

D(7:0)

16-bit mode (TQ FP-100 package only)

General

Purpose Port

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-18 09.99

1.3 Typical Applications

PASSAT devices can be used in LAN-WAN inter-networking applications such as

Routers, Switches and Trunk cards and support the common V. 35, ISDN BRI (S/T) and

RFC1662 standards. Its new features provide powerful hardware and software

interfaces to develop high performa n ce systems.

1.3.1 System Integration Example

Figure 1-2 System Integration

. . .

Transceiver,

Framer

System Bus

CPU

RAM

Bank

PASSAT

PEB 20525

PEF 20525

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-19 09.99

F igure 1-3 System Integration With External DMA Controller

. . .

Transceiver,

Framer

System Bus

CPU

RAM

Bank DMA

Controller

PASSAT

PEB 20525

PEF 20525

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-20 09.99

1.3.2 Serial Conf iguration Examples

PASSAT supports a variety of serial configurations at Layer-1 and Layer-2 level. The

outstanding variety of clock modes supporting a large number of combinations of

external and internal clock sourc es allows easy inte gratio n in application envir onm ents .

Figure 1-4 Point-to-Point Configuration

. . .

TxDRxD RxD TxD

serial transmission

optional modem cont rol signals

Layer-2 LAPD/B or SS7

Protocol Support

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-21 09.99

Figure 1-5 Point-to-Multipoint Bus Conf iguration

F igure 1-6 Multimaster Bus Configuration

. . .

TxDRxD RxD TxD

. . .

RxD TxD

...

. . .

TxD

CxDCxDCxD

RxD

Master

Slave nSlave 2Slave 1

Layer-1 collision detection

Layer-2 SD LC-NRM operation

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

. . .

TxDRxD RxD TxD

. . .

RxD TxD

...

CxDCxDCxD

Master nMaster 2Master 1

Layer-1 collision det ecti on

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

PASSAT

PEB 20525

PEF 20525

PEB 20525

PEF 20525

Introduction

Preliminary Data Sheet 1-22 09.99

1.4 Differences between PASSAT and the HSCX/ESCC Family

This chapter is useful for all being familiar with the HSCX/ESCC family.

1.4.1 Enhancements to the HSCX Serial Core

The PASSAT SCC cores contain the core logic of the HSCX as th e heart of the device.

Some enhancem ents are incor pora ted in the SCCs. These are:

• Octet-and Bit Synchr onous PPP protoco l suppo rt as in RFC-1662

• Signal in g System #7 (SS7) support

• 4-kByte packet length byte counter

• Enhan ced addr ess fil tering (16- bit maskable)

• Enhan ced tim e slot assigner

• Suppo rt of high data rates (12.5 Mbit/s)

1.4.2 Simplifications to the HSCX Serial Core

The following features of the HSCX core have been removed:

• Extended transpare nt mode 0

(this mode provided octet buffered data reception without usage of FIFOs; PASSAT

supports octet buffered reception via appropriate threshold configurations for the SCC

receive FIFOs)

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-23 09.99

2 Pin Descriptions

2.1 Pi n Diagram P-LFBGA-80-2

(top view)

•

Figure 2-1 Pin Configuration P-LFBGA-80-2 Package

DRTA

VSS

TEST2

VSS

VDD

READY#

DTACK#

RD#

DRRA

VDD

VSS

WR#

TMS

VSS

VDD

DACKA#

DRRB/

GP1

TEST1

VDD

CLK

CS#

R/W#

RTSB#

VSS

DACKB#

GP2

VSS

DS#/

BHE#/

LDS#

VDD

BM/

ALE

VSS

RxDB

VDD

DRTB/

GP0

VSS

A0/

BLE#/

UDS#

TxCLKB

RxCLKB

VDD

TxDB

XTAL2

TxDA

VDD

VSS

CDB/

FSCB/

RCGB#/

OSTB

VSS

XTAL1

CDA/

FSCA/

RCGA#/

OSTA

TxCLKA

VSS

TDI

TRST#

TCK

VSSA

CTSA#/

CxDA/

TCGA#/

OSRA

RxCLKA

VSS

RESET#

TDO

VDD

CTSB#/

CxDB/

TCGB#/

OSRB

VDDA

RxDA

VDD

RTSA#

INT/

INT#

VDD

123456789

P-LFBGA-80-2

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-24 09.99

2.2 Pin Diagram P-TQFP-100-3

(top view)

•

Figure 2-2 Pin Configuration P-TQFP-100-3 Package

TDO

TCK

VDD

VSS

CTSB#/CxDB/TCGB#/OSRB

VSSA

XTAL2

XTAL1

VDDA

CTSA#/CxDA/TCGA#/OSRA

CDA/FSCA/RCGA#/OSTA

RxDA

RxCLKA

TxDA

VDD

VSS

TxCLKA

RTSA#

RESET#

INT/INT#

VDD

VSS

GP10

GP9

GP8

VSS

VDD

VSS

VDD

TMS

R/W#

DS#/BHE#/LDS#

CS#

BM/ALE

VSS

VDD

A0/BLE#/UDS#

VDD

VSS

WIDTH

VSS

VDD

GP6

D11

D10

VSS

VDD

TEST2

TEST1

VSS

VDD

VSS

VDD

CLK

READY#/DTACK#

WR#

RD#

VSS

VDD

VSS

D12

D13

D14

D15

VDD

VSS

DRTA

DACKA#

DRRA

DRRB/GP1

DRTB/GP0

DACKB#/GP2

RTSB#

RxDB

VDD

VSS

RxCLKB

TxDB

TxCLKB

CDB/FSCB/RCGB#/OSTB

VDD

TRST#

TDI

100

P-TQFP-100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-25 09.99

2.3 Pi n Definitions and Functions

T able 2-1 Micropro cessor Bus Interface

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

D15

D14

D13

D12

D11

D10

I/O Da ta Bus

The data bus lines are bi-directional tri-state lines

which interfac e with the system ’s data bus.

The PASSAT in the P-LFBGA-80-2 package does

not support 16-bit bus mo des.

Address Bus

These pins con nect to the system’ s addre ss bus

to select one of the internal registers for read or

write.

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-26 09.99

J5 39 A0

BLE

UDS

Address Line A0 (8-bit modes)

In Motorola and in Intel 8-bit mode this signal

repr esents the least significant address l ine .

Byte Low Enable (16-bit Intel bus mode)

This signal indicat es a data transfer on the low er

byte of the data bus (D7..D0). Toget her with

signal BHE the typ e of bus acces s is determined

(byt e or word acce ss at even or odd addres s).

Upper Data Strobe (16-bit Motorola bus mode)

This active low strobe signal serve s to control

read/write operations. Together with signal LDS

the type of bus acce ss is determi ned.

J6 42 BM

ALE

Bus Mode

– BM = static ’1’ for operation in Motorola bus

mode (de-multiplexed).

– BM = static ’0’ for operation in Intel bus mode

with de-multiplexed addr ess and dat a buses.

– Pin BM/ALE has the function of an Address

Latch Enable (ALE) for operation in Intel bus

mode with a multiplexed address/data bus. A

falling edge on this pin selects Intel multiplexed

bus mode.

Address Latch Enable (mux’e d Intel bus)

The address is latched by the PASSAT with the

falling edge of ALE.

The address input pins A(7:0) must be externally

connect ed to the data bus pins D(7:0).

For operation of the 8-bit PASSAT ( P-LFBGA-80-

2 package) in a 16-bit environment, A(7:0) should

be connected to address/data lines AD(8:1) of the

external bus. D(7:0) interface to AD(7:0) of the

external bus.

Table 2-1 Microprocessor Bus Interface

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-27 09.99

G6 44 DS

BHE

LDS

Data Strobe (8-bi t Motorola bus mode only)

This active low strobe signal serves to control

read/write oper ations .

Bus High Enable (16-bit Intel bu s mode only)

This signal indicates a data transfer on the upper

byte of the data bus (D15..D8). In 8-bit Intel bus

mode this signal has no functi on.

Lower Data Strobe (16-bit Motorola bus mode)

This active low strobe signal serves to control

read/write oper ations . Together with signal UDS

the type of bus access is determined (byte or word

access at even or odd addre ss).

In 8-bit Intel bus mode, a pull-up resistor to V

DD3

is recommended on this pin.

J9 52 RD IRead Strobe (Intel bus mode only)

This signal indicates a read operation. The bus is

able to accept data on lines D(7:0) / D(15:0)

during an active RD signal .

In Motorola bus mode, a pull-up resistor to V

DD3

recom me nded on this pin.

J7 45 R/W IRead/Wri te Enable (Motorola bus mode)

This signal distinguishes between read and write

operation. As an input it must be valid during data

strobe (DS).

In Intel bus mode, a pull-up resistor to V

DD3

recom me nded on this pin.

H7 43 CS IChip Sele c t

A low signal selects PASSAT for read/write

operations.

T able 2-1 Micropro cessor Bus Interface

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-28 09.99

G8 53 WR IWrite Strobe (Intel bus mode only)

This signal indicates a write operation. Valid data

is present data on lines D(7:0) / D(15:0) during an

active WR si gnal .

In Motorola bus mode, a pull-up resistor to V

DD3

recom m ended on th is pin.

-33WIDTHIWidth Of Bus Interface

A low signal on this input selects the 8-bit bus

interface m ode.

A high signal on this input selects the 16-bit bus

interface mode. In this case word transfer to/from

the internal registers is enabled . Byte transfers

are implemented by using BLE and BHE (Intel bus

mode) or LDS and UDS (Motorola bus mo de)

In P-LFBGA-80-2 package this signal is not

available, since only 8 bit bus width is supported.

G7 55 CLK I Clock

The system clock for PASSAT is provided through

this pi n .

H1 20 INT/INT O

o/d Interrupt Request

The INT/INT goes active when one or more of the

bits in register s ISR0..ISR2 are set to ’1’. A read

to these registers clears the interrupt. The INT/

INT line is inactive when all interrupt status bits

are rese t.

Interrupt sources can be unmas ked in registers

IMR0..IMR2 by setting the corres ponding bi ts to

’0’.

Table 2-1 Microprocessor Bus Interface

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-29 09.99

H9 54 READY

DTACK O

OReady (Intel bus mode)

Data Transfer Acknowledge (Motorola mode)

During a slave access (register r ead/ w rite) this

signal (output) indicates , that the PASSAT is

ready for data transfer. The signal remains active

until the data strobe (D S in Mot orola bus m ode,

RD/WR in Intel bus mode) and/or the chip select

(CS) go inactive.

This line is tri-state when unused.

A pull-up resistor to V

DD3

is recommended if this

function is not used.

H2 19 RESET IReset

With this act ive low signal the on-chip reg ister s

and state machines are forced to reset state.

During Reset all pins are in a high impedanc e

state.

T able 2-1 Micropro cessor Bus Interface

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-30 09.99

Table 2-2 External DMA Interface

Pin No. Sym bol In (I)

O ut (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

A9 84 DRTA O DMA Request Trans mitter Channel A

The transmitter on a this channel requests a DMA

transfer by activating the DRTA line. The request

rem ains active as long as the Transmit FIFO

requires data transfers. The amount of data bytes

to be transferred from the syst em mem ory to the

serial channel (= Byte Count) must be written first

to the XBCL, XBCH registers. Always blocks of

da ta (n x 32 bytes + rest ; n=0,1,…) are

transferred till the Byte Count is reached. DRTA is

deactivated with the beginning of the last write

cycle.

A8 86 DRRA O DMA Request Recei ver Channel A

The receiver on this serial channel requests a

DMA transfer by activating the DRRA line. The

reques t remains act ive as long as the Receiv e

FIFO require s data transfer s, thus alwa ys blocks

of data are transferred. DRRA is deactivated

immediately following the falling edge of the last

read cyc le.

B7 85 DACKA IDMA Acknowledge Channel A

A low signal on this pin informs the PASSAT that

the requested DMA cycle controlled via DRTA or

DRRA of thi s channel is in pr ogress, i. e. th e DMA

control le r has achieved bus masters hip from the

CPU and will start data transfer cycles (eit her

write or read). In conjunct ion with a read or write

operati on this input serves as Access Enable

(similar to CS) to the respective FIFOs. If DACKA

is active, the input to pins A(7:0) and CS is ignored

and the FIFOs are implicitly selected.

If not used, a pull-up resistor to V

is required for

this pin.

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-31 09.99

D5 88 DRTB

GP0

I/O

DMA Request Transmi tter Channel B

(corresponding to channel A)

General Purpose Pin #0

If DMA support is not enabled, this pin serves as

a general pupose in put /output pin.

After reset this pin serves as a general purpose

input. A pull-up resistor to V

DD3

is recommended.

C7 87 DRRB

GP1

I/O

DMA Request Receiv er Channel B

(corresponding to channel A)

General Purpose Pin #1

If DMA support is not enabled, this pin serves as

a general pupose in put /output pin.

After reset this pin serves as a general purpose

input. A pull-up resistor to V

DD3

is recommended.

C6 89 DACKB

GP2

I/O

DMA Acknowledge Channel B

(corresponding to channel A)

General Purpose Pin #2

If DMA support is not enabled, this pin serves as

a general pupose in put /output pin.

A pull-up resistor to V

DD3

is recommended if this

pin is not used.

T able 2-2 Externa l DMA Interface

Pin No. Symbol In (I)

Out (O ) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-32 09.99

Table 2-3 Serial Port Pins

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

F3 17 TxCLK

AI/O Transmit Clock Channel A

The functi on of this pin depends on the selected

cloc k mode and the value of bit ’TOE’ (CCR0L

registe r, refer to Table 3-2 "Clock Modes of the

SCCs" on page 3-45).

If programmed as Input ( CCR0L.TOE=’0’),

either

– the transmit clock for the channel (clock

mode 0a, 2a, 4, 5b, 6a), or

– a transmit strobe signal for the channel (clock

mode 1)

can be provided to this pin.

If programmed as Output (CCR0L.TOE=’1’),

this pin supplies ei ther

– the transmit clock from the baud rate generator

(clock mode 0b, 2b, 3b, 6b, 7b) , or

– the transmit clock from the DPLL c ircuit (clock

m ode 3a, 7a ), or

– an active-low control signal marking the

programmed transmit time-slot in clock mode

5a.

F2 13 RxCLK

AIReceive Clock Channel A

The functi on of this pin depends on the sele cted

clock mode (refer to Table 3-2 "Clock Modes of

the SCCs" on page 3-4 5) .

A signal provided on pin RxCLKA m ay suppl y

– the receive clock (clock mode 0, 4, 5b) , or

– the receive and transmit clock (clock mode 1,

5a), or

– the clock input for the baud rate generator

(clock mode 2, 3).

PEB 20525

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Pin Descriptions

Preliminary Data Sheet 2-33 09.99

E3 11 CDA

FSCA

RCGA

OSTA

Carrier Detect Channel A

The function of this pin depends on the selected

clock mode.

It can supply

– either a modem control or a general purpose

inpu t (clo ck m odes 0, 2, 3, 6, 7). If aut o-s tart is

programmed, it functions as a receiver enable

signal.

– o r a receive strobe signal (clock mode 1).

Polarity o f CDA can be set to ’a ctive low’ with bit

ICD in register CCR1H.

Additiona lly, an interrupt may be issued if a stat e

transition occurs at the CDA pin (programmable

feature).

Frame Sync Clock Channel A (cm 5a)

When the SCC is in the time-slot oriented clock

mode 5a, this pin functions as the Frame

Synchron iza tion Clock input.

Receive Clock Gating Channel A (cm 4)

In clock mode 4 this pin is used as Receive Clock

Gating signal.

If no clock gating functio n is required, a pull-up

resi stor to V

DD3

is recommended.

Octet Sync Transmit Channel A (cm 5b)

When the SCC is in the time-slot oriented clock

mode with octe t-alignment (clock m ode 5b), a

synchro niz ation pulse on this input pin aligns

transmit octets.

Table 2-3 Serial Port Pins ( cont’ d)

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-34 09.99

G1 18 RTSA OReque st to Send Channel A

The function of this pin depends on the settings of

bits RTS, FRTS in register CCR1H .

In bus configuration, RTS can be programmed to:

– go low during the actual transmission of a

frame shifted by one clock period, excluding

collision bits.

– go low during reception of a data frame.

– stay always high (RTS disabled).

E2 10 CTSA

CxDA

TCGA

OSRA

Clear to Send Channel A

A low on the CTSA input enab les the transmitter.

Additionally, an interrupt may be issued if a state

transition occurs at the CTSA pin (programmable

feature).

If no ’Clear To Send’ function is required, a pull-

down resistor to V

is recommended.

Collision Data Channel A

In a bus configuration, the external serial bus

must be connected to the corresponding CxDA

pin for collision dete ction.

A collision is detected whenever a logical ’1’ is

driven on the open drain TxDA output but a

logical ’0’ is detected via CxDA input.

Transmit Clock Gating Channel A (cm 4)

In clock mode 4 these pins are used as Transmit

Clock G ating si gnal s.

If no clock gating functi on is required, a pull-up

resi st or to V

DD3

is recommended.

Octet Sync Receive Cha nnel A (cm 5b)

(clock mode 5b)

When th e SCC is in the time-slot oriented clock

mode with oct et-align men t (clock mode 5b) ,

received octets are aligned to this synchronization

pulse input.

Table 2-3 Serial Port Pins (cont’d)

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

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Pin Descriptions

Preliminary Data Sheet 2-35 09.99

F4 14 TxDA O

o/d Transmit Data Channel A

Transm it data is shifted out via this pin. It can be

configured as push/pull or open drain output

characteristic via bit ’ODS’ in register CCR1L.

E1 12 RxDA I Receive D ata Channel A

Serial data is received on this pin.

A4 96 TxCLK

BI/O Tra nsmit Clock Channel B

(corresponding to channel A)

B4 94 RxCLK

BIReceive C lock Channel B

(corresponding to channel A)

B3 97 CDB

FSCB

RCGB

OSTB

Carrier Detect Channel B

Frame Sync Clock Channel B (cm 5a)

Receive Clock Gating Channel B (cm 4)

Octet Sync Transmit Channel B (cm 5b)

(corresponding to channel A)

A6 90 RTSB ORequest to Send Channel B

(corresponding to channel A)

C1 5 CTSB

CxDB

TCGB

OSRB

Clear to Send Channel B

Collision Data Channel B

Transmit Clock Gating Channel B (cm 4)

Octet Sync Receive Channe l B (cm 5b)

(correspon din g to channe l A)

D4 95 TxDB O

o/d Transmit Data Channel B

(corresponding to channel A)

Table 2-3 Serial Port Pins ( cont’ d)

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

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Pin Descriptions

Preliminary Data Sheet 2-36 09.99

B5 91 RxDB I Receive Dat a Channel B

(corresponding to channel A)

E4 8

7XTAL1

XTAL2 I

OCrystal Connection

If the intern al oscilla tor is used for clock

generati on (clock m odes 0b, 6, 7) the external

crystal has to be connected to these pins. The

internal oscillator should be powered up

(GMODE:OSCPD = ’0’) and the signal shaper

may be act ivated (GMODE:DSHP = ’0’).

Moreover, XTAL1 may be used as input for a

common clock source to both SCCs, provided by

an external clock generator (oscillator). In this

case the oscillator unit may be powered down and

it is recommended to bypass the shaper of the

internal oscillator unit by setting bit ’DSHP’ to ’1’.

A pull-down res istor to V

is recommended for

pin XTAL1 if not used.

Table 2-4 General Purpose Pins

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

-23

GP10

GP9

GP8

GP6

I/O General Purpose Pins

These pins serve as general purpose input/output

pins.

Table 2-3 Serial Port Pins (cont’d)

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

PEB 20525

PEF 20525

Pin Descriptions

Preliminary Data Sheet 2-37 09.99

T able 2-5 Test Interface Pins

Pin No. Symbol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

B2 99 TRST IJTAG Reset Pin (internal pull-up)

For proper device operation, a reset for the

boundary scan controller must be supplied to this

active low pin.

If the boundary scan of the PASSAT is not used,

this pin can be connected to V

to keep it in reset

state.

C2 2 TCK I JTAG Test Clock ( internal pull-up)

If the boundary scan of the PASSAT is not used,

this pin may remain unconnected.

A2 100 TDI I JTAG Test Data Input (internal pull-up)

If the boundary scan of the PASSAT is not used,

this pin may remain unconnected.

A1 1 TDO O JTAG Test Data Output

H8 46 TMS I JTAG Test Mode Select (i nternal pull-up)

If the boundary scan of the PASSAT is not used,

this pin may remain unconnected.

D7 68 TEST1 I Test Input 1

When connected to VDD3 the PASSAT works in a

vendor specific test mode.

This pin must be connected to V

C9 69 TEST2 I Test Input 2

When connected to VDD3 the PASSAT works in a

vendor specific test mode.

This pin must be connected to V

PEB 20525

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Pin Descriptions

Preliminary Data Sheet 2-38 09.99

Table 2-6 Power Pins

Pin No. Sym bol In (I)

Out (O) Function

P-

LFBGA-

80-2

P-TQFP-

100-3

A7, B1,

B8, C4,

C5, E7,

F1, G4,

G9, H6,

3, 15,

21, 27,

35, 40,

47, 49,

56, 62,

70, 76,

82, 92,

VDD3 -Digi tal Supply Voltage 3.3 V ±0.3 V

All pins must be conn ected to the same volt age

potential.

A3, A5,

B6, B9,

C3, E9,

F5, F6,

F8, G2,

H3, J8

4, 16,

22, 28,

34, 41,

48, 50,

51, 57,

63, 71,

77, 83,

VSS -Digital Ground (0 V)

All pins must be conn ected to the same volt age

potential.

D1 9 VDDA -Analog Supply Voltage 3.3 V ±0.3 V

This pin supplie s the on-chi p oscillator of the

PASSAT. It can be directly connected to VDD3.

D2 6 VSSA -Analog Ground (0 V)

This pin supplie s the ground level to the on-chip

oscillator of the PASSAT. It can be direct ly

connect ed to VSS.

---N.C.-Not Connected

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-39 09.99

3 Functional Overview

The functional blocks of PASSAT can be divided into two major domains:

– the microprocessor interface of PASSAT provides access to internal on-chip and to

the system portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally

these FIFOs can be acce ssed by an ext erna l 4-channel DMA controll er.

– the Serial Communication Controller (SCC) is capable of processing bit-synchronous

(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully

transparent dat a traffic.

Data exchange between the serial communication controller and the microprocessor

interface is performed using FIFOs, decou pling these two cl ocking dom ai ns.

3.1 Block Diagram

F igure 3-1 Block Diagram

Microprocessor

Interface

JTAG Test

Interface

External DMA

Interface

Serial Channel A

Decoder/

Collision

Detection

Clock

Control

DPLL

T ransm it FIFO

(3 2 B yte )

Receive FIF O

(3 2 B yte )

Transm it FIFO

(32 Byte)

Receive FIFO

(32 Byte)

Receive FIFO

(32 Byte)

Transm it FIFO

(32 Byte)

Transmit

Protocol

Machine

Receive

Protocol

Machine BRG

LAP C ontrol

Serial Channel B

TSA

26 Oscillator

PEB 20525
PEF 20525
Functional Over view
Preliminary Data Sheet  3-40 09.99
 
3.2 Serial Communication Controller (SCC)
3.2.1 Protocol Modes Overview
The SCC is a mult i-protocol communi cat ion cont roll er. The core l ogi c provides different
protocol modes w hich are listed bel ow:
• HDLC Modes
– HDLC  Tran spar ent Oper ation (Address Mode 0)
– HDLC  Addre ss Recogni t ion (A ddress Mode 1, Address Mode 2 8/16-bit)
–Full-Duplex LAPB/LAPD Operation (Automode 8/16-bit)
–Half -Duplex SD LC -NRM  Operation (Automode 8-bit)
–Signa ling System #7 (SS7) Operation
• Point-to-Point Prot ocol (PPP) Modes
–Bit Synchronous PPP
–Octet Synchronous PPP
•Extended Transparent Mode
A detailed description of these protocol modes is given in Chapter 4, starting on page 4-
80.
3.2.2 S CC FIFOs
Each SCC provides its own transmit and receive FIFOs to handle internal arbitration and
microcont ro ller late nci es.
3.2.2.1 SCC Transmit FIFO
The SCC transmit FIFO is divided into two parts of 32 bytes each (’transmit pools’). The
interface between the two parts provides clock synchronization between the system
clock domai n and the protocol logic working with  the serial transmit clock.

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-41 09.99

Figure 3-2 SCC Transmit FIFO

The 32 bytes system clocked FIFO part is accessable by the CPU/DMA controller; it

accepts transm it data eve n if the SCC is in power-down condition (register CCR0H bit

PU=’0’).

The only exception is a transmit data underrun (XDU) event. In case of an XDU event

(e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer

anot her byte to the protocol logic. This XDU block ing mechanism prevent s unexpect ed

serial data. The blocking condition must be cleared by reading the interrupt status

shoul d not be masked i n register IMR1.

T ransfer of data t o the 32 byte shado w par t only takes place if the SCC i s in pow er-up

condition and an appropriate transmit clock is provided depending on the selected clock

mode.

Serial data transmission will start as soon as at least one byte is transferred into the

shadow FIFO and transmission is enabled depending on the selected clock mode (CTS

sign al acti ve, clock stro be signal activ e, timesl ot valid or clock gappi ng signal inac tive) .

3.2.2.2 SCC Receive FIFO

The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between

the two parts provides clock synchronization between the system clock domain and the

protocol logic working with the serial receive clock.

32 byte Transm it Pool

(accessable by CPU)

32 byte Shadow part

(not accessable by CPU)

Microprocessor/DMA

Interface

Transmit

Protocol M achine

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-42 09.99

Figure 3-3 SCC Receive F IFO

New receive data is announced to the CPU with an interrupt latest when the FIFO fill

level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register

"CCR3H" on page 5-149). Default value for this threshold level is 32 bytes.

If the SCC receive FIFO is completely filled, further incoming data is ignored and a

receive data overflow condition (’RDO’) is detected. As soon as the receive FIFO

provides em pt y space, r ecei ve data is accepted again after a frame end or f ram e abort

sequence. The automatically generated receive status byte (RSTA) will contain an ’RDO’

indication in this case and the next incoming frame will be received in a normal way.

Therefore no further CPU intervention is necessary to recover the SCC from an ’RDO’

condition.

A "frame" with ’RDO’ status might be a mixture of a frame partly received before the

’RDO’ event occured and the rest of this frame received after the receive FIFO again

accepted data and the frame was still incoming. A quite arbitrary series of data or

complete frames might get lost in case of an ’RDO’ event. Every frame which is

completely discar ded because of an ’RDO’ conditi on genera tes an ’RFO’ interrupt.

The SCC receive FIFO can b e cleared by command ’RRES’ in register CMDRH. Note

that clearing the receive FIFO during operation might delete a frame end / block end

indication. A frame which was already partly transferred cannot be "closed" in this case.

A new frame received after receiver reset command will be appended to this "open"

frame.

Microprocessor/DMA

Interface

Receive

P rotocol M achine

32 byte Receive Pool

(accessable by CP U)

32 byte Shadow part

(not accessable by CPU)

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-43 09.99

3.2.2.3 SCC FIFO Access

Figure 3-4 and Figure 3-5 illustrate byte interpretation for Intel and Motorola 16-bit

accesses to the transmit and receive FIFOs.

F igure 3-4 XFIFO/RFIFO Word Access (Intel Mode)

F igure 3-5 XFIFO/RFIFO Word Access (Motorola Mode)

te 1

te 2

te 3

te 4

te 5

te 32

(

7:0

)

(

15:8

)

te 1

te 2

te 3

te 4

te 5

te 32

(

7:0

)

(

15:8

)

XFIFO RFIFO

te 1

te 2

te 3

te 4

te 5

te 32

(

7:0

)

(

15:8

)

te 1

te 2

te 3

te 4

te 5

te 32

(

7:0

)

(

15:8

)

XFIFO RFIFO

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-44 09.99

3.2.3 Clocking System

The PASSAT includes an internal Oscillator (OSC) as well as two independent Baud

Rate Generato rs (BRG) and two Digital Phase Locked Loop (DPLL) circ uits.

The transmit and receive clock can be generated either

• exter nal ly, and suppli ed directly via the RxCLK and/or TxCLK pi ns

(called external clock modes)

• inte rnally, by selecting

– the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG)

– the internal DPLL, recovering the receive (and optionally transmit) clock from the

receive dat a stream .

(called inte rnal clo ck mode s)

There are a total of 14 different clocking modes programmable via bit field ’CM’ in

shown in Table 3-2.

The transmit clock pins (TxCLK) may also be configured as output clock and control

signals in certain cl ock mo des if enabl ed via bit ’TOE’ in register CCR0L.

The clocking source for the DPLL’s is always the internal channel specific BRG; the

scaling factor (divider) of the BRG can be programmed through BRRL and BRRH

registers.

There are two channel spec ific interna l operationa l clocks in the SCC:

One operational clock (= transmit clock) for the transmitter part and one operational clock

(= receive clock) for the rece iver part of the protocol logic.

Note: The internal timers always run using the internal transmit clock.

Table 3-1 Overview of Clock Modes

Clock

Type Source Generation Clock Mode

Receive

Clock

RxCLK Pins Externally 0, 1, 4, 5

OSC,

DPLL,

BRG,

Internally 2, 3a, 6, 7a

3b, 7b

Transmit

Clock

TxCLK Pins,

RxCLK Pins Externa lly 0a , 2a, 4, 6a

1,5

OSC,

DPLL,

BRG/BCR,

BRG

Internally 3a , 7a

2b, 6b

0b, 3b, 7b

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-45 09.99

The internal structure of each SCC channel consists of 3 clocking domains, transmit,

receive, and system. These three function blocks are clocked with internal transmit

frequency fTRM, internal re cei ve f reque ncy fREC and system frequency fSYS, re spective ly

(system frequency fSYS only supplies the SCC receive and transmit FIFO part facing the

microprocessor interface). The internal FIFO interfaces are used to transfer data

between the different clock domain s.

The clocks fTRM and fREC are internal clock s only and need not be identical to external

clock inputs e.g. fTRM and TxCLK input pin.

The features of the different clock modes are summarized in Table 3-2.

T able 3-2 Clock Modes of the SCC s

Channel

Configuration Clock Sour ces Control Sources

Clock

Mode

CCR0L:

CM(2..0) CCR0L:

SSEL to

BRG to

DPLL to

REC to

TRM CD R- Strobe X- Strobe Frame-

Sync

Tx Rx

Output

via

TxCLK

(if CCR0L:

TOE = ‘1’)

–

OSC

–

RxCLK

–

OSC

–

BRG

–

BRG

–

RxCLK

DPLL

BRG

RxCLK

DPLL

BRG

TxCLK

BRG

RxCLK

TxCLK

BRG/16

DPLL

BRG

TxCLK

RxCLK

TxCLK

BRG/16

DPLL

BRG

–

RCG

(TSAR/

PCMRX)

(TSAR/

PCMRX)

–

TxCLK

–

TCG

(TSAX/

PCMTX)

(TSAX/

PCMTX)

–

FSC

OST

–

FSC

OSR

–

BRG

–

BRG/16

DPLL

BRG

TS-Control

–

BRG/16

DPLL

BRG

PEB 20525

PEF 20525

Functional Over view

Preliminary Data Sheet 3-46 09.99

Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) is

enabled which allows connection of an external crystal to pins XTAL1-XTAL2. The

output signal of the OSC can be used for one serial channel, or for both serial

channels (independent baud rate generators and DPLLs). Moreover, XTAL1

alone can be used as input for an externally generated clock.

The first two columns of Table 3-2 list all possible clock modes configured via bit field

’CM’ and bit ’SSEL’ in register CCR0L.

For example , clock mode 6b is ch oosen by writing a ’6’ to regis ter CCR0L.CM (2:0) and

by setting bit CCR0L.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock

Sources’) specify the source of the internal clocks. Columns REC and TRM correspond

to the domain clock f reque nci es fREC and fTRM .

The columns grouped as ’Control Sources’ cover additional clock mode dependent

control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or

synchronization signals (clock mode 5). The last column describes the function of signal

TxCLK which in some clock modes can be enabled as output signal monitoring the

effective transm it clock or provid ing a time slot control signal (clock mode 5).

The following is an example of how to read Table 3-2:

For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate

generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is

derived from the internal oscillat or which is supplied by pi n XTAL1 and XTAL2.

The REC clock (col umn ’REC’) is supplied by the inter nal D PLL which itself is supp lied

by the baud rate generator (column ’DPLL’) again.

Note: The REC clock is DPLL clock di vi ded by 16.

If enabled by bit ’TOE’ in registe r CCR0L the res ulting transmit cl ock can be monitored

via pin TxCLK (last column, row ’6b’).

PEB 20525

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Functional Over view

Preliminary Data Sheet 3-47 09.99

T he clockin g concept is illustrated i n a block diagram manner in the follow i ng figure:

Additional control signals are not illustrated (please refer to the detailed clock mode

de scr iptions bel ow ).

F igure 3-6 Clock Supply Overview

Oscillator

XTAL1

XTAL2

RxD

BRG

6a/b

7a/b

2a/b

3a/b

DPLL 16:1

RxCLK

TxCLK

DPLL

BRG

BRG/16

RxCLK

TxCLK

DPLL

BRG

RxCLK

TRM

Transmitter Receiver

REC

TTL

CRYSTAL

DPLL

BRG

BRG/16

RxCLK

TxCLK

7a 0b

6b 1

5a 0a

2a/b

6a/b

7b 0a/b

5a/b

settings controlled by:

selects the clock mode number

selects the additional a/b option

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Functional Over view

Preliminary Data Sheet 3-48 09.99

Clock Modes

3.2.3.1 Clock Mode 0 (0a/0b)

Separate, externa lly gener ated receive and transmit clocks are sup plied t o the SCC via

their respective pins. The transmit clock may be directly supplied by pin TxCLK

(clock mode 0a) or generated by the internal baud rate generator from the clock supplied

at pin XTAL1 ( clock mode 0b).

In clock mode 0b the r esul ting transmit clock can be dri ven ou t to pin TxC LK i f enabl ed

via bit ’TOE’ in registe r CCR0L.

Figure 3-7 Clock Mode 0a/0b Configuration

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

(tx clock monitor output)

clock mode 0b

clock mode 0a

OSC

Ctrl.

BRG

= f

OSC

K=(n+1)/2

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Functional Over view

Preliminary Data Sheet 3-49 09.99

3.2.3.2 Clock Mode 1

Externally generated RxCLK is supplied to both the receiver and transmitter. In addition,

a rece ive strobe c an be connected vi a CD and a tra nsmit strobe v ia TxCLK pin. The se

strobe signals work on a per bit basis. This operating mode can be used in time division

mult iplex appli cat ions or for adjusting dispara te transmi t and receive data rates.

Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte

synchronization (byte alignment).

This means that the strobe signal needs to be detected once only to transmit or

recei ve a com ple te byte.

F igure 3-8 Clock Mode 1 Configurat ion

RxCLK

CTS

, Cx D , TCG

, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clo ck suppl

clock m ode 1

receive strobe

transmit strobe

RxD

(rx stro b e)

TxCLK

(tx stro b e)

RxCLK

TxD

(enables transm it)

Note: In ext e nd ed tr an spa r e nt mod e th e strob e s i

nals need to be dete cted once onl

transm it or receive a complete b

te. Th u s b

te ali

nme nt is provid ed in this mo de.

Ctrl.

PEB 20525

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Functional Over view

Preliminary Data Sheet 3-50 09.99

3.2.3.3 Clock Mode 2 (2a/2b)

The BRG i s driven by an external cl ock (RxC LK pin) and delivers a reference cloc k for

the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies

the i nternal receive clock. Depending on the pr ogramming of r egister CCR0L bi t ’SSEL’,

the transmit clock will be either an external input clock signal provided at p in TxCLK in

clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the

latter case, the transm i t c lock can be dr iven out t o pin TxC LK i f enabled via bit ’ TO E’ in

Figure 3-9 Clock Mode 2a/2b Configuration

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

(tx clock monitor output)

clock mode 2b

clock mode 2a

BRG

DPLL 2

BRG

DPLL 16:1

Ctrl.

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Preliminary Data Sheet 3-51 09.99

3.2.3.4 Clock Mode 3 (3a/3b)

The BRG is fed with an externally generated clock via pin RxCLK. Depending on the

value of bit ’SSEL’ in re gis ter CCR0L the BRG del ivers either a reference clock f or the

DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or

delivers directly the receive and transmit clock (clock mode 3b). In the first case the

DPLL output clock is used as receive and transm i t clock.

F igure 3-10 Clock Mode 3a/3b Configuration

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

RxCLK

CTS, CxD, TCG

CD, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

(tx clock monitor output)

clock mode 3b

clock mode 3a

BRG

DPLL

(tx clock monitor output)

BRG

Ctrl.

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Preliminary Data Sheet 3-52 09.99

3.2.3.5 Clock Mode 4

Separate, externally generated receive and transmit clocks are supplied via pins RxCLK

and TxCLK. In addition sepa rate recei ve and tra nsmit clock gating signals are supplied

via pins RC G and TCG. These gating signal s work on a per bit basis.

Figure 3-11 Clock Mo de 4 Configuration

RxCLK

CTS, CxD,

TCG

CD, FSC,

RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock suppl

clo ck m ode 4

transm it clock

ate si

nal

receive clock

ate si

nal

TxCLK

TCG

TxD

RxCLK

RCG

RxD

1 clock delay

Ctrl.

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Preliminary Data Sheet 3-53 09.99

3.2.3.6 Clock Mode 5a (Time S lot Mo de)

This operation mode has been designed for application in time-slot oriented PCM

systems.

Note: Fo r correct operati on NRZ data coding/e ncodi ng shoul d be used.

The receive and transmit clock are common for each channel and must be supplied

exte rnall y v ia pi n RxCLK. The SCC r ecei ves and t ran smits only during fixed time- slo ts.

Either one time-slot

– of programmabl e w idth (1 … 512 bit, via TTSA and RTSA re gisters), and

– of programmable location with respect to the frame synchronization signal (via pin

FSC)

or up to 32 time-slots

– of consta nt width (8 bits), and

– of programmable location with respect to the frame synchronization signal (via pin

FSC)

can be sele cted.

The time-slot locations can be programmed independently for receive and transmit

direct ion via TTSA/RTSA and PCMTX/PCMRX registers.

Dep ending on the value pr ogrammed via tho se registers, the re ceive/transmit time-s lot

starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame

synchronization signal.

Figure 3-12 shows how to select a time-slot of programmable width and location and

Figure 3-13 show s how to select one or more time-slots of 8-bit width.

If bit ’TOE’ in register CCR0L is set, the selected transmit time-slot(s) is(are) indicated at

an outp ut stat us signal vi a pin TxCL K, which is driven to ‘low’ during t he activ e transm it

window.

Bit ’TSCM’ in register CCR1H determines whether the internal offset counters are

continuously running even if no synchronization pulse is detected at FSC signal or

stopping at their maximum value.

In the continuo us case th e repeti tion rate of offset coun ter operation is 1024 transmit or

receive clocks respectively. An FSC pulse detected earlier resets the counters and starts

opera tion agai n.

In the non-continuous case the time slot assigner offset counter is stopped after the

count er reached i ts maxi mum val ue and is started again if an FSC pulse is detected.

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Preliminary Data Sheet 3-54 09.99

Figure 3-12 Se lectin g one time-slot of programmab le delay and width

TTSN TCSTCC 0

RTSN RCSRCC 0

TT SA0..3: T ransm it Time Slot Assi

nmen t R e

ister

RTSA0 ..3 : Re c eiv e Time Slo t Ass i

nm ent R e

ister

T EPCM = '0': T PCM Mask D isabled

RE P CM = '0 ': RP C M Mask D isabled

TS d e la y (tra n s mit):

1 + TTS N *8 + T CS

(1...1024)

T S de la y (rec eive):

1 + RT SN *8 + R CS

(1...1024)

TS wid th (tra n smit) :

TCC

(1...5 1 2 c lo c ks )

T S w idth (rec eive):

RCC

(1..512)

FSC

RxCLK

active

time slo t

TTSA1 7TTSA0 0707

TTSA3 TTSA2

700RTSA1 7RTSA0 0

707

RTSA3 RTSA2

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Preliminary Data Sheet 3-55 09.99

Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame

itself to achieve synchronization (at least for the 2nd and subsequent PCM

frames ): DELAY = PCM frame length = 1 + xTSN*8 + xC S. xTSN and xCS have

to be set appropria tely.

Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected.

PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7.

Note: In extended transparent mode the width x CC of the selected time-slot has to be

8 bit because of character synchronization (byte alignment). In all other modes

the width can be used to define w indows down to a minimum length of one bit.

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Preliminary Data Sheet 3-56 09.99

Figure 3-13 Se lectin g one or more time-slots of 8-bit width

The common transmit and receive clock is supplied at pin RxCLK and the common frame

synchronisation signal at pin FSC. The "strobe signals" for active time slots are

generated internally by the time slot assigner block (TSA) independent in transmit and

receive direction.

When the transmit and receive PCM masks ar e enabled, bit fields ’TCC’ and ’RCC’ are

ignored because of the constant 8-bit time slo t width.

TS delay (transm it):

1 + TTSN*8 + TCS

(1..1024)

TS delay (rece ive):

1 + RTSN*8 + RCS

(1..1024)

31 24 23 16 15 8 7 0

PCMTX0..3: Transmit PCM Mask Register

...

TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17

8 bit

REPCM = '1': TPCM Mask Enabled

31 24 23 16 15 8 7 0

PCMRX0..3: Re ceive PCM Mask Register

FSC

RxCLK

active

tim e s lo t

700

TTSN TCS

TCC 1

TTSA0..3: Transmit Time Slot Assignment Register

TEPCM = '1': TPCM Mask Enabled

TTSA1 7TTSA0 0707

TTSA3 TTSA2

PCMTX1 PCMTX0

PCMTX3 PCMTX2

RTSN RCS

RCC 1

RTSA0..3: Receive Tim e Slot Assignment Register

700RTSA1 7RTSA0 07 07

RTSA3 RTSA2

PCMRX1 PCMRX0

PCMRX3 PCMRX2

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Functional Over view

Preliminary Data Sheet 3-57 09.99

F igure 3-14 Clock Mode 5a Configuration

Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’

and ’TCC’ in registers TTSA0..TTSA3.

The receive time slot delay and width is programmable via bit fields ’RTSN’, ’RCS’

and ’RCC’ in reg is ters RTSA0..RTSA3.

RxCLK

CTS

, CxD , TCG

CD,

FSC

, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock suppl

clock m ode 5a

time slo t in d ic a tor s i

nal

Tim e S lot

Assigner

(TSA)

RxCLK

FSC

internal

tx s trobe

TS delay TS width

TxCLK

TS-Control

TxD

internal

rx s tro be

TS de lay TS w idth

RxD

012n... 0n

Ctrl.

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Functional Over view

Preliminary Data Sheet 3-58 09.99

The following figures provide a more detailed description of the TSA internal counter

operation and exce ptional cases:

Figure 3-15 Clock Mo de 5a "Continuous Mo de"

...

FSC

RxCLK,

TxCLK

active

time slot

load offset

ocnt

:= 1024 -

TSdelay ocnt

:= 1024

ocnt

:= 0

load offset

ocnt

:= 1024 -

TSdelay

load duration

dcnt

ocnt

TSdelay

dcnt

:= 0

dcnt

TSwidth

- 1

dcn t

:= 0

dcnt

:= 255

active

time slots according

PCMTX/PCMRX

Mode TEPCM/ REPCM = '0'

Mode TEPCM/REPCM = '1'

Exceptions:

a) FSC pulse period > 1024:

The offset counter

ocnt

will automaically restart after 1024 clock cycles

and will be restarted again by the late FSC pulse!

b) FSC pu lse period < (

TSdelay

TSwidth

), i.e. FSC pulse detected while duration counter still active:

The offset counter

ocnt

will automaically restart,

but duration counter

dcnt

continues operation (transmit/receive in active time slots)

clo ck mode 5a

bit TSCM='0' (c onti nuou s m ode)

ocnt

start

TSdelay

+ 1024 clock cycles

ocnt

restart

FSC

< 1024 clock cycles

FSC

dcnt

start

TSdelay

= 1 + xT SN*8 + xCS

(1...1024)

ocnt

restart

ocnt

restart

ocnt

start

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Functional Over view

Preliminary Data Sheet 3-59 09.99

Each frame sync p ulse st ar ts t he int ern al of fse t count er w i th (10 24 - TSdela y) whereas

TSdelay

is the c onf igured value def in ing the start positi on. Whenever the offset counter

reach es its max imum value 1024, it triggers the duration counter to start operat ion.

If continuous mode is selected (bit CCR1H.TSCM=’0’) the offset counter continues

starting with value 0 until another frame sync puls is detected or again the maximum

valu e 1024 is reached.

Once the duration counter is triggered it runs out independently from the offset counter,

i.e. an active time slot period may overlap with the next frame beginning (frame sync

event , refer to exception b) in Figure 3-15).

Figure 3-16 Clock Mode 5a "Non Continuous Mode"

If non-continuous mode is selected (bit CCR1H.TSCM=’1’) the offset counter is stopped

on its maximum value 1024 until another frame sync puls is detected. This allows frame

sync periods greater than 1024 clock cycles, but the accesible part is limited by the range

of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM

mask is sele c te d .

ocnt

TSdela

- 1

Exceptions:

)

FSC pulse period > 1024:

Th e o ffs et c o u n te r

ocnt

will s t op o n it s ma x imu m v a lu e 10 2 4, whic h tr i

er s th e d ur a tio n co u n te r

dcnt

a n d w ill b e re s tarte d a

ain b

the 'late' FSC pulse!

clo ck m o de 5a

bit TSCM='1' (non continuous mode)

ocnt

start

TSdela

+ 1024 clock c

cles

ocnt

stop

ocnt

start

FSC

A differen t beh avior to clock m o de 5a c ontino us m ode is

ive n o nly in

ca se of Exce ptio n a ).

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Preliminary Data Sheet  3-60 09.99
 
3.2.3.7 Clock Mode 5b (Octet Sync Mode)
This operation mode has been designed for applications using Octet Synchronous PPP.
It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported,
i.e. bits TTSA1.TEPCM and RTSA1.REPCM must be set to ’1’. Clock mode 5b provides
octet alignment to time slots if Octet Synchronous PPP protocol mode or extended
transparent mode is selected.
Note: For correct operation NRZ  data coding/ encoding should  be used.
The receive and transmi t clock s are  separ at e and m ust  be supplied  at pins  RxC LK and
TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of
programmable location with respect to the octet synchronization signals (via pins OSR
and OST)
The time-slot locations can be programmed independently for receive and transmit
direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 /
PCMRX0..PCMRX3. 
Figure 3-17 sho ws  how to select one or more octet wide time-slots.
Bit ’ TSCM’ in register CCR1H determines whether the internal counters are continuously
running even if no synchronization pulse is detected at OST/OSR signals or stopping at
t h ei r ma ximum  va lu e .
In the continuous case the repetition rate of operation is 1024 transmit or receive clocks
respectively. An OST/OSR pulse detected earlier resets the corresponding offset
counter and starts operation again.
In the non-continuous case the transmit/receive time slot assigner offset counter is
stopped after the counter reached its maximum value and is started again if an OST/
OSR pulse is detected.

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Preliminary Data Sheet 3-61 09.99

F igure 3-17 Selecting one or more octet wide t ime- slots

The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet

synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for

active time slots are generated internally by the time slot assigner blocks (TSA)

inde pendent in transmit and recei ve directio n.

Bit fields ’TCC’ and ’RCC’ are ignored because of the constant 8-bit time slot width.

T S de lay (tra ns mit):

1 + TTSN*8 + TCS

(1...1024)

TS dela y (receive):

1 + RTSN*8 + RCS

(1...1024)

...

TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17

8 bit

OSR

OST

RxCLK

TxCLK

active

time slo t

31 24 23 16 15 8 7 0

PCMTX0..3: Transm it PCM Mask Re

ister

700

TTSN TCSTCC 1

T T S A 0 ..3: T ra ns mit T ime S lo t A ssi

nm en t R e

ister

T E PCM = '1': TP CM Ma s k En a b led

TTSA1 7TTSA0 07 07

TTSA3 TTSA2

P C M T X1 PC M T X 0

PCMTX3 PCMTX2

R EP CM = '1': T PC M Mask Enab led

31 24 23 16 15 8 7 0

PCMRX0..3: Receive PCM Mask Re

ister

RTSN RCSRCC 1

R T S A 0..3 : Receive Time Slot A ss i

nme nt Re

ister

0RTSA1 7RTSA0 0707

RTSA3 RTSA2

PCMRX1 PCMRX0PCMRX3 PCMRX2

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Preliminary Data Sheet 3-62 09.99

Figure 3-18 Clock Mo de 5b Configuration

Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’

and ’TCC’ in registers TTSA0..TTSA3.

The receive time sl ot delay and width is programmable via bit fields ’RTSN’, ’RCS’

and ’RCC’ in registers RTSA0..RTSA3.

RxCLK

CTS, CxD, TCG,

OST

CD, FSC, RCG,

OSR

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock suppl

clock mode 5b

Time Slot

Assigner

(RTSA)

RxCLK

TxCLK

OSR

OST

internal

tx s tro be

TS delay TS width

TxD

internal

rx strob e

TS delay TS width

RxD

012n... 0n

Ctrl.

Time Slot

Assigner

(TTSA)

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Preliminary Data Sheet 3-63 09.99

3.2.3.8 Clock Mode 6 (6a/6b)

This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG

is supp lied at pin XTAL1.

T he BRG is driven by the int erna l oscillator and del i vers a reference clock for the D PLL

which is 16 times the resulting DPLL output frequency which in turn supplies the internal

receive clock. Depending on the programming of register CCR0L bit ’ SSEL’, the transmit

clock will be either an external input clock signal provided at pin TxCLK in clock mode

6a or the clock delivered by the BRG divided by 16 in clock mode 6b. In the latter case,

the transmit clock can be driven out to pin TxCLK if enabled via bit ’TOE’ in register

CCR0L.

F igure 3-19 Clock Mode 6a/6b Configuration

RxCLK

CTS

, CxD, TCG

, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

clock supply

RxCLK

CTS

, CxD, TCG

, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

(tx clock monitor output)

clock mode 6b

clock mode 6a

BRG

DPLL

BRG

DPLL 16:1

OSC

Ctrl.

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Preliminary Data Sheet 3-64 09.99

3.2.3.9 Clock Mode 7 (7a/7b)

This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG

is supplied at pin XTAL1.

The BRG is driven by the internal oscillator. Depending on the value of bit ’SSEL’ in

the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and

transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and

transmit data.

Figure 3-20 Clock Mo de 7a/7b Configuration

RxCLK

CTS

, CxD, TCG

, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

RxCLK

CTS

, CxD, TCG

, FSC, RCG

TxCLK

RTS

RxD

TxD

XTAL1

XTAL2

(tx clock monitor output)

clock mode 7b

clock mode 7a

BRG

DPLL (tx clock monitor output)

BRG

OSC

Ctrl.

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Preliminary Data Sheet 3-65 09.99

3.2.4 Baud Rate G enerato r (BRG)

Each serial channel provides a baud rate generator (BRG) whose division factor is

controlled by registers BRRL and BRRH. Whether the BRG is in the clocking path or not

depends on the selected clock mode.

The clock division factor k is calculated by:

3.2.5 Clock Recovery (DPLL)

T he SCC offers the a dvantage o f recov ering the received clock fro m the rece ived data

by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock

informat ion via a separ ate serial clock line . For this purpose, the D PLL is supplied w ith

a ‘ref erence clock ’ from the BRG which is 16 times the expected data clock rate (clock

mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG

by a constant fac tor of 16 ( clock m ode 2b, 6b; bit ’SSEL’ in register CCR0L set) or al so

direct ly from the DPLL (clock mode 3a, 7a).

The main task of the DPLL is to derive a receive clock and to adjust its phase to the

inco ming dat a stream in order to enable optimal bit sampling.

T he mechan ism for clock r ecovery depends on t he select ed data en coding (see "Data

Encoding" on page 3-71).

The following functions have been implemented to facilitate a fast and reliable

synchronization:

Table 3-3 BRRL/BRRH Register and Bit-Fields

Offset Pos. Name Default Description

BRRL

38H/88H

5..0 BR N 0 Baud Rate Factor N

range N = 0..63

BRRH

39H/89H

11..8 BRM 0 Baud Rate Factor M,

range M = 0..15

kN1

+()

×=

fBRG fin k

⁄=

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Preliminary Data Sheet  3-66 09.99
 
Interference Rejection and Spike Filtering
Two or more edges in the same directional data stream within a time period of 16
reference clocks are considered to be interference  and consequently no additional clock
adjustmen t is performed.
Phase Adjustment (PA)
Referring to Figure 3-21, Figure 3-22 and Figure 3-23, in the case where an edge
appears in the data stream within the PA fields of the time window, the phase will be
adjusted by 1/16 of the data.
Phase Shift (PS) (NRZ, NRZI only)
Referring to Figure 3-21 in the case where an edge appears in the data stream within
the PS field of the time w in dow, a s econd s amp ling of  the bit i s forced an d the  phase is
shifted by 180 degrees.
Note: Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications . Above all, it implies a very fast synchronization beca use of the phase shif t
feature: one  edge o n the received  data st ream is enough  for the D PLL to  synchron ize,
thereby eliminating the need for synchronization patterns, sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
The SCC offers the option to disable the Phase Shift function for NRZ and NRZI
encodings by setting bit ’PSD’ in register CCR0L to ’1’. In this case, the PA fields are
extended as shown i n  Figure 3-22.
Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach
the optimal sampling position. To ensure correct data sampling, preambles should
precede the data informa tion.
Figure 3-21, Figure 3-22 and Figure 3-23 explain the DPLL algorithms used for the
different data encodings.

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Preliminary Data Sheet 3-67 09.99

Figure 3-21 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled)

Figure 3-22 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled)

012345678910 11 12 13 14 15

0 +PA PS -PA 0

Bit Cell

DPLL

Count

Output

DPLL

Correction

ITD01806

0123456789101112131415

0+PA -PA 0

Bit Cell

DPLL

Count

Output

DPLL

Correction

ITD04820

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Functional Over view
Preliminary Data Sheet  3-68 09.99
 
Figure 3-23 DPLL Algorithm for FM0, FM1 and Manchest er Encoding 
To supervise correct function when using bi-phase encoding, a status flag and a
maskable inter rupt infor m about synchr onous/asynchr onous  state of the DPLL.
3.2. 6 SC C Tim e r Op eration
Each SCC provides a general purpose timer e.g. to support protocol functions. In all
operating modes the timer is clocked by the effective transmit clock. In clock mode 5
(time-slot oriented mode) the clock  source for the timer can be optionally switched to the
frame sync clock (input pin FSC) by setting bit ’SRC’ in register TIMR3.
The timer  i s c ont rolle d by th e C PU  vi a access  to  re gis ters CMDRL and  TIMR0..TIMR3.
The timer can be sta rted any t ime by setting bit ’STI’ in register CMDRL. After the timer
has expired it generates a time r interrupt (’TIN’). 
Wit h bit f ield  ’CNT( 2..0) ’ in  regist er TIMR3 the number of automatic timer restarts can be
programmed. If the maximum value ’111’ is entered, a timer interrupt is generated
periodically, with the time period determined by bit field ’TVALUE’ (registers
TIMR0..TIMR3).
The timer can be stopped any time by setting bit ’TRES’ in register  CMDRL to ’1’.
In HDLC Automode the timer is used internally for autonomous protocol functions (refer
to the chapter "Automode" on page 4-81). If this operating mode is selected, bit ’TMD’ in
register TIMR3 m ust  be set to ’1’.
0123456789101112131415
0 +PA - ignore - -PA 0
Bit Cell (FM  Coding)
DPLL
Count
Clock
Transmit
Correction
ITD01807
76543210
Bit Cell (Manchester Co ding )
+PA - ignore -
Receive
Clock

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Preliminary Data Sheet 3-69 09.99

3.2.7 SCC Serial Bus Configuration Mode

Besid e the point-to-po int configur ation, the SCC ef fectively sup ports point-to-mult ipoint

(pt-m pt, or bus) configuration s by m eans of internal idle a nd col lision detect i on/col lision

resolution methods.

In a pt-mpt configuration, comprising a central station (master) and several peripheral

stations (slaves), or in a multimaster configuration, data transmission can be initiated by

each station over a common transmit line (bus). In case more than one station attempts

to transmit data simultaneously (collision), the bus has to be assigned to only one

stati on. A coll ision-resolution pro cedure is implemented i n the SCC. Bus assignment is

based on a priority mechanism with rotating priorities. This allows each station a bus

access within a predetermined maximum time delay (deterministic CSMA/CD), no

matte r how many transmitters are connected to the serial bus.

Prer equisites f or bus operation ar e:

• NRZ encoding

• ‘OR’ing of data from every transmitter on the bus (this can be realized as a wired-OR,

using the TxD open drain capability)

• Feedba ck of bus info rmation (CxD i nput ).

The bus configuration is selected via bitfield SC(2:0) in register CCR0H.

Note: Central clock supply for each station is not necessary if both the receive and

transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the

ph ase shift between the individua l transm it clocks.

The bus configuration mode operates independently of the clock mode, e.g. also

together with clock mode 1 (receive and transmit strobe operation).

3.2.8 Serial Bus Access Procedure

T he idle state of the bus is i dentified by eight or m ore co nsecutive ‘1’ s. Whe n a devi ce

starts transmissi on of a fram e, the bus is reco gni zed t o be busy by the ot her d e vices at

the moment the first ‘zero’ is transmitted (e.g. first ‘zero’ of the opening flag in

HDLC mode).

After the frame has been transmit ted, the bus become s availab le again (idle).

Note: If the bu s is occupied by other transmitters and/ or there is no trans mit request in

the SCC, logica l ‘1’ will be continuous ly transmitted on TxD.

3.2.9 Serial Bus Collisions and Recovery

During the transmission, t he data transmitted on TxD is compared with t he data on CxD.

In case of a mismatch (‘1’ sent and ‘0’ detected, or vice versa) data transmission is

imme dia tely abor ted , and idle (logical ‘1’) is transmitted.

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Functional Over view

Preliminary Data Sheet 3-70 09.99

HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the

first part of t he frame is still present in the SCC transmit FIFO. If not, an XMR i nterrupt is

generated.

Since a ‘zero’ (‘low’) on the bus prevails over a ‘1’ (high impedance) if a wired-OR

connection is implemented, and since the address fields of the HDLC frames sent by

different s tations normally differ from one anot her, the fact that a collision has oc curred

will be detected prior to or at the latest within the address field. The frame of the

transmitter with the highest temporary priority (determined by the address field) is not

affected and is transmitted successfully. All other stations cease transmission

immediate ly and return to bus moni toring state.

Note: If a wired-OR connection has been realized by an external pull-up resistor without

decoupling, the data output (TxD) can be used as an open drain output and

connected direc tly to the CxD input.

For correct identification as to which frame is aborted and thus has to be repeated

after an XMR int errupt has o ccurred, the content s of SCC transm it FIFO have t o

be unique, i.e. SCC transmit FIFO should not contain data of more than one frame.

For this purpose new data may be provided to the transmit FIFO only after ’ALLS’

interrupt status is detected.

3.2.10 Serial Bus Access Priority Scheme

To ensure that all competing stations are given a fair access to the transmission medium,

a two-stage bus access priority scheme is supported by PASSAT:

Once a station has successfully completed the transmission of a frame, it is given a lower

level of priority. Thi s priority me chani sm is based on t he re quirem ent that a station m ay

attempt transmitting only when a determined number of consecutive ‘1’s are detected on

the bus.

Normally , a transmission can star t wh en ei ght consecut ive ‘ 1’s on the bus are det ect ed

(through pin CxD). When an HDLC frame has been successfully transmitted, the internal

priority class is decreased. Thus, in order for the same station to be able to transmit

another fram e, ten consec utive ‘1’s o n the bus must be detect ed. This gu arantees tha t

the transmission requests of other stations are satisfied before the same station is

allowed a second bus access. When ten consecutive ‘1’s have been detected,

transmission is allowed again and the priority class (of all stations) is increased (to eight

‘1’s).

Inside a priority class, the order of transmission (individual priority) is based on the HDLC

address, as explained in the preceding paragraph. Thus, when a collision occurs, it is

always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a

bit position of the address field that wins, all other stations cease transmission

immediately.

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Functional Over view

Preliminary Data Sheet 3-71 09.99

3.2.11 Serial Bus Confi guration Timing Modes

If a bus configura tion has been selected, the SCC provides two timing modes, diffe ring

in the time interval between sending data and evaluation of the transmitted data for

collision detection.

• Timing mode 1 (CCR0H:SC (2:0) = ‘001’)

Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated

1/2 a clock period later at the CxD pin with the falling clock edge.

• Timing mode 2 (CCR0H:SC (2:0) = ‘011’)

Data is output with the falling clock edge and evaluated with the next falling clock

edge. Thus one complete clock per iod is avai lable between data out put and c ol lision

detection.

3.2.12 Functions Of Si gnal RTS in HDLC Mode

In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC

bits) to be active when data (frame or character) is being transmitted. This signal is

delayed by one clock period with respect to the data output TxD, and marks all data bits

that could be transmitted without collision (see Figure 3-24). In this way a configuration

may be implemented in which the bus access is resolved on a local basis (collision bus)

and wh ere the data are sent one clock per iod later on a separate trans mission line.

Figure 3-24 Reques t-to-Send in Bus Opera tion

Note: For details on the functions of the RTS pin refer to "Modem Control Signals

(RTS, CTS, CD)" on page 3-74.

3.2.13 Data Encoding

The SCC supports the following coding schemes for serial data:

– Non- Re tu rn -To-Z e ro (NRZ)

– Non-Return-To-Zero-Inverted (NRZI)

– F M 0 (also known as Bi-P hase Space)

– F M 1 (also known as Bi-P hase Ma rk)

ITT00242

Collision

TxD

CxD

RTS

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Functional Over view

Preliminary Data Sheet 3-72 09.99

– Manche ste r (also known as Bi-Phase )

The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H.

3.2.13.1 NRZ and NRZI Encoding

NRZ: The signal level corresponds to the value of the data bit. By programming bit ’DIV’

(CCR1L regist er), the SCC ma y invert the transmis sion and recep tion of data.

NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the

beginning of the bit cell.

Figure 3-25 NRZ and NRZI Data Encoding

3.2.13.2 FM0 and FM1 En coding

FM0: An edge occurs at the beginning of every bit cell. A logical ‘0’ has an additional

edge in the center of the bit cell, whereas a logical ‘1’ has none. The transmit clock

precedes the recei ve clock by 90°.

FM1: An edge occurs at the beginning of every bit cell. A logical ‘1’ has an additional

edge in the center of the bit cell, a logical ‘0’ has none. The transmit clock precedes the

receive clock by 90°.

0110010

ITD05313

Transmit/

Receive Clock

NRZ

NRZI

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Functional Over view

Preliminary Data Sheet 3-73 09.99

F igure 3-26 FM0 and FM1 Data Encoding

3.2.13.3 Manchester Encod ing

Manchester: In the first half of th e bit cell , the phys ical signal level corre sponds t o the

logical value of the data bit. At the center of the bit cell this level is inverted. The transmit

clock precedes the receive clock by 90°. The bit cell is shifted by 180° in comparison with

F M coding.

Figure 3-27 Manchester Data Encoding

110010

ITD01809

Receive

Clock

FM0

FM1

Transmit

Clock

110010

ITD01810

Receive

Clock

Manchester

Transmit

Clock

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Functional Over view

Preliminary Data Sheet 3-74 09.99

3.2.14 Modem Control Signals (RTS, CTS, CD)

3.2.14.1 RTS/CTS Handshaking

The SCC provides two pins (RTS, CTS) per serial channel supporting the standard

request-to-send modem handshaking procedure for transmission control.

A tr ansmit request will be indicated by outputting logical ‘0’ on the request-to-send output

(RTS). It is also possible to control the RTS output by software. After having received the

permission to trans mit (CTS ) the SCC starts data transmission.

In the case where permission to transmit is withdrawn in the course of transmission, the

frame is a borted and IDLE is sent. After transmission is enabled again by re-activation

of CTS, and if the beginning of the fra me is still avai lable in th e SCC, the frame will be

re-transmi tted (self-recover y). However, if the permission to transm it is withdrawn af ter

the data available in the shadow part of the SCC transmit FIFO has been completely

transmitted and the pool is released, the transmitter and the SCC transmit FIFO are

reset, the RTS output is deactivated and an inter rupt (XMR ) is generated.

Note: For correct identification as to which frame is aborted and thus has to be repeated

after an XMR int errupt has o ccurred, the content s of SCC transm it FIFO have t o

be unique, i.e. SCC transmit FIFO should not contain data of more than one frame,

which could happen if transmission of a new frame is started by providing new

data to the transmitter too early. For this purpose the ’All Sent’ interrupt

(ISR1.ALLS) has to be waited for before providing new transmit data.

Note: In the case where permission to transmit is not required, the CTS input can be

connected direc tly to

and/or bit ’FCTS’ (register CCR1H) may be set to ’1’.

Additionally, any transition on the CTS input pin, sampled with the transmit clock, will

generate an interrupt indicated via register ISR1, if this function is enabled by setting the

’CSC’ bit in register IMR1 to ’0’.

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Functional Over view

Preliminary Data Sheet 3-75 09.99

Figure 3-28 RTS/CTS Handshaking

Beyond this standard RTS function, signifying a transmission request of a frame

(Reques t To Send), in HDLC mode the RTS output may be programmed for a special

function via SOC1, SOC0 bits in the CCR1L register. Thi s is onl y availab le if the serial

channel is operating in a bus configuration mode in clock mode 0 or 1.

• If SOC1, SOC0 bits are set to ‘11’, the RTS output is active (= low) during the

reception of a frame.

• If SOC1, SOC0 bits are set to ‘10 ’, the RTS output function is disab led and the RTS

pin remains always high.

3.2.14.2 Carrier Detect (CD) Receiver Control

Similar to the RTS/CTS control for the transmit ter, the SCC suppor ts the car rier detect

modem control function for the serial receiver if the Carrier Detect Auto Start (CAS)

function is programmed by setting the ’CAS’ bit in register CCR1H. This function is

always available in clock modes 0, 2, 3, 6, 7 via the CD pin. In clock mode 1 the CD

func tion is not supporte d. See Table 3-2 for an overview.

If the CAS function is selected, the receiver is enabled and data reception is started when

the CD input is detected to be high. If CD input is set to ‘low’, reception of the current

char acter (byte ) is st ill comple ted.

3.2.15 Local Loop Test Mode

T o provide fast and efficient testin g, the SCC can be operate d in a test mode by setting

the ’TLP’ bit in register CCR2L. The on-chip serial data input and output signals (TxD,

ITT00244

Sampling

CTS

TxCLK

TxD

RTS

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Functional Over view

Preliminary Data Sheet 3-76 09.99

RxD) are connected, generating a local loopback. As a result, the user can perform a

self-test of the SCC.

Figure 3-29 SCC Test Loop

Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L.

Note: A sufficient clock mode must be used for test loop operation such that receiver and

transmitter operate with the same frequencies depending on the clock supply (e.g.

clock mode 2b or 6b).

3.3 Microprocessor Interface

The communication between the CPU and PASSAT is done via a set of directly

accessi ble registers. The interface m ay be config ured as Intel or Motorola type (refer to

description of pin ’BM’) with a selectable data bus width of 8 or 16 bit (refer to description

of pin ’WIDTH’).

Note: For the PASSAT in P-LFBGA-80-2 package only an 8-bit wide bus interface is

supported.

The CPU transfers data to/from PASSAT (via 64 byte deep FIFOs per direction and

channel), sets the operating modes, controls function sequences, and gets status

informa tion by wri ting or reading contr ol/stat us regist ers .

All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is

selected, ac cess to the lower/upper part of the data bus is determi ned by signal s BHE/

BLE as shown in Table 3-4 (I ntel mod e) or by the upp er and l ower dat a strobe signal s

UDS/LDS as shown in Table 3-5 (Motorola mo de).

SC C transmit

SCC receive

TLP='0'

TLP='1'

RxD

TxD

TLPO='0'

TLPO='1'

ID LE '1 '

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Functional Over view

Preliminary Data Sheet 3-77 09.99

Each of the two serial channels of PASSAT is controlled via an identical, but completely

independent register set (Channel A and B). Global functions that are common to or

inde pendent from the two serial channel s ar e located in global registers .

3.4 External DMA Controller Support

The PASSAT comprises a 4-channel DMA interface for fast and effective data transfers

using an external DMA controller. For both serial channels, a separate DMA Request

output for Transmit (DRT) and Receive direction (DRR) as well as a DMA

Acknowledgement input (DACK ) is provided.

The PASSAT activates the DRR/DRT line as long as data transfers are needed from/to

the spec ific FIFO (level triggered dem and transf er mode of DMA con troller ).

It is the responsibility of the DMA controller to perform the correct amount of bus cycles.

Either read cycles will be performed if the DMA transfer has been requested from the

receiver, or write cycles if DMA has been requested from the transmitter. If the DMA

cont rolle r p rovides a DMA a cknow l edge signal (DACK pin, input to the PASSAT), ea ch

bus cycle implicitly selects the top of the specific FIFO and neither address (via A0..A7)

nor chip select need to be supplied (I/O to Memory transfers). If no DACK signal is

provided, normal read/write operations (providing addresses) must be performed

(Mem or y t o Memo ry tra nsfers).

T he PASSAT deactivates th e DRR/DRT line i mmediately af ter the last read/w rite cycle

of the data transfer has started.

Table 3-4 Data Bus Access 16-bit Intel Mode

BHE BLE Register Access Data Pins Used

0 0 Word access (16 bit) D(15:0)

0 1 Byte access (8 bit), odd address D(15: 8)

1 0 Byte access (8 bit), even address D(7:0)

1 1 no data transfer -

T able 3-5 Dat a Bus Access 16-bi t Motorola Mode

UDS LDS Register Access Data Pins Used

0 0 Word access (16 bit) D(15:0)

0 1 Byte access (8 bit), even address D(15:8)

1 0 Byte access (8 bit), odd address D(7:0 )

1 1 no data transfer -

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Functional Over view
Preliminary Data Sheet  3-78 09.99
 
3.5 Interrupt Architecture
For certain events in PASSAT an interrupt can be generated, requesting the CPU to read
status information from PASSAT. The interrupt line INT/INT is asserted w ith the outpu t
characteristics programmed in bit field ’IPC(1..0)’ in register "GMODE" on page 5-109
(open drain/push pull, active low/high).
Since only one interrupt request output is provided, the cause of an interrupt must be
determined by  the CPU by read ing the interrupt status registers (GSTAR, ISR0, ISR1,
ISR2, DISR, GPISL/GPISH).
Figure 3-30 Int erru pt Status Registers
Each interrupt indication of registers  ISR0, ISR1, ISR2, DISR and  GPISL/GPISH can be
selectively unmasked by resetting the corresponding bit in the corresponding mask
registers IMR0, IMR1, IMR2, DIMR and GPIML/GPIMH. Use of these registers depends
on the selected serial mo de. 
If b it ’V IS’ in regi ster CCR0L is set to ’1’, masked interrupt status bits are visible in the
interrupt status registers ISR0..ISR2. Interrupts masked in registers IMR0..IMR2 wi ll not
generate an interrupt though. A read access to the interrupt status registers clears the
bits.
A global interrupt mask bit (bit ’GIM’ in register GMODE) suppresses interrupt generation
at all. To e nabl e the interrupt system  after reset, this bit must be set to ’0’ .
GPIM
GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0
GPIS
IMR2 (ch A)
ISR2 (ch A)
IMR1 (ch A)
ISR1 (ch A)
IMR0 (ch A)
ISR0 (ch A)
Chan nel A
Chan nel B
GSTAR
DIMR
DISR

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Functional Over view
Preliminary Data Sheet  3-79 09.99
 
The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel
related interrupts and general purpose port interrupts.
3.6 General Purpose Port Pins 
3.6.1 G PP Fun ctional Description
Gen eral pur pose por t pins ar e pro vi ded on pins G P6, GP 8, GP9 and GP10 in P-TQFP-
100-3 package (not provided in P-LFBGA-80-2 package). If external DMA support is not
enabl ed,  pins GP0...GP2 are avai lable  as gener al  purp ose pi ns (in bo th P-TQFP-100- 3
and P-LFBGA-80 -2 pack age). 
Every  pi n i s separat ely pr ogrammable via t he General Pur pose Port  Dir ection  re gis ters
GPDIRL/GPDIRH to operate as an output (bit GPnDIR=’0’) or as an input (bit
GPnDI R =’1’, reset value) .
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data r egisters GPDATL/GPDATH. Read acc ess to these registers delivers the current
state of all GPP pins (input and output signals) .
If defined as input, the state of the pin is  monitored. The signal state of  the corresponding
GP pins is sampled with a rising edge of CLK and is readable via registers GPDATL/
GPDATH. 
3.6.2 GPP Interrupt Indication
The GPP block generates interrupts for transitions on each input signal. All changes may
be indicated via interrupt (optional). To enable interrupt generation, the corresponding
interr upt  mask  bit in registers GPIML/GPIMH mus t be re s e t to  ’0’. 
Bit PI in the gloabl interrupt status register (GSTAR) is set to ’1’ if an interrupt was
generated by any one or more of the the general purpose port pins. The GPP pin causing
the interru pt can be located by reading th e GPISL/GPISH re gisters.

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PEF 20525
Detailed Protocol Description
Preliminary Data Sheet  4-80 09.99
 4 Detailed Protocol Descr iption
The following Table 4-1 provides an overview of all supported protocol modes and . The
desired protocol mode is selected via bit fields in the channel configuration registers
CCR2L and CCR3L.
Table 4-1 Protocol Mode Overview
All modes are discuss ed in details in this chapter.
4.1 HDLC /SDLC Protocol  Modes
The HDLC controller of each serial channel (SCC) can be programmed to operate in
various modes, which are different in the treatment of the HDLC frame in receive
direction. Thus, the receive data flow and the address recognition features can be
performed  in a  very flexible way satisfying almost any application specific requirements.
There are 4 different HDLC operating modes which can be selected via register CCR2L. 
The following table provides an overview of the different address comparison
mechani sm s in HDLC  operat in g modes :
Protocol Mode Register CCR2L - Bit Field: CCR3L
MDS ADM  PPPM ESS7
HDLC Automode
(LAP D / LAP B / SDLC- NRM) 16 bit ’00’ ’1’ ’00’ ’0’
8 bit ’00’ ’0’
HDLC Address Mode 2 16 bit ’01’ ’1’
8 bit ’01’ ’0’
HDLC Address Mode 1 ’10’ ’1’
HDLC Address Mode 0 ’10’ ’0’
Signaling Syste m #7 (SS7) Operation ’10’ ’0’ ’00’ ’1’
Bit Synchronous PPP  M ode ’10’ ’0’ ’11’ ’0’
Octet Synchron ous PPP Mode ’01’
Extended Transparent Mode1)
1) Ext ended tra nsparent mode is a fully bit-transparent tr ansmission/reception mode.
’11’ ’1’ ’00’ ’0’

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Detailed Protocol Description
Preliminary Data Sheet  4-81 09.99
 
4.1.0.1 Automode
Characteristics: Window size 1, random message length, address recognition.
The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, I-field data of the frames and an additional status byte
are tempo rar ily stored in the SCC receive FIFO.
Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte
address reco gnition. 
If a 2-byte address field is selected, the high address byte is compared with the fixed
value F EH or FCH (group address) as well as with two  individually programmable values
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high
byte address will be interpreted as COMMAND/RESPONSE  bit (C/R), depending on the
setting of the CRI bit in RAH1, a nd will be excluded  from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the SCC can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through  the address combination RAH1/RAL1 will be pr ocessed in
the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match  any of the address combinat io ns,  are ignored by the SCC.
T able 4-2 Address Comparison Overview
Mode A ddr ess 
Field Recognized Address Bytes for a Match:
High Address Byte Low Address Byte
Address 
Mode 2
-
Auto 
Mode
16 bit FEH / FCH (1111 11 C/R 02)
and
RAL1
FEH / FCH (1111 11 C/R 02)
and
RAL2
RAH1
and
RAL1
RAH2
and
RAL2
8 bit RAL1
don’t care
RAL2
don’t care
Address
Mode 1 8 b it FEH / F CH (1111 11 C/R 02)
don’t care
RAH1
don’t care
RAH2
don’t care
Address
Mode 0 None
don’t care don’t care

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Detailed Protocol Description

Preliminary Data Sheet 4-82 09.99

In the case of a 1-byte address, only RAL1 and RAL2 will be used as comparison values.

According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as

COMMA ND and the value in RAL2 as RESPONSE.

The address bytes can be masked to allow selective broadcast frame recognition. For

further information see "Receive Address Handling" on page 4-85.

4.1.0.2 Address Mode 2

Characteristics: address recogni tion, arbitrary wi ndow siz e.

All frames with valid addresses (address recognition identical to auto-mode) are

forwarded direct ly to the RFIFO.

The HDLC contr ol fi eld, I-fie ld data and an addi tional st atus byt e ar e t em porar ily s tored

in the SCC rec eive FIFO.

In address mode 2, all frames with a valid address are treated sim ilarly.

The address bytes can be mas ked to allow select ive broad cast frame recogni tion.

4.1.0.3 Address Mode 1

Characteristics: address recogni tion hig h byte.

Only the high byte of a 2-byte address field will be compared. The address byte is

compared with the fixed value FEH or FCH (group address) as well as with two

individually programmable values RAH1 and RAH2. The whole frame excluding the first

address byte will be stored in the SCC receive FIFO.

The address bytes can be mas ked to allow select ive broad cast frame recogni tion.

4.1.0.4 Address Mode 0

Characteristics: no address recog nitio

No address recognition is performed and each complete frame will be stored in the SCC

receive FIFO.

4.1.1 HDLC Receive Data Processing

The following figures give an overview about the management of the received frames in

the different HDLC operating modes. The graphics show the actual HDLC frame and

how PASSAT interprets the incoming octets. Below that it is shown which octets are

stored in the RFIFO and will thus be transferred into memor y.

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Detailed Protocol Description

Preliminary Data Sheet 4-83 09.99

Figure 4-1 HDLC Receive Data Processing in 16 bit Automode

Figure 4-2 HDLC Receive Data Processing in 8 bit Automode

Figure 4-3 HDLC Receive Data Processing in Address Mode 2 (16 bit)

CRC16

FLAGFLAG (high) (low)

16 bit ADDR

CTRL I-field (data)

/32

to RFIFO

RAH1,2 RAL1,2

option 1) option 2)

RSTA

registers

involved (address

compare)

Automode

16 bit

CRC16

FLAGFLAG (low)

8 bit

ADDR

CTRL I-field (data)

/32

to RFIFO

RAL1,2

opt. 1) option 2)

RSTA

registers

involved (address

compare)

Automode

8 bit

CRC16

FLAGFLAG (high) (low)

16 bit ADDR

data

/32

to RFIFO

RAH1,2 RAL1,2

option 1) option 2)

RSTA

registers

involved (address

compare)

Address Mode 2

16 bit

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Detailed Protocol Description

Preliminary Data Sheet 4-84 09.99

Figure 4-4 HDLC Recei ve Data Processing in Address Mode 2 (8 bit)

Figure 4-5 HDLC Recei ve Data Processing in Address Mode 1

Figure 4-6 HDLC Recei ve Data Processing in Address Mode 0

option 1)

The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can

optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H)

option 2)

The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in

CRC16

FLAGFLAG (low)

8 bit

ADDR

data

/32

to RFIFO

RAL1,2

opt. 1) option 2)

RSTA

registers

involved (address

compare)

Address Mode 2

8 bit

CRC16

FLAGFLAG

8 bit

ADDR

data

/32

to RFIFO

RAH1,2

opt. 1) option 2)

RSTA

registers

involved (address

compare)

Address Mode 1

16 bit ADDR

CRC16

FLAG

FLAG data

/32

to RFIFO option 2)

RSTA

registers

involved

Address Mode 0

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Detailed Protocol Description
Preliminary Data Sheet  4-85 09.99
 
4.1.2 Receive Address Handling 
T he Receive Addr ess Low/ High  Bytes ( reg isters RAL1/RAH1 and  RAL2/RAH2) can be
masked on a per bit basis by setting the corresponding bits in the mask registers
AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address
recognition. Masked bit positions always match in comparison of the received frame
address with the respect iv e addres s field s in the Rece ive Address Low /H igh  registers.
This feature is applicable to all HDLC protocol modes with address recognition (auto
mode , address mode 2 and  addre ss mode 1). It is disabled if all bits of mask bit fields
AMRAL1/AMRAH1 and AMRAL2/AMRAH2 are set to ‘zero’ (which is the reset value).
Detect ion of the fixed gr oup addr ess FEH or FCH, if applicable to the selected operating
mode, rem ains unchanged.
As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit
addre ss f ield of  re ceived f rames can be p ushed t o t he r ecei ve data buffer (first on e/two
bytes of the frame). This function is especially useful in conjunction with the extended
broadcast address recognition. It is enabled by setting control bit ’RADD’ in register
CCR3H.
4.1.3 HDLC Transmit Data Processing 
T wo different  types of frames can be transmit ted:
– I-frames and
– transparent frame s
as shown below.

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Detailed Protocol Description

Preliminary Data Sheet 4-86 09.99

Figure 4-7 SCC Transmi t Data Flow (HDLC Modes)

For transmission of I-frames (selected via transm it command ’ XIF’ in register CMDRL),

the address and control f ields are genera ted a uton omo usl y by the SC C and the data in

the correspo ndi ng t rans mit data buffer is ent ered into the i nf ormat ion fiel d of the frame .

This is possible only if the SCC is operated in Automode.

For (address-) transparent frames, the address and the control fields have to be entered

in the transmit data buffer by software. This is possible in all operating modes and used

also in auto-mode for sending U-fram es .

If bit ’XCRC’ in register CCR2H is set, the CRC checksum will not be generated

internally. The c hecksum has t o be pr ovi ded via t he t rans mit data buffer as t he l ast two

or four bytes by software. The transmitted frame will be closed automatically only with a

(closing) flag.

CRC16

FLAG

8 bit

ADDR

data

/32

XFIFO

XAD1

option 2)

registers

involved

Frames with automatic 8 or 16 bit Address and Control Byte Generation

(Automode):

option 2)

Generation o f the 16 or 32 bit CRC fi eld can optionall y be disabled by setti ng bit 'XCRC' in

bytes of the transmit FIFO, to immediately proceed closing f lag.

16 bitADDR

XAD2

CRC16

FLAGFLAG data

/32

XFIFO option 2)

Frames w ithout automatic Address and C ont rol Byte Generation

(Address Mode 2/1/0):

CTRL

internally

generated

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-87 09.99

Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,

to be transm itt ed make s sense according the HDLC prot ocol or not .

4.1.4 Shared Flags

If the ‘Shared Flag’ feature is enabled by setting bit ’SFLG’ in register CCR1L the closing

flag of a previously transmitted frame simultaneously becomes the opening flag of the

follo wing frame if there is one already avai lable in the SCC transmit FIFO.

In receive direction the SCC always expects and handles ’Shared Flags’. ’Shared

Z eroes ’ of consecuti ve flags are also supp orted.

4.1.5 One Bit Insertion

Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC

protocol, the SCC offers a feature of inserting/deleting a ’one’ after seve n consecutive

‘zeros’ into the transmit/receive data stream, if the serial channel is operating in bus

configuration mode. This method is useful if clock recovery is performed by DPLL.

Since only NRZ data encoding is supported in a bus configuration, there are possibly

long sequences without edges in the receive data stream in case of successive ‘0’s

received, and the DPLL may lose synchr onizat ion .

Enabling the one bit insertion feature by setting bit ’OIN’ in register CCR2H, it is

guaranteed that at least after

– 5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and after

– 7 consecutive ‘0’s a ‘1’ will appear (one insertion)

and thus a correct function of the DPLL is ensured.

Note: As with the bit stuff ing , the ‘one insertion’ is fully tr ansparent t o the user, but it is

not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary

systems using circuits that also implement this function, such as the PEB 20542

and PEB 20532.

4.1.6 Pream ble Transmission

If ena bled via bit ’EPT’ i n regist er CCR2H, a program mable 8-bi t pattern is transmitt ed

wit h a selectable numb er o f repet i tions a fter Interfr ame Timef ill transm i ssi on is stopped

and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed

in reg ister PREAMB and the repetition time in bit field ’PRE’ of register CCR2H.

Note: Ze ro Bit I nsertion is disabled during preamble transm i ssi on.

4.1 .7 CRC Generatio n and C hecki ng

In HDLC/SDLC mode , error protection is do ne by CRC generation and checking.

PEB 20525
PEF 20525
Detailed Protocol Description
Preliminary Data Sheet  4-88 09.99
 
In standard applications, CRC- CCITT algorithm is used. The Frame Check Sequence  at
the end of each frame consists of two bytes of CRC che cksum .
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via bit ’C32’ in register CCR1L. In this case the Frame Check Sequence
consists of four bytes.
Optionally the internal handling of received and transmitted CRC checksum can be
influenced via control bits ’RCRC’, ’DRCRC’ in register CCR3H a nd ’XCRC’  in register
CCR2H.
Receive direction:
If n o t disable d  b y  setting b it ’D RCRC’ (re g is te r  CCR3H), the  re c e iv e d  CRC c h ecksum  is
always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame,
immediately preceding a closing flag. If bit ’RCRC’ is set, the received CRC ch ecksum
is treated as data and will be forwarded to the RFIFO, where it precedes the frame status
byte. Nevertheless the r eceived CRC checksum is additionally checked for correctness.
If C RC che cki ng is disable d w i t h bit  CCR3H:D RCRC,  t he limits for  ‘ Val id  Fr am e’  check
are modified accordingly (refer to description of the Receive Status Byte, RSTA:VFR).
Transmit direction:
If bi t ’XCRC’ is set,  the CRC checksum is not generated  internally. The checksum  has  to
be provided via the transmit data buffer by software. The transmitted frame  will only be
closed automatically with a (closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transmitted makes sense or not according the HDLC protocol.
4.1.8 Receive Length Check Feature
The SCC offers the possibility to supervise the maximum length of received frames and
to terminate data reception in the case that this length is exceeded.
This feature is controlled via the special Receive Length Check Registers RLCRL/
RLCRH.
The function is enabled by setting bit ’RCE’ (Receive Length Check Enable) and the
maximum frame length to be checked is programmed via bit field ’RL’. The maximum
receive length can be determined as a multiple of 32-byte blocks as follows:
MAX_LENGTH = (RL + 1)  × 32 ,
where RL is the value written to bit field ’RL’. Thus, the maximum length of receive
frames can be program me d between 32 and 65536 bytes.
All frames  exceeding  this length are tre ated as if  they had been a borted b y the remote
station, i.e. the CPU is informed via
– an ’RME’ interrupt generated by the SCC, and
– t he rece ive  abort indication  ’RAB’ in the Receive Status Byte (RSTA).

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-89 09.99

Additionally an optional ’FLEX’ interrupt is generated prior to ’RME’, indicating that the

max imum receive fram e length was exceeded.

Rec eive operati on cont inues wit h the beginning of the next receive fram e.

4.2 Point-to-Point Protocol (PPP) Mo des

PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC,

synchronous HDLC, and octet synchronous. The PASSAT supports bit and octet

synchronous HDLC PPP for use over dial-up connections. The octet synchronous mode

of PPP protocol (RFC 1662) supports PPP over SONET applications.

The synchronous HDLC PPP modes are submodes of the HDLC mode. The appropriate

PPP mode is selected via bit field ’PPPM’ in register CCR2L.

The PPP-support hardware allows soft ware to perform segmentation and reassembly of

PPP payloads, and allows PASSAT to perform the synchronous HDLC PPP protocol

conver si ons as requ ired for the network interf ace.

4.2.1 Bit Synchronous PPP

The PASSAT transmits a data block, inserts HDLC Header (Opening Flag), and appends

the HD LC Trailer (CRC, Endi ng Flag). Zero-bit stuffing algor ithm is also performed. No

character mapping is performed. The bit-synchronous PPP mode differs from the HDLC

mode (address mode 0) only in the abort sequence:

HDLC requires at least 7 consecutive ’1’ bits as abort sequence, whereas PPP requires

at least 15 ’1’ bits.

For r eceive operation PASSAT monitors the incoming data stream for the Opening Flag

(7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data

and are pro cesse d as normal HDLC packet including checking of CRC.

4.2.2 Octet Syn chronous PPP

The PASSAT transmits a data block, inserts HDLC Header (Opening Flag), and appends

the HDLC Trailer (CRC, Ending Flag). Beside this standard HDLC operation, zero-bit

stuff ing is not performed, but chara cter map ping is performed .

For r eceive operation PASSAT monitors the i ncoming data stream for the Opening Flag

(7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data

and are processed as normal HDLC packet including checking of CRC. Received

mapped characters are unmapped.

4.2.3 Data Transparency in PPP Mode

When transporting bit-files (as opposed to text files), or compressed files, the characters

could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-90 09.99

MODEM would not pass through. PASSAT m aintains an Async Control Charac ter Map

(ACCM) for characters 00-1F Hex. Whene ver there is a mappe d character in the data

stream, the tra nsm itte r pr ecedes that character wit h a cont ro l-escape char act er of 7DH.

After the cont rol-e scape, t he character i tself is transmitted wi th bit 5 inverted. char act er

e.g. 13H is mapped to 7DH, 33 H).

At the rece ive end, a 7DH character is discarded and the following character is modified

by inverting bit 5 (e.g. if 7DH, 33H is received, the 7DH is discarded and the 33H is

changed to 13H the original character).

The 32 lookup octet values (00H-1FH) are stored within the on-chip registers ACCM0..3.

In addition to the ACCM, 4 user programmable characters (especially outside the range

00-1F Hex) c an also be mapped using the control-escape seq uence described above.

These characters are specified in registers UDAC0..3.

The receiver disca rds all char acters which are rec eiv ed unmapped, but expected to be

mapped becau se of ACCM0..3 and UDAC0..3 register content s. If this occurs within an

HDLC frame , the u nexpected char act ers are dis card ed bef or e forwar ded t o t he r ecei ve

CRC checking unit.

7DH (control-escape) and 7EH (flag) octets in the data stream are mapped in general.

The sequence of mappi ng cont rol logic is:

1. 7DH and 7EH octets,

2. ACCM0..3,

3. UDAC0..3.

This mechanism is applied to octet synchronous HDLC PPP mode.

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-91 09.99

•

Figure 4-8 PPP Ma pping/Unmapping Example

A CCM0 . .3: A s

nc Control Character M ap Re

ister

...

UDAC0..3: User Defined As

nc C ontrol Chara cter M ap R e

ister

7Eh 7Eh 7Eh

20h

13H20H01H02H

d a ta in

transmit

FIFO:

HDLC

framing: 13H20H01H02H

7EH7EH

33H00H01H02H

7EH7DH7DH7EH

PPP

mapping:

33H00H01H02H

7EH7DH7DH7EH

received

character:

13H20H01H02H

7EH7EH

PPP

unmapping

13H20H01H02H

d a ta in

receive

FIFO:

serial

line

Note: CRC

eneration/checkin

is assum ed to be disabled in this exam ple; accordin

the PPP m appin

unmappin

, C R C ch aracters are treated as 'd ata' charac te rs bein

m a pped/unmapp ed if neces sar

UDAC1 UDAC0

UDAC3 UDAC2 70070707

ACCM1 ACCM0ACCM3 ACCM2

070707

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-92 09.99

4.3 Extended Transparent Mode

Characteristics: full y transpar ent

When programmed in the extended transparent mode via the CCR2L register (bits

MDS1, MDS0, ADM = ‘111’), the SCC performs fully transparent data transmission and

reception without HDLC fram in g, i.e. without

• FLAG ins ertion and deleti on

• CRC generation and checking

• bit stuf fing.

This feature can be profitably used e.g. for:

• use r specif ic protocol vari ations

• line state monitoring, or

• test purposes, in particular for monitoring or intentionally generating HDLC protocol

rule violations (e.g. wrong CRC)

Character or octet boundary synchronization can be achieved by using clock mode 5 or

clock mode 1 with an extern al receive strobe input to pin CD.

Setting invokes this ou t-of-band flow control for the receiver. When the shadow part of

the receive FIFO has reached a set threshold of 28 byt es, the signal is forced inac tive

(high). When the shadow part of the receive FIFO is empty, the is re-asserted (low).

Note that the data is i mmedi ately transf erred from the sh adow receiv e FIFO to the us er

accessible RFIFO (as long as there is space available). So when the shadow receive

FIFO reaches the 28 bytes threshold, there is 4 more byte storage available before

overflow can occur. This allows suf ficient time f or t he far end tra nsm itte r to r eact to t he

change in the signal and stop sending more data.

A transmit data underrun condition in the XFIFO is indicated with an ’XDU’ interrupt.

Nevertheless, transmission continues inserting SYN characters into the data stream until

new data i s available in t he transm it FIFO. Inserte d SYN characters are not par t of the

fra me a nd th u s not used fo r CRC calc u la tion.

4.4 Procedural Support (Layer-2 Functions)

When operating i n t he auto m ode, t he SCC offers a high degr ee of protocol support. In

addition to address recognition, the SCC autonomously processes all (numbered) S- and

I-frames (window size 1 only) with either normal or extended control field format

(modulo-8 or modulo-128 sequence numbers – selectable via register CCR2H bit

’MCS’).

The following functio ns will be performe d:

– updating of transmit and receive counter

– evaluation of trans mit and receive count er

– processing of S commands

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-93 09.99

– flow control with RR/RNR

– generation of responses

– recognition of protocol errors

– transmission of S comman ds, if ackn ow ledgeme nt is not received

– continuous status query of remote station after RNR has been received

– programmable timer/repeater functions.

In ad dition, all unn umbered frame s are forward ed directly to the pr ocessor. The l ogical

link c an be initiali zed by software at any ti me (Reset HDLC Receiver by RRES command

in reg ister CMDRH).

Additional logical connections can be operated in parallel by software.

4.4.1 Full-Duplex LAPB/LAPD Operation

Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured

to function as a combined (primary/secondary) station, where they autonomously

perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol.

Reception of Frames:

The logical processing of received S-frames is performed by the SCC without

interrupting the host. The host is merely informed by interrupt of status changes in the

remote station (receiver ready / receiver not ready) and protocol errors (unacceptable

N(R), or S-frame with I-field).

I-frames are also processed autonomously and checked for protocol errors. The I-frame

will not be accepted in the case of sequence errors (no inter rupt is forwarded to t he host),

but is im med iatel y confi rmed by an S-response. If the host set s the SC C into a ‘re ceive

not ready’ status, an I-fr ame will not be accepted (no int errupt) and an RNR response is

transmitted. U-frames are always stored in the RFIFO and forwarded directly to the host.

T he logi cal sequence and the r ecept io n of a frame i n auto m ode i s ill ustrated in Figure

4-9.

Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the

SCC checks only the least significant bit of the receive and transmit counter

regar dless of the sele cted modulo count .

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-94 09.99

Figure 4-9 Processing of Received Fram es in Auto Mode

ITD00230

Command

with p=1

Ready

Rec. N

f=p

Trm RR

ActivRec.

Set RRNR

Response

PCE

Int :

Response

Trm RNR

f=p

Overflow

Data

:Int RME

Set RDO

Response

Trm RR

f=p

RMEInt:

N(S) (R)+1

Rec. Ready :Int RME

Set RDO

Data

Overflow

ALLSInt :

Acknowledge

RESET Wait for

(S)=Y

=VN(R) (S)+1

Acknowledge

Wait for

:Int XMR

RESET Wait for

Acknowledge

RESET Wait for

ALLSInt :

Response

f=1

(S)+1N(R)=V

Wait for

Acknowledge

CRC Error

Set CRCE

Set RAB

Aborted

U Frame

YProt. Error

PCEInt:

:Int RME

Set CRCE N

CRC Error

Set RAB

Aborted

I Frame

YProt. Error

or Abort

CRC Err or

RNR

RESET RRNR

YCRC Error

or Abort

Prot . Error

:Int PCE

SREJREJRR,

(R)+1(R)=VV

V(S)

(S) +1 Y

ALLS:Int

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-95 09.99

T ransmis sion of Frames:

The SCC autonomously transmits S commands and S responses in the auto mode.

Either transparent or I-frames can be transmitted by the user. The software timer has to

be operated in the internal timer mode to transmit I-frames. After the frame has been

transmitted, the timer is self-started, the XFIFO is inhibited, and the SCC waits for the

arrival of a positive acknowledgement. This acknowledgement can be provided by

mean s of an S- or I-frame.

If no positive acknowledgement is received during time t1, the SCC transmits an S-

command (p = ‘1’), which must be answered by an S-response (f = ‘1’). If the S-response

is not received, the process is performed n1 times (in HDLC known as N2, refer to

Upon the arrival of an acknowledgement or after the completion of this poll procedure

the XFIFO is enabled and an interrupt is generated. Interrupts may be triggered by the

following:

• message has been positively acknowledged (ALLS interrupt)

• message must be repeated (XMR interrupt)

• response has not been received (TIN interrupt).

In automode, only when the ALLS interrupt has been issued data of a new frame may

be provided to the XFIFO!

Upon arri v al o f an RNR frame , the s o ftware t imer i s start e d a nd the status o f the re mo te

station is polled periodically after expiration of t1, until the status ‘receive ready’ has been

detected. The user is informed via the appropriate interrupt. If no response is received

after n1 times, a TIN interrupt, and t1 clock periods thereafter an ALLS interrupt is

generated and the process is terminated.

Note: Th e internal timer mode shoul d onl y be used in the auto mode.

T ransp aren t frames can be transm itted in all operating modes.

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-96 09.99

Figure 4-10 Timer Procedure/Poll Cycle

ITD00231

Wait fo r

Acknowledge

Set

with f=1

Response

Wait for

Acknowledge

RRNR

Y Y

(R) (S)+1VN

1tLoad

Rec.RNRRec.RRIRec. Frame

T Proc.Activ

TINInt:

Load t1

Ready

Rec. N

Command p=1

Trm RR

Trm RNR

Command p=1

n1 n1-1=

n1= 7

n1= 0

Run Out

1 2

Load t1

Trm RR/RNR

CMDR ; STI

Command p=1

Trm I Frame

Acknowledge

Set wait for

InactivT Proc. 1

RNR

Set RRNR

Rec.

Load n1

11.06.1996 B/R

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-97 09.99

Examples

The interaction between SCC and the host during transmission and reception of I-frames

is il lustrated in the foll owing two figures. The flow control with RR/ RNR of I- frames during

transmission/reception is illustrated in Fi gure 4-11. Both, the sequence of the poll cycle

and protocol errors are show n in Figure 4-12.

F igure 4-11 Transm ission/R eception of I-Frames and Flow Control

Figure 4-12 Flow Control: Reception of S-Commands and Protocol Er rors

RME

WFA

Transmit with

FrameI

Confirm I Frame

ALLS

ALLS WFA

Reception FrameI

Transmit FrameI

RR(1)

(0.0)

RR(1)

I(0.1)

(1.1)

(1.2)

RR(2)

RR(0)f=1

RNR

RSC

(RNR)

RSC

(RR)

XMR

WFA

t1 RR(0)p=1

RNR(0)f=1

RNR(0)

I(0.0)

RR(0)p=1

ALLS

WFA = Wait For Acknowledge (see Status Register)

RNR

RME

XRNR

RNR(0)

(0.0)

RR(0)p=1

RR(0)f=1

RR(0)p=1

RR(0)f=1

I(0.0)

RR(1)

RRp=1

Poll Cycle

Protocol Erro r

RR(0)p=1

RR(1)

RR(2)

ALLS

PCE

TIN

WFA

ALLS

RR(0)

WFA

RRp=1

(0.0)

WFA = Wait For Acknowledge (see Status Register)

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-98 09.99

Protocol Error Handling:

Depending on the error type, erroneous frames are handled according to Table 4-3.

Note: The s tation variabl es ( V(S), V(R) ) are not changed.

4.4.2 Half-Dup lex SD LC-NR M Opera tion

The LAP controllers of the two serial channels can be configured to function in a half-

duplex Normal Response Mode (NRM), where they operate as a slave (secondary)

station, by setting the NRM bit in the CCR2L register of the correspondi ng channel.

In contrast to the full-duplex LAP B/LAP D operation, where the combined

(primary + secondary) station transmits both commands and responses and may

transmi t data at an y time, the NRM mode al lows only r esponses t o be transm itted and

the secondary station may transmit only when instructed to do so by the master (primary)

station. The SCC gets the permission to transmit from the primary station via an S- , or I-

frame with the poll bit (p) set.

The NRM mode can be profitably used in a poin t-to-multipoint configuratio n with a fixed

master-slave relationship, which guarantees the absence of collisions on the common

transmit line. It is the responsibility of the master station to poll the slaves periodically

and to handle error situation s.

Prerequisite for NRM oper ation is:

– aut o mo de with 8-bit address field sel ected

Regist er CCR2L bit fields ’MDS1’, ’MDS0’, ’ADM’ = ‘000’

– Register TIMR3 bit ’ TMD’ = ‘0 ’

– sam e transm i t and recei ve addre sses, since only respons es can be transm itt ed, i.e.

Regist er XAD1 = XAD2 and register RAL1 = RAL2 (address of secondar y).

Table 4-3 Error Handling

Frame Type Error Type G enerated

Response Generated

Interrupt Rec. Status

I CRC erro r

Aborted

Unexpected N(S)

Unexpected N(R)

–

S-frame

–

RME

–

PCE

CRC erro r

Abort

–

S CRC erro r

Aborted

Unexpected N(R)

With I-field

–

PCE

–

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-99 09.99

Note: The broadcast address may be programmed in register RAL2 if broadcasting is

required.

In this case register s RAL1 and RAL2 are not equal.

T he primary st ation has to operate in transp arent HDL C mode.

Reception of Frames:

The reception of frames functions similarly to the LAPB/LAPD operation (see "Full-

Duplex LAPB/LAPD Operation" on page 4-93).

T ransmi ssion of Frame s:

The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station

via an S-, or I-frame with the poll bit set.

T he SCC can be to ld to send an I- frame i ssuing the t ra nsm it command ’ XIF’ in r egi ster

CMDRL. The transmission of the frame, however, will not be initiated by the SCC until

recep tion of either an

• RR, or

• I-frame

with pol l bi t set (p = ‘1’).

After the frame has been transmitted (with the final bit set), the host has to wait for an

ALLS or XMR interrupt.

A secondary does not poll the primary for acknowledgements, thus timer supervision

mus t be done by the primary station.

Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an

interrupt is forwarded to the host, either the

– message has been positively acknowledged (ALLS interrupt), or the

– message must be repeated (XMR interrupt).

Additionally, the on-chip timer can be used under host control to provide timer recovery

of the secondar y if no acknowl edgem ent s are recei ved at all.

Note: A secondary will transmit transparent frames only if the permission to send is

given by receiving an S-frame or I-frame with poll bit set (p = ‘1’).

Examples:

A few examples of SCC/host interaction in the case of normal response mode (NRM)

mode are shown in Figure 4-13 and Figure 4-14.

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-100 09.99

Figure 4-13 No Data to Send: Data Reception/Transmission

Figure 4-14 Dat a Transmi ssio n (without error), Data Transmission (with error)

4.4.3 Signaling System #7 (SS7) Operation

The PASSAT supports the signaling syst em #7 ( SS7) which i s described in ITU-Q .703 .

SS7 support must be activated by setting bit ’ESS7’ in register CCR3L.

RR(0)f=1

RR(0)p=1

Secondary Primary

ITD01800

(0,1)f=1

(0,0 )p = 1

ITD00237

(1,1 )p = 1

RR(2)f=1

ALLS

RME

XIF I

(0,0)f=1

RR(0)p=1

ITD00238

RR(1)p=0

ALLS

XIF

I (0,0)f=1

RR(0)p=1

ITD01801

RR(0)p=1

XMR

XIF

RR(0)f=1

PEB 20525
PEF 20525
Detailed Protocol Description
Preliminary Data Sheet  4-101 09.99
 
Receive
The SS7 protocol is supported by the following hardware features in receive direction:
• Recogni tion  of Signaling Unit type
• Discard of repeatedly received FISUs and LSSUs if content is unchanged (optional)
• Check if the length of the received signaling unit is at least six octets (including the
opening flag)
• Check if the signal information field of a received signaling unit consists of more than
272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current
signaling unit will be aborted.
• Counting and processing of errored signaling units
In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed
automaticall y. By examinin g the length indicato r of a received Signal Unit (SU) PASSAT
decides whether a FISU has been received. Consecutively received FISUs will be
compared and optionally not stored in the RFIFO, if the content is equal to the previous
one. The same applies to Link Status Signaling Units (LSSUs), if enabled with bit
CCR3L.CSF. The different types of Signaling Units as Messag e Signaling Unit (MSU),
Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated in the
RSTA byte (bit f ield ’SU’), which is automatically added to the RFIFO  with each received
Signaling Unit. The complete Signaling Unit exce pt start and end flags  is stored in the
receive FI FO. The functions of bi ts CCR3H.RCRC and CCR3H.RADD are also  v alid in
SS7 mode, with bit ’RADD’ related to BSN (backward sequence number) and FSN
(forward sequence number).
Errored signaling units are counted and processed according to ITU-T Q.703. The SU
counter and errored-SU counter are reset by setting CMDRH.RSUC to ’1’. The error
threshol d can  be sel ected t o be 6 4 (default) or  32 by  cl ear ing /se tting bi t  CCR3L.SUET.
If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not
mas ked by bit IMR1.SUEX.
Transmit
In transmi t direction,  following featur es are supp orted:
• single or repetitive transm issi on of signali ng units
• autom atic generation of  Fill-In Signaling Units (FISU)
Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or
repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been
transmitted completely, PASSAT optionally starts sending of Fill In Signaling Units
(FISUs) containing the forward sequence number (FSN) and the backward sequence
numb er (BSN)  of the previously transm i tted signal ing unit. Setting bit CCR3L.AFX to ’1’
causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from
XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has
been initiated, the current FISU is completed and the new SU is sent. After this,

PEB 20525

PEF 20525

Detailed Protocol Description

Preliminary Data Sheet 4-102 09.99

transmission of FISUs continues. The internally generated FISUs contain FSN and BSN

of the last transm i tted signaling uni t written to XFIFO.

Using CMDRL.XREP=’1’, the contents of XFIFO (1..32 bytes) can be sent continuously.

This cyclic trans missi on can be stopped w ith the CMDRL.XR ES com mand.

PEB 20525
PEF 20525
Regist er Descript ion
Preliminary Data Sheet  5-103 09.99
 5 Register Description
5.1 Register Overview
The PASSAT global registers are used to configure and control the Serial
Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation.
All regist ers ar e 8-bit organized regist ers, but grouped and optimi zed for 16 bit access.
16 bit access (P-T QF P-10 0-3 package) is supported to even addresses only.
T able 5-1 provides an overvi ew about  all on-chip registers :
T able 5-1 Registe r Ov erview 
Offset
Ch A Ch B Register
read write Res
Val Meaning Page
Global registers:
00HGCMDR 00HGlobal Command Register 5-108
01HGMODE 0FHGlobal Mode Register 5-109
02H
Reserved
03HGSTAR 00HGlobal Status Register 5-112
04HGPDIRL 07HG PP D irection  Register (Lo w Byte) 5-114
05HGPDIRH FFHGPP Direct ion Regist er (High Byte) 5-114
06HGPDATL -GPP Data Register (Low Byte) 5-116
07HGPDATH -GPP D ata Regist er (High Byte) 5-116
08HGPIML 07HGPP Interrupt Mask Register (Low Byte) 5-118
09HGPIMH FFHGPP Interrupt Mask Register (High Byte) 5-118
0AHGPISL 00HGPP Interrupt Status R egi ster (Low Byte) 5-120
0BHGPISH 00HGPP Interrupt Status Regi ster (High Byte) 5-120
0CHDCMDR 00HDMA Command Register 5-122
0DH
Reserved
0EHDISR 00HDMA Interrupt Status Register 5-123
0FHDIMR 77HDMA Interrupt Mask Register 5-124
Cha nnel specific registers:
10H60HRFIFO XFIFO -Receive/Transmit FIFO (Low Byte) 5-125
11H61H-Receive/Transmi t FIFO (High Byte) 5-125

PEB 20525
PEF 20525
Regist er Descript ion
Preliminary Data Sheet  5-104 09.99
 
12H62HSTARL 00HStatus Registe r (Low Byte) 5-128
13H63HSTARH 10HStatus Register (High Byte) 5-128
14H64HCMDRL 00HCommand R egist er (Low Byte) 5-132
15H65HCMDRH 00HCo mmand R egist er (High Byte ) 5-132
16H66HCCR0L 00HChannel Configur ation Regi ste r 0 (Low 
Byte) 5-136
17H67HCCR0H 00HChannel Configur ation Regi ste r 0 (High 
Byte) 5-136
18H68HCCR1L 00HChannel Configur ation Regi ste r 1 (Low 
Byte) 5-139
19H69HCCR1H 00HChannel Configur ation Regi ste r 1 (High 
Byte) 5-139
1AH6AHCCR2L 00HChannel  Con figur ation Regi ster 2 (Low 
Byte) 5-144
1BH6BHCCR2H 00HChannel  Con figur ation Regi ster 2 (High 
Byte) 5-144
1CH6CHCCR3L 00HChannel Configur ation Regi ste r 3 (Low 
Byte) 5-149
1DH6DHCCR3H 00HChannel Configur ation Regi ste r 3 (High 
Byte) 5-149
1EH6EHPREAMB 00HPreamble Re gister 5-153
1FH6FH
Reserved
20H70HACCM0 00HPPP ASYNC Control Character Map 0 5-154
21H71HACCM1 00HPPP ASYNC Control Character Map 1 5-154
22H72HACCM2 00HPPP ASYNC Control Character Map2 5-155
23H73HACCM3 00HPPP ASYNC Control Character Map 3 5-155
24H74HUDAC0 7EHUser Defined  PPP ASYNC Control 
Character Map 0 5-157
25H75HUDAC1 7EHUser Defined  PPP ASYNC Control 
Character Map 1 5-157
26H76HUDAC2 7EHUser Defined  PPP ASYNC Control 
Character Map 2 5-158
Table 5-1 Regi st er O verview   (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page

PEB 20525
PEF 20525
Regist er Descript ion
Preliminary Data Sheet  5-105 09.99
 
27H77HUDAC3 7EHUser De fined PPP ASYNC Co ntrol 
Cha racter  Map 3 5-158
28H78HTTSA0 00HTransmit Time Slot Assignment Register 0 5-160
29H79HTTSA1 00HTransmit Time Slot Assignment Register 1 5-160
2AH7AHTTSA2 00HTransmit Time Slot Assignment Register 2 5-161
2BH7BHTTSA3 00HTransmit Time Slot Assignment Register 3 5-161
2CH7CHRTSA0 00HReceive Time Slot Assignment Register 0 5-163
2DH7DHRTSA1 00HReceive Time Slot Assignment Register 1 5-163
2EH7EHRTSA2 00HReceive Time Slot Assignment Register 2 5-164
2FH7FHRTSA3 00HReceive Time Slot Assignment Register 3 5-164
30H80HPCMTX0 00HPCM Mask Tran s mit Direc t ion Register  0 5-166
31H81HPCMTX1 00HPCM Mask Tran s mit Direc t ion Register  1 5-166
32H82HPCMTX2 00HPCM Mask Tran s mit Direc t ion Register  2 5-167
33H83HPCMTX3 00HPCM Mask Tran s mit Direc t ion Register  3 5-167
34H84HPCMRX0 00HPCM Mask Receive Direction Register 0 5-169
35H85HPCMRX1 00HPCM Mask Receive Direction Register 1 5-169
36H86HPCMRX2 00HPCM Mask Receive Direction Register 2 5-170
37H87HPCMRX3 00HPCM Mask Receive Direction Register 3 5-170
38H88HBRRL 00HBaud Rate Register (Low Byte) 5-172
39H89HBRRH 00HBaud Rate Register (High Byte) 5-172
3AH8AHTIMR0 00HTi m er Regi ste r 0 5-174
3BH8BHTIMR1 00HTi m er Regi ste r 1 5-174
3CH8CHTIMR2 00HTimer Regi ster 2 5-175
3DH8DHTIMR3 00HTimer Regi ster 3 5-175
3EH8EHXAD1 00HTransmit Address 1 Register 5-178
3FH8FHXAD2 00HTransmit Address 2 Register 5-178
40H90HRAL1 00HRec eive Address  1 Low Register 5-180
41H91HRAH1 00HReceive Address 1 High Register 5-180
42H92HRAL2 00HRec eive Address  2 Low Register 5-181
43H93HRAH2 00HReceive Address 2 High Register 5-181
T able 5-1 Register Overview  (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page

PEB 20525
PEF 20525
Regist er Descript ion
Preliminary Data Sheet  5-106 09.99
 
44H94HAMRAL1 00HMask Receive Address 1 Low Register 5-183
45H95HAMRAH1 00HMask Receive Address 1 High Register 5-183
46H95HAMRAL2 00HMask Receive Address 2 Low Register 5-184
47H96HAMRAH2 00HMask Receive Address 2 High Register 5-184
48H98HRLCRL 00HReceive Length Che ck Re gister (Low 
Byte) 5-186
49H99HRLCRH 00HReceive Length Che ck Re gister (Hig h 
Byte) 5-186
4AH9AH
...
Reserved
4FH9FH
50HA0HISR0 00HInterrupt Status Register 0 5-188
51HA1HISR1 00HInterrupt Status Register 1 5-188
52HA2HISR2 00HInterrupt Status Register 2 5-189
53HA3HReserved
54HA4HIMR0 FFHInterrupt Mask Register 0 5-194
55HA5HIMR1 FFHInterrupt Mask Register 1 5-194
56HA6HIMR2 03HInterrupt Mask Register 2 5-195
57HA7HReserved
58HA8HRSTA 00HReceive Status Byte 5-197
59HA9H
... Reserved
5FHAFH
Channel specific DMA registers:
B0HCAH
...
Reserved
B7HD1H
B8HD2HXBCL 00HTransmit Byte Count (Low Byte) 5-202
B9HD3HXBCH 00HTransmit Byte Count (High Byte) 5-202
BAHD4H
Table 5-1 Regi st er O verview   (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page

PEB 20525
PEF 20525
Regist er Descript ion
Preliminary Data Sheet  5-107 09.99
 
...
Reserved
C3HDDH
C4HDEHRMBSL 00HReceive Maximum Buffer Size (Low Byte) 5-204
C5HDFHRMBSH 00HRecei ve Ma ximu m Buf fer  Siz e (Hi gh  Byte ) 5-204
C6HE0HRBCL 00HReceive Byte Count (Low Byte) 5-206
C7HE1HRBCH 00HReceive Byte Count (High Byte) 5-206
C8HE2HReserved
C9HE3HReserved
Miscellaneous:
E4H
... Reserved
EBH
ECHVER0 03HVersion Register 0 5-208
EDHVER1 F0HVersion Register 1 5-208
EEHVER2 05HVersion Register 2 5-209
EFHVER3 10HVersion Register 3 5-209
T able 5-1 Register Overview  (cont’d)
Offset
Ch A Ch B Register
read write Res
Val Meaning Page

PEB 20525

PEF 20525

Regist er Descript ion

Preliminary Data Sheet 5-108 09.99

5.2 Detailed Register Description

5.2.1 Global Register s

Each register description is organized in three parts:

• a head with general information about reset value, access type (read/write), offset

address and usual handling;

• a table con taining the bit information (na me of bit positions) ;

• a secti on containing t he detailed descr ip tion of each bit.

Global Command Register

CPU Accessibili ty: read/write

Reset Va lu e: 00H

Offset Address: 00H

typical usage: w ritten by CPU,

evaluated by PASSAT

Bit76543210

Global Command Bits

0000000SWR

SWR Software Reset Command

Self clearing comm and bi t:

bit=’0’ No software reset command is issued.

bit=’1’ Causes PASSAT to perform a complete reset identical to

hardware reset.

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PEF 20525

Preliminary Data Sheet 5-109 09.99

Reg ister 5-2 GMODE

Global Mode Register

CPU Acc e ssibilit y : read/write

Reset Value: 0FH

Offs et Address: 01H

typical usage: written by CPU

evaluated by PASSAT

Bit76543210

DMA and Global Interrupt Control

0 EDMA IPC(1:0) OSCPD

Reserved

DSHP GIM

EDMA Enable Externa l DMA Support

This bit field controls the DMA operation mo de:

EDMA=’0’ The external DMA controller support functions are

disabled. PASSAT is operated in standard register access

controlled mode.

EDMA=’1’ External DMA controller support functions are enabled.

IPC(1:0) Interrupt-Port Configuration

These bits control the function of interrupt output pin INT/INT:

IPC(1:0) Output Function:

’00’ Ope n Drain active low

’01’ Pu sh/ Pu ll active low

’10’ Reserved.

’11’ Push/ Pu ll active high

PEB 20525

PEF 20525

Preliminary Data Sheet 5-110 09.99

OSCPD Oscillator Power Down

Setting this bit to ’0’ enables the internal oscillator. For power saving

purposes (escpecially if clock modes are used which do not need the

i nt e rn a l o scillator) this bit may re ma in set to ’1 ’.

OSCPD=’0’ The interna l oscillator is active.

OSCPD=’1’ The internal oscilla tor is in power down mode.

Note: After res et th is bit is set to ’1 ’, i.e. th e oscillato r is in power d own

mode!

Reserved

Reserved Bit

The rese t value of this bit is ’1’.

It should be set to ’0’ during configuration in any case.

Note: This bit is a redundant control bit for the shaper in the oscillator

unit. In later revisions of PASSAT the shaper will be controlled with

bit ’DSH P’ only!

DSHP Disable Shaper

This bit has to be set to ’0’ if the shaping function in the oscillator unit is

desired. The shape r amplifies the osci llator signal and improves the

slope of the clock edges.

DSHP=’0’ Shaper is enabled. Recommended setting if a crystal is

connect ed t o pins XTAL1/XTAL2.

DSHP=’1’ Shaper is disa bled (bypas sed) . Recom m ended set ting if

- a TTL level clock signal is supplied to pin XTAL1

- the oscillator unit is unused

Note: (1)

After rese t this bit is set to ’1’, i.e. the shaper is disabled!

(2)

For correct operation the reserved bit 2 must be set to ’0’ (in

later revisions the sha per will be controlled with bit ’DSHP’ only)!

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PEF 20525

Preliminary Data Sheet 5-111 09.99

GIM Global Interrupt Mas k

This bits disables all interrupt indications via pin INT/INT. Internal

operation (interrupt generation, interrupt status register update,...) is not

affected.

If s et, pin INT/INT immediately changes or remains in inactive state.

GIM=’0’ Global interrupt mask is cleared. Pin INT/INT is controlled

by the internal interrupt control logic and activated as long

as at least one unmasked interrupt indication is pending

(not yet confi rmed by read acc ess to corresponding

interr upt status reg ister ).

GIM=’1’ Global interrupt mask is set. Pin INT/I NT remains inactive.

Note: After reset this bit is set to ’1’, i.e. all i nterr upts are disabl ed!

PEB 20525

PEF 20525

Regist er Descript ion (GSTAR)

Preliminary Data Sheet 5-112 09.99

Reg ister 5-3 G STAR

Global Status Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Offs et Address: 03H

typical usage: written by PASSAT evaluated by CPU

Bit76543210

Global Interrupt Status Information

GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0

GPI General Purpose Port Indication (-)

This bit indicates, that a GPP port interrupt indication is pending:

GPI=’0’ No general purpose port interrupt indication is pending.

GPI=’1’ General purpose port interrupt indication is pending. The

source for this interrupt can be further determined by

reading reg isters GPISL/GPISH (refer to page 5-120).

DMI D MA Interrupt Indication (-)

This bit indicates, that a DMA interrupt indication is pending:

DMI=’0’ No DM A interrupt indicat ion is pending.

DMI=’1’ DMA interrupt indication is pending. The source for this

interrupt (chann el A/B, receive/tran smit ) can be further

determined by reading register DISR (ref er to page 5-

123).

PEB 20525

PEF 20525

Regist er Descript ion (GSTAR)

Preliminary Data Sheet 5-113 09.99

ISA2 Channel A Interrupt Status Register 2

ISA1 Channel A Interrupt Status Register 1

ISA0 Channel A Interrupt Status Register 0

ISB2 Channel B Interrupt Status Register 2

ISB1 Channel B Interrupt Status Register 1

ISB0 Channel B Interrupt Status Register 0

These bits indicate, that an interrupt indication is pending in the

corresponding interrupt status register(s) ISR0/ISR1/ISR2 of the serial

commu nication cont ro ller (SCC):

bit=’0’ No inte rrupt indication is pendi ng.

bit=’1’ An interrupt indicat ion is pending.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-114 09.99

Reg ister 5-4 G PDIRL

GPP Direc tion Register (Low By te)

CPU Acc e ssibilit y : read/write

Reset Value: 07H

Offs et Address: 04H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

GPP I/O Direction Control

00000

GP10DIR GP9DIR GP8DIR

Reg ister 5-5 G PDIRH

GPP Direc tion Register (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: FFH

Offs et Address: 05H

typical usage: written by CPU evaluated by PASSAT

Bit76543210

GPP I/O Direction Control

1GP6DIR 111

GP2DIR GP1DIR GP0DIR

PEB 20525

PEF 20525

Regist e r Description (GPDIRH)

Preliminary Data Sheet 5-115 09.99

GPnDIR GPP Pin n Direction Control (-)

This bit selects between input and output function of the correspondi ng

GPP pin:

bit = ’0 ’ outpu t

bit = ’1’ input (reset value)

PEB 20525

PEF 20525

Regist er Descript ion (GPDATL)

Preliminary Data Sheet 5-116 09.99

Reg ister 5-6 G PDA TL

GPP Data Register (Low Byte )

CPU Acc e ssibilit y : read/write

Reset Value: -

Offs et Address: 06H

typical usage: written by CPU(o utputs) and PASSAT(inputs),

evaluated by PASSAT(outputs) and CP U(inputs)

Bit76543210

GPP Data I/O

-----

GP10DAT GP9DAT GP8DAT

Reg ister 5-7 G PDA TH

GPP Data Register (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: -

Offs et Address: 07H

typical usage: written by CPU(o utputs) and PASSAT(inputs),

evaluated by PASSAT(outputs) and CP U(inputs)

Bit76543210

GPP Data I/O

-GP6DAT ---

GP2DAT GP1DAT GP0DAT

PEB 20525

PEF 20525

Preliminary Data Sheet 5-117 09.99

GPnDAT GPP Pin n Data I/O Value (-)

This bit indicates the value of the correspondi ng GPP pin:

bit = ’0’ If direction is input: input level is ’low’;

if dir ect io n is outp ut : out p u t level is ’low’.

bit = ’1’ If direction is input: input level is ’high’;

if direction is output: output level is ’high’.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-118 09.99

Reg ister 5-8 G PIML

GPP Interrupt Mask Regist er (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 07H

Offs et Address: 08H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

GPP Interrupt Mask Bits

00000

GP10IM GP9IM GP8IM

Reg ister 5-9 G PIMH

GPP Interrupt Mask Regist er (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: FFH

Offs et Address: 09H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

GPP Interrupt Mask Bits

1GP6IM 111

GP2IM GP1IM GP0IM

PEB 20525

PEF 20525

Preliminary Data Sheet 5-119 09.99

GPnIM GPP Pin n Interrupt Mask (-)

This bit controls the interrupt mask of the corresponding GPP pin:

bit = ’0’ Interrupt generation is enabled. An interrupt is generated

on any state transition of the corresponding port pin

(inputs).

bit = ’1 ’ Interrupt generati on is disabled (reset value).

PEB 20525

PEF 20525

Preliminary Data Sheet 5-120 09.99

Reg ister 5-1 0 G P IS L

GPP Interrupt Status Regist er (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Offs et Address: 0AH

typical usage: written by PASSAT, r ead and evaluated by CPU

Bit76543210

GPP Interrupt Status Bits

00000

GP10I GP9I GP8I

Reg ister 5-1 1 G P ISH

GPP Interrupt Status Regist er (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Offs et Address: 0BH

typical usage: written by PASSAT, r ead and evaluated by CPU

Bit76543210

GPP Interrupt Status Bits

0GP6I 000

GP2I GP1I GP0I

PEB 20525

PEF 20525

Preliminary Data Sheet 5-121 09.99

GPnI GPP Pin n Interrupt Indiction (-)

This bit indicates if an interrupt event occured on the corresponding GPP

pin:

bit = ’0 ’ No inte rrupt indication is pendi ng at this pin (no state

tra nsi tion has occu red) .

bit = ’1 ’ An interrupt indicat ion is pending (a state transitio n

occur ed). The interrupt indicati on is cleare d after read

access.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-122 09.99

Reg ister 5-1 2 D C M DR

DMA Command Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Offs et Address: 0CH

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

DMA Controller Reset C ommand Bi ts

RDTB 0 RDRB 0 RDTA 0 RDRA 0

RDTB Reset DM A Transmit Channel B

RDRB Reset DM A Recei ve C hannel B

RDTA Reset DM A Transmit Channel A

RDRA Reset DMA Receive Channel A

Self-clearing com ma nd bit.

These bits bring the external DMA supp ort logic to the r eset sta te:

bit=’0’ No reset is performed .

bit=’1’ Reset is performed.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-123 09.99

Reg ister 5-13 DISR

DMA Inter rupt Status Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Offs et Address: 0EH

typical usage: written by PASSAT, evaluated by CPU

Bit76543210

DMA Interrupt Status Register

0 RBFB RDTEB TDTEB 0 RBFA RDTEA TDTEA

RBFB Receive Buffer Full Channel B

RBFA Receive Buffer Full Channel A

If a receive buffer size is defined in registers RMBSL/RMBSH and during

reception the end of the receive buffer is reached th is interrupt is

generated indicating that the receive buffer is full. If the external DMA

controller supp ort s len gth protection for re ceive buffers itself this

interrupt is obsolete. In that case, the receiv e buffer length check can be

disabled by settin bit RMBSH:DRMBS to ’1’.

RDTEB Receive DMA Transfer End Channel B

RDTEA Receive DMA Transfer End Channel A

This bit set to ’1’ indicates that a DMA transfer of receive data is finished

and the receive data is completely mo ved to the correspon ding receive

buffer in host memory.

TDTEB Transmit DMA Transfer End Channel B

TDTEA Transmit DMA Transfer End Channel A

This bit set to ’1’ indicates that the data is completely moved from the

transmit buffer to the on-chip transmit FIFO, i.e. the transmit byte count

programmed in registers XBCL/XBCH is reached.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-124 09.99

Reg ister 5-1 4 D I MR

DMA Interrupt Mask Register

CPU Acc e ssibilit y : read/write

Reset Value: 77H

Offs et Address: 0FH

typical usage:

Bit76543210

DMA Interrupt Mask Register

0 MRBFB MRDTEB MTDTEB 0 MRBFA MRDTEA MTDTEA

MRBFB Mask Receive Buffer Full Interrupt Channel B

MRBFA Mask Receive Buffer Full Interrupt Channel A

MRDTEB Mask Receiv e DMA Transfer End Interrupt Cha nnel B

MRDTEA Mask Receiv e DMA Transfer End Interrupt Cha nnel A

MTDTEB Mask Transmit DMA Transfer End Interrupt Channel B

MTDTEA Mask Transmit DMA Transfer End Interrupt Channel A

If a bit in this interrupt mask register is set to ’1’, the corresponding

interrupt is not generated and not indica ted in the correspondi ng bit

position in the DISR register . After reset all interrupts are masked.

PEB 20525

PEF 20525

Regist er Descr iption (FIFOL)

Preliminary Data Sheet 5-125 09.99

5.2.2 Channel Specific SCC Register s

Each regist er desc ription is organized in three parts:

• a head with gene ral inf ormation about reset value, access type (read/ write), channel

specific offset addresses and usual handling;

• a table containing the bit information (name of bit positions);

• a section containing the detailed description of each bit.

Reg ister 5-15 FIFOL

Receive/Transmit FIFO (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: -

Channel A Channel B

Offs et Address: 10H60H

typical usage: XFIFO: written by CPU, evaluated by PASSAT

RFIFO: written by PASSAT, evaluated by CPU

Bit76543210

RF IFO/XF IFO Access Low Byte

FIFO(7:0)

Reg ister 5-16 FIFOH

Receive/Transmit FIFO (High Byt e)

CPU Acc e ssibilit y : read/write

Reset Value: -

Channel A Channel B

Offs et Address: 11H61H

typical usage: XFIFO: written by CPU, evaluated by PASSAT

RFIFO: written by PASSAT, evaluated by CPU

Bit76543210

RFIFO/XFIFO Access High Byte

FIFO(15:8)

PEB 20525
PEF 20525
Register Description  (FIFOH )
Preliminary Data Sheet  5-126 09.99
 
Receive FIFO (RFIFO)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
dependi ng on th e selected mic roprocessor bus width using signal  ’WIDTH ’. 
Note: Th e ’W IDTH’ signal is available for the P-TQFP-10 0-3 package only.  W it h th e P-
LFBGA-80-2 package only 8-bit accesses are supported.
The size of the accessible part of RFIFO is determined by programming the RFIFO
threshold level in bit  field CCR3H.RFTH(1:0). The threshold can be adjusted to 32 (reset
valu e), 16, 4 or 2 b yte s.
• Interrupt Co ntrolled  Data Transfer  (GMODE.EDMA=’0’)
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt (see ISR0 register). The address provided during an RFIFO read
acces s is not inc remental; it is always 10 H fo r channe l A or 60H for channel B.
RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is
reach ed. The message is not yet complete. A fix number of bytes, dependent from the
threshol d level, has to be read. 
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
The content of the RFIFO is released by issuing the “Receive Message Complete”
command (CMDRH.RMC).
• DMA Cont roll ed Data Transfer (GMODE.EDMA=’1’)
If DMA operation is enabled, the PASSAT autonomously requests data transfer by
assert ing  the DRR l ine  to the e xter nal DMA c ontr olle r. The  DRR lin e rema ins a cti ve unti l
the beginning of the last receive data byte/word transfer. For a detailed decription of the
external DMA interface operation refer to "Ext ernal DMA Controller Support" on page 3-
77.
Transmit FIFO (XFIFO)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
dependi ng on th e selected mic roproces sor bus wi dth using signal  ’WIDTH ’.
Note: Th e ’W IDTH’ signal is available for the P-TQFP-10 0-3 package only.  With th e P-
LFBGA-80-2 package only 8-bit accesses are supported.
• Interrupt Co ntrolled  Data Transfer  (GMODE.EDMA=’0’)
F ollowi ng an XPR (or an ALLS) interrupt , u p t o 32 bytes/16 w ords  of  new  tran smit  dat a
can be written into the XFIFO. Transmit data can be released for transmission with an
XTF  command. The address provided during  an XFIFO write access is not incremental;
it is always 10H for channel A or 60H for channel B.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-127 09.99

• DMA Cont roll ed Data Transfer (GMODE.EDMA=’1’)

If DMA operation is enabled, the PASSAT au tonomously requests data tr ansfer to the

XFIFO by as serti ng the DR T l ine to t he externa l D MA controll er. The DRT li ne r em ai ns

active until the beginning of the last transmit data byte/word transfer. For a detailed

decription of the external DMA interface operation refer to "External DMA Controller

Support" on page 3-77.

PEB 20525

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Preliminary Data Sheet 5-128 09.99

Reg ister 5-17 STARL

Status Register (Low Byte)

CPU Acc e ssibilit y : read only

Reset Value: 00H

Channel A Channel B

Offs et Address: 12H62H

typical usage: updated by PASSAT

read and evaluat ed by C PU

Bit76543210

Command Status Transmitter Status

XREPE 0 0CEC 0 XDOV XFW CTS

Reg ister 5-18 STARH

Status Register (High Byte)

CPU Acc e ssibilit y : read only

Reset Value: 10H

Channel A Channel B

Offs et Address: 13H63H

typical usage: updated by PASSAT

read and evaluat ed by C PU

Bit76543210

Receiver Status Automode Status

0 0 CD RLI DPLA WFA XRNR RRNR

PEB 20525

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Preliminary Data Sheet 5-129 09.99

XREPE Transmit Repetition Execut ing

XREPE=’0’ No t rans mit repetition command is in execution.

XREPE=’1’ A XREP command (regis ter CMDRL) is cu rrently in

execution.

CEC Comm and Executing

CEC=’0’ No com m and is currently in execut ion. The comman d

regist ers CMDRL/CMDRH can be written by CPU.

CEC=’1’ A com m and (wr itten previousl y to registers CMDRL/

CMDRH) is currently in execution. No further command

can be written to register s CMDRL/CMDRH by CPU.

Note: CEC will be active at most 2.5 receive or transmit clock cycles

(depending on whether a receiver or transmitter related command

is executed).

CEC will stay active if the SCC is in power-down mode or if no

serial clock, needed for comm and exec ution, is available.

XDOV Transmit FIFO Data Overflow

XDOV=’0’ Less than or equal to 32 bytes have been written to the

XFIFO.

XDOV=’1’ More than 32 bytes have been written to the XFIFO. This

bit is reset by:

– a transmitter reset command ’XRES’

– or when all bytes in the accessible half of the XFIFO

have been moved into the inaccess ible hal f.

XFW Transmit FIFO Write Enable

XFW=’0’ The XFIFO is not able to accept further transmit data.

XFW=’1’ Tr ansm i t data can be written to the XFIFO.

PEB 20525

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Preliminary Data Sheet 5-130 09.99

CTS CTS (Clear To Send) Input Signal State

CTS=’0’ CTS input signal is inactive (high level)

CTS=’1’ CTS input signal is active (low level)

Note: A transmit clock must be provided in order to detect the signal

state of the CTS input pin.

Optionally this input can be programm ed to generate an interrupt

on signal level changes.

CD CD (Car rier Detect) Input Sig nal State

CD=’0’ CD input signal is low.

CD=’1’ CD input signal is high.

Note: A receive clock must be provided in order to detect the signal state

of the CD input pin.

Optionally this input can be programm ed to generate an interrupt

on signal level changes.

RLI Receive Line Inactive

This bit indicates that neither flags as interfram e time fill nor data are

being received via the receive line.

RLI=’0’ Rec eive line is active, no constant high leve l is detected.

RLI=’1’ Rec eive line is inactive, i.e. more than 7 conse cutive ’1’

are detect ed on the line.

Note: A receive clock must be provided in order to detect the receive line

state.

DPLA DPLL Asynchronous

This bit is only valid if the receive clock is recover ed by the DPLL and

FM0, FM1 or Manchester data encodi ng is selected. It is set when the

DPLL has los t synch ronizat i on. In this case rec eption is disa ble d

(receive abort condition) until synchronization has been regained. In

addition transmi ssi on is interrupte d in all cases where transm it clo ck is

derived from the DPLL (clock mode 3a, 7a). Interruption of transmission

is performed the same way as on deactivation of the CTS signal .

DPLA=’0’ DPLL is synchronized.

DPLA=’1’ DPLL is asynchrono us (re -syn chronization pro cess i s

started automatically).

PEB 20525

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Preliminary Data Sheet 5-131 09.99

WFA Wait For Acknowledgement

This status bit is significant in Automode only. It indicates whether the

Automode state machine expects an acknowledging I- or S-Frame for a

previously sent I-Frame.

WFA=’0’ No acknowle dge I/S-Frame is expected.

WFA=’1’ The Automode state machine is waiting for an

achnow ledgi ng S- or I-Frame.

XRNR Transmit RNR Status

This status bit is significant in Automode only. It indicates the receiv er

status of the local station (SCC).

XRNR=’0’ The receiver is ready and will autom aticall y answer poll -

frames with a S-Frame with ’receiv er-ready ’ indication.

XRNR=’1’ The receiver is NOT ready and will automat ica lly answer

poll-frames with a S-Frame with a ’receiver-not-ready’

indication.

RRNR Received RNR (Receiver Not Ready ) Status

This status bit is significant in Automode only. It indicates the receiv er

status of the remote station.

RRNR=’0’ The remote station receiver is ready.

RRNR=’1’ The remo te rece iv e r is NOT ready .

(A ’recei ver -not-r eady’ ind ica tion was recei ved from the

remo te sta tion)

PEB 20525

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Preliminary Data Sheet 5-132 09.99

Reg ister 5-1 9 C M D RL

Command Register (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 14H64H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

Timer T ransmitter Commands

STI TRES XIF XRES XF XME XREP 0

Reg ister 5-2 0 C M D RH

Command Register (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 15H65H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

Receiver Commands

RMC RNR 0 0 RSUC 0 0 RRES

PEB 20525

PEF 20525

Preliminary Data Sheet 5-133 09.99

STI Start Timer Command

Self-clearing com ma nd bit:

HDLC Automode:

In HDLC Automode the timer is used internally for the autonomous

protocol support functions. The timer is started automatically by the SCC

when an I-Frame is sent out and needs to be acknowledged.

If the ’ S TI’ command is issued by software:

STI=’1’ A n S-Frame with poll bit set is sent out and the internal

timer is started expec ting an acknowledge from the

remote station via an I- or S-Frame.

The timer is stopped after receivi ng an acknowledg e

otherw is e the timer expires gener ating a time r interrupt.

Note: In HDLC Automode, bit ’TMD’ in register TIMR3

must be set to ’1’

All protocol modes except HDLC Autom ode:

In these modes the timer is operating as a general purpose t imer.

STI=’1’ This comm ands st arts timer operat ion.

The timer can be stopped by setting bit ’TRES’.

Note: Bit ’TMD’ in register TIMR3 must be cleared for

proper operation

TRES Timer Reset

Self-clearing com ma nd bit.

This bit deactiva tes timer operat io n:

TRES=’0’ Timer operat ion enable d.

TRES=’1’ Timer operat ion stoppe d.

XIF Transmit I-Frame

Self-clearing com ma nd bit.

This command bit is significant in HDLC Automode only.

XIF=’1’ Initiates the transmission of an I-frame in auto-mode.

Additional to the opening flag, the address and control

fields of the frame are added by PASSAT.

PEB 20525

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Preliminary Data Sheet 5-134 09.99

XRES Transmi tter Reset Command

Self-clearing com ma nd bit:

XRES=’1’ The SCC transmit FIFO is cleared and the transmitter

protocol engi nes are reset to their initial state.

A transmitter reset command is recommended after all

changes in protocol mode configurations (e.g. switching

between sub-modes of HDLC).

XF Transmit Frame

This self-clearing command bit is significant in interrupt driven operation

only (GMODE.EDMA=’0’).

XF=’1’ Aft er having written up to 32 bytes to the XFIFO, this

command initiates transmission. In packet oriented

protocols like HDLC/PPP the opening flag is automatically

added by PASSAT. If the end of the packe t is part of t he

transm it data, bit ’XME’ sho uld be set in addition.

DMA Mode

After having w ritten the length of the data block to be

tra nsm itte d to registers XBCL and XBCH, this command

initiates the data transfer from host memory to PASSAT

by DMA. Transmission on the serial side starts as soon as

32 bytes are transferred to the XFI FO or the transmit byte

count er value is reached .

XME Transmit Message End

Self-clearing com ma nd bit:

XME=’1’ Indi cates th at the data block written l ast to the XFIFO

contains the end of the packet. This bit should always be

set in conjunction with a transmit command (’XF’ or ’XIF’).

XREP Transmissi on Repeat Command

Self-clearing com ma nd bit:

XREP=’1’ If bit ’XREP’ is set together with bit ’XME’ and ’XF’,

PASSAT repeatedly transm its the contents of the XFIFO

(1..32 bytes).

The cycl ic transmissi on can be st opped with th e ’XRES’

command.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-135 09.99

RMC Receive Message Complete

Self-clearing com ma nd bit:

RMC=’1’ With this bit the CPU indicates to PASSAT that the current

receive data has been fetched out of the RFIFO. Thus the

corresponding space in the RFIFO can be released and

re-used by PASSAT for further incom ing data.

RNR Recei ver Not Ready C omm and

NON self-clearing com m and bit:

This command bit is significant in HDLC Automode only.

RNR=’0’ Forces the receiver to enter its ’receiver-ready’ state. The

receiver acknowledges received poll or I-Frames with a

’receiver-ready’ indication.

RNR=’1’ Forces the receiver to enter its ’receiver-not-ready’ state.

The receiver acknowledges received poll or I-Frames with

a ’receiver-not-ready’ indication.

RSUC Reset Signaling Unit Counter

Self-clearing com ma nd bit:

This command bit is significant if HDLC SS7 mode is selected.

RSUC=’ 1’ The Signaling System #7 (SS7) unit counter is reset.

RRES R eceiver Reset Comman d

Self-clearing com ma nd bit:

RRES= ’1’ T he SC C r eceiv e F IFO i s cleare d and t he re ceiver

protocol engi nes are reset to their initial state.

The SCC receive FIFO accepts new receive data from the

protocol engine immediately after receiver reset

procedure.

It is recommended to disable data reception befor e

iss uing a receiver reset comm and by set ting bi t

CCR3L.RAC = ’0’ and enabling data reception afterwards.

A ’receive r reset’ command is recommended after all

changes in protocol mode configurat ion s.

PEB 20525

PEF 20525

Registe r Description (CCR0L)

Preliminary Data Sheet 5-136 09.99

Channel Configuration Register 0 (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 16H66H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc. Clock Mode Selection

VIS PSD 0 TOE SSEL CM(2:0)

Channel Configuration Register 0 (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 17H67H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Power Line Coding

PU SC(2:0) 0 0 0 0

PEB 20525

PEF 20525

Preliminary Data Sheet 5-137 09.99

PU Power Up

PU=’0’ The SCC is in ’power-down’ mode. The protocol engines

are switched off (standby) and no operation is performed.

This may be used to save power when SCC is not in use.

Note: The SCC transmit FIFO accepts transmit data even

in ’powe r-dow n’ mode.

PU=’1’ The SCC is in ’pow er -up ’ mode.

SC(2:0) Serial Port Configuration

This bit field selects the line coding of the serial port.

Note, that special operation modes and settings may require or exclude

operation in special line coding modes. Refer to the ’prerequisites’ in the

dedicated mode descripti ons.

SC = ’000’ NRZ data encoding

SC = ’001’ Bus configuration, timing mode 1 (NRZ data encoding)

SC = ’010’ NRZI data encoding

SC = ’011’ Bus configuration, timing mode 2 (NRZ data encoding)

SC = ’100’ FM0 data encoding

SC = ’101’ FM1 data encoding

SC = ’110’ Manchester data encoding

SC = ’111’ Reserved

Note: If bus conf igur ation mo de is selected, onl y NRZ data enc oding i s

supported.

VIS Masked Interrupts Visible

VIS=’0’ Masked interrupt status bits are not displayed in the

interr upt status reg ister s (ISR0..ISR2).

VIS=’1’ Masked interrupt status bits are visible and automatically

cleared after interrupt status register (ISR0..ISR2) rea d

access.

Note: Interrupts masked in registers IMR0..IMR2 will not generate an

interrupt.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-138 09.99

PSD DPLL Phase Shift Disable

This option is only applicable in the case of NRZ or NRZI line encoding

is selected.

PSD=’0’ N or m al DPLL operation.

PSD=’1’ The phase shift func tion of the DPLL is disabled. The

window s for phase adjus tment are extended.

TOE Transmit Clock Out Enable

For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock

can be monitored on pin TxCLK as an output signal. In clock mode 5, a

time slot control signal marking the active transmit time slot is output on

pin TxCLK.

Bit ’TOE’ is invalid for all other clock modes.

TOE=’0’ TxCLK pin is input.

TOE=’1’ TxC LK pin is switched to output function if applicab le for

the select ed cl ock mo de.

SSEL Clock Sourc e Select

Distinguishes between the ’a’ and ’b’ option of clock modes 0, 2, 3, 5, 6

and 7.

SSEL=’0’ Option ’a’ is selected.

SSEL=’1’ Option ’b’ is selected.

CM(2:0) Clock Mode

This bit field selects one of main clock modes 0..7. For a detailed

description of the clock modes refer to Chapter 3. 2.3

CM = ’000’ cloc k mode 0

CM = ’001’ cloc k mode 1

CM = ’010’ cloc k mode 2

CM = ’011’ cloc k mode 3

CM = ’100’ cloc k mode 4

CM = ’101’ c lock mode 5 (time-slot orien ted clocking modes)

CM = ’110’ cloc k mode 6

CM = ’111’ cloc k mode 7

PEB 20525

PEF 20525

Registe r Description (CCR1L)

Preliminary Data Sheet 5-139 09.99

Channel Configuration Register 1 (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 18H68H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

CRL C32 SOC(1:0) SFLG DIV ODS 0

Channel Configuration Register 1 (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 19H69H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

0 ICD 0 RTS FRTS FCTS CAS TSCM

PEB 20525

PEF 20525

Preliminary Data Sheet 5-140 09.99

CRL CRC Reset Value

This b it d ef in e s the in itial val ue o f the int er n a l tra nsmit/rece iv e CRC

generators:

CRL=’0’ Initial value is 0xFFFFH (16 bit CRC), 0xFFFFFFFFH

(32 bit CRC).

This is the default value for most HDLC/ PPP appl ications.

CRL=’1’ Initial value is 0x0000 H (1 6 bit CRC), 0 x00000 000H

(32 bit CRC).

C32 CRC 32 Select

This b it e nab le s 32- b it CRC o per a tio n fo r transm it a nd rec e iv e .

C32= ’0 ’ 16-bit CRC- CCITT generation/check ing .

C32=’1’ 32- b it CRC g ener at io n /c he c ki n g .

Note: The internal ’valid frame’ criteria is updated depending on the

selected number of CRC-bytes.

SOC(1:0) Serial Output Control

This bit field selects the RT S signal output function.

(This bit field is only valid in bus configuration modes selected via bit field

SC (2 :0) in re g ister CCR0H).

SOC = ’0X’ RTS ouput signal is active during transmission of a frame

(act ive low).

SOC = ’10’ RTS ouput signal is always inactive (high).

SOC = ’11’ RTS ouput signal is active during recep tion of a frame

(act ive low).

SFLG Shared Flags Transmission

This bit enables ’shared flag transmission’ in HDLC protocol mode. If

another transmit frame begin is stored in the SCC transmit FIFO, the

closing flag of the preceding frame becomes the opening flag of the next

frame (shared flags):

SFLG = ’0’ Shared flag transmissi on disabl ed.

SFLG = ’1’ Shared flag transmission enabled.

Note: The receiver always supports shared flags and shared zeros of

consecutive flags .

PEB 20525

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Preliminary Data Sheet 5-141 09.99

DIV Data Inversion

This bit is only valid if NRZ data encoding is selected via bit field SC(2:0)

in register CCR0H.

DIV=’0 ’ No Data Inversion.

DIV=’1’ Data is transmit ted/recei ved in verted (on a per bit basis).

In HDLC and HDLC Sy nchr onous PPP modes the

cont inuo us ’1’ idle seque nce is NOT inverted.

Interf ra me time fill flag transm i ssi on is inver ted.

ODS Output Driver Select

The transmit data output pin TxD can be configured as push/pull or open

drain output chract er istic.

ODS=’0’ TxD pin is open drain output.

ODS=’1’ TxD pin is push/pull output.

ICD Invert Carrier Detect Pin Polarity

ICD=’0’ Carrier Detect (CD) input pin is active high.

ICD=’1’ Carrier Detect (CD) input pin is active low.

RTS Request To Send Pin Control

The request to send pin RTS can be controlled by PASSAT as an output

autonomousl y or via setting/c learing bit ’RTS’.

This bit is not valid in clock mode 4.

RTS=’0’ Pin RTS (output ) pin is controlled by PASSAT

autonomously.

RTS is activated during transmission. In bus configuration

mode the functionali ty depe nds on bit field ’SOC’ setting.

RTS=’1’ Pin RTS can be controlled by software. The output level of

this pin depends on bit ’FRTS’ .

Note: For RTS pin control a transmit clock is necessary.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-142 09.99

FRTS Flow Control (using signal RTS )

Bit ’FR TS’ together with bit ’RTS’ determine the function of signal RTS:

RTS, FRTS

0, 0 Pin RTS is controlled by PASSAT autonomously.

RTS is activated (low) as soon as trans mit data is

avai lable within the SCC transmit FIFO.

0, 1 Pin RTS is controlled by PASSAT autonomously

suppor ting bi-direc tional data flow control.

RTS is activated (low) if the shadow part of the SCC

receive FI FO is empty and de-act iva ted (high ) when the

SCC receive FIFO fill level reaches its receive FIFO

threshold.

1, 0 Forces pin RTS to active st at e (low).

1, 1 Forces pin RTS to inac tive state ( high ).

Note: For RTS pin control a transmit clock is necessary.

FCTS Flow Control (using signal CTS )

This bit controls the function of pin CTS.

FCTS = ’0’ The transmitter is stopped if CTS input signal is inactive

(high) and ena bled if active (low).

FCTS = ’1’ The transmitter i s enabled, disregarding CTS input signal.

CAS Carrier Detect Auto Sta rt

CAS = ’0’ The CD pin is used as general input.

In clock mode 1, 4 and 5, clock mode speci fic control

signals must be provided at this pin (receive strobe,

receive gat i ng RCG, frame sync cl ock FSC ).

A pull-up/dow n resistor is recommended if unused.

CAS = ’1’ The CD pin enables/disables the receiver for data

reception. (Polarity of CD pin can be configured via bit

’ICD’.)

Note: (1) In clock mode 1, 4 and 5 this bit must be set to ’0’.(3) A receive

clock must be provided in order to detect the signal state of the CD

input pin.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-143 09.99

TSCM Time Slot Control Mode

This bit controls internal counter operation in time slot oriented clock

mode 5:

TSCM=’0’ The internal coun ter keeps run ning, restarting with zero

after being expi re d.

TSCM=’1’ The internal counter stops at its maximum value and

restarts w ith the next frame sync pulse agai n.

PEB 20525

PEF 20525

Registe r Description (CCR2L)

Preliminary Data Sheet 5-144 09.99

Channel Configuration Register 2 (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 1AH6AH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

MDS1 MDS0 ADM NRM PPPM(1:0) TLPO TLP

Channel Configuration Register 2 (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 1BH6BH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

MCS EPT NPRE(1:0) ITF 0 OIN XCRC

PEB 20525

PEF 20525

Preliminary Data Sheet 5-145 09.99

MDS(1:0) Mode Select

This bit field selects the HDLC protocol sub-mode including the

’extended transpar ent mode ’ .

MDS = ’00’ Automode.

MDS = ’01’ Address Mode 2.

MDS = ’10’ Address Mode 0/1.

(Opt io n ’0’ or ’1’ is sele c ted vi a bit ’ADM’. )

MDS = ’11’ Extended transparent mode (bit transparent transmission/

reception).

Note: ’M DS(1:0) ’ mu st be set t o ’10’ if any PPP mode is enabled via bit

field ’PPPM’ or if SS7 is enabled via bit ’ESS7’ in register CCR3L.

ADM Address Mode Select

The meaning of this bit depends on the selected protocol sub- mod e:

Automode, Address Mode 2:

Determine s the address field len gth of an HDLC frame.

ADM = ’0’ 8 -bit address field.

ADM = ’1’ 1 6-bit address field.

Address Mode 0/1:

Determines whether address mode 0 or 1 is selected.

ADM = ’0’ Ad dres s Mode 0 (no address recognit ion).

ADM = ’1’ Ad dres s Mode 1 (high byte addre ss reco gni tion).

Extended Transparent Mode:

ADM = ’1’ recom m ended setting

NRM Normal Response Mode

This bit is valid in HDLC Automode operation only and determines the

function of the Automode LAP-Controller:

NRM = ’0’ Full-d uplex LAP-B / LAP-D operation.

NRM = ’1’ Hal f-dup lex normal response mode (NRM) oper ation.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-146 09.99

PPPM(1:0) PPP Mode Select

This bit field enables and selects the HDLC PPP protocol modes:

PPPM = ’00’ No PPP protocol operation. The HDLC sub-mode is

determined by bit field ’MDS’.

PPPM = ’01’ Octet synchronous PPP protocol operation.

PPPM = ’10’

Reserved

PPPM = ’11’ Bit synchronous PPP protocol operation.

Note: ’Address Mode 0’ m ust be selected by set ting bi t fie ld ’MDS(1:0)’

to ’10’ and bit ’ADM’ to ’0’ if a ny PPP mode is enabled.

TLPO Test Loop Out Function

This bit is only valid if test loop is enabled and controls whether test loop

transmit data is driven on pin TxD:

TLPO = ’0’ Test loop transmi t data is driven to TxD pin.

TLPO = ’1’ Test loop transmit data is NOT driven to TxD pin. TxD pin

is idle ’1’. Depending on the selected output characteristic

the pin is high impedance (bit CCR1L.ODS =’0’) or driving

high (CCR1L.ODS =’ 1’ ).

TLP Test Loop

This bit controls the internal test loop between transmit and receive data

signals. The test loop is closed at the far end of serial transmit and

receive line just before the respective TxD and RxD pins:

TLP = ’0’ Test loop disabled.

TLP = ’1’ Test loop enabled.

The software is responsible to select a clock mode which

allows correct reception of transmit data depending on the

external clock supply. Transmit data is sent out via pin

TxD if not d isabled with bit ’TLPO’. The receive input pin

RxD is internally disconnected during test loop operation.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-147 09.99

MCS Modulo Count Sele ct

This bit is valid in HDLC Automode operation only and determines the

control field format:

MCS = ’0’ Basic operation, one byte control field (modulo 8 counter

operation).

MCS = ’1’ Ex ten ded opera tion, two bytes control field (modu lo 128

count er operat ion).

EPT Enable Preamble Transmission

This bit enables preamble transmission. The preamble is started after

interframe time fill (ITF) transmission is stopped because a new frame is

ready to be transmitted. The preamble pattern consists of 8 bits defined

in register PREAMB, which is sent repetitively. The number of repetitions

is determined by bit field ’PRE(1:0)’:

EPT=’0’ Pream bl e transmission is disabled.

EPT=’1’ Preamble transmission is enabled.

Note: Preamble operation does NOT influence HDLC shared flag

transmission if enabled.

NPRE(1:0) Number of Preamble Repetitions

This bit field determines the numbe r of pream bles transm itted :

NPRE = ’00’ 1 preamble.

NPRE = ’01’ 2 preambles.

NPRE = ’10’ 4 preambles.

NPRE = ’11’ 8 preambles.

ITF Interframe Time Fill

This bit selects the idle state of the transmit pin TxD:

ITF=’0’ Continuous logical ’1’ is sent during idle phase.

ITF=’1’ Continuous flag sequences are sent (’01111110’ flag

pattern).

Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.

continuous ’1’s are sent as idle sequence and data encoding is

NRZ.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-148 09.99

OIN One Ins e rt io n

In HDLC mode a one-insertio n mech anis m similar to the zero-inser tion

can be activated :

OIN=’0’ The ’1’ insertion mechanism is disabled.

OIN=’1’ In transmit direction a logical ’1’ is inserted to the serial

data stream after 7 consecutive zeros.

In receiv e direction a ’1’ is deleted from the receive data

stream after receiving 7 consecut ive zeros.

This ena bles clock informat ion to be recovered from the

receive data stream by means of a DPLL, even in the case

of NRZ data encoding, because a transition at bit cell

boundary occurs at least every 7 bits.

XCRC Transmit CRC Checking Mode

XCRC=’0’ The transmit checksum (2 or 4 bytes) is generated and

appended to the transmit data automatical ly.

XCRC=’1’ The transmit checksum is not generated automatically.

The checksum is expected to be provided by software as

the last 2 or 4 bytes in the transm it data buffe r.

PEB 20525

PEF 20525

Registe r Description (CCR3L)

Preliminary Data Sheet 5-149 09.99

Channel Configuration Register 3 (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 1CH6CH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

ELC AFX CSF SUET RAC 0 0 ESS7

Channel Configuration Register 3 (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 1DH6DH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

misc.

0 DRCRC RCRC RADD 0 0 RFTH(1:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-150 09.99

ELC Enable Length Check

This bit is only valid in HDLC SS7 mode:

If the num ber of received octets excee ds 272 + 7 within one Signaling

Unit, reception is aborted and bit RSTA.RAB is set.

ELC=’0’ Length Check disabled.

ELC=’1’ Length Check enabled.

AFX Automatic FISU Transmission

This bit is only valid in HDLC SS7 mode:

After the c ont ents of the transmit FIFO (XFIFO) has been transmitted

completely, FISUs are transmited automatically. These FISUs contain

the FSN and BSN of the la st transmitted Sig naling Unit (provided i n

XFIFO).

AFX=’0’ Automatic FISU transmission disabled.

AFX=’1’ Automatic FISU transmission enabled.

CSF Compare Status Field

This bit is only valid in HDLC SS7 mode:

If the st atu s fields of consecutive LSSUs are equa l, only the first will be

stored and every follow ing is ignored

CSF=’0’ Compare is disabled, all received LSSUs are stored in the

receive FIFO.

CSF=’1’ C om par e is enabled , only the first one of c onsecutive

equal LSSUs is stored in the receive FIFO.

SUET Signalling Unit Counter Threshold

This bit is only valid in HDLC SS7 mode:

Def ines the number of signaling units received in error t hat will caus e an

error rate high indication (ISR1.SUEX).

SUET=’0’ thr eshol d is 64 errored signaling unit s.

SUET=’1’ thr eshol d is 32 errored signaling unit s.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-151 09.99

RAC Recei ver active

Switches the receiver between operational /inoperat ion al states:

RAC=’0’ Receiver inactive , receive line is ignored.

RAC=’1’ Receiver active.

ESS7 Enable SS7 Mode

This bit is only valid in HDLC mode only.

ESS7=’0’ Disable signaling system #7 (SS7) support.

ESS7=’1’ Enable signaling system #7 (SS7) support.

Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by

setting bit field CCR2L:MDS(1:0) to ’10’ and bit CCR2L:ADM to ’0’.

DRCRC Disable Receive CRC Checking

DRCRC=’0’ The rec eiver expec ts a 16 or 32 bit CRC within a HDLC

frame. CRC pro cessing depends on the setting of bit

’RCRC’.

Frames shorter than expected are marked ’invalid’ or are

discarded (refer to RSTA desc ription) .

DRCRC=’1’ The rec eiver does not ex pec t a ny CRC within a HDLC

frame. The criteria for ’valid frame’ indication is updated

accor din gly (refer to RSTA description).

Bit ’RCRC’ is ignored.

RCRC Receive CRC Checking Mode

RCRC=’0’ The received checksum is evaluated, but NOT forwarded

to the receive FIFO.

RCRC= ’1 ’ The received checksum (2 or 4 bytes) is eval uat ed and

forwarded to the receive FIFO as data.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-152 09.99

RADD Receive Address Forward to RFIFO

This bit is only v alid

– if an HDLC sub-mode with address field support is selected

(Automode, Address Mode 2, Address Mode 1)

– in SS7 mode

RADD=’0’ The received HDLC address field (either 8 or 16 bit,

depending on bit ’ADM’) is evaluated, but NOT forwarded

to the receive FIFO.

In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are

NOT forwarded to the receive FIFO.

RADD=’1’ The received HDLC address field (either 8 or 16 bit,

depending on bit ’ADM’) is evaluated and forwarded to the

receive FIFO.

In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are

forwa rded to the rec eive FIFO.

RFTH(1:0) Receive FIFO Threshold

This bit field defines the level up to which the SCC receive FIFO is filled

with valid data before an ’RPF’ interrupt is generated.

(In case of a ’fra me end ’ condi t ion the PASSAT notifies the CPU

imm edi ate ly, disregardi ng this thresho ld.)

RFTH(1:0) Threshold level in number of data bytes.

’00’ 32 byte

’01’ 16 byte

’10’ 4 byte

’11’ 2 byte

PEB 20525

PEF 20525

Preliminary Data Sheet 5-153 09.99

Reg ister 5-29 PREA M B

Preamble Regis ter

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 1EH6EH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Preamble Pattern

PRE(7:0)

PRE(7:0) Preamble

This bit field determines the preamble pattern which is send out during

preamble transm i ssi on.

Note: In HDLC-mode, zero-bit insertion is disabled during preamble

transmission.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-154 09.99

PPP ASYNC Control Character Map 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 20H70H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character Control Map 07..00

07 06 05 04 03 02 01 00

PPP ASYNC Control Character Map 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 21H71H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC C haracter Control Map 0F..08

0F 0E 0D 0C 0B 0A 09 08

PEB 20525

PEF 20525

Preliminary Data Sheet 5-155 09.99

PPP ASYNC Control Character Map2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 22H72H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character Control Map 17..10

17 16 15 14 13 12 11 10

PPP ASYNC Control Character Map 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 23H73H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC C haracter Control Map 1F..18

1F 1E 1D 1C 1B 1A 19 18

PEB 20525

PEF 20525

Preliminary Data Sheet 5-156 09.99

ACCM ASYNC Character Cont rol Map

This bit field is valid in HDLC octet-synchronous PPP mode only:

Each bit selects the correspondi ng char act er (indicated as hex val ue

1FH..00H in the register description table) as control character which has

to be mapped into the transmit data stream.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-157 09.99

User Defined PPP ASYNC Control Character Map 0

CPU Acc e ssibilit y : read/write

Reset Value: 7EH

Channel A Channel B

Offs et Address: 24H74H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character 0

AC0

User Defined PPP ASYNC Control Character Map 1

CPU Acc e ssibilit y : read/write

Reset Value: 7EH

Channel A Channel B

Offs et Address: 25H75H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character 1

AC1

PEB 20525

PEF 20525

Preliminary Data Sheet 5-158 09.99

User Defined PPP ASYNC Control Character Map 2

CPU Acc e ssibilit y : read/write

Reset Value: 7EH

Channel A Channel B

Offs et Address: 26H76H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character 2

AC2

User Defined PPP ASYNC Control Character Map 3

CPU Acc e ssibilit y : read/write

Reset Value: 7EH

Channel A Channel B

Offs et Address: 27H77H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

ASYNC Character 3

AC3

PEB 20525

PEF 20525

Preliminary Data Sheet 5-159 09.99

AC3. .0 User Defined ASYNC Chara cte r Control Map

This bit field is valid in HDLC octet-synchronous PPP mode only:

These bit fields define user determined characters as control characters

which have to be mapped into the transm it data stream.

In register ACCM only characters 00 H..1FH can be selected as control

charact ers. Re gister UDAC allows to spe cify any fo ur charact ers in the

range 00H..FFH .

The default value is a 7EH flag which must be always mapped. Thus no

additional char acter is mappe d if 7EH ’s are programe d to bit fields

AC3...0 (reset value).

(7EH is mapped automat ica lly, even if not defined via a AC bit fiel d. )

PEB 20525

PEF 20525

Preliminary Data Sheet 5-160 09.99

Reg ister 5-38 TTSA0

Transmit Time Slot Assignment Register 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 28H78H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Tx Cloc k S hift

00000 TCS(2:0)

Reg ister 5-39 TTSA1

Transmit Time Slot Assignment Register 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 29H79H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Tx Time Slot Number

TEPCM TTSN(6:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-161 09.99

Reg ister 5-40 TTSA2

Transmit Time Slot Assignment Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2AH7AH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Transmit Channel Capacity

TCC(7:0)

Reg ister 5-41 TTSA3

Transmit Time Slot Assignment Register 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2BH7BH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Transmit Channel Capacity

0000000TCC8

PEB 20525

PEF 20525

Preliminary Data Sheet 5-162 09.99

The following register bit fields allow flexible assignment of bit- or octet-aligned transmit

time-slots to the serial channel. For more detailed information refer to chapters "Clock

Mode 5a (Time Slot Mode)" on page 3-53 and "Clock Mode 5b (Octet Sync Mode)" on

page 3-60.

TCS(2:0) Transmit Clock Shift

This bit field determines the transm it clock shift .

TEPCM Enable PCM Mask Transmit

This bit selects the additional Transmi t PCM Mask (refe r to register

PCMTX0..PCMTX3):

TEPCM=’0’ Standa rd time-slot configuration .

TEPCM=’1’ The time-slot width is constant 8 bit, bit fields ’TTSN’ and

’TCS’ determine the offset of the PCM mask and ’TCC’ is

igno red. Each time -slot selec ted via register

PCMTX0..PCMTX3 is an activ e transmit timeslot.

TTSN(6:0) Transmi t Time Slot Number

This bit field selects the start position of the timeslot in time-slot

configuration mode (clock mode 5a/5b):

Offset = 1+TTSN*8 + TCS (1..1024 clocks)

TCC(8:0) Transmit Channel Capacity

This bit field determines the transmit time-slot width in standard time-slot

configuration (bit TEPCM=’0’):

Number of bits = TCC + 1, ( 1. .512 bi ts /time-sl ot)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-163 09.99

Reg ister 5-42 RTSA0

Receive Time Slot Assignment Register 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2CH7CH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Rx Clock Shift

00000 RCS(2:0)

Reg ister 5-43 RTSA1

Receive Time Slot Assignment Register 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2DH7DH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Rx Time Slot Number

REPCM RTSN(6:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-164 09.99

Reg ister 5-44 RTSA2

Receive Time Slot Assignment Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2EH7EH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Channel Capacity

RCC(7:0)

Reg ister 5-45 RTSA3

Receive Time Slot Assignment Register 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 2FH7FH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Channel Capacity

0000000RCC8

PEB 20525

PEF 20525

Preliminary Data Sheet 5-165 09.99

The following register bit fields allow flexible assignment of bit- or octet-aligned receive

time-slots to the serial channel. For more detailed information refer to chapters "Clock

Mode 5a (Time Slot Mode)" on page 3-53 and "Clock Mode 5b (Octet Sync Mode)" on

page 3-60.

RCS(2:0) Receive Clock Shift

This bit field determines the receive cl ock shif t.

REPCM Enable PCM Mask Receive

This bit selects the additional Receive PCM Mask (refer to register

PCMRX0..PCMRX3):

REPCM=’0’ Standa rd time-slot configuration .

REPCM=’1’ The ti me-slot width is constant 8 bi t, bit f ields ’RTSN’ and

’RCS’ determine the offset of the PCM mask and ’RCC’ is

igno red. Each time -slot selec ted via register

PCMRX0..PCMRX3 is an active receive timeslot.

RTSN(6:0) Receive Time Slot Number

This bit field selects the start position of the timeslot in time-slot

configuration mode (clock mode 5a/5b):

Offset = 1 +RTSN *8 + RC S (1..102 4 clocks)

RCC(8:0) Receive Channel Capacity

This bit field determines the receive time-slot width in standard time-slot

configuration (bit REPCM=’0’):

Number of bits = RCC + 1, (1..512 bits/time-slot)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-166 09.99

Reg ister 5-46 PCM TX0

PCM Mask Transmit Direct ion Register 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 30H80H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

PCM Mask for Transmit Direction

T07 T06 T05 T04 T03 T02 T01 T00

Reg ister 5-47 PCM TX1

PCM Mask Transmit Direct ion Register 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 31H81H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

PCM Mask for Transmit Direction

T15 T14 T13 T12 T11 T10 T09 T08

PEB 20525

PEF 20525

Preliminary Data Sheet 5-167 09.99

Reg ister 5-48 PCM TX2

PCM Mask Transmit Direct ion Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 32H82H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

PCM Mask for Transmit Direction

T23 T22 T21 T20 T19 T18 T17 T16

Reg ister 5-49 PCM TX3

PCM Mask Transmit Direct ion Register 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 33H83H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit151413121110 9 8

PCM Mask for Transmit Direction

T31 T30 T29 T28 T27 T26 T25 T24

PEB 20525

PEF 20525

Preliminary Data Sheet 5-168 09.99

PCMTX PCM Mask for Transmit Direction

This bit field is valid in HDLC clock mode 5 only and the PCM mask must

be enabled via bit ’TEPCM’ in register TTSA1.

Each bit selects one of 32 (8-bit) transmit time-slots. The offset of time-

slot zero to the frame sync pulse can be programmed via register TTSA1

bit field ’TTSN’.

PEB 20525

PEF 20525

Regist er Descript ion (PCMRX0)

Preliminary Data Sheet 5-169 09.99

Reg ister 5-50 PCM R X0

PCM Mask Receive Direction Register 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 34H84H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

PCM Mask for R e ceiv e Direction

T07 T06 T05 T04 T03 T02 T01 T00

Reg ister 5-51 PCM R X1

PCM Mask Receive Direction Register 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 35H85H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit151413121110 9 8

PCM Mask for R e ceiv e Direction

T15 T14 T13 T12 T11 T10 T09 T08

PEB 20525

PEF 20525

Regist er Descript ion (PCMRX2)

Preliminary Data Sheet 5-170 09.99

Reg ister 5-52 PCM R X2

PCM Mask Receive Direction Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 36H86H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

PCM Mask for R e ceiv e Direction

T23 T22 T21 T20 T19 T18 T17 T16

Reg ister 5-53 PCM R X3

PCM Mask Receive Direction Register 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 37H87H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit151413121110 9 8

PCM Mask for R e ceiv e Direction

T31 T30 T29 T28 T27 T26 T25 T24

PEB 20525

PEF 20525

Regist er Descript ion (PCMRX3)

Preliminary Data Sheet 5-171 09.99

PCMRX PCM Mask for Receive D irection

This bit field is valid in HDLC clock mode 5 only and the PCM mask must

be enabled via bit ’REPCM’ in register RTSA1.

Each bit selects one of 32 (8-bit) receive time-slots. The offset of time-

slot zero to the frame sync pulse can be programmed via register RTSA1

bit field ’RTSN’.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-172 09.99

Baud Rate Register (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 38H88H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Baud Rate Generator F actor N

0 0 BRN(5:0)

Baud Rate Register (H igh Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 39H89H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Ba ud Rate Generator Factor M

0000 BRM(3:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-173 09.99

BRM(3:0) Baud Rate Factor ’M ’

BRN(5:0 ) Baud Rate Factor ’N’

These bi t fields determi ne the divisi on factor of the internal baud rate

generator. The baud rate generator input clock and the usage of baud

rate generator output depe nds on the select ed clock mo de.

The division factor k is calculated by:

with M=0..15 and N=0..63.

kN1

+()

×=

fBRG fin k

⁄=

PEB 20525

PEF 20525

Preliminary Data Sheet 5-174 09.99

Reg ister 5-56 TIMR0

Ti mer Re g ister 0

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3AH8AH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Time r Value

TVALUE(7:0)

Reg ister 5-57 TIMR1

Ti mer Re g ister 1

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3BH8BH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Time r Value

TVALUE(15:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-175 09.99

Reg ister 5-58 TIMR2

Ti mer Re g ister 2

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3CH8CH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Time r Value

TVALUE(23:16)

Reg ister 5-59 TIMR3

Ti mer Re g ister 3

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3DH8DH

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Timer Configuration

SRC 0 0 TMD 0 CNT(2:0)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-176 09.99

SRC Clock Source (valid in clock mode 5 only)

This bit selects the clock source of the internal timer:

SRC = ’0’ The timer is clocked by the effective transmit clock.

SRC = ’1’ The timer is clocked by the frame-sync synchronization

signal supplied via the FSC pin in clock mode 5.

TMD Timer Mode

This bit must be set to ’1’ if HDLC Automode operation is selected. In all

other protocol modes it mus t remain ’0’:

TMD=’0’ The timer is controlled by the CPU via access to registers

CMDRL and TIMR0..TIMR3.

The timer can be starte d any time by setting bit ’STI’ in

regist er CMDRL. After the timer has expired it generates

a timer interrupt . The timer can be stopped any time by

setting bit ’TRES’ in register CMDRL to ’1’.

TMD=’1’ The timer is used by the PASSAT for protocol specific

time-out and retry transactions in HDLC Automode.

CNT(2:0) Counter

The meaning of this bit field depends on the selected protocol mode.

In HDLC Automode, with bit TMD=’1’:

• Ret ry Counter (in HDL C protocol know n as ’N2’):

Bit fie ld ’CNT’ indicates the number of S-Command frames (with poll

bit set) which are transmitted autonomously by PASSAT after every

expiration of the time out period ’t’ (determined by ’TVALUE’), in case

an I-Frame gets not acknowledged by the opposite station. The

maximum value is 6 S-command frames. If ’CNT’ is set to ’7’, the

number of S-commands is unlimited in case of no acknowledgement.

In all other modes, with bit TMD=’0’:

• Rest art Counte r :

Bit field ’CNT’ indicates the number of automatic restarts which are

performed by PASSAT after every expiration of the time-out period ’t’,

in case the timer is not stopped by setting bit ’TRES’ in register

CMDRL to ’1 ’. T he ma xi mum val ue is 6 res ta rts . If ’C NT ’ is se t to ’7 ’,

a timer interrupt is generated periodically with time period ’t’

determined by bi t field ’TVALUE’.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-177 09.99

TVALUE

(23:0) Timer Expiration Value

This bit field determines the timer expi ration period ’t’:

(’CP’ is the clock period, depending on bit ’SRC’.)

tTVALUE1

+()

⋅=

PEB 20525

PEF 20525

Regist e r Description (XAD1 )

Preliminary Data Sheet 5-178 09.99

Reg ister 5-60 XAD1

Transmit Address 1 Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3EH8EH

typical usage: w r itt en by CPU; read and evaluat ed by PASSAT

Bit76543210

Transmit Address (high)

XAD1 (high byte) 0 XAD1_0

or XAD1 (COM MAND)

Reg ister 5-61 XAD2

Transmit Address 2 Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 3FH8FH

typical usage: w r itt en by CPU; read and evaluat ed by PASSAT

Bit76543210

Transmit Address (low)

XAD2 (low byte)

or XAD2 (RESPONSE)

PEB 20525

PEF 20525

Regist e r Description (XAD2 )

Preliminary Data Sheet 5-179 09.99

XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address f ield

handling only (Automode, Address Mode 1, Non-Automode). They can be programmed

with one individu al address byte w hic h is inserted automa tically into the address field

(8 or 16 bit) of a HDLC transmit frame. The function depends on the selected protocol

mode and addr ess field size (bit ’ADM’ in register CCR2L).

XAD1 Transmit Address 1

– 2-byte address field:

Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit

1 must be set to ’0’. According to the ISDN LAP-D protocol, bit 1 is

interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is

manipulated automatically by PASSAT accordin g to the setting o f bit

’CRI’ in regist er RAH1. The following is the C/R value (on bit 1), when:

- transmitting COMMANDs: ’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’)

- transmitting RESPONSEs: ’0’ (if ’CRI’=’1’) ; ’1’ (if ’CRI’=’0’)

(In ISDN LAP-D, the high byte is known as ’SAPI’.)

In a ccor dance wi th th e HD LC protoco l, bit ’XAD1_0’ s houl d be s et t o

’0’, to indicate that the address field contains (at least) one more byte.

– 1-byte address field:

According to the X.25 LAP-B protocol, XAD1 is the address of a

’COMMAND’ frame .

XAD2 Transmit Address 2

– 2-byte address field:

Bit fi e ld XAD2 constitute s the low byte of the 2-byte addr ess fiel d.

(In ISDN LAP-D, the low byte is known as ’TEI’.)

– 1-byte address field:

According to the X.25 LAP-B protocol, XAD2 is the address of a

’RESPONSE’ frame.

PEB 20525

PEF 20525

Regist e r Description (RAL1 )

Preliminary Data Sheet 5-180 09.99

Reg ister 5-6 2 R A L1

Receive Address 1 Low Regist er

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 40H90H

typical usage: w r itt en by CPU; read and evaluat ed by PASSAT

Bit76543210

Receive Address 1 (low)

RAL1

Receive Addres s 1 High Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 41H91H

typical usage: w r itt en by CPU; read and evaluat ed by PASSAT

Bit76543210

Receive Address 1 (high)

RAH1 CRI RAH1_0

or RAH1

PEB 20525

PEF 20525

Regist e r Description (RAL2 )

Preliminary Data Sheet 5-181 09.99

Reg ister 5-6 4 R A L2

Receive Address 2 Low Regist er

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 42H92H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Address 2 (low)

RAL2

Receive Addres s 2 High Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 43H93H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Address 2 (high)

RAH2

PEB 20525
PEF 20525
Registe r Description (RAH2)
Preliminary Data Sheet  5-182 09.99
 
In operating modes that provide address recognition, the high/low byte of the received 
address is compared with the individually programmable values in register RAH2/
RAL2/RAH1/RAL1.
This addresses can be masked on a per bit basis by setting the correspon ding  bits in 
register s AMRAL1/AMRAH1/AMRAL2/AMRAH2 to allow extended broadcast address 
recognition. This feature is applicable to all HDLC sub-modes with address recognition.
RAH1 Receive Address 1 By te High  
In HDLC Automode bit ’1’ is reserved for ’CRI’ (Comma nd Re sponse 
Interpretation). In all other modes RAH1 i s an 8 bit address.
CRI Command/Response Interpretation
The setting of this bit effects the meaning of the ’C/R’ bit in the rec eive 
status byte (RSTA). This status bit ’C/R’ should be interpreted after 
reception as follows:
’0’ (if ’CRI’=’1’) ; ’1’ (if ’CRI’=’0’) : COMMAND received
’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’) : RESPONSE received
Note: If 1-byte address field is selected in HDLC Automode, RAH1 mu st
be set to 0x00
H
.
RAL1 Recei ve Address 1 Byte Low  
The general functio n and its meaning depe nds on the selected H DL C 
operating mode:
•Automode / Address Mode 2 (16-bit address)
RAL1 can be programmed with the value of the first individual low
address byte.
•Automode / Address Mode 2 (8-bit address)
According to X.25 LAP-B pr otocol,  the  address in RAL1 is considered
as the address of a ’COM MAND ’ frame.
RAH2 Receive Address 2 By te High  
RAL2 Recei ve Address 2 Byte Low  
Value of the second individually programmable high/low address byte. If 
a 1-byte address field is selected, RAL2  is considered as the address of 
a ’RESPONSE’ frame according to X.25 LAP-B protocol.

PEB 20525

PEF 20525

Re gister Descr iption (AMRAL1)

Preliminary Data Sheet 5-183 09.99

Reg ister 5-66 AMRAL1

Mask Recei ve Ad dress 1 Low Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 44H94H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Mask Address 1 (low )

AMRAL1

Mask Recei ve Ad dress 1 High Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 45H95H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Recei ve Mask Address 1 (high)

AMRAH1

PEB 20525

PEF 20525

Re gister Descr iption (AMRAL2)

Preliminary Data Sheet 5-184 09.99

Reg ister 5-68 AMRAL2

Mask Recei ve Ad dress 2 Low Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 46H96H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Mask Address 2 (low )

AMRAL2

Mask Recei ve Ad dress 2 High Register

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 47H97H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Recei ve Mask Address 2 (high)

AMRAH2

PEB 20525
PEF 20525
Register Description  (AMRAH2)
Preliminary Data Sheet  5-185 09.99
 
AMRAH2 Receive Mask Address 2 Byte High  
AMRAL2 Receive Mask Address 2 Byte Low  
AMRAH1 Receive Mask Address 1 Byte High  
AMRAL1 Receive Mask Address 1 Byte Low  
Setting a bit in this regist ers  to ’1’ masks the correspondi ng bit in 
register s RAH2/RAL2/RAH1/RAL1.  A masked bit position always 
matches when comparing the received frame address with registers 
RAH2/RAL2/RAH1/RAL1, allowi ng exte nded broa dcast mec hani sm .
bit = ’0 ’ Th e dedicate d bit position is NOT maske d. This bit 
po sition in the received addres s must match w ith the  
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.
bit = ’1’ The dedicated bit position is masked. This bit position in 
the recei ved addr ess N EED NO T match with the 
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.

PEB 20525

PEF 20525

Regist er Description (RLCRL)

Preliminary Data Sheet 5-186 09.99

Receive Length Check Register (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 48H98H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Length Limit

RL(7:0)

Receive Lengt h Check Registe r (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 49H99H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

Receive Length Check Control Receive Length Limit

RCE 0000 RL(10:8)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-187 09.99

RCE R ecei ve Length Check Enable

This bit is valid in HDLC mode only and enables/disables the receive

length check function:

RCE = ’0’ No r eceiv e le ngt h check on rec e iv e d HDLC fr ame s is

performed.

RCE = ’1’ The receive length check is enabled. All bytes of a H DLC

frame whi ch are trans ferred to the receive FIFO

(depending on the selected protocol sub-mode and

receive CRC handling) are counted and checked against

the m aximum len gth che ck lim it which is progr am med in

bit field ’RL’.

A frame exceed ing the maximum length is treated as if it

were abor ted on the receive line (’RME’ interrupt and bit

’RAB’ (receive abort) set in the RSTA byte).

In addition a ’FLEX’ interrupt is generated prior to ’RME’,

if enabled.

Note: The Receive Status Byte (RSTA) is part of the

frame lengt h checki ng.

RL(10:0) Receive Length Check Limit

This bit-field defines the receive length check limit (32..65536 bytes) if

checking is enabled via bit ’RCE’:

RL(10:0) The receive length limit is calculated by:

Limit RL 1

+()

⋅=

PEB 20525

PEF 20525

Regist er Description (ISR0)

Preliminary Data Sheet 5-188 09.99

Reg ister 5-7 2 I S R0

Interrupt Status Register 0

CPU Acc e ssibilit y : read only

Reset Value: 00H

Channel A Channel B

Offs et Address: 50HA0H

typical usage: updated by PASSAT

read and evaluat ed by C PU

Bit76543210

ISR0

RDO RFO PCE RSC RPF RME RFS FLEX

Reg ister 5-7 3 I S R1

Interrupt Status Register 1

CPU Acc e ssibilit y : read only

Reset Value: 00H

Channel A Channel B

Offs et Address: 51HA1H

typical usage: updated by PASSAT

read and evaluat ed by C PU

Bit76543210

ISR1

TIN CSC XMR XPR ALLS XDU SUEX 0

PEB 20525

PEF 20525

Regist er Description (ISR2)

Preliminary Data Sheet 5-189 09.99

Reg ister 5-7 4 I S R2

Interrupt Status Register 2

CPU Acc e ssibilit y : read only

Reset Value: 00H

Channel A Channel B

Offs et Address: 52HA2H

typical usage: updated by PASSAT

read and evaluat ed by C PU

Bit76543210

ISR2

000000PLLACDSC

PEB 20525
PEF 20525
Regist er Description (ISR2)
Preliminary Data Sheet  5-190 09.99
 
RDO Recei ve Data Overflow Interrupt  
This bit is set to ’1’, if receive data of the current frame got lost becaus e
of a SCC receive FIFO full condition. However the rest of the frame is
received and di scarded as l ong as the receive FI FO remains f ull and is
stored as soon as FIFO space is available again. The receive status byte
(RSTA) of such a frame contains an ’RDO’ indication. In DMA operation
the ’RDO’ indication is also set in the receive byte count register RBCH.
RFO Receive FIFO Overflow Interrupt  
This bit is set to ’1’, if the SCC receive FIFO is full and a complete frame
must be discarded. This interrupt can be used for statistical purposes,
indicating that the host was not able to service the SCC receive FIFO
quickly enough,  e.g. due to high bus latency.
PC E P ro to c o l E rror In te rrup t  
This bit is  valid in HDLC Aut omo de only .
It is set to ’1’, if the receiver has detected a protocol error, i. e. one of the
following events occured:
• an S- or I-frame was receive d with wrong N(R ) counter value;
• an S-frame contai ni ng an Information  fie ld was rec eived.
RSC Receive Status Change Interrupt  
This bit is  valid in HDLC Aut omo de only .
It is set to ’1’, if  a status change  of the remote station receiver has been 
detected by receiving a S-frame with receiver ready (RR) or receiver not 
ready (RNR) indication. Because only a status change is indicated via 
th is  interru p t, the current s tatu s  c a n  b e  evalua ted b y  readi n g b it ’RRNR’  
in status register STARH.
RPF Receive Pool Full Interrupt
This bit is set to ’1’ if the RFIFO threshold le vel, set with bit field 
’ RFTH(1 :0 )’ i n regi ste r CCR3H, is reached. Default threshold level is 32 
data bytes.

PEB 20525
PEF 20525
Regist er Description (ISR2)
Preliminary Data Sheet  5-191 09.99
 
RME Receive Message End Interrupt
This bit set to ’1’ indicates that the receptio n of one message is 
completed, i.e. either
– one message which fits into RFIFO not exceeding the receive FIFO
threshol d, or
– the last part of a message, all in all exceeding the receive FIFO
threshold
is stored in the RFIFO.
The complete message length can be determined by r eading the RBCL/
RBCH registers. The number of bytes stored in RFIFO is given by the 5, 
4, 2 or 1 lea st significant bits of register RBCL, dependi ng on the 
selected RFIFO  threshold (bit field ’RFTH( 1:0 )’ in register CCR3H). 
Additional frame status information is available in the RSTA byte, stored 
in the RFIFO as the last byte of each frame.
RFS Receive Frame Start Interrupt  
This bit is set to ’1’, if the beginning of a va lid frame is detected b y th e
receiver. A valid frame start is detected either if a valid address field is
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes with no address recognition).
FLEX Frame Length Exceeded Interrupt  
This bit is set to ’1’, if the frame length check fe ature is enabl ed and th e
current received frame is aborted because the programmed frame length
limit was exceeded (refer to registers RLCRL/RLCRH for detailed
description).
TIN Timer Interrupt  
This bit is set to ’1’, if the internal timer was activated and has expired
(refer also to description of timer registers TIMR0..TIMR3).
CSC CTS Status Change  
This bit is set to ’1’, if a transition occurs on signal CTS. The current state
of signal CTS i s monitored  by status bit ’CTS’ in status register STARL.

PEB 20525

PEF 20525

Regist er Description (ISR2)

Preliminary Data Sheet 5-192 09.99

XMR Transmit Message R epeat

This b it is set to ’ 1’, i f t rans mission of t he last f rame has t o be repeated

(by software) , beca use

• the SCC has received a negative acknowledge to an I-frame (in HDLC

Automode oper ation);

• a collision occured after at least 31 bytes of data have been

completely sent out, i.e. automatic re-transmission cannot be

performed by the SCC;

•CTS

signal w as deasserted after at le ast 31 b y tes of dat a hav e been

compl et ely sent out.

Note: For easy recovery from a collision event (in bus configuration

only), the SCC transmit FIFO should not contain more than one

complete frame. This can be achieved by using the ’ALLS’

interrupt to control the corresponding transmit channel forwarding

a new frame on all sent (ALLS) event only.

XPR Transmit Pool Ready Interrupt

This bit is set to ’1’, if a transmitter reset command was executed

successfully (command bit ’XRES’ in register CMDRL) and whenever

the XFIFO is able to accept new transmit data again.

An ’XPR’ interrupt is not generated, if no sufficient transmit clock is

available (depending on the selected clock mode).

ALLS ALL Sent Interrupt

This bit is set to ’1’:

• if the last bit of the current HDLC frame is sent out via pin TxD and no

further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO

is empty (Address Mode 2/1/0);

• if an I-frame is sent out completely via pin TxD and either a valid

acknowledge S-frame has been received or a time-out condition

occured because no valid acknowledge S-frame has been received in

time (Autom ode) .

PEB 20525

PEF 20525

Regist er Description (ISR2)

Preliminary Data Sheet 5-193 09.99

XDU Transmit Data Underrun Interrupt

This bit is set to ’1’, if the current frame was terminated by the SCC with

an abort sequence, because neither a ’frame end’ indication was

detected in the FIFO (to complete the current frame) nor more data is

available in the SCC transmit FIFO.

Note: The transmitter is stopped if this condition occurs. The XDU

condition MUST be cleared by reading register ISR1, thus bit

’ XDU’ s h ould not be mask e d vi a reg ister IMR1.

SUEX Signalling Unit Count er Exceed ed Interrupt

This bit is set to ’1’, if 256 correct or inco rre ct SU’s have bee n received

and the internal counter is reset to 0.

PLLA DPLL Asynchronous Interrupt

This bit is only valid, if the receive clock is derived from the internal DPLL

and FM0, FM1 or Ma nchester data encoding is selected (dep ending o n

the selected clock mode and data encoding mode). It is set to ’1’ if the

DPLL has lost synchronization. Reception is disabled until

synchronization has been regained again. If the transmitter is supplied

with a clock derived from the DPLL, transmission is also interrupted.

CDSC Carrier Detect Status Change Interrupt

This bit is s et to ’1’ , if a stat e t rans ition has been de tected at signal CD .

Because only a state transition is indicated via this interrupt, the current

status can be evalu at e d by readin g bi t ’CD’ in status regi s te r STARH.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-194 09.99

Reg ister 5-7 5 I MR0

Interrupt Mask Register 0

CPU Acc e ssibilit y : read/write

Reset Value: FFH

Channel A Channel B

Offs et Address: 54HA4H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

IMR0

RDO RFO PCE RSC RPF RME RFS FLEX

Reg ister 5-7 6 I MR1

Interrupt Mask Register 1

CPU Acc e ssibilit y : read/write

Reset Value: FFH

Channel A Channel B

Offs et Address: 55HA5H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

IMR1

TIN CSC XMR XPR ALLS XDU SUEX 1

PEB 20525

PEF 20525

Preliminary Data Sheet 5-195 09.99

Reg ister 5-7 7 I MR2

Interrupt Mask Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 03H

Channel A Channel B

Offs et Address: 56HA6H

typical usage: written by CPU;

read and evaluated by PASSAT

Bit76543210

IMR2

000000PLLACDSC

PEB 20525
PEF 20525
Register Description  (IMR 2)
Preliminary Data Sheet  5-196 09.99
 
(IM) Interr upt Mask Bits  
Each SCC interrupt event can generate an interrupt signal indication via 
pin INT/INT. Each bit position of registers IMR0..IMR2 is a mask for the 
corresponding interrupt event in the interrupt status registers 
ISR0..ISR2. Masked interrupt events never generate an interrupt 
indication via pin INT/INT.
bit = ’0’ The corresponding interrupt event is NOT masked and will 
gener ate an interrup t indication vi a pin INT/INT.
bit = ’1’ The corresponding interrupt  event is masked and will 
NEIT HE R generate an inter rupt vect or NOR an interrupt 
indication via pin INT/I NT.
Moreover, masked interrupt events are:
• not di spl ayed i n the  interrupt  status r egi ste rs ISR0..ISR2 if bit ’VIS’ in
register CCR0L is progr amm ed t o ’0’.
• displayed in interrupt status registers ISR0..ISR2 if bit ’VIS’ in register
CCR0L is programm ed to ’1’.
Note: After RESET, all interrupt events are masked.
For detailed interrupt event description refer to the corresponding bit
position in registers ISR0..ISR2.

PEB 20525

PEF 20525

Registe r Description (RSTA)

Preliminary Data Sheet 5-197 09.99

The Receive Status Byte ’RSTA’ contains comprehensive status information about the

last received frame (HDLC/PPP).

The SCC attaches this status byte to the receive d ata and thus it should be read from

the RFIFO.

In HDLC/PPP modes the RSTA value can optionally be read from this register address.

In extended t rans pare nt mode this status field does not apply.

Reg ister 5-78 RSTA

Receive Status Byte

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: 58HA8H

typical usage: written by PASSAT to RFIFO;

read from RFIFO and evaluated by CPU

Bit76543210

Receive Status Byte

VFR RDO CRCOK RAB HA(1:0)/

SU(1:0) C/R LA

PEB 20525

PEF 20525

Registe r Description (RSTA)

Preliminary Data Sheet 5-198 09.99

VFR Valid Frame

Determines whether a valid frame has been received.

VFR=’0’ The received frame is invalid.

An invalid frame is either a frame which is not an integer

numb er of 8 bits (n * 8 bits) in length (e.g. 25 bits), or a

frame which is too short, taking into account the operation

mode selected via CCR2L (M DS 1 , MDS0, ADM) a nd the

selected CRC alg orithm (CCR1L:C32 ) as follows:

for CCR3H:DRCRC = ’0’ (CRC recep tion enabled):

• automode / address mode 2 (16-bit address)

4 bytes (CRC-CCITT) or 6 (CRC-3 2 )

• aut omo de / address mo de 2 (8-bit address )

3 bytes (CRC-CCITT) or 5 (CRC-3 2 )

• addr ess m ode 1:

3 bytes (CRC-CCITT) or 5 (CRC-3 2 )

• addr ess m ode 0:

2 bytes (CRC-CCITT) or 4 (CRC-3 2 )

for CCR3H:DRCRC = ’1’ (CRC r ecep tion disable d ):

• aut omo de / address mo de 2 (16-bit addres s):

2bytes

• aut omo de / address mo de 2 (8-bit address ):

1 byte

• addr ess m ode 1:

1 byte

• addr ess m ode 0:

1 byte

Note: Shorter frames are not reported at all.

VFR=’1’ The received frame is valid.

RDO Receive Data Overflow

RDO=’0’ No receive data overflo w has occurr ed.

RDO=’1’ A data overflow has occurred during reception of the

frame. Additionally, an interrupt can be generated (refer to

ISR0:RDO/IMR0:RDO).

PEB 20525
PEF 20525
Registe r Description (RSTA)
Preliminary Data Sheet  5-199 09.99
 
CRCOK CRC Compare/Check  
CRCOK=’0’ CRC check failed, receive d frame contains errors.
CRCOK=’1’ CRC check OK; the received frame does not contain CRC 
errors.

PEB 20525

PEF 20525

Registe r Description (RSTA)

Preliminary Data Sheet 5-200 09.99

C/R Command/Response

Significant only if 2-byte address mode has been sel ect ed.

Value of the C/R bit (b it 1 of high address byte) in the received fram e.

The interpretation depends on the setting of the ’C RI’ bit in the RAH1

LA Low Byte Address Compare

Significant in automode and address mode 2 only.

The low byte address of a 2-byte address field, or the single address byte

of a 1-byte address field is compared with two addresses (RAL1, RAL2).

LA=’0’ RAL2 has been recognized.

LA=’1’ RAL1 has been recognized.

According to the X.25 LAPB protocol, RAL1 is interpreted as the address

of a COMMAND frame and RAL2 is interpreted as the address of a

RESPONSE frame.

PEB 20525

PEF 20525

Registe r Description (RSTA)

Preliminary Data Sheet 5-201 09.99

5.2.3 Channel Specific DMA Registers

Each regist er desc ription is organized in three parts:

• a head with gene ral inf ormation about reset value, access type (read/ write), channel

specific offset address and usual handling;

• a table containing the bit information (name of bit positions);

• a section containing the detailed description of each bit.

PEB 20525

PEF 20525

Registe r Description (XBCL)

Preliminary Data Sheet 5-202 09.99

Reg ister 5-79 XBCL

Transmit Byte Count (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: B8HD2H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

XBC(7:0)

Reg ister 5-80 XBCH

Transmit Byte Count (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: B9HD3H

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

XME XF XIF 0 XBC(11:8)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-203 09.99

XBC

(11:0) Transmit Byte Count

This register is used in DMA Mode only, to program the length (1…4096

bytes) of the next frame to be transmitted. The length of the block in

number of bytes is:

This allows the PASSAT to request the cor rect amount of DMA cycles

after an ’XF’ or’ XIF’ comman d.

XME Transmit Message End Command

Only valid in ext ern al DMA controller mode.

This bit is identical to ’XME’ command bit (refer to register "CMDRL" on

page 5-132).

XF Transmit Frame Comm and

Only valid in ext ern al DMA controller mode.

This bit is ide ntical to ’XF’ comma nd bit (refer to register "CMDRL" on

page 5-132).

XIF Transmit I-Frame Command

Only valid in ext ern al DMA controller mode.

This bit is ide ntical to ’XIF’ command bit (ref er to register "CM DRL" on

page 5-132) .

Length XBC 1

PEB 20525

PEF 20525

Preliminary Data Sheet 5-204 09.99

Reg ister 5-8 1 R M B SL

Receive Maximum Buffer Size (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: C4HDEH

typical usage: written by CPU, evaluated by PASSAT

Bit76543210

Receive Maximum Buffer Size

RMBS(7:0)

Reg ister 5-8 2 R M B SH

Receive Maximum Buffer Size (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: C5HDFH

typical usage: written by CPU, evaluated by PASSAT

Bit151413121110 9 8

Receive Maximum Buffer Size

RE DRMBS 0 0 RMBS(11:8)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-205 09.99

RE Receive DMA Enable

Only valid if external DMA controller support is enabled.

Self-clearing com ma nd bit:

RE=’0’ The DMA controller is not set up to forward receive data

into a buffer in memory .

RE=’1’ Setting this bit to ’1’ enables the DMA support logic to

request the external DMA controller to transfer receive

data when avai labl e in RFIFO.

DRMBS D isable Receive Max imum Buffer Size (RMBS) Check

Only valid if external DMA controller support is enabled.

DRMBS=’0’ Evalu ation of bit field RMBS(11:0) is enable d.

DRMBS=’1’ Evalu ation of bit field RMBS(11:0) is disab led.

RMBS(11:0) Receive Maxim um Buffer Size

Only valid if external DMA controller support is enabled.

The size of the receive buffer in host memory can be set up in this bit field

to ensure that request for DMA transfers are inhibited w hen the

maximum buffer size is reache d. An RBF interrupt is generated (if

unmasked ) to inform the CPU. If the external DMA controller supp orts

this function, it can be disabled by setting bit ’DRMBS’ to ’1’.

PEB 20525

PEF 20525

Preliminary Data Sheet 5-206 09.99

Receive Byte Count (Low Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: C6HE0H

typical usage: written by PASSAT, evaluated by CPU

Bit76543210

RBC(7:0)

Receive Byte Count (High Byte)

CPU Acc e ssibilit y : read/write

Reset Value: 00H

Channel A Channel B

Offs et Address: C7HE1H

typical usage: written by PASSAT, evaluated by CPU

Bit76543210

RDO 0 0 0 RBC(11:8)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-207 09.99

RBC(11:0) Receive Byte Count

This bit field determines the receive byte count (1..4095) of the currently

received frame/block.

RDO RDO Indication

Only valid in DMA controller mode.

This bit is identical to the ’RDO’ status bit belonging to this frame (see

description of register "RSTA" on page 5-197).

PEB 20525

PEF 20525

Preliminary Data Sheet 5-208 09.99

5.2.4 Miscella n eous Registers

Reg ister 5-85 VER0

Version Register 0

CPU Acc e ssibilit y : read/write

Reset Value: 83H

Offs et Address: ECH

typical usage: evaluated by CPU

Bit76543210

Manufacturer Code Fix ’1’

VER(7:0)

Reg ister 5-86 VER1

Version Register 1

CPU Acc e ssibilit y : read/write

Reset Value: F0H

Offs et Address: EDH

typical usage: evaluated by CPU

Bit76543210

Device Code (bi ts 3 .. 0) Manufacturer Code

VER(15:8)

PEB 20525

PEF 20525

Preliminary Data Sheet 5-209 09.99

Reg ister 5-87 VER2

Version Register 2

CPU Acc e ssibilit y : read/write

Reset Value: 05H

Offs et Address: EEH

typical usage: evaluated by CPU

Bit76543210

Device Code (bits 11 .. 4)

VER(23:16)

Reg ister 5-88 VER3

Version Register 3

CPU Acc e ssibilit y : read/write

Reset Value: 10H

Offs et Address: EFH

typical usage: evaluated by CPU

Bit76543210

Versi on Number Device Code (bits 15 .. 12)

VER(31:24)

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Preliminary Data Sheet 5-210 09.99

VER(31:0) Version Register

Identical to 32 bi t bounda ry scan ID string.

The 32 bit string consists of the bit fields:

VER(31:28) 1HVe rsion Number

VER(27:12) 005FHDevi ce Co de

VER(11:0) 083HM anu fac turer Code (LSB fixed to ’1’)

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Programming
Preliminary Data Sheet  6-211 09.99
 6 Programming
6.1 Initialization
After Reset the CPU has to write a minimum set of registers and an optional set
depending on the required features and operating modes.
F irst, the following initializat ion steps must  be taken:
• Select  serial protocol  m ode ( refer to Tabl e 4- 1 "Proto col  Mode  Ov erview"  on page 4-
80), 
• Select  encoding of the  serial dat a (refer to Chapter  3.2.13  "Data Encoding"  o n page
3-71),
• Program the output characteristics of 
- pin TxD (selected with bit ’ODS’ in "Channel Configuration Register 1 (Low Byte)" on
page 5-139)  and 
- interrupt pin INT/INT (selected with bi t fie ld ’IPC(1:0)’ in "Global Mode R egister " on
page 5-109),
• Choose a cl ock mo de (refer to Table 3-1 "Overview  of Clock Modes" on page 3-44).
• Power-up the oscillator  unit (with or without shaper) by re-setting bit  GMODE:OSCPD
to ’0’, if appropriate (GMODE:DSHP= ’0’ enables the shaper ).
The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the
PASSAT between power-up and power-down mode. This has no influence upon the
contents of the registers, i.e. the internal state remains stored. In power-down mode
how ever, all inte rnal clocks ar e disab led, no interrup ts from  the corres ponding c hannel
are forwarded to the CPU.  This state can be used as a standby mode, when the channel
is (tem por arily) not  used, thus subst ant ia lly redu cin g powe r consu mpti on.
The PASSAT should usually be initialized in Power-Down mode.
The need for programming further registers depends on the selected features (serial
mode , clock mo de speci fic features,  operating mod e, address mode, user demands) .
6.2 Inter rupt Mode
6.2.1 Data Transmission (Interrupt Driven)
In transmit direction 2 × 32 byte FIFO buffers (transmit pools) are provided for each
channel .  After checking  the XFIFO status by polling the Transm it FIFO Wr ite Enable bit
( bi t ’XF W ’ in STARL reg ister ) or af te r a  Tran smit  Pool R eady (’XPR’) inte rrupt, up to 32
byte s may be entered  by the CPU into the XFIFO.
The transmission of a packet can be started by issuing an ’XF’ or ’XIF’ command via the
CMDRL register. If enabled, a specified number of preambles (refer to registers CCR2H
and PREAMB) are sent out optionally before transmission of the current packet starts. 

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Programming

Preliminary Data Sheet 6-212 09.99

If the transmit command does not include an end of message indication (CMDRL.XME),

PASSAT will repeat edly req uest for the next data block by means of an ’XPR’ interrup t

as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is

accessible to the CPU.

This process will be repeated until the CPU indicates the end of message per ’XME’

command, after which packet transmission is finished correctly by appending the CRC

and closing flag sequence. Consecutive packets may be transmitted as back-to-back

packets and may even share a flag (enabled via CCR1L.SFLG) , if s ervice of XFI FO is

quick enough .

In case no more data is available in the XFIFO pr ior t o the arrival of the end-of-message

indiction (’XME’), the transmission of the packet is terminated with an abort sequence

and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet

ma y also be aborte d per softwar e at any time (CMDRL.XRES).

The data transmission sequence, from the CPU’s point of view, is outlined in Figure 6-1.

Figure 6-1 Interrupt Driven Data Transmission (Flow Diagram)

START

XFIFO

READY

'X P R ' In te rr up t

R e s e t T ra n smitte r

(CMDRL.XRES)

Wr ite Da ta to

XFIFO

(u p to 32 b yte s )

End of Messa

Yes

Issue Com m and

CMDRL.XF+.XME

CMDRL.XIF+.XME

Issue Com m and

CMDRL.XF

CMDRL.XIF

A c tion ta k e n

by C PU

Interrupt

in dic a tion to CPU

T ransmit serial

data and

append trailer

T ransmit serial

data

A c tion ta k e n

by the SC C

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Programming
Preliminary Data Sheet  6-213 09.99
 
6.2.2 Data Reception (Int errupt D riven)
Also 2 × 32 byte FI FO buffers (recei ve pools) are prov ided for each  channel in recei ve
direction.
There are different interrupt indications concerned with the reception of data:
•’RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited
with the receive FI FO threshold in register CCR3H, bit  field ’RFTH(1..0)’; default  is 32
bytes) can be read from RFIFO and the received message is not yet complete.
•’RME’ (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
- one message which fits into RFIFO not exceeding the receive FIFO threshold, or 
- the last part of a message, all in all exceeding the receive FIFO threshold 
is stored in the RFIFO.
In addition to the message end (’RME’) interrupt the following information about the
received  packet  is stored by PASSAT in special registers and/or  RFIFO:
Note: After the received data has been read from the RFIFO, this must be explicitly
acknowledged by the CPU issuing an ’RMC’ (Receive Message Complete)
command. The CPU has to handle the ’RPF’ interrupt before the complete 2 x 32-
byte FIFO is filled up with receive data which would cause a “Receive Data
Overflow” condition.
T he data reception  sequence, from the CPU’s point of view, is outlined in Figure 6-2.
T able 6-1 Status Information after RME interupt
Status  In f o rmation Location
Length of received message registers RBCH, RBCL
CRC result ( good/bad) RSTA register (or  last byte of received data)
Valid frame (yes/no) RSTA register (or  last byte of received data)
ABORT sequence reco gnized (yes /no ) RSTA register (or last byte of received data)
Data over flow (yes /no) RSTA register (or last byte of received data)
Results from address comparison
(with aut oma tic address handl i ng) RSTA register (or last byte of received data)
Type of frame (COMMAND/RESPONSE)
(with aut oma tic address handl i ng) RSTA register (or last byte of received data)
T ype of Signaling Unit
(in SS7 mode) RSTA register (or  last byte of received data)

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Programming

Preliminary Data Sheet 6-214 09.99

1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field

RFTH(1:0) in re gister .

2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register (depending

on the selected r eceive threshold RFTH(1:0)).

Figure 6-2 I nt errupt Driven Data Reception (Flow Diagram)

START

WAIT F O R

INTERRUPT

Reset Receiver

(CMDRH.RRES)

A c tiva te R e c e ive r

(CCR3L.RAC)

A c tion ta k e n

by C PU

Interrupt

in dic a tio n to CP U

'RPF'

Interrupt

Read

[32]

b yte s fro m RF IF O

Release RFIFO

(CMDRH.RMC)

Read re

isters

RBCL, RBCH

(Rc Byte C ount)

'RME'/'TCD'

Interrupt

Read

[R B CL % 3 2]

1), 2)

b yte s fro m RF IF O

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Programming

Preliminary Data Sheet 6-215 09.99

6.3 External DMA Suppor ted Mode

The following table provides a definition of terms used in this chapter to describe the

opera tion with external DM A cont roller suppo rt.

6.3.1 Data Transmission (With External DMA Support)

Any packet transm is sion is prepar ed by initializing the external DMA control ler with t he

tr ansm it buffer st art addres s and wr itin g the packet size i n numb er of byt es to registers

XBCL/XBCH.

Now there are two possible scenarios:

• If the prepared transmit buffer in memory contains a complete packet, the start

command for DMA transmission is issued by setting bits ’XF’ and ’XME’ in register

XBCH to ’1’. The DMA support logic will request the external DMA controller to

transfer data into the XFIFO . After the last byte has been transmitted, the protocol

machine appends the trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit

DMA Transfer End (TDTE) interrupt is generated (ref er to Figure 6-3).

• If a transmit pac ket is d istributed over mor e than one transm it buf fer in memor y, the

’XF’ command (without setting the ’XME’ bit) forces PASSAT to request data transfers

from the external DMA controller from this buffer. A Transmit DMA Transfer End

T able 6-2 DMA Terminology

Packet A "Packe t" is a connected block of data bytes. If a receive

status byte (RSTA) is attached to data bytes, it is also

considered as par t of the packet.

Buffer A "Buffer" is a limited space in memory that i s r eserved for

DMA reception/transmission. PASSAT can optionally keep

track of predefined (recei ve) buffer limits and notify the

CPU with an appropriate interrupt if this functionality is not

provided by the extern al DMA controller .

A packet can go into one single buffer, or it can go

fragmented into mu ltiple buffers.

Block A "B lock" is the amoun t of data that is transfered from the

memory to the XFIFO ( transmi t DMA transfer) or from the

RFIFO to the memory. The bl ock size is 32 bytes by

default. It can be lowered with the receive FIFO threshol d

in register CCR3H, bit field ’RFT H(1..0)’.

Bus Cycle A "Bus Cycle" corresponds to a single byte/word transfer.

Multiple bus cycles make up a block transfer.

DMA Transfer A "DM A Transfer" is the move ment of complet e buffers

and/or packets between the XFIFO/RFIFO and the

memory by the external DMA controller.

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Programming

Preliminary Data Sheet 6-216 09.99

(TDTE) interrupt is generated whenever a block of <XBC> bytes is completely

transferred. For the last buffer, containing the end of the transmit packet, the ’XF’

comm and is issue d together with bit ’XME’ set (refer to Figure 6- 4).

After transmission is complete, the optional generation of the ALLS interrupt indicates

that all transmit data has been sent on pin TxD.

Note: In HDLC Automode, the ’XF’ command may be replaced by the ’XIF’ command in

the same register, when transm i ssion of an I-frame is desired .

Figure 6-3 DMA Transmit (Single Buffer per Packet)

XBC

(prepare external D MA contro ller

with buffer base address)

(wr ite transmit byte count with

command bit 'XF'+'XME')

...

TFIFO

DMA transfer of

<XBC> transmit data

bytes

TDTE interrupt

ALLS interrupt (optional)

XBC

(write transmit byte count with command

bit 'XF'+'XME')

...

Packet n:

Packet (n+1):

(prepare external D MA contro ller

with buffer base address)

CPU / M EMORY PASSAT

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Programming

Preliminary Data Sheet 6-217 09.99

Figure 6-4 Fragmented DMA Transmission (Multiple Buffers per Packet)

XBC

(write transm it byte count with

command bit 'XF')

...

TFIFO

DMA transfer of

<XBC> transmit data

bytes

TDTE interrupt

ALLS interrupt (optional )

XBC

(write transm it byte count with command

bit 'XF')

...

TFIFO

DMA transfer of

<XBC> transmit data

bytes

TDTE interrupt

XBC

(write transm it byte count with command

bit 'XF'+'XME')

...

TFIFO

DMA transfer of

<XBC> transmit data

bytes

TDTE interrupt

Packet n, Buffer 0:

Packet n, Buffer 1:

Packet n, Buffer m:

(prepare exte rnal DMA control ler

with buffer base address)

(prepare exte rnal DMA control ler

with buffer base address)

(prepare exte rnal DMA control ler

with buffer base address)

CPU / MEMORY PASSAT

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Programming
Preliminary Data Sheet  6-218 09.99
 
6.3.2 Data Reception (With Ex ternal DMA Support)
The receive DMA support logic is able to limit its re questing for data transfers  to a byte
count programmed in register RMBSL/RMBSH.  If the external DMA controller is capable
of handli ng maximu m receive buf fer sizes  itself, this featu re can be dis abled by set ting
bit RMBSH:DRMBS to ’1’. 
If a new  pac ket  is  received  by t he SC C , the DM A support logic  w i ll request  th e ext erna l
DMA controller to move recei ve data out of the RFIFO. 
Now t here  are two possibl e scenar i os:
• If the maximum buffer size programmed in register RMBSL/RMBSH has been
transferred (only if RMBSH:DRMBS = ’0’), PASSAT stops requesting for data
transfers and a Receive Buffer Full (RBF) interrupt is generated. The CPU now
updates  the recei ve buff er bas e addr ess i n the  external D MA co ntroller and releases
the receive DMA control logic by setting the ’RE’ bit in register RMBSH. Optionally the
maximum buffer size value can be updated with the same register write access.
• If the end of a received packet/block is part of the curent DMA transfer, PASSAT
generates a Receive DMA Transfer End (RDTE) interrupt and stops operation. The
CPU now reads the received byte count from registers RBCL/RBCH. The receive
DMA support logic will not continue requesting for data transfer until it is set up again
with the ’RE’ command in  register RMBSH. 
If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size
RMBS is chosen to be larger than the expected receive packets, each buffer will  contain
the whole packet (see Figure 6-5). In this case (or if RMBSH:DRMBS = ’1’) a  Receive
Buffer Full (RBF) interrupt will never occur, simplifying the software. To ensure that no
packets exceeding the maximum buffer size are forwarded from the SCC to the RFIFO,
the receive packet length should be limited with registers RLCRL/RLCRH.

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Programming

Preliminary Data Sheet 6-219 09.99

Figure 6-5 DMA Receive (Single Buffer per Packet)

Figure 6-6 shows an example for fragmented reception of a packet larger than the

prepared receive buffers in memory. In this case the length of the received packet is 199

bytes, each of the buffers in host memory is 128 bytes deep:

RMBS

(prepare exter nal DMA contr oller

with receive buffer start address)

...

RFIFO

DMA transfer of all

receive data bytes

RDTE interrupt

...

Pack et 0:

Pack et 1:

RBC

(read RBC register)

(set m ax. receive buffer size

and issue 'RE' command)

(prepare exter nal DMA contr oller

with receive buffer start address)

CPU / MEMORY PASSAT

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Programming

Preliminary Data Sheet 6-220 09.99

Figure 6-6 Fragmented Reception per DMA (Example)

After the external DMA controller is initialized with the base address of receive buffer #1

and the maximum buffer size RMBS is written to PASSAT, simultaneously activated with

the ’RE’ command, requesting of DMA transfer from the RFIFO to the receive buffer

takes place in blocks of 32 bytes (unless changed with bit field ’RFTH’ in register

CCR3H).

After four 32-byte-blocks have been transferred, the first receive buffer is filled up

completely with receive data. The PASSAT indicates this by generating the RBF

interrupt.

Now the CPU has to provide the base address of the second receive buffer to the

external DMA controller and issue the ’RE’ command to PASSAT again. This allows the

external DMA cont rolle r to cont inue data tra nsfers into the secon d receive b uffer. After

another two 32-byte-blocks have been transferred, the DMA request for the remaining 7

bytes (inc lud ing the RSTA byte ) is generated to the ext er nal D MA co ntrol ler, foll wed by

the generation of the RDTE inte rrupt. Now the DM A transf er is compl et ed and sof t ware

has to read the number of received bytes from the Receive Byte Cou nt registers RBCL/

RBCH.

The following figure (Figure 6-7) gives the sequence of actions from both, the PASSAT

and the CPU for this example (fragmented reception of 199 bytes into two receive

buffers):

32 32 32 32 32 32 7

128

...

199 Bytes Payload

128

1st packet

fragment 2nd packet

fragment

...

Receive Buffe rs

in Memory

Packet

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Programming

Preliminary Data Sheet 6-221 09.99

F igure 6-7 Fr agme nted Recept ion Sequence (Example)

RMBS

(issue 'RE' command)

RFIFO

DMA transfer of 128

receive data bytes

RBF interrupt

...

Pack et 1, Fragment 1:

Pack et 2, Fragment 1:

RBC

(read RBC register)

RFIFO

DMA transfer of 71

receive data bytes

RDTE interrupt

Pack et 1, Fragment 2:

RFIFO

RMBS

(set max. receive buffer size to 128 bytes

and issue 'RE' comm and)

(prepare exter nal DMA contr oller

with receive buffer start address)

(prepare exter nal DMA contr oller

with receive buffer start address)

(prepare exter nal DMA contr oller

with receive buffer start address)

CPU / MEMORY PASSAT

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-222 09.99

7 Electrical Characteristics (Preli minary)

All electrical characteristi cs giv en in this chapter are preliminar y and subject to change .

7.1 Absolut e Maximum Rat ings

Note: Stresses above those listed here may cause permanent damage to the

device. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

7.2 Operating Range

Note: In the operating range , the functions given in the circuit descri ption are fulfilled.

Parameter Symbol Limit Values Unit

Ambient temperature under bias PEB

PEF TA

0 to 70

– 40 to 85 °C

°C

Storage temperature Tstg – 65 to 125 °C

IC supply volta ge VDD3 – 0.3 to 3.6 V

Voltage on any signal pin with respect to

ground VS– 0.3 to 5.5 V

ESD robustness1)

HBM: 1.5 kΩ, 100 pF

1) According to MIL-St d 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.

VESD,HBM 2500 V

Parameter Symbol Limit Values Uni t Test Condition

min. max.

Ambient temperaturePEB

PEF TA

-40 70

85 °C

°C

Junction temper atu re TJ0125

°C

Supply voltage VDD3 3.0 3.6 V

Ground VSS 00V

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-223 09.99

7.3 Therm al Package Characteristics

T able 7-1 Therma l Package Character istics P-TQFP-100 -3

Parameter Symbol Value Unit

T hermal Packa ge Resistance Junct ion to Ambient

Airflow: Ambient Temperature:

without airflow T A=-40°C θJA(0,-40) 45.7 K/W

without airflow TA=+25°C θJA(0,25) 41.5 K/W

airflow 1 m/s (~200 lfpm) TA=+25°C θJA(1,25) 39.6 K/W

airflow 2 m/s (~400 lfpm) TA=+25°C θJA(2,25) 38.8 K/W

airflow 3 m/s (~600 lfpm) TA=+25°C θJA(3,25) 38.4 K/W

T able 7-2 Therma l Package Character istics P-LFBGA-80- 2

Parameter Symbol Value Unit

T hermal Packa ge Resistance Junct ion to Ambient

Airflow: Ambient Temperature:

without airflow T A=-40°C θJA(0,-40) 56.1 K/W

without airflow TA=+25°C θJA(0,25) 50.6 K/W

airflow 1 m/s (~200 lfpm) TA=+25°C θJA(1,25) 48.2 K/W

airflow 2 m/s (~400 lfpm) TA=+25°C θJA(2,25) 47.2 K/W

airflow 3 m/s (~600 lfpm) TA=+25°C θJA(3,25) 46.6 K/W

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-224 09.99

7.4 DC Characteristics

Parameter Symbol Limit Values Uni t Notes

min. max.

In put low vo lta ge VIL – 0.4 0. 8 V

Input high voltage VIH 2.0 5.5 V

Output low voltage VOL 0.45 V IOL =7mA

IOL =2mA

1) Apply to the next pins:

tbd

2) Appl y to all the I/O and O pins that do not appear in th e list in note 1), except

tbd

The listed characteristics are ensu red o ver the ope rating range of the integrated

circuit. Typic al characterist ics specify m ean values e xpected o ver the production

spread. If no t otherw is e specified, typical char acteristics app ly at

= 25

C and

the given supply voltage.

Output high voltage VOH 2.4 V IOH =–1.0mA

Power

supply

current

operational

(average) ICC (AV)

tbd

mA VDD =3.3V,

TA=25°C,

CLK = 20 MHz,

XTAL = 20 MHz,

inputs at VSS/VDD,

no output loads

power down

(no clocks) ICC (PD)

tbd

mA VDD =3.3V,

TA=25°C

Power dissipat ion P100 mW VDD =3.3V,

TA=25°C,

CLK = 20 MHz,

XTAL = 20 MHz,

inputs at VSS/VDD,

no output loads

Input leakage current IIL

tbd

µAVDD =3.3V,

GND = 0 V;

inputs at VSS/VDD,

no output loads

Output leakage cur rent IOZ

tbd

µAVDD =3.3V,

GND = 0 V;

VOUT =0V,

VDDP +0.4

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-225 09.99

7.5 AC Characteristics

Interface Pins

TA = 0 to + 70 °C; VDD3 = 3.3 V ± 0.3 V

Inputs are driven to 2.4 V for a logical “1” and to 0.4 V for a logical “0”. Timing

meas urem ents are made at 2.0 V for a logical “1” and at 0.8 V for a logical “0”.

The AC testing input/output waveforms are shown below.

Figure 7-1 Input/Output Waveform for AC Tests

7.6 Capacitances

Interface Pins

T able 7-3 Capacitances

TA = 25 °C; VDD3 = 3.3 V ± 0.3 V, VSS = 0 V

Parameter Symbol Limit Values Unit Test Condition

min. max.

Inpu t capac itance CIN

tbd tbd

Output capacitance COUT

tbd tbd

I/O-capacitance CIO

tbd tbd

ITS09800

= 50 pF

Load

Test

Under

Device

0.45

2.4 2.0

0.80.8

2.0 Test Points

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-226 09.99

7.7 T imin g Diagr am s

7.7.1 Microprocessor Interface Timing

7.7.1.1 Microprocessor Interface Clock Timing

Figure 7-2 Microprocessor Interface Clock Timing

Table 7-4 Microprocessor Interface Clock Timing

No. Parameter Limit Values Unit

min. max.

1 CLK clock period 30 ns

CLK frequency 33 MHz

2 CLK high time 11 ns

3 CLK lo w time 11 n s

CLK

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-227 09.99

7.7.1.2 Siemens/Intel Bus Interface Timing

•

F igure 7-3 Si em ens/Int el Read Cycle Timing

•

Figure 7-4 Siemens/Intel Write Cycle Timing

(1) Signals BHE and D(15:8) only av ailable in 16-bit Intel bus mode

(2) Interrupt signal show n is push-pull, active high. Same timings apply to push-pull, active low interru pt signal. In

case of open-drain output the timing depends on external components.

A(7:0)

BHE

)

D(7:0)

D(15:8)

)

DTACK

4657

14a 15a

11a

INT

)

14 15

A(7:0)

BHE

)

D(7:0)

D(15:8)

)

DTACK

4657

12 13

14a 15a

14 15

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-228 09.99

Table 7-5 Siemens/Intel Bus Interface Timing

No. Parameter Limit Values Unit

min. max.

4 active addres s to activ e RD/WR setup time 10 ns

5 inactive RD/WR to inactive address hold time 0 ns

6active CS

to active RD/WR setup time 0 ns

7 inactive RD/WR to inactive CS hold ti m e 0 ns

8RD

active pulse width tbd ns

9WR

active pulse width 30 ns

10 active RD to valid data delay 15 ns

11 inactive RD to invalid data hold time 5 ns

11a inactive RD to data high impedance delay 15 ns

12 valid data to inactive WR setup time 15 ns

13 inactive WR to invalid data hold time 5 ns

14 active RD/WR to active DTACK delay 10 ns

14a active CS to driven DTACK delay tbd ns

15 inactive RD/WR to in active DTACK delay 10 ns

15a inactive CS to DTAC K high impedance del ay tbd ns

16 inactive RD to inactive INT/INT delay 1 TCLK

17 RD/WR in a c tive pul se wid th tbd ns

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-229 09.99

7.7.1.3 Motorola Bus Interface Timing

•

Figure 7-5 Motorola Read Cycle Timing

•

F igure 7-6 M otorola Write Cycle Timing

(1) Signals LDS , UDS and D(15:8) only available in 16-bit Motorola bus mode

(2) Interrupt signal show n is push-pull, active high. Same timings apply to push-pull, active low interru pt signal. In

case of open-drain output the timing depends on external components.

A(7:0)

A(7:1)

)

R/W

D(7:0)

D(15:8)

)

LD S, UD S

)

DTACK

44 45

52a 53a

INT

)

49a

52 53

A(7:0)

A(7:1)

)

R/W

D(7:0)

D(15:8)

)

LD S, U DS

)

DTACK

44 45

50 51

52a 53a

52 53

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-230 09.99

Table 7-6 Motorola Bus Interface Timing

No. Parameter Limit Values Unit

min. max.

40 act ive address to active DS setup time 10 ns

41 inactive DS to inactive address hold time 0 ns

42 active CS to active DS setup tim e 0 ns

43 inactive DS to inactive CS hold time 0 ns

44 active R/W to active DS setup time 0 ns

45 inactive DS to inactive R/W hold time 0 ns

46 DS ac tive pulse w idth (read acces s) tbd ns

47 DS ac tive pul se width (writ e access) 3 0 ns

48 active DS (read) to valid data delay 15 ns

49 inactive DS (read) to invalid data hold time 5 ns

49a inactive DS (read) to data high impedance delay 15 ns

50 valid data to inactive DS (write) setup time 15 ns

51 inactive DS (write) to invalid data hold time 5 ns

52 active DS to active DTACK delay 10 ns

52a active CS to driving DTACK delay tbd ns

53 inactive DS to inactive DTACK delay 10 ns

53a inactive CS to DTAC K high impedance del ay tbd ns

54 inactive DS (read) to inactive INT/INT del ay 1 T CLK

55 DS inactive pulse width tbd ns

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-231 09.99

7.7.2 PCM Serial Interface Timing

7.7.2.1 Clock Input Timing

F igure 7-7 C lock Input Timing

T able 7-7 Clock Input Timing

No. Parameter Limit Values Uni t

min. max.

81 RxCLK clock period tbd ns

82 RxCLK high t ime tbd ns

83 RxCLK low tim e tb d ns

84 TxCLK cl ock per i od tb d ns

85 Tx C LK hi gh ti m e tbd ns

86 TxCLK low time tbd ns

87 XTAL1 clock period (interna l oscillator used) t bd ns

XTAL1 clock period (TTL clock signal suppl i ed) tbd ns

88 XTAL1 high time (internal oscillator used) tbd ns

XTAL1 high time (TTL clock signal suppli ed) tbd ns

89 XTAL1 low time (internal oscillator used) tbd ns

XTAL1 low time (TTL clock signal supplied) tbd ns

RxCLK

TxCLK

XTAL1

81,84,87

82,85,88 83,86,89

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-232 09.99

7.7.2.2 Receive Cycle Timing

Figure 7-8 Receive Cycle Timing

Note:

1. Whichever supplies the receive clock depending on the selected clock mode:

external ly clocke d via RxCLK or XTAL1 or

internally clocked via DPLL or BRG.

(No edge relation can be measured if the internal receive clock is derived from the

exter nal clock source by dev ision st ages (BR G) or DPLL)

2. NRZ, NRZ I and Manches ter data enco din g

3. FM0 and FM1 data encoding

4. If Carrier Detect auto start feature enabl ed (not for clock mode s 1 and 5)

91 92

93 94

Receive Clock

(

Note 1

)

RxD

(

Note 2

)

RxD

(

Note 3

)

(

Note 4

)

91 92

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-233 09.99

T able 7-8 Rece ive Cycle Timing

No. Parameter Limi t Values Unit

min. max.

Receive

data rates externa lly clocked

(HDLC) 16 Mbit/s

internally clocked

(DPLL modes) 2Mbit/s

internally clocked

(non DPLL modes) 2Mbit/s

90 Clock

period externa lly clocked

tbd

internally clocked

(DPLL modes)

tbd

internally clocked

(non DPLL modes)

tbd

91 RxD to RxCLK setup time

tbd

92 RxD to RxCLK hold time

tbd

93 CD to RxC LK rising edge set up tim e

tbd

94 CD to RxCLK falling edge hol d time

tbd

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-234 09.99

7.7.2.3 Transmit Cycle Timing

Figure 7-9 Transmit Cycle Timing

Note:

1. Whichever suppl ies the transmit clo ck depending on the selected clock mode:

external ly clocke d via TxCLK, RxCLK or XTAL1 or

internally clocked via DPLL or BRG.

(No edg e relation can be measured if the internal transmit clock is derived from the

exter nal clock source by dev ision st ages (BRG ) or DPLL)

2. N RZ , NRZI and Manchester data encodin g

3. FM 0 and FM1 data encodi ng

4. I f TxCLK output featu re is enabled (only in some clo ck mod es)

5. The timing is valid for non bus configuration modes and bus configuration mode 1. In

bus configuration mode 2, TxD and RTS a re right shifted for 0.5 TxCLK periods i.e.

driven by the falling TxCLK edge.

100

101

Transmit Clock

(Note1)

TxD

(Note2,5)

TxD

(Note3)

TxCLK

(Note4)

106

102

103

104 105

106

102

103

CxD

CTS

RTS

(Note5)

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-235 09.99

T able 7-9 Transm it Cycle Timing

No. Parameter Limit Values U nit

min. max.

Transmit

data rates externally clocked 16 Mbit/s

internall y clo cked

(DPLL modes) 2Mbit/s

internall y clo cked

(non DP LL mode s) 2Mbit/s

100 Clock

period externally clocked

tbd

internall y clo cked

(DPLL modes)

tbd

internall y clo cked

(non DP LL mode s)

tbd

101 TxD to TxCLK delay (NRZ , NRZI encoding)

tbd

102 TxD to TxCLK delay (FM0, FM1, Manchester

encoding)

tbd

103 TxD to TxCLK(out) delay (output function enabled)

tbd tbd

104 CxD to TxCLK setup time,

CTS to TxCLK s et u p time

tbd

105 CxD to Tx CLK ho ld time,

CTS to TxCLK hold time

tbd

106 RTS to TxCLK delay (not bus configuration mode)

tbd

RTS to TxCLK delay (bus configuration mode)

tbd

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-236 09.99

7.7.2.4 Clock Mode 1 Strobe Timing

Figure 7-10 Clock Mode 1 Strobe Timing

Note:

1. No bus configuration mode and bus configuration mode 1

2. Bus conf i gura tion mode 2

3. TxD Idle is either

active high

high impedance

if ’open drain’ output type is selected.

Table 7-10 Clock Mode 1 Strobe Timing

No. P ara meter Limit Values Unit

min. max.

110 Receive st robe to RxCL K setup

tbd

111 Receive strobe to RxCLK hold

tbd

112 Transm it strobe to RxCLK setup

tbd

113 Transmit strobe to RxCLK hold

tbd

114 TxD to RxCLK delay

tbd

115 TxD to RxCLK high impedance delay

tbd

110 111

valid

112 113

114

115

RxCLK

(RxStrobe)

RxD

(Note1)

TxCLK

(TxStrobe)

TxD

(Note1,3)

TxD

(Note2,3)

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-237 09.99

7.7.2.5 Clo ck Mode 5 Frame Synchronisation Timi ng

F igure 7-11 Clock Mode 5 Frame Synchronisat ion Timing

Note:

1. Normal operation and bus configuration mode 1

2. Bus configuration mode 2

T able 7-11 Clock Mode 5 Frame Synchronisat ion Timing

No. Parameter Limit Values Uni t

min. max.

13 0 Sync pulse to RxCLK set up time

tbd

131 Sync pulse to RxCLK hol d time

tbd

132 TxCLKout to RxCLK delay (time slot monitor)

tbd tbd

132

130 131

RxCLK

(FSC)

TxCLK

Note1

TxCLK

Note2

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-238 09.99

7.7.2.6 Clock Mode 4 Rec eive Cycle Timing

Figure 7-12 Cl ock Mo de 4 Receive Timing

Table 7-12 Cl ock Mo de 4 Receive Timing

No. P ara meter Limit Values Unit

min. max.

140 RCG setup time

tbd

141 RCG hold time

tbd

142 RxD setup time

tbd

143 RxD hold time

tbd

RxCLK

RCG

RxD

140

141

142

143

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-239 09.99

7.7.2.7 Clo ck Mode 4 Transmit Cycle Timing

F igure 7-13 Clock Mode 4 Transmit Timing

Note: T

TxCLK

is the TxCLK signal time period .

Timing 149 results from a constant functional one clock offset + signal delay.

T able 7-13 Clock Mode 4 Transmit Timing

No. Parameter Limit Values Uni t

min. max.

145 TCG setup time

tbd

146 TCG hold time

tbd

147 TxCLK to TxD delay

tbd

149 TxD to TCG active delay 1 TTxCLK

tbd

(ns)

TxCLK

TCG

TxD

145

146

149

147

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-240 09.99

7.7.3 Reset Timing

Figure 7-14 Res et Timing

Note: RESET may be asynchronous to CLK when asserted or deasserted. RESET may

be asserted during power-up or asserted after power-up. Nevertheless

deassertion must be clean.

Table 7-14 Reset Timing

No. Param et er Limit Values Unit

min. max.

150

RESET

pulse wid th

tbd

150 Number of CLK cycles during

RESET active

tbd

CLK

cycles

power-on

VDD3

CLK

RST

150

151

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Electrical Characteristics (Preliminary)

Preliminary Data Sheet 7-241 09.99

7.7.4 J TAG-B o undary Scan Timin g

Figure 7-15 JTAG-Bounda ry Scan Timing

Table 7-15 JTAG-Bounda ry Scan Timing

No. Parameter Limit Values Uni t

min. max.

160 TCK period

tbd

∞ns

161 TCK high time

tbd

162 TCK low time

tbd

163 TMS setup time

tbd

164 TMS hold time

tbd

165 TDI setup time

tbd

166 TDI hold time

tbd

167 TDO valid delay

tbd

160

161 162

163 164

165 166

167

TCK

TMS

TDI

TRST

TDO

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Test Modes

Preliminary Data Sheet 8-242 09.99

8 Test Modes

8.1 JTAG Boundary Scan Interface

In the PASSAT a T est Access Port (TAP) controller is implemented. The essential part

of the TAP is a finite state machine (16 states) controlling the different operational modes

of the boundary s can. Both, TAP controller an d boundary sca n, meet the requirements

given by the JTAG standard: IEEE 1149.1. Figure 8-1 gives an overview about the TAP

controller.

Figure 8-1 Block Diagram of Test Access Port and Boundary Scan Unit

If no boundary scan operation is planned TRST has to be connected with VSS. TMS, TCK

and TDI do no t need to be con nected si nce pull-up t ransistors ensu re high inpu t levels

in this case. Nevertheless it would be a good practice to put these unused inputs to

defined levels, using pull-up resistors.

Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),

TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the

TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains

unconnect ed due to its i ntern al pul l-up. Test data at TD I are loaded w i th a 4- MHz cl ock

Clock Generation

Test Access Port (TAP)

TAP Controller

- Finite State Machine

- Instruction Register (3 bit)

- Test Signal Generator

CLOCK

TCK

TRST

TMS

Reset

Data in

TDI

Test

Control

TDO

Enable

Data out

CLOCK

BS Data IN

Identification Scan (32 bit)

Boundary Scan (n bit)

Control

Bus

ID Data out

SS Data

out n

Pins

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Test Modes

Preliminary Data Sheet 8-243 09.99

sign al connect ed t o TC K. ‘1’ or ‘0 ’ on TMS ca uses a transition from one controll er stat e

to another ; constant ’1’ on TMS leads to normal operation of the chip.

Table 8-1 Boundary Scan Sequence of PASSAT

TDI ->

Seq.

No. Pin I/O Number of

Boundary Scan Cells Constant Value

In, Out, Enable

100

001

011

10 3 111

11 3 000

12 1 0

13 3 100

14 1 0

15 2 00

16 2 11

17 2 00

18 2 00

19 2 00

20 2 00

21 2 00

22 2 00

23 1 0

24 2 00

25 2 00

26 2 00

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Test Modes

Preliminary Data Sheet 8-244 09.99

27 2 00

28 2 00

29 2 00

30 2 00

31 2 00

32 1 0

33 3 000

34 3 000

35 3 000

36 2 00

37 2 00

38 2 00

39 2 00

40 2 00

41 2 00

42 2 00

43 2 00

44 3 000

45 3 000

46 1 0

47 1 0

48 3 000

49 3 0

50 3 000

51 3 000

52 1 0

53 3 000

54 3 000

55 3 000

56 3 000

Seq.

No. Pin I/O Number of

Boundary Scan Cells Constant Value

In, Out, Enable

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Test Modes

Preliminary Data Sheet 8-245 09.99

-> T DO

An in put pin (I) u ses one boun dary scan cell (data in), an output p in (O) uses tw o cells

(data out , enabl e) and an I/O-p in (I/O) uses three cells (data i n, dat a out , enabl e). N ot e

that some functional output and input pins of PASSAT are tested as I/O pins in boundary

scan, hence using three cells. The boundary scan unit of PASSAT contains a total of

n = 158 scan cells.

The right column of Table 8-1 gives the initi al ization val ues of the cells.

The desired test mode is selected by serially loading a 3-bit instruction code into the

instr uction re gister via TDI (LSB first); see Table 8-2.

EXTEST is used to examine the interconnection of the devices on the board. In this test

mode at first all input pins capture the current level on the corresponding external

57 3 000

58 3 000

59 3 000

60 3 000

61 3 000

62 3 000

63 3 000

64 3 000

65 2 00

66 1 0

67 1 0

68 3 000

69 2 00

70 1 0

71 1 0

72 1 0

73 1 0

74 1 0

Seq.

No. Pin I/O Number of

Boundary Scan Cells Constant Value

In, Out, Enable

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Test Modes

Preliminary Data Sheet 8-246 09.99

interconnection line, whereas all output pins are held at constant values (‘0’ or ‘1’,

accordi ng to Table 8-1). Then t he contents of the bound ary scan is shifted to TDO. At

the same time the next scan vector is loaded from TDI. Subsequently all output pins are

updated accordin g to the new boundary scan contents and all input pins again capture

the current external level afterwar ds, and so on.

INTEST supports internal testing of the chip, i.e. the output pins capture the current level

on the corresponding internal line whereas all input pins are held on constant values (‘0’

or ‘1’, according to Table 8-1). The resulting boundary scan vector is shifted to TDO.

The next test vector is serially loaded via TDI. Then all input pins are updated for the

fo llo wing test cycle .

Note: In capture IR-state the code ‘001’ is automatically loaded into the instruction

SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during

normal opera tion.

IDCODE: A 32-bit identification register is serially read out via TDO. It contains the

version nu mbe r (4 bits), the dev ice code ( 16 bits) and the man ufacturer cod e ( 11 b it s).

The LSB is fixed to ‘1’.

Note: Since in test logic reset state the code ‘011’ is automatically loaded into the

instruction register, the ID code can easily be read out in shift DR state which is

reached by TMS = 0, 1, 0, 0.

BYPASS: A bit entering TDI is s hifted to TDO after one TCK clock cyc le.

Table 8-2 Boundary Scan Test Modes

Instruction (Bit 2 … 0) Test Mode

000

001

010

011

111

others

EXTEST (external testing)

INTEST (internal testing)

SAMPLE/PRELOAD (snap-shot testing)

IDCODE (reading ID code)

BYPASS (bypass operation)

handled like BYPASS

TDI -> 0001 0000 0000 0101 1111 0000 1000 001 1 -> TDO

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Package Outlines

Preliminary Data Sheet 9-247 09.99

9 Package Outlines

P-LFBGA-80-2

(Low-Profile Fine -Pitch Ball Grid Array)

GPA09236

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”. Dimensions in mm

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Package Outlines

Preliminary Data Sheet 9-248 09.99

P-TQFP-100-3

(Plastic Thin Quad Flat Package)

GPP09189

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”. Dimensions in mm