LP38841T-0.8/NOPB - Texas Instruments

OUT

S/D

0.1 PF

10 PF

Ceramic

OUT

S/D

GND

BIAS

LP38841

BIAS

5V ± 10%

GND GND

4.7 PF*

LP38841

www.ti.com

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

LP38841 0.8A Ultra Low Dropout Linear Regulators

Stable with Ceramic Output Capacitors

Check for Samples: LP38841

1FEATURES DESCRIPTION

The LP38841 is a high current, fast response

2• Ideal for Conversion from 1.8V or 1.5V Inputs regulator which can maintain output voltage

• Designed for Use with low ESR Ceramic regulation with minimum input to output voltage drop.

Capacitors Fabricated on a CMOS process, the device operates

• 0.8V, 1.2V and 1.5V Standard Voltages from two input voltages: Vbias provides voltage to

drive the gate of the N-MOS power transistor, while

Available Vin is the input voltage which supplies power to the

• Ultra Low Dropout Voltage (75mV at 0.8A typ) load. The use of an external bias rail allows the part

• 1.5% Initial Output Accuracy to operate from ultra low Vin voltages. Unlike bipolar

• Load Regulation of 0.1%/A (typical) regulators, the CMOS architecture consumes

extremely low quiescent current at any output load

• 30nA Quiescent Current in Shutdown (typical) current. The use of an N-MOS power transistor

• Low Ground Pin Current at all Loads results in wide bandwidth, yet minimum external

• Over Temperature/over Current Protection capacitance is required to maintain loop stability.

• Available in 5 Lead TO-220 and DDPAK/TO-263 The fast transient response of these devices makes

Packages them suitable for use in powering DSP,

Microcontroller Core voltages and Switch Mode

•−40°C to +125°C Junction Temperature Range Power Supply post regulators. The parts are available

in TO-220 and DDPAK/TO-263 packages.

APPLICATIONS Dropout Voltage: 75 mV (typ) at 0.8A load current.

• ASIC Power Supplies In:

– Desktops, Notebooks, and Graphics Cards, Quiescent Current: 30 mA (typ) at full load.

Servers Shutdown Current: 30 nA (typ) when S/D pin is low.

– Gaming Set Top Boxes, Printers and Precision Output Voltage: 1.5% room temperature

Copiers accuracy.

• Server Core and I/O Supplies

• DSP and FPGA Power Supplies

• SMPS Post-Regulator

TYPICAL APPLICATION CIRCUIT

* Minimum value required if Tantalum capacitor is used (see Application Hints).

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP38841

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

CONNECTION DIAGRAM

Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View

PIN DESCRIPTIONS

Pin Name Description

BIAS The bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and

provides drive voltage for the N-FET.

OUTPUT The regulated output voltage is connected to this pin.

GND This is both the power and analog ground for the IC. Note that both pin three and the tab of the TO-220 and

DDPAK/TO-263 packages are at ground potential. Pin three and the tab should be tied together using the PC board

copper trace material and connected to circuit ground.

INPUT The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin.

Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred

millivolts above the output voltage.

SHUTDOWN This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not

used.

BLOCK DIAGRAM

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SNVS289C –DECEMBER 2004–REVISED APRIL 2013

ABSOLUTE MAXIMUM RATINGS (1)

If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C

Lead Temp. (Soldering, 5 seconds) 260°C

ESD Rating

Human Body Model (2) 2 kV

Machine Model (3) 200V

Power Dissipation (4) Internally Limited

VIN Supply Voltage (Survival) −0.3V to +6V

VBIAS Supply Voltage (Survival) −0.3V to +7V

Shutdown Input Voltage (Survival) −0.3V to +7V

IOUT (Survival) Internally Limited

Output Voltage (Survival) −0.3V to +6V

Junction Temperature −40°C to +150°C

(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for

which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical

Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.

(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.

(3) The machine model is a 220 pF capacitor discharged directly into each pin.

(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.

θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be

assumed. θJ-A for DDPAK/TO-263 devices is approximately 35°C/W if soldered down to a copper plane which is at least 1 square inch in

area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

RECOMMENDED OPERATING CONDITIONS

VIN Supply Voltage (VOUT + VDO) to 5.5V

Shutdown Input Voltage 0 to +5.5V

IOUT 0.8A

Operating Junction Temperature Range −40°C to +125°C

VBIAS Supply Voltage 4.5V to 5.5V

VOUT 0.8V to 1.5V

Product Folder Links: LP38841

LP38841

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

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ELECTRICAL CHARACTERISTICS

Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL= 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1

µF CER, VS/D = VBIAS. Min/Max limits are specified through testing, statistical correlation, or design.(1)

Symbol Parameter Conditions Min Typ (2) Max Units

VOOutput Voltage Tolerance 10 mA < IL< 0.8A 0.788 0.812

0.8

VO(NOM) + 1V ≤VIN ≤5.5V 0.776 0.824

4.5V ≤VBIAS ≤5.5V 1.182 1.218

1.2 V

1.164 1.236

1.478 1.523

1.5

1.455 1.545

ΔVO/ΔVIN Output Voltage Line Regulation (3) VO(NOM) + 1V ≤VIN ≤5.5V 0.01 %/V

ΔVO/ΔILOutput Voltage Load Regulation (4) 10 mA < IL< 0.8A 0.4

0.1 %/A

1.3

VDO Dropout Voltage (5) IL= 0.8A 120

75 mV

205

IQ(VIN) Quiescent Current Drawn from VIN 10 mA < IL< 0.8A 35

30 mA

Supply 40

VS/D ≤0.3V 1

0.06 µA

IQ(VBIAS) Quiescent Current Drawn from VBIAS 10 mA < IL< 0.8A 4

2 mA

Supply 6

VS/D ≤0.3V 1

0.03 µA

ISC Short-Circuit Current VOUT = 0V 2.6 A

Shutdown Input

VSDT Output Turn-off Threshold Output = ON 0.7 1.3 V

Output = OFF 0.3 0.7

Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 µs

Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15

IS/D S/D Input Current VS/D =1.3V 1 µA

VS/D ≤0.3V −1

θJ-A Junction to Ambient Thermal TO-220, No Heatsink 65 °C/W

Resistance DDPAK/TO-263, 1 sq.in Copper 35

AC Parameters

PSRR (VIN) Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz 80

VIN = VOUT + 1V, f = 1 kHz 65 dB

PSRR Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz 58

(VBIAS)VBIAS = VOUT + 3V, f = 1 kHz 58

enOutput Noise Density f = 120 Hz 1 µV/Hz

Output Noise Voltage BW = 10 Hz −100 kHz 150 µV (rms)

VOUT = 1.5V BW = 300 Hz −300 kHz 90

(1) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to

ground.

(2) Typical numbers represent the most likely parametric norm for 25°C operation.

(3) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

(4) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load

to full load.

(5) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.

Product Folder Links: LP38841

1000 10000 100000 1000000

FREQUENCY (Hz)

100

PSRR (dB)

100

CBIAS = 1 PF Tantalum

IL = 0

VOUT = 1.2V

1000 10000 100000 1000000

FREQUENCY (Hz)

PSRR (dB)

COUT = 4.7 PF Tantalum

CBIAS = 1 PF Tantalum

IL = 10 mA

1000 10000 100000 1000000

FREQUENCY (Hz)

100

PSRR (dB)

COUT = 4.7 PF Tantalum

ILOAD = 10 mA

1.45

1.46

1.47

1.48

1.49

1.50

1.51

1.52

1.53

1.54

1.55

VOUT (V)

TEMPERATURE (oC)

-40 0 40 120

-20 20 60 140100

0.8

ILOAD (A)

DROPOUT VOLTAGE (V)

0.60.40.20

0.02

0.06

0.04

0.08

0.10

0.12

25oC

-40oC

125oC

VBIAS = 5V

20 Ps/DIV

VBIAS (V)

VBIAS

VOUT

'VOUT (mV)

IL = 10 mA

VOUT = 1.2V

VIN = 1.7V

-10

LP38841

www.ti.com

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified: TJ= 25°C, CIN = 10 µF CER, COUT = 22 µF CER, CBIAS = 1 µF CER,S/D Pin is tied to VBIAS, VOUT

= 1.2V, IL= 10mA, VBIAS = 5V, VIN = VOUT + 1V.

VBIAS Transient Response Dropout Voltage Over Temperature

Figure 3. Figure 4.

VOUT vs Temperature VBIAS PSRR

Figure 5. Figure 6.

VBIAS PSRR VIN PSRR

Figure 7. Figure 8.

Product Folder Links: LP38841

LP38841

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

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APPLICATION HINTS

EXTERNAL CAPACITORS

To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.

OUTPUT CAPACITOR

An output capacitor is required on the LP3884X devices for loop stability. The minimum value of capacitance

necessary depends on type of capacitor: if a solid Tantalum capacitor is used, the part is stable with capacitor

values as low as 4.7µF. If a ceramic capacitor is used, a minimum of 22 µF of capacitance must be used

(capacitance may be increased without limit). The reason a larger ceramic capacitor is required is that the output

capacitor sets a pole which limits the loop bandwidth. The Tantalum capacitor has a higher ESR than the

ceramic which provides more phase margin to the loop, thereby allowing the use of a smaller output capacitor

because adequate phase margin can be maintained out to a higher crossover frequency. The tantalum capacitor

will typically also provide faster settling time on the output after a fast changing load transient occurs, but the

ceramic capacitor is superior for bypassing high frequency noise.

The output capacitor must be located less than one centimeter from the output pin and returned to a clean

analog ground. Care must be taken in choosing the output capacitor to ensure that sufficient capacitance is

provided over the full operating temperature range. If ceramics are selected, only X7R or X5R types may be

used because Z5U and Y5F types suffer severe loss of capacitance with temperature and applied voltage and

may only provide 20% of their rated capacitance in operation.

INPUT CAPACITOR

The input capacitor is also critical to loop stability because it provides a low source impedance for the regulator.

The minimum required input capacitance is 10 µF ceramic (Tantalum not recommended). The value of CIN may

be increased without limit. As stated above, X5R or X7R must be used to ensure sufficient capacitance is

provided. The input capacitor must be located less than one centimeter from the input pin and returned to a clean

analog ground.

BIAS CAPACITOR

The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).

BIAS VOLTAGE

The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage

must be in the range of 4.5 - 5.5V to assure proper operation of the part.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage

is below approximately 4V.

SHUTDOWN OPERATION

Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a

pull-up resistor (10 kΩto 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high

and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to

VBIAS if not used.

POWER DISSIPATION/HEATSINKING

A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of

the application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

PD= (VIN−VOUT)IOUT+ (VIN)IGND (1)

where IGND is the operating ground current of the device.

The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the

application, and the maximum allowable junction temperature (TJmax):

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LP38841

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SNVS289C –DECEMBER 2004–REVISED APRIL 2013

TRmax = TJmax−TAmax (2)

The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the

formula:

θJA = TRmax / PD(3)

These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount

of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥60 °C/W

for TO-220 package and ≥60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can

dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat

sink is required.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on

a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for

DDPAK/TO-263 package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance,

θHA≤ θJA − θCH − θJC. (4)

In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal

resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for

θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value

is unknown, 2°C/W can be assumed.

HEATSINKING DDPAK/TO-263 PACKAGE

The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of this package is

soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263

package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the

copper area for heat sinking.

Figure 9. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 Package

As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.

The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.

Figure 10 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient

temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.

Product Folder Links: LP38841

LP38841

SNVS289C –DECEMBER 2004–REVISED APRIL 2013

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Figure 10. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package

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LP38841

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SNVS289C –DECEMBER 2004–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision B (April 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 8

Product Folder Links: LP38841

PACKAGE OPTION ADDENDUM

www.ti.com 4-Nov-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP38841S-0.8/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38841S

-0.8

LP38841S-1.2 NRND DDPAK/

TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP38841S

-1.2

LP38841S-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38841S

-1.2

LP38841S-1.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 45 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38841S

-1.5

LP38841SX-1.2/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38841S

-1.2

LP38841SX-1.5/NOPB ACTIVE DDPAK/

TO-263 KTT 5 500 Pb-Free (RoHS

Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38841S

-1.5

LP38841T-0.8/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38841T

-0.8

LP38841T-1.2/LF03 ACTIVE TO-220 NDH 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM LP38841T

-1.2

LP38841T-1.2/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38841T

-1.2

LP38841T-1.5/NOPB ACTIVE TO-220 KC 5 45 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38841T

-1.5

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

PACKAGE OPTION ADDENDUM

www.ti.com 4-Nov-2016

Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP38841SX-1.2/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

LP38841SX-1.5/NOPB DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP38841SX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

LP38841SX-1.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

9.25

7.67

6.86

5.69

3.05

2.54

14.73

12.29

5X 1.02

0.64

4X 1.7

8.89

6.86

12.88

10.08

(6.275)

4.83

4.06 1.40

1.14

3.05

2.03

0.61

0.30

-3.963.71

6.8

2X (R1)

OPTIONAL

16.51

MAX

10.67

9.65

(4.25)

4215009/A 01/2017

TO-220 - 16.51 mm max heightKC0005A

TO-220

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for

reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Shape may vary per different assembly sites.

0.25 C A B

PIN 1 ID

(OPTIONAL)

OPTIONAL

CHAMFER

SCALE 0.850

NOTE 3

AAAA

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND

0.07 MAX

ALL AROUND (1.45)

(2)

(R0.05) TYP

4X (1.45)

4X (2)

5X ( 1.2) (1.7) TYP

(6.8)

FULL R

TYP

TO-220 - 16.51 mm max heightKC0005A

TO-220

4215009/A 01/2017

LAND PATTERN

NON-SOLDER MASK DEFINED

SCALE:12X

PKG

METAL

TYP

SOLDER MASK

OPENING, TYP

MECHANICAL DATA

NDH0005D

www.ti.com

MECHANICAL DATA

KTT0005B

www.ti.com

BOTTOM SIDE OF PACKAGE

TS5B (Rev D)

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LP38841MR-ADJ LP38841MRX-ADJ LP38841S-0.8 LP38841S-0.8/NOPB LP38841S-1.2 LP38841S-1.2/NOPB

LP38841S-1.5 LP38841S-1.5/NOPB LP38841SX-0.8 LP38841SX-0.8/NOPB LP38841SX-1.2 LP38841SX-1.2/NOPB

LP38841SX-1.5 LP38841SX-1.5/NOPB LP38841T-0.8 LP38841T-0.8/NOPB LP38841T-1.2 LP38841T-1.2/LF03

LP38841T-1.2/NOPB LP38841T-1.5 LP38841T-1.5/NOPB