1 Mbit (128K x8) Page-Write EEPROM SST29EE010 SST29EE / VE0101Mb (x8) Page-Write, Small-Sector flash memories Data Sheet FEATURES: * Single Voltage Read and Write Operations - 4.5-5.5V for SST29EE010 * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 2.7V - Standby Current: 10 A (typical) * Fast Page-Write Operation - 128 Bytes per Page, 1024 Pages - Page-Write Cycle: 5 ms (typical) - Complete Memory Rewrite: 5 sec (typical) - Effective Byte-Write Cycle Time: 39 s (typical) * Fast Read Access Time - 4.5-5.5V operation: 70 and 90 ns - 2.7-3.6V operation: 150 and 200 ns * Latched Address and Data * Automatic Write Timing - Internal VPP Generation * End of Write Detection - Toggle Bit - Data# Polling * Hardware and Software Data Protection * Product Identification can be accessed via Software Operation * TTL I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm, 8mm x 20mm) - 32-pin PDIP * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST29EE010 is a 128K x8 CMOS Page-Write EEPROMs manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010 write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE010 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Page-Write, the SST29EE010 provides a typical Byte-Write time of 39 sec. The entire memory, i.e., 128 Kbyte, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a Write cycle. To protect against inadvertent write, the SST29EE010 has on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE010 is offered with a guaranteed Page-Write endurance of 10,000 cycles. Data retention is rated at greater than 100 years. applications, the SST29EE010 significantly improves performance and reliability, while lowering power consumption. The SST29EE010 improves flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the SST29EE010 is offered in 32-lead PLCC and 32-lead TSOP packages. A 600-mil, 32-pin PDIP package is also available. See Figures 2, 3, and 4 for pin assignments. Device Operation The SST Page-Write EEPROM offers in-circuit electrical write capability. The SST29EE010 does not require separate Erase and Program operations. The internally timed Write cycle executes both erase and program transparently to the user. The SST29EE010 has industry standard optional Software Data Protection, which SST recommends always to be enabled. The SST29EE010 is compatible with industry standard EEPROM pinouts and functionality. The SST29EE010 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system (c)2009 Silicon Storage Technology, Inc. S71061-13-000 3/09 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SSF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Read writing to the selected page and will leave the SST29EE010 protected at the end of the Page-Write. The page-load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal Write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Read operations of the SST29EE010 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 5). The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE010 before the initiation of the internal Write cycle. During the internal Write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the PageWrite feature of SST29EE010 allows the entire memory to be written in as little as 5 seconds. During the internal Write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FFH. Write The Page-Write to the SST29EE010 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The SST29EE010 contains the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. The first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes, The Proper Use of JEDEC Standard Software Data Protection and Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories. See Figures 6 and 7 for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 100 s, the SST29EE010 will stay in the pageload cycle. Additional bytes are then loaded consecutively. The page-load cycle will be terminated if no additional byte is loaded into the page buffer within 200 s (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page-load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 s. The page to be loaded is determined by the page address of the last byte loaded. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled Write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP threebyte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal Write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The Write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 6 and 7 for WE# and CE# controlled Page-Write cycle timing diagrams and Figures 16 and 18 for flowcharts. Software Chip-Erase The SST29EE010 provides a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 11 for timing diagram, and Figure 20 for the flowchart. The Write operation has three functional cycles: the Software Data Protection load sequence, the page-load cycle, and the internal Write cycle. The Software Data Protection consists of a specific three-byte load sequence that allows (c)2009 Silicon Storage Technology, Inc. S71061-13-000 2 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Write Operation Status Detection Hardware Data Protection The SST29EE010 provides two software means to detect the completion of a Write cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal Write cycle. Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Software Data Protection (SDP) The SST29EE010 provides the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three-byte load operations to precede the data loading operation. The three-byte load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. The SST29EE010 is shipped with the Software Data Protection disabled. Data# Polling (DQ7) The software protection scheme can be enabled by applying a three-byte sequence to the device, during a pageload cycle (Figures 6 and 7). The device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 6 and 7 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 10 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~300 s. SST recommends Software Data Protection always be enabled. See Figure 18 for flowcharts. When the SST29EE010 is in the internal Write cycle, any attempt to read DQ7 of the last byte loaded during the byteload cycle will receive the complement of the true data. Once the Write cycle is completed, DQ7 will show true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. See Figure 8 for Data# Polling timing diagram and Figure 17 for a flowchart. Toggle Bit (DQ6) The SST29EE010 Software Data Protection is a global command, protecting all pages in the entire memory array once enabled. Therefore using SDP for a single PageWrite will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled. During the internal Write cycle, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 9 for Toggle Bit timing diagram and Figure 17 for a flowchart. The initial read of the Toggle Bit will typically be a "1". Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The SST29EE010 should be programmed using the SDP command sequence. Data Protection The SST29EE010 provides both hardware and software features to protect nonvolatile data from inadvertent writes. (c)2009 Silicon Storage Technology, Inc. S71061-13-000 3 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TABLE 1: Product Identification Please refer to the following Application Notes for more information on using SDP: * * Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories The Proper Use of JEDEC Standard Software Data Protection Manufacturer's ID Address Data 0000H BFH 0001H 07H Device ID SST29EE010 T1.4 1061 Product Identification Product Identification Mode Exit The Product Identification mode identifies the device as the SST29EE010 and manufacturer as SST. This mode is accessed via software. For details, see Table 4, Figure 12 for the software ID entry and read timing diagram and Figure 19, for the ID entry command sequence flowchart. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. The Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. See Table 4 for software command codes, Figure 13 for timing waveform, and Figure 19 for a flowchart. X-Decoder A16 - A0 SuperFlash Memory Address Buffer & Latches Y-Decoder and Page Latches CE# OE# WE# Control Logic I/O Buffers and Data Latches DQ7 - DQ0 1061 B1.0 FIGURE 1: Functional Block Diagram (c)2009 Silicon Storage Technology, Inc. S71061-13-000 4 3/09 1 Mbit Page-Write EEPROM SST29EE010 NC VDD 4 3 2 1 32 31 30 29 NC A16 A6 A15 5 A12 A7 WE# Data Sheet A14 6 28 A13 A5 7 27 A8 A4 8 26 A9 A3 9 25 A11 A2 10 24 OE# A1 11 23 A10 A0 12 22 CE# DQ0 13 21 14 15 16 17 18 19 20 DQ7 32-lead PLCC Top View DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 1061 32-plcc P01.0 FIGURE 2: Pin Assignments for 32-lead PLCC A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1061 32-tsop F02.0 FIGURE 3: Pin Assignments for 32-lead TSOP NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 1061 32-pdip P03.0 FIGURE 4: Pin Assignments for 32-pin PDIP (c)2009 Silicon Storage Technology, Inc. S71061-13-000 5 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TABLE 2: Pin Description Symbol Pin Name Functions A16-A7 Row Address Inputs To provide memory addresses. Row addresses define a page for a Write cycle. A6-A0 Column Address Inputs Column Addresses are toggled to load page data DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. To provide: VDD Power Supply VSS Ground NC No Connection 5.0V supply (4.5-5.5V) for SST29EE010 Unconnected pins. T2.3 1061 TABLE 3: Operation Modes Selection Mode CE# Read Page-Write Standby Write Inhibit OE# WE# DQ Address VIL VIL VIL VIH VIH DOUT AIN VIL DIN VIH X1 AIN X VIL X High Z X X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIH VIL DIN AIN, See Table 4 Software Mode VIL VIH VIL Manufacturer's ID (BFH) Device ID2 See Table 4 SDP Enable Mode VIL VIH VIL See Table 4 SDP Disable Mode VIL VIH VIL See Table 4 Software Chip-Erase Product Identification T3.4 1061 1. X can be VIL or VIH, but no other value. 2. Device ID = 07H for SST29EE010 (c)2009 Silicon Storage Technology, Inc. S71061-13-000 6 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TABLE 4: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle Addr1 Data 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data Addr1 Data Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data 5555H AAH 2AAAH 55H 5555H A0H Addr2 Software Chip-Erase3 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H Alternate Software ID Entry6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H Software Data Protect Enable & Page-Write T4.3 1061 1. Address format A14-A0 (Hex), Addresses A15 and A16 can be VIL or VIH, but no other value. 2. Page-Write consists of loading up to 128 Bytes (A6-A0) 3. The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if you require this function for an industrial temperature part. 4. The device does not remain in Software Product ID mode if powered down. 5. With A14-A1 = 0; SST Manufacturer's ID = BFH, is read with A0 = 0, SST29EE010 Device ID = 07H, is read with A0 = 1 6. Alternate six-byte Software Product ID command code Note: This product supports both the JEDEC standard three-byte command code sequence and SST's original six-byte command code sequence. For new designs, SST recommends that the three-byte command code sequence be used. (c)2009 Silicon Storage Technology, Inc. S71061-13-000 7 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range for SST29EE010 Range Commercial Industrial Ambient Temp VDD 0C to +70C 4.5-5.5V -40C to +85C 4.5-5.5V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF See Figures 14 and 15 TABLE 5: DC Operating Characteristics VDD = 4.5-5.5V for SST29EE010 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min, VDD=VDD Max Read 30 mA CE#=OE#=VIL, WE#=VIH, all I/Os open Program and Erase 50 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max ISB1 Standby VDD Current (TTL input) 3 mA CE#=OE#=WE#=VIH, VDD=VDD Max ISB2 Standby VDD Current (CMOS input) 50 A CE#=OE#=WE#=VDD -0.3V, VDD=VDD Max ILI Input Leakage Current 1 A VIN =GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT =GND to VDD, VDD=VDD Max VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 0.8 2.0 0.4 2.4 V VDD=VDD Min V VDD=VDD Max V IOL=2.1 mA, VDD=VDD Min V IOH=-400 A, VDD=VDD Min T5.4 1061 (c)2009 Silicon Storage Technology, Inc. S71061-13-000 8 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TABLE 6: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Write Operation 5 ms TPU-WRITE 1 T6.1 1061 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T7.0 1061 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: Reliability Characteristics Symbol NEND 1 Parameter Minimum Specification Units Endurance Test Method 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 mA JEDEC Standard 78 T8.5 1061 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2009 Silicon Storage Technology, Inc. S71061-13-000 9 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters for SST29EE010 SST29EE010-70 Min SST29EE010-90 Symbol Parameter Max Min TRC Read Cycle Time TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 30 40 ns TCLZ1 CE# Low to Active Output 0 0 ns TOLZ1 OE# Low to Active Output 0 0 ns TCHZ1 CE# High to High-Z Output 20 30 ns TOHZ1 OE# High to High-Z Output 20 30 ns TOH1 Output Hold from Address Change 70 Max Units 90 0 ns 0 ns T9.2 1061 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Page-Write Cycle Timing Parameters SST29EE010 Symbol Parameter Min Max Units 10 ms TWC Write Cycle (Erase and Program) TAS Address Setup Time 0 TAH Address Hold Time 50 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 0 ns TCP CE# Pulse Width 70 ns TWP WE# Pulse Width 70 ns TDS Data Setup Time 35 ns TDH1 Data Hold Time TBLC1 Byte Load Cycle Time 0.05 TBLCO1 Byte Load Cycle Time 200 TIDA1 Software ID Access and Exit Time 10 s TSCE Software Chip-Erase 20 ms ns 0 ns 100 s s T10.5 1061 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2009 Silicon Storage Technology, Inc. S71061-13-000 10 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TRC TAA ADDRESS A16-0 TCE CE# TOE OE# TOH TOLZ VIH WE# TCLZ DQ7-0 TOH HIGH-Z DATA VALID TOH DATA VALID HIGH-Z 1061 F04.0 FIGURE 5: Read Cycle Timing Diagram Three-Byte Sequence for Enabling SDP ADDRESS A16-0 5555 2AAA TAH TAS 5555 TCH TCS CE# TOES TOEH OE# TWP TBLC TBLCO WE# TDH DQ7-0 AA 55 A0 SW0 SW1 SW2 DATA VALID TWC TDS BYTE 0 BYTE 1 BYTE 127 1061 F05.0 FIGURE 6: WE# Controlled Page-Write Cycle Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71061-13-000 11 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Three-Byte Sequence for Enabling SDP ADDRESS A16-0 5555 2AAA TAH TAS 5555 TCP TBLC TBLCO CE# TOES TOEH OE# TCS TCH WE# TDH DQ7-0 AA 55 SW0 SW1 DATA VALID A0 TDS SW2 BYTE 0 TWC BYTE 1 BYTE 127 1061 F06.0 FIGURE 7: CE# Controlled Page-Write Cycle Timing Diagram ADDRESS A16-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 D D# D# D TWC + TBLCO 1061 F07.0 FIGURE 8: Data# Polling Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71061-13-000 12 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet ADDRESS A16-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWC + TBLCO TWO READ CYCLES WITH SAME OUTPUTS 1061 F08.0 FIGURE 9: Toggle Bit Timing Diagram Six-Byte Sequence for Disabling Software Data Protection ADDRESS A14-0 DQ7-0 5555 AA 2AAA 5555 55 5555 80 2AAA AA TWC 5555 55 20 CE# OE# TBLCO TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5 1061 F09.0 FIGURE 10: Software Data Protect Disable Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71061-13-000 13 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TSCE Six-Byte Code for Software Chip-Erase 5555 ADDRESS A14-0 2AAA AA DQ7-0 5555 55 2AAA 5555 80 AA 5555 55 10 CE# OE# TBLCO TWP WE# TBLC SW0 SW1 SW2 SW3 SW4 SW5 1061 F10.0 FIGURE 11: Software Chip-Erase Timing Diagram Three-Byte Sequence for Software ID Entry ADDRESS A14-0 5555 5555 2AAA 0000 0001 TAA DQ7-0 AA 55 90 BF DEVICE ID TIDA CE# OE# TWP WE# TBLC SW0 SW1 SW2 DEVICE ID = 07H for SST29EE010 = 08H for SST29VE010 1061 F11.1 FIGURE 12: Software ID Entry and Read (c)2009 Silicon Storage Technology, Inc. S71061-13-000 14 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Three-Byte Sequence for Software ID Exit and Reset ADDRESS A14-0 DQ7-0 5555 AA 2AAA 5555 55 F0 TIDA CE# OE# TWP WE# TBLC SW0 SW1 SW2 1061 F12.0 FIGURE 13: Software ID Exit and Reset (c)2009 Silicon Storage Technology, Inc. S71061-13-000 15 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 1061 F13.0 AC test inputs are driven at VIHT (2.4V) for a logic "1" and VILT (0.4 V) for a logic "0". Measurement reference points for inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% 90%) are <10 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 14: AC Input/Output Reference Waveforms VDD TO TESTER RL HIGH TO DUT CL RL LOW 1061 F14.0 FIGURE 15: A Test Load Example (c)2009 Silicon Storage Technology, Inc. S71061-13-000 16 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Start Software Data Protect Write Command See Figure 18 Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 No Byte Address = 128? Yes Wait TBLCO Wait for end of Write (TWC, Data# Polling bit or Toggle bit operation) Write Completed 1061 F15.0 FIGURE 16: Write Algorithm (c)2009 Silicon Storage Technology, Inc. S71061-13-000 17 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Internal Timer Toggle Bit Data# Polling Page-Write Initiated Page-Write Initiated Page-Write Initiated Wait TWC Read a byte from page Read DQ7 (Data for last byte loaded) Write Completed Read same byte No Is DQ7 = true data? Yes No Does DQ6 match? Write Completed Yes Write Completed 1061 F16.0 FIGURE 17: Wait Options (c)2009 Silicon Storage Technology, Inc. S71061-13-000 18 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Software Data Protect Enable Command Sequence Software Data Protect Disable Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Write data: 80H Address: 5555H Load 0 to 128 Bytes of page data Optional Page Load Operation Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Wait TBLCO Write data: 20H Address: 5555H Wait TWC Wait TBLCO SDP Enabled Wait TWC SDP Disabled 1061 F17.0 FIGURE 18: Software Data Protection Flowcharts (c)2009 Silicon Storage Technology, Inc. S71061-13-000 19 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Write data: F0H Address: 5555H Pause 10 s Pause 10 s Read Software ID Return to normal operation 1061 F18.0 FIGURE 19: Software Product Command Flowcharts (c)2009 Silicon Storage Technology, Inc. S71061-13-000 20 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Software Chip-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 10H Address: 5555H Wait TSCE Chip-Erase to FFH 1061 F19.0 FIGURE 20: Software Chip-Erase Command Codes (c)2009 Silicon Storage Technology, Inc. S71061-13-000 21 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet PRODUCT ORDERING INFORMATION SST 29 XX xE 010 XX XXXX - 70 - XXX - 4C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads or pins Package Type N = PLCC E = TSOP (type 1, die up, 8mm x 20mm) P = PDIP W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 200 = 200 ns 150 = 150 ns 90 = 90 ns 70 = 70 ns Device Density 010 = 1 Mbit Function E = Page-Write Voltage E = 4.5-5.5V V = 2.7-3.6V Product Series 29 = Page-Write Flash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". (c)2009 Silicon Storage Technology, Inc. S71061-13-000 22 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet Valid combinations for SST29EE010 SST29EE010-70-4C-NHE SST29EE010-90-4C-NHE SST29EE010-70-4I-NHE SST29EE010-70-4C-WHE SST29EE010-90-4C-WHE SST29EE010-70-4I-WHE SST29EE010-70-4C-EHE SST29EE010-90-4C-EHE SST29EE010-70-4C-PHE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software Chip-Erase function is not supported by the industrial temperature part. Please contact SST if this function is required in an industrial temperature part. (c)2009 Silicon Storage Technology, Inc. S71061-13-000 23 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet PACKAGING DIAGRAMS TOP VIEW Optional Pin #1 Identifier .048 .042 SIDE VIEW .495 .485 .453 .447 2 1 32 .112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 FIGURE 21: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH (c)2009 Silicon Storage Technology, Inc. S71061-13-000 24 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 FIGURE 22: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH (c)2009 Silicon Storage Technology, Inc. S71061-13-000 25 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 0.70 0.50 Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2.All linear dimensions are in millimeters (max/min). 3.Coplanarity: 0.1 mm 4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads. 1mm 32-tsop-EH-7 FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 20mm SST Package Code: EH (c)2009 Silicon Storage Technology, Inc. S71061-13-000 26 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet 32 CL Pin #1 Identifier 1 1.655 1.645 .075 .065 7 4 PLCS. Base Plane Seating Plane .625 .600 .550 .530 .200 .170 .050 .015 .080 .070 .065 .045 .022 .016 .100 BSC .150 .120 0 15 .012 .008 .600 BSC Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-pdip-PH-3 FIGURE 24: 32-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PH (c)2009 Silicon Storage Technology, Inc. S71061-13-000 27 3/09 1 Mbit Page-Write EEPROM SST29EE010 Data Sheet TABLE 11: Revision History Revision Description Date 07 * 2002 Data Book May 2002 08 * * Removed 200 ns Read Access Time for SST29LE010 Clarified IDD Write to be Program and Erase in Tables 5 and 6 on page 8 Mar 2003 09 * * 2004 Data Book Added non-Pb MPNs and removed footnote (See page 23) Nov 2003 10 * Added 150 ns MPNs for SST29VE010 Mar 2004 11 * Removed 3V device and associated MPNs: refer to EOL Product Data Sheet S71061(01) Added non-Pb MPN for SST29EE010 PDIP Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 22 Updated the solder reflow temperature to the "Absolute Maximum Stress Ratings" on page 8. Sep 2005 May 2008 * Updated "Valid combinations for SST29EE010" and "Valid combinations for SST29VE010" on page 25 to remove unused parts. EOl'ed all Pb devices: refer to EOL Data Sheet S71601(03). * End of Life all SST29VE010 valid combinations. See S71601(04) Mar 2009 * * * 12 13 * Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2009 Silicon Storage Technology, Inc. S71061-13-000 28 3/09