Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Block Diagram
952001 Rev A 01/24/02
Pin Configuration
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V
• 2 - AGP @ 3.3V
• 2 - ZCLKs @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Programmable output frequency, divider ratios, output
rise/falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
• For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
• Uses external 14.318MHz crystal.
Key Specifications:
• PCI - PCI output skew: < 500ps
• CPU - SDRAM output skew: < 1ns
• AGP - AGP output skew: <150ps
Programmable Timing Control Hub for P4 processor
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
48-Pin 300-mil SSOP and TSSOP
Functionality
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Note: For additional margin testing frequencies, refer to Byte 4
VDDREF
FS0/REF0
*FS1/REF1
X1
X2
GNDZ
ZCLK0
VDDPCI
PCICLK0
PCICLK1
GNDPCI
VDDPCI
**
*
**FS2/REF2
GNDREF
ZCLK1
VDDZ
*PCI_STOP#
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
VDDSD
SDRAM
GNDSD
CPU_STOP#
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL
GND48
*
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
*
ICS952001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
I REF
CPU
DIVDER
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
ZCLK (1:0)
PCICLK (9:0)
AGP (1:0)
PCICLK_F (1:0)
2
2
2
6
2
X1
X2 XTAL
OSC
ZCLK
DIVDER
PCI
DIVDER Stop
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
AGP
DIVDER
Stop
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 C P U SD R AM Z C LK AG P
FS4
FS3
FS2
FS1
FS0
(M Hz)
(M Hz)
(M Hz)
(M Hz)
0
0
0
0
0
66.67 66.67 66.67 66.67
0
0
0
0
1
100.00 100.00 66.67 66.67
0
0
0
1
0
100.00 200.00 66.67 66.67
0
0
0
1
1
100.00 133.33 66.67 66.67
0
0
1
0
0
100.00 150.00 60.00 60.00
0
0
1
0
1
100.00 125.00 62.50 62.50
0
0
1
1
0
100.00 160.00 66.67 66.67
0
0
1
1
1
100.00 133.33 80.00 66.67
0
1
0
0
0
100.00 200.00 66.67 66.67
0
1
0
0
1
100.00 166.67 62.50 62.50
0
1
0
1
0
100.00 166.67 71.43 83.33
0
1
0
1
1
80.00 133.33 66.67 66.67
0
1
1
0
0
80.00 133.33 66.67 66.67
0
1
1
0
1
95.00 95.00 63.33 63.33
0
1
1
1
0
95.00 126.67 63.33 63.33
01111
66.67 66.67 50.00 50.00
2
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Pin Description
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
PIN NUMBER PIN NAME TYPE DESCRIPTION
1, 11, 13, 19, 29,
42, 48
VDD PW R Power supply for 3.3V
FS0 IN Frequency select pin.
REF0 OUT 14.318 MHz refere nce clock.
FS1 IN Frequency select pin.
REF1 OUT 14.318 MHz refere nce clock.
FS2 IN Frequency select pin.
REF2 OUT 14.318 MHz refere nce clock.
5, 8, 18, 24, 25,
32, 37, 41, 46
GND PWR Ground pin for 3V outputs.
6 X1 IN Crystal input,nomi nally 14.318MHz.
7 X2 OUT Crystal output, nominally 14.318MHz.
10, 9 ZCLK(1:0) OUT Hyperzip clock outputs.
12 PCI_STOP# IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
FS3 IN Frequency select pin.
PCICLK_F0 OUT PCI cloc k output, not affec ted by P CI_STOP#
FS4 IN Frequency select pin.
PCICLK_F1 OUT PCI cloc k output, not affec ted by P CI_STOP#
23, 22, 21, 20, 17,
16
PCICLK (5:0) OUT PCI cloc k outputs.
MULTISEL IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs.
24_48MHz OUT Clock output for super I/O/USB default is 24MHz
27 48MHz OUT 48MHz output clock
28, 36 AVDD PWR Analog power supply 3.3V
30, 31 AGPCLK (1:0) OUT AGP outputs defined as 2X PCI. These may not be stopped.
PD# IN
Asynchronous active low input pin used to power down the device into a
low po wer sta te. The in te rnal clocks a re di sabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
Vtt_PWRGD IN
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
34 SDATA I/O
Data pin for I
2
C circuitry 5V tolerant
35 SCLK IN
Clock pin of I
2
C circuitry 5V tolerant
38 I REF OUT This pi n establi shes the ref erence current for the C PU CLK
pairs. Thi s pin r equir es a f i xed preci si on r esi st or t i ed t o gr ound
in order to establ ish the appropriat e current .
43, 39 CPUCLKC (1 :0) OUT "Complemen tar y" clo cks of di fferen ti al p air CPU outp uts . These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
44, 40 CP UCLKT ( 1: 0) OUT "True" clocks of di ff erentia l pair CPU ou tp uts. These clocks are in ph ase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
45 CPU_STOP# IN Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
47 SDRAM OUT SDRA M clock output.
15
26
33
2
3
4
14
3
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
0LESTLUM 32etyB 7tiB tegraTdraoB ZmreT/ecarT
,RecnerefeR =ferI )rR*3(/ddV
tuptuO tnerruC ,Z@hoV Am23.2=ferI
00 smho06 %1574=rR Am23.2=ferI ferI*5=hoI06@V17.0
00 smho05 %1574=rR Am23.2=ferI ferI*5=hoI05@V95.0
01 smho06 %1574=rR Am23.2=ferI ferI*4=hoI06@V65.0
01 smho05 %1574=rR Am23.2=ferI ferI*4=hoI05@V74.0
10 smho06 %1574=rR Am23.2=ferI ferI*6=hoI062/V58.0
10 smho05 %1574=rR Am23.2=ferI ferI*6=hoI05@V17.0
11 smho06 %1574=rR Am23.2=ferI ferI*7=hoI06@V99.0
11 smho05 %1574=rR Am23.2=ferI ferI*7=hoI05@V28.0
00 )viuqeCD(03 %1122=rR Am5=ferI ferI*5=hoI03@V57.0
00 )viuqeCD(52 %1122=rR Am5=ferI ferI*5=hoI02@V26.0
01 )viuqeCD(03 %1122=rR Am5=ferI ferI*4=hoI02@06.0
01 )viuqeCD(52 %1122=rR Am5=ferI ferI*4=hoI02@V5.0
10 )viuqeCD(03 %1122=rR Am5=ferI ferI*6=hoI03@V09.0
10 )viuqeCD(52 %1122=rR Am5=ferI ferI*6=hoI02@V57.0
11 )viuqeCD(03 %1122=rR Am5=ferI ferI*7=hoI03@V50.1
11 )viuqeCD(52 %1122=rR Am5=ferI ferI*7=hoI02@V48.0
CPUCLK Swing Select Functions
4
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General I2C serial interface information for the ICS952001
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
*See notes on the following page.
ICS (Slave/Receiver)
T
WR ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Bloc k Write Operation
Slave Address D2(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3(H)
Index Block Read Operation
Slave Address D2(H)
Beginning Byte = N ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
5
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Byte4: Functionality and Frequency Select Register (default = 0)
Bytes 0-3: Are reserved for external clock buffer.
tiBnoitpircseDDWP
2tiB 4:7tiB
2tiB7tiB6tiB5tiB4tiB
00000 1etoN
4SF3SF2SF1SF0SFUPCMARDSKLCZPGAICPegatnecerPdaerpS
0000 0 76.6676.6676.6676.6633.33daerpSnwoD%5.0-ot0
0000 1 00.00100.00176.6676.6633.33daerpSnwoD%5.0-ot0
000 10 00.00100.00276.6676.6633.33daerpSnwoD%5.0-ot0
000 1 1 00.00133.33176.6676.6633.33daerpSnwoD%5.0-ot0
0010 0 00.00100.05100.0600.0600.03daerpSretneC%52.0-/+
0010 1 00.00100.52105.2605.2652.13daerpSretneC%52.0-/+
00110 00.00100.06176.6676.6633.33daerpSretneC%52.0-/+
0011 1 00.00133.33100.0876.6633.33daerpSnwoD%5.0-ot0
01000 00.00100.00276.6676.6633.33daerpSretneC%52.0-/+
0100 1 00.00176.66105.2605.2652.13daerpSnwoD%5.0-ot0
01010 00.00176.66134.1733.3876.14daerpSretneC%52.0-/+
01011 00.0833.33176.6676.6633.33daerpSretneC%52.0-/+
01100 00.0833.33176.6676.6633.33daerpSretneC%52.0-/+
0110 1 00.5900.5933.3633.3676.13daerpSretneC%52.0-/+
01110 00.5976.62133.3633.3676.13daerpSretneC%52.0-/+
01111 76.6676.6600.0500.0500.52daerpSretneC%52.0-/+
100 0 0 00.50100.04100.0700.0700.53daerpSretneC%52.0-/+
100 0 1 09.00109.00172.7672.7636.33daerpSretneC%52.0-/+
100 1 0 00.80100.44100.2700.2700.63daerpSretneC%52.0-/+
100 1 1 09.00135.43172.7672.7636.33daerpSretneC%52.0-/+
10 10 0 00.21133.94176.4776.4733.73daerpSretneC%52.0-/+
10 10 1 33.33100.00176.6676.6633.33daerpSnwoD%5.0-ot0
10 1 1 0 33.33133.33176.6676.6633.33daerpSretneC%52.0-/+
10 1 1 1 33.33176.66176.6676.6633.33daerpSretneC%52.0-/+
1100 0 00.00100.33100.0876.6633.33daerpSretneC%52.0-/+
1100 1 00.00100.00100.0876.6633.33daerpSretneC%52.0-/+
110 10 00.00176.66133.3805.2652.13daerpSretneC%52.0-/+
110 1 1 33.33100.06100.0876.6633.33daerpSretneC%52.0-/+
1110 0 00.00100.33100.00176.6633.33daerpSretneC%52.0-/+
1110 1 00.00100.00100.00176.6633.33daerpSretneC%52.0-/+
11110 00.00176.66100.00105.2652.13daerpSretneC%52.0-/+
1111 1 33.33100.06100.00176.6633.33daerpSretneC%52.0-/+
3tiB stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0 4:72,tiBybdetcelessiycneuqerF-1 0
1tiB lamroN-0 delbanEmurtcepSdaerpS-1 0
0tiB gninnuR-0 stuptuollaetatsirT-1 0
6
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 5: Control Register
(1 = enable, 0 = disable)
Byte 7: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Output Control Register
(1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB511 1F_KLCICP
6tiB411 0F_KLCICP
5tiB321 5KLCICP
4tiB221 4KLCICP
3tiB121 3KLCICP
2tiB021 2KLCICP
1tiB711 1KLCICP
0tiB611 0KLCICP
tiB#niPDWPnoitpircseD
7tiB031 1KLCPGA
6tiB131 1KLCPGA
5tiB620 zHM84_42LES )zHM84=0,zHM42=1(
4tiB51X kcaBdaeR4SF
3tiB41X kcaBdaeR3SF
2tiB4X kcaBdaeR2SF
1tiB3X kcaBdaeR1SF
0tiB2X kcaBdaeR0SF
Byte 8: Byte Count Read Back Register
tiBemaNDWPnoitpircseD
7tiB7etyB0
erugifnoclliwretsigersihtotgnitirW:etoN eblliwsetybynamwohdnatnuocetyb F0sitluafed,kcabdaer
H
.setyb51=
6tiB6etyB0
5tiB5etyB0
4tiB4etyB0
3tiB3etyB1
2tiB2etyB1
1tiB1etyB1
0tiB0etyB1
tiB#niPDWPnoitpircseD
7tiB011 1KLCZ
6tiB91 0KLCZ
5tiB410 lortnocpots0F_KLCICP potS=1;gninnuReerF=0
4tiB510 lortnocpots1F_KLCICP potS=1;gninnuReerF=0
3tiB93,041 lortnocpots0C/TKLCUPC potS=1;gninnuReerF=0
2tiB34,441 lortnocpots1C/TKLCUPC potS=1;gninnuReerF=0
1tiB04,931 lortnoctuptuo0C/TKLCUPC
0tiB44,341 lortnoctuptuo1C/TKLCUPC
7
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 10: Programming Enable bit 8 W atchdog Control Register
Byte 9: W atchdog Timer Count Register
tiBemaNDWPnoitpircseD
7tiB margorP elbanE 0tibelbanEgnimmargorP ybdetceleseraseicneuqerF.gnimmargorpon=0 0etyBrosehctalWH Illaelbane=1
2
.gnimargorpC
6tiBelbanEDW0 tibelbanEgodhctaW
5tiBmralADW0 sutatsmrala=1lamron=0sutatSmralAgodhctaW
4tiB4FS0 stibesehtotgnitirW.stibycneuqerfefasgodhctaW otgnidnopsrrocycneuqerfefasehterugifnoclliw elbat4:7,2tiB0etyB
3tiB3FS0
2tiB2FS0
1tiB1FS0
0tiB0FS1
tiBemaNDWPnoitpircseD
7tiB7DW0
stib8esehtfonoitatneserperlamicedehT godhctawehtsm092•Xotdnopserroc edommralaotseogtierofebtiawlliwremit
.
gnittesefasehtotycneuqerfehtteserdna 6.4=sm092•61sipurewoptatluafeD .sdnoces
6tiB6DW0
5tiB5DW0
4tiB4DW1
3tiB3DW0
2tiB2DW0
1tiB1DW0
0tiB0DW0
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
tiBemaNDWPnoitpircseD
7tiB8vidNX 8tibredividN
6tiB6vidMX
)0:6(vidMfonoitatneserpserlamicedehT .eulavredividecnereferehtotdsopserroc dehctalehtotlauqesipurewoptatluafeD .noitcelesstupni
5tiB5vidMX
4tiB4vidMX
3tiB3vidMX
2tiB2vidMX
1tiB1vidMX
0tiB0vidMX
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
tiBemaNDWPnoitpircseD
7tiB7vidNX
)0:8(vidNfonoitatneserperlamicedehT .eulavredividOCVehtotdnopserroc dehctalehtotlauqesipurewoptatluafeD nidetacolsi8vidNecitoN.notcelesstupni .11etyB
6tiB6vidNX
5tiB5vidNX
4tiB4vidNX
3tiB3vidNX
2tiB2vidNX
1tiB1vidNX
0tiB0vidNX
8
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 13: Spread Spectrum Control Register
tiBemaNDWPnoitpircseD
7tiB7SSX lliwtib)0:21(murtcepSdaerpSehT daerpS.egatnecerpdaerpsehtmargorp nodesabdetaluclacebotsdeentnecerp ,eliforpgnidaerps,ycneuqerfOCVeht
t
I.ycneuqerfdaerpsdnatnuomagnidaerps roferawtfosSCIesuotdednemmocersi sinorewoptluafeD.gnimmargorpdaerps .redividSFdehctal
6tiB6SSX
5tiB5SSX
4tiB4SSX
3tiB3SSX
2tiB2SSX
1tiB1SSX
0tiB0SSX
Byte 14: Spread Spectrum Control Register
Byte 15: Output Divider Control Register
tiBemaNDWPnoitpircseD
7tiBdevreseRXdevreseR
6tiBdevreseRXdevreseR
5tiBdevreseRXdevreseR
4tiB21SSX 21tiBmurtcepSdaerpS
3tiB11SSX 11tiBmurtcepSdaerpS
2tiB01SSX 01tiBmurtcepSdaerpS
1tiB9SSX 9tiBmurtcepSdaerpS
0tiB8SSX 8tiBmurtcepSdaerpS
tiBemaNDWPnoitpircseD
7tiB3viDDSX ebnacoitarredividkcolcMARDS .yllaudividnistib4esehtaivderugifnoc otreferelbatnoitcelesredividroF dehctalsipurewoptatluafeD.1elbaT .redividSF
6tiB2viDDSX
5tiB1viDDSX
4tiB0viDDSX
3tiB3viDUPCX ebnacoitarredividkcolcC/TKLCUPC .yllaudividnistib4esehtaivderugifnoc otreferelbatnoitcelesredividroF dehctalsipurewoptatluafeD.1elbaT .redividSF
2tiB2viDUPCX
1tiB1viDUPCX
0tiB0viDUPCX
Byte 16: Output Divider Control Register
tiBemaNDWPnoitpircseD
7tiB3viDPGAX ebnacoitarredividkcolcPGA stib4esehtaivderugifnoc noitcelesredividroF.yllaudividni tatluafeD.1elbaTotreferelbat .redividSFdehctalsipurewop
6tiB2viDPGAX
5tiB1viDPGAX
4tiB0viDPGAX
3tiB3viDKLCZX ebnacoitarredividkcolcKLCZ stib4esehtaivderugifnoc noitcelesredividroF.yllaudividni tatluafeD.1elbaTotreferelbat .redividSFdehctalsipurewop
2tiB2viDKLCZX
1tiB1viDKLCZX
0tiB0viDKLCZX
9
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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 17: Output Divider Control Register
Table 1 Table 2
)2:3(viD 00100111
)0:1(viD 002/4/8/61/
103/6/21/42/
015/01/02/04/
117/41/82/65/
)2:3(viD 00100111
)0:1(viD 004/8/61/23/
103/6/21/42/
015/01/02/04/
117/41/82/65/
Byte 18: Group Skew Control Register
tiBemaNDWPnoitpircseD
7tiB1wekS_UPC1 )0:1(C/TKLCUPCehtyaledstib2esehT .skcolcrehtollaottcepserhtiwskcolc sp052=10sp0=00sp057=11sp005=01
6tiB0wekS_UPC0
5tiB1wekS_DS0 ottcepserhtiwMARDSehtyaledstib2esehT KLCUPC sp057=11sp005=01sp052=10sp0=00
4tiB0wekS_DS1
3tiB)devreseR(1
)devreseR(
2tiB)devreseR(1
1tiB)devreseR(1
0tiB)devreseR(1
Byte 19: Group Skew Control Register
tiBemaNDWPpotSyaleDelbammargorP
7tiB
lortnocstib4esehT
)0:1(KLCZ-UPC
1 0000 sn58.1 1000 sn50.3
6tiB 0 0001 sn00.21001sn02.3
5tiB00010sn51.21010sn53.3
4tiB00011sn03.21011sn05.3
3tiB
lortnocstib4esehT
)0:1(PGA-UPC
10100 sn54.21100sn56.3
2tiB00101sn06.21101sn08.3
1tiB00110sn57.2 1110 sn59.3
0tiB00111sn09.2 1111 sn01.4
tiBemaNDWPnoitpircseD
7tiBVNI_PGA0 tibnoisrevnIesahPPGA
6tiBVNI_KLCZ0 tibnoisrevnIesahPKLCZ
5tiBVNI_DS0 tibnoisrevnIesahPMARDS
4tiBVNI_UPC0 tibnoisrevnIesahPKLCUPC
3tiB3viDICPX ebnacoitarredividkcolcICP stib4esehtaivderugifnoc noitcelesredividroF.yllaudividni tatluafeD.2elbatotreferelbat .redividSFdehctalsipurewop
2tiB2viDICPX
1tiB1viDICPX
0tiB0viDICPX
10
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Byte 20: Group Skew Control Register
tiBemaNDWPpotSyaleDelbammargorP
7tiB
lortnocstib4esehT
)0:1(F_KLCICP-UPC
0 0000 sn58.1 1000 sn50.3
6tiB 1 0001 sn00.21001sn02.3
5tiB00010sn51.21010sn53.3
4tiB00011sn03.21011sn05.3
3tiB
lortnocstib4esehT
)0:5(KLCICP-UPC
00100 sn54.21100sn56.3
2tiB10101sn06.21101sn08.3
1tiB00110sn57.2 1110 sn59.3
0tiB00111sn09.2 1111 sn01.4
Byte 21: Slew Rate Control Register
tiBemaNDWPnoitpircseD
7tiB welS_84/42 0.stiblortnocetarwelskcolczHM84/42 kaew=01;lamron=11,00;gnorts=10
6tiB0
5tiB welS_PGA 0.stiblortnocetarwelskcolcPGA kaew=01;lamron=11,00;gnorts=10
4tiB0
3tiB welS_KLCZ 0.stiblortnocetarwelskcolcKLCZ kaew=01;lamron=11,00;gnorts=10
2tiB0
1tiB welS_FER 0.stiblortnocetarwelskcolcFER kaew=01;lamron=11,00;gnorts=10
0tiB0
Byte 22: Slew Rate Control Register
Byte 23: Output Control Register
tiB#niPDWPnoitpircseD
7tiB-0 lortnoCtuptuOferI
6tiB-1 kcabdaeRLESTILUM
5tiB741 MARDS
4tiB721 zHM84
3tiB621 zHM84_42
2tiB412FER
1tiB311FER
0tiB210FER
tiBemaNDWPnoitpircseD
7tiB welSMARDS 0.stiblortnocetarwelskcolcMARDS kaew=01;lamron=11,00;gnorts=10
6tiB0
5tiB )devreseR( X)devreseR(
4tiBX
3tiB F_KLCICPwelS 0.stiblortnocetarwelskcolcF_KLCICP kaew=01;lamron=11,00;gnorts=10
2tiB0
1tiB welSKLCICP 0.stiblortnocetarwelskcolcKLCICP kaew=01;lamron=11,00;gnorts=10
0tiB0
11
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . 115°C
Electrical Characteristic s - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Vol tage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%( unl ess o t her w ise st at ed )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
Input High Current IIH VIN = VDD -5 5 mA
Input Low Current IIL1 VIN = 0 V; I nputs w it h no pul l-up r es istor s - 5 m A
Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resis tors -200 mA
Operating IDD3.3OP CL = 30 pF; C P U @ 13 3 M H z 280 mA
Supply Cur r ent
Power Down IDD3.3PD CL = 0 pF 25 m A
Supply Cur r ent
Input frequency FiVDD = 3. 3 V 14.32 M Hz
Pin I nduct anc e Lpin 7nH
Input Capac itanc e1CIN Logic Inputs 5 pF
Cout O ut put pin c apac i tanc e 6 pF
CINX X1 & X2 pins 27 45 pF
Trans ition Time1Ttrans To 1s t c ross ing of tar get Fr eq. 3 m S
Settling Time1TsFr om 1 s t cr oss i ng to 1% t ar g et Fr eq. 3 m S
Clk St abi liz ation1TSTAB Fr om VDD = 3. 3 V t o 1% t ar g et Fr e q. 3 m S
Delay tPZH,tPZH out put en able del ay (a ll ou tpu ts) 1 10 nS
tPLZ,tPZH out put dis able delay ( all outputs) 1 10 nS
1Guar anteed by desi gn, not 100% tes t ed in produc ti on.
12
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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
El e ct ric al C haract eri st i cs - C PU
TA = 0 - 70C, V DDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
S
Output Im pedance
R
DSP2B
1V
O
= V
DD
*(0.5) 13.5 45 Ω
Output Im pedance
R
DSN2B
1V
O
= V
DD
*(0.5) 13.5 45 Ω
Output High Voltage V
OH2B
I
OH
= -1 mA 2 V
Output Low Voltage V
OL2B
I
OL
= 1 mA 0.4 V
Outp ut High Cur r e nt I
OH2B
V
OH @MIN
= 1.0V , V
OH@ MAX
= 2.375V -27 -27 mA
Output Low Current I
OL2B
V
OL @MIN
= 1.2V , V
OL@ MA X
= 0.3V 27 30 mA
Rise Time
t
r2B
1V
OL
= 0.4 V , V
OH
= 2.0 V 0.4 1.6 ns
Fall Ti me
t
f2B
1V
OH
= 0. 4 V, V
OL
= 2.0 V 0.4 1.6 ns
Duty Cycle
d
t2B
1V
T
= 1.25 V 455055ns
Skew
t
sk2B
1V
T
= 1.25 V 175 ps
Jitter t
jcyc-cyc
1VT = 1.25 V 250 ps
1
Guarenteed by design, not 100% tested i n production.
Electrical Ch aracteristics - PC I
TA = 0 - 70C; VDD = 3.3 V + /-5% ; CL = 30 pF (unles s ot herwis e s t ated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
S
O utput Impedanc e R
DSP1
1V
O
= V
DD
*(0.5) 12 55 Ω
O utput Impedanc e R
DSN1
1V
O
= V
DD
*(0.5) 12 55 Ω
Out put High V olt age V
OH1
I
OH
= -18 m A 2. 4 V
Out put Low V oltage V
OL1
I
OL
= 9. 4 m A 0.4 V
Output High Current I
OH1
V
OH
= 2.0 V -22 m A
O utput Low Current I
OL1
V
OL
= 0. 8 V 25 m A
Ris e T im e t
r1
1V
OL
= 0. 4 V , V
OH
= 2. 4 V 2.0 ns
Fall T im e t
f1
1V
OH
= 2.4 V , V
OL
= 0. 4 V 2.0 ns
Duty Cy c le d
t1
1V
T
= 1. 5 V 45.0 55. 0 %
S k ew W indow t
sk1
1V
T
= 1. 5 V 500 ps
Jitter tj1s11VT = 1.5 V 250 ps
1Guarenteed by des ign, not 100% t es t ed in product ion.
13
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Integrated
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Systems, Inc.
ICS952001
Preliminary Product Preview
Electrical Characteristics - 24M, 48M, REF
TA = 0 - 70C; V DD = VDDL = 3. 3 V +/ -5%; CL = 20 pF (unles s ot herwise s tat ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
S
Out put Im pedanc e R
DSP5
1V
O
= V
DD
*(0.5) 20 60 Ω
Out put Im pedanc e R
DSN5
1V
O
= V
DD
*(0.5) 20 60 Ω
Out put High V olt age V
OH5
I
OH
= -14 m A 2. 4 V
Out put Low V oltage V
OL5
I
OL
= 6. 0 m A 0. 4 V
Output High Current I
OH5
V
OH
= 2.0 V -20 mA
Out put Low Current I
OL5
V
OL
= 0. 8 V 10 m A
Rise Ti me t
r5
1V
OL
= 0. 4 V, V
OH
= 2.4 V 4. 0 ns
Fall Time t
f5
1V
OH
= 2.4 V , V
OL
= 0.4 V 4. 0 ns
Duty Cy cle d
t5
1V
T
= 1. 5 V 45. 0 55. 0 %
Jitter tj1s51VT = 1. 5 V 500 ps
1
Guarant eed by des i gn, not 100% t est ed in p roduct ion.
Electrical Characteristics - SDRA M
TA = 0 - 70 C; VDD =VDDL 3. 3 V +/ -5 % ; CL = 30 pF (unless ot herwis e s tat ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
S
Out put I m pedanc e R
DSP2A
1V
O
= V
DD
*(0.5) 10 20 Ω
Out put I m pedanc e R
DSN2A
1V
O
= V
DD
*(0.5) 10 20 Ω
Out put High V oltage V
OH2A
I
OH
= -28 m A 2.4 V
O ut put Low V oltage V
OL2A
I
OL
= 19 mA 0.4 V
Out put High Current I
OH2A
V
OH
= 2. 0 V -42 m A
O ut put Low Cu rrent I
OL2A
V
OL
= 0.8 V 33 m A
Ris e T im e t
r2A
1V
OL
= 0.4 V , V
OH
= 2.4 V 0. 5 2.0 ns
Fall Tim e t
f2A
1V
OH
= 2. 4 V, V
OL
= 0.4 V 0. 5 2 ns
Duty Cyc le d
t2A
1V
T
= 1.5 V 45 55 %
Jitter
1
tcyc-cyc VT = 1.5 V 250.0 ps
1G uarenteed by des ign, not 100% t es ted in produc t ion.
14
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
15
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ICS952001
Preliminary Product Preview
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low . There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
16
Ordering Information
ICS952001yFT
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXX y F - T
INDEX
AREA
INDEX
AREA
1 2
N
Dh x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
α
0°
8°
0°
8°
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.63 5 BASIC 0.025 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
17
Ordering Information
ICS952001yFT
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G=TSSOP
Revision Designator
Device T ype (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP
MIN MAX MIN MAX
A - 1.20 - .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e 0.50 BASIC 0.020 BASIC
L 0.45 0.75 .018 .30
N
α0° 8° 0° 8°
aaa - 0.10 - .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
MO-153 JEDEC
Doc.# 10 -0 03 9 7/6/00 Rev B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COM MON DIMENSIONS In Inches
COMMON DIMENSI ONS
SEE VARIATIONS
8.10 BASIC 0.319
ND mm. D (inch)
SEE VARIATIONS
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IDT
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952001 (Desktop Chipsets)
Description
SIS 645/650 style chipsets.
Market Group
PC CLOCK
Additional Info
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the
ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952001 is
part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line
which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device
can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew,
the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset
feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz
increment.
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Related Orderable Parts
Attributes 952001AF 952001AFLF 952001AFLFT 952001AFT
Voltage 3.3 V (PV48) 3.3 V (PVG48) 3.3 V (PVG48) 3.3 V (PV48)
Package SSOP 48 SSOP 48 SSOP 48 SSOP 48
Speed NA NA NA NA
Temperature C C C C
Status Active Active Active Active
Sample Yes Yes No No
Minimum Order Quantity 90 90 1000 1000
Factory Order Increment 30 30 1000 1000
Related Documents
Type Title Size Revision Date
Datasheet 952001 Datasheet 212 KB 03/27/2006
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