TLE6288R
Smart 6 Channel Peak & Hold Switch
Data Sheet, Rev. 2.5, Oct. 2010
Automotive Power
Data Sheet 2 Rev. 2.5, 2010-10-11
TLE6288R
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Gerneral Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.1 Output Stage Control: Parallel Control and SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.2 Current Regulator: Peak Current Control with Fixed Off-Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.1 Parallel Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3.2 Electrical Characteristics: Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Electrical Characteristics: SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 SPI Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4 SPI Commands, Values and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5 SPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6 Bit Assignment and Default Settings for Internal Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Electrical Characteristics Input / Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 Power Supply, Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Zthjc Diagram Junction - Case for Single channel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2 Thermal Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3 Overload/Low Inductance Load Detection in Current Regulation Mode . . . . . . . . . . . . . . . . . . . . . . . 29
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table of Contents
Data Sheet 3 Rev. 2.5, 2010-10-11
Type Package
TLE6288R PG-DSO-36-54
TLE6288R
Features
• 3 Channel high side with adjustable Peak & Hold current
control
• 3 Channel high/low side configurable
• Protection
– Overcurrent (current limitation)
– Overtemperature
– Overvoltage (active clamping)
• Diagnosis
– Overcurrent
– Overtemperature
– Open load (Off-State)
– Short to Ground (Off-state, lowside configuration)
–Short to VB (Off-state, highside configuration)
• Interface and Control
– 16-Bit Serial Peripheral Interface (2 bit/CH)
– Device programming via SPI
– Separate diagnosis output for each CH (DIAG1
to 6)
– General Fault Flag + Overtemperature Flag
– Direct parallel control of all channels
– General enable signal to control all channels
simultaneously
• Low Quiescent Current
• Compatible with 3.3 V and 5 V microcontrollers
•Electrostatic discharge (ESD) protection of all pins
• Green Product (RoHS compliant)
• AEC Qualified
Application
• Peak & Hold Loads (valves, coils)
• Solenoids, Relays and Resistive Loads
• Fast protected Highside Switching
(PWM up to > 10 kHz)
General Description
The TLE6288R is a 6-channel (150 mΩ) Smart Multichannel Switch in Smart Power Technology. The IC has
embedded protection, diagnosis and configurable functions. Channels 1-3 are highside channels with integrated
charge pump and can be programmed individually to do autonomous peak and hold current regulation with PWM.
Channel 4-6 (also with integrated charge pump) can be configured to work as highside switch or lowside switch.
This IC can be used to drive standard automotive loads in highside or lowside applications with switching
frequencies up to 10 kHz. In addition the TLE6288R can be used to drive autonomously up to 3 inductive
peak & hold (valves, coils) loads with programmable peak and hold current values.
Table 1 Product Summary
Parameter Symbol Values Unit
Logic Supply voltage VCC 4.5 … 5.5 V
On resistance RDS(ON)1-6 0.15 typ. @ 25 °C Ω
Lowside clamping voltage Vcll(max) +55 V
Highside clamping voltage Vclh(max) -19 V
Peak current range Ipk 1.2 … 3.6 A
Hold current range Ihd 0.7 … 2 A
Peak time range Ip0 … 3.6 ms
Fixed off time range Ifo 100 … 400 μs
TLE6288R
Block Diagram
Data Sheet 4 Rev. 2.5, 2010-10-11
1 Block Diagram
Figure 1 Block Diagram
Charge
pump
VCP
GNDFSIN
Channel 3
Highside 300 mΩ
Peak&Hold
Channel 2
Highside 300 mΩ
Peak&Hold
Channel 1
Highside 300 mΩ
Peak&Hold
Channel 4
Highside/ Lowside
300 mΩ
Channel 5
Highside/ Lowside
300 mΩ
Channel 6
Highside/ Lowside
300 mΩ
VB
VCC DOUT 3 / VB
SOUT 3
SOUT 2
SOUT 1
DOUT 4
SOUT 4
DOUT 5
SOUT 5
DOUT 6
SOUT 6
SPI
SCLK
CS
SI
SO
Logic
Driver
Diagnosis
IN 1
DIAG 1
IN 2
IN 3
IN 4
IN 5
DIAG 5
IN 6
DIAG 6
Overtemp.
Reset VDO
CLKProg
Fault
.
.
Vcc
Vcc
.
Vcc
.
.
Vcc
.
.
.
.
.
.
.
GND
GND
DOUT 2
DOUT 1
Data Sheet 5 Rev. 2.5, 2010-10-11
TLE6288R
Pin Configuration
2 Pin Configuration
2.1 Pin Assignment
Figure 2 Pin Configuration PG-DSO-36-54
2.2 Pin Definitions and Functions
Pin Symbol Function
1 SOUT4 Source Output CH 4 (high/low side)
2 DOUT4 Drain Output CH 4 (high/low side)
3 DOUT1 Drain Output CH 1 (high side)
4 SOUT1 Source Output CH 1 (high side)
5 IN4 Control Input Channel 4
6 IN1 Control Input Channel 1
7 DIAG1 Diagnostic Output CH 1
8 DIAG2 Diagnostic Output CH 2
9 DIAG3 Diagnostic Output CH 3
10 DIAG4 Diagnostic Output CH 4
11 DIAG5 Diagnostic Output CH 5
12 DIAG6/Overtemp Diagnostic Output CH 6 / Overtemp
13 IN2 Control Input Channel 2
14 IN5 Control Input Channel 5
15 SOUT2 Source Output CH 2 (high side)
16 DOUT2 Drain Output CH 2 (high side)
TLE6288R
Pin Configuration
Data Sheet 6 Rev. 2.5, 2010-10-11
2.3 Pin Description
17 DOUT5 Drain Output CH 5 (high/low side)
18 SOUT5 Source Output CH 5 (high/low side)
19 SOUT3 Source Output CH 3 (high side)
20 DOUT3 Drain Output CH 3 (high side)
21 VCP Charge Pump capacitor pin
22 FSIN All Channels Enable/Disable
23 GND Logic Ground
24 Fault General Fault Flag
25 IN3 Control Input Channel 3
26 IN6 Control Input Channel 6
27 Reset Reset pin (+ Standby Mode)
28 VCC Logic Supply Voltage (5 V)
29 VDO Supply pin for digital outputs
30 SO SPI Serial Data Output
31 CLKProg Program pin of SPI Clock
32 SCLK SPI Serial Clock
33 CS SPI Chip Select
34 SI SPI Serial Data Input
35 DOUT6 Drain Output CH 6 (high/low side)
36 SOUT6 Source Output CH 6 (high/low side)
Symbol Description
DOUT1-3 Drain of the 3 highside channels. These pins must always be connected to the same power (battery)
supply line (VB).
SOUT1-3 Source of the 3 highside channels. Outputs of the highside channels where the load is connected.
DOUT4-6 Drain pins of the 3 configurable channels. In highside configuration they must be connected to the
same voltage as DOUT1-3. In lowside configuration they are the output pins and connected to the
load.
SOUT4-6 Source of the 3 configurable channels. In highside configuration they are the outputs and connected
to the load. In lowside configuration they must be connected with GND.
IN1-6 Parallel input pins for the 6 power outputs. These pins have an internal pull-down structure.
GND Logic ground pin, the heat slug has to be connected to this potential.
FSIN Disable pin. If the FSIN pin is in a logic low state, it switches all outputs OFF. The pin has an internal
pull-up structure.
Reset Reset pin. When the reset is low all channels are off, the internal biasing is deactivated, all internal
registers are cleared and the supply-current consumption is reduced (standby mode). The pin has an
internal pull-up structure.
Fault General Fault pin. There is a general fault pin (open drain) which shows a high to low transition as
soon as an error is latched into the diagnosis register. When the diagnosis register is cleared this flag
is also reset (high ohmic). This fault indication can be used to generate a μC interrupt.
Pin Symbol Function
Data Sheet 7 Rev. 2.5, 2010-10-11
TLE6288R
Pin Configuration
For more details about the SPI see Chapter 5.
CLKProg Programming pin for the SPI Clock signal. This pin can be used to configure the clock signal input of
the SPI. In low state the SPI will read data at the rising clock edge and write data at the falling clock
edge. In high state the SPI will read data at the falling clock edge and write data at the rising clock
edge. The pin has an internal pull-down structure.
DIAG1-5 Parallel diagnostic pins (push-pull) change state according to the input signal of the corresponding
channel. For further details refer to Chapter 4.3.1
DIAG6/
Overtemp
VCP Pin to connect the external capacitor of the integrated charge pump. Connect a ceramic capacitor with
47 nF between this pin and DOUT3 (VB).
VDO Supply pin of the push-pull digital output drivers. This pin can be used to vary the high-state output
voltage of the SO pin and the DIAG1-6 pins.
VCC Logic supply pin. This pin is used to supply the integrated circuitry.
CS Chip Select of the SPI (active low)
SO Signal Output of the Serial Peripheral Interface
SI Signal Input of the Serial Peripheral Interface. The pin has an internal pull-down structure.
SCLK Clock Input of the Serial Peripheral Interface. The pin has an internal pull-up structure
(if CLKProg = L) or an pull-down structure (if CLKProg = H).
Symbol Description
TLE6288R
General Product Characteristics
Data Sheet 8 Rev. 2.5, 2010-10-11
3 General Product Characteristics
3.1 Absolute Maximum Ratings
Attention: Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings 1)
Tj = -40 ⋅C to +150 ⋅C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit PIN / Conditions
Min. Max.
Voltages
3.1.1 Power Supply Voltage 1 static
dynamic: 1 min. 25 °C
dynamic: Test cond. see Figure 3
VB
VB
VB
-0.3
–
–
20
24
40
VDOUT1-3
DOUT1-32)
DOUT1-32)
2) As long as max. junction temperature Tj is not exceeded.
3.1.2 Power Supply Voltage 2 VCC
VDO
-0.3 7 V VCC
VDO
3.1.3 Continuous Drain Source Voltage
(lowside configuration)
VDSL – 40 V DOUT - SOUT
(channel 4 to 6)
Continuous Source Voltage
(highside configuration)
VSH -9 VBV SOUT - GND
(channel 4 to 6)
3.1.4 Input Voltage VIN -0.3 VCC + 0.3 V IN1-6, Reset,
FSIN, CS, SCLK,
SI, CLKProg
3.1.5 Output Voltage VOUT -0.3 VCC + 0.3 V Fault
DIAG1-6
SO
3.1.6 Output Voltage VCP –VB + 10 V VCP; no voltage
must be applied
Currents
3.1.7 Reverse Current (1 ms) Irev -4 – A between DOUT
and SOUT;
Channel 4 to 6
Temperatures
3.1.8 Operating Temperature Tj-40 +150 °C–
3.1.9 Storage Temperature Tstg -55 +150 °C–
ESD Susceptibility
3.1.10 ESD (Human Body Model)
C = 100 pF, R = 1.5 kΩ
Applied to all terminals 3 times
VESDb –2000V–
3.1.11 ESD (Machine Model)
C = 200 pF, R = 0 Ω
Applied to all terminals 3 times
VESDm –250V–
Data Sheet 9 Rev. 2.5, 2010-10-11
TLE6288R
General Product Characteristics
Attention: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the data sheet. Fault conditions are considered as “outside” normal operating
range. Protection functions are not designed for continuous repetitive operation.
Figure 3 Test Condition
3.2 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
3.2.1 –
3.2.2 Junction to Case1)
1) Not subject to production test, specified by design.
RthjC 1K/W
2)
2) Channel 1-6 continously turned on, 0.8W power dissipation per channel
3.2.3 Junction to ambient1) RthjA 15.5 K/W 2) 3)
3) Specified RthjA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board ; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70μm Cu, 2 x 35μm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Further informations can be found in Chapter 7.2
12V
40V 10 times
(once/ 30sec)
160ms
350ms
TLE6288R
Description
Data Sheet 10 Rev. 2.5, 2010-10-11
4 Description
4.1 General Functional Description
Channel 1 to 3
• High Side Configuration with Charge Pump
• On / off Current Control
• Peak & Hold Current Control with fixed off time, values adjustable by SPI
• Type of current control can be selected by SPI
• Peak Current,Peak Time, Hold Current and Off-Time can be selected by SPI to set average and ripple current
for a given load (refer to Figure 6)
Channel 4 to 6
• Configurable as either High or Low Side switch (by SPI)
• On / Off operation
4.1.1 Output Stage Control: Parallel Control and SPI Control
A Boolean operation (either AND or OR) is performed on each of the parallel inputs IN 1 … 6 and respective SPI
data bits, in order to determine the states of the respective outputs. The type of Boolean operation performed is
programmed via the serial interface. Both, parallel inputs and respective SPI databits are high active.
Figure 4 Serial Input Bits 6-11 of Command “Channels on/off”
Each output is independently controlled by an output latch and a common reset line FSIN, which disables all
outputs. A logic high input ‘data bit’ turns the respective output channel ON, a logic low ‘data bit’ turns it OFF.
Table 2 Truth Table
Parallel Input SPI Bit Output OR Output AND
00OFFOFF
0 1 ON OFF
1 0 ON OFF
1 1 ON ON
OR
AND
Output
Driver
IN 1…6
Serial Input bits 6 -11 of command
„Chann els on / off „
Data Sheet 11 Rev. 2.5, 2010-10-11
TLE6288R
Description
4.1.2 Current Regulator: Peak Current Control with Fixed Off-Time
•Hold only: When the channel is turned on externally (SPI or parallel input) the current rises to the programmed
hold current level. Then the channel is internally turned off and a timer is started for a fixed off-time (e.g.
200 μs). After this time the channel is internally turned on again until the hold current level is reached again
and so on. This regulation works automatically until the channel is turned of externally.
•Peak and hold mode with minimum peak time: When the channel is turned on the current rises to the
programmed peak current level. Then the channel is internally turned off, the current regulator changes to hold
current values and a timer is started for a constant off-time. After this time the channel is internally turned on
again until the hold current value is reached and then again turned off for the fixed off time. This regulation
works automatically until the channel is turned of externally.
•Peak and hold mode with programmed peak time: When the channel is turned on the current rises to the
programmed peak current level. Then the channel is internally turned off and a timer is started for a fixed off-
time. After this time the channel is internally turned on again until the peak current value is reached and then
again turned off. This works until the programmed peak time is over. Then the current regulator changes to
hold current values and works as described under “hold only”.
Peak Current, Peak Time, Hold Current and fixed Off-Time can be set via SPI.
To avoid regulation disturbances by current transients during switching (e.g. caused by ESD capacitors at the
outputs) the current regulator has a “leading edge blanking” of typical 20 μs in all three regulation modes. After
turning on the DMOS (internally or externally) the current regulation circuit is deactivated for the first 20 μs. This
guarantees that switching of the DMOS itself or charging of small capacitors at the output (e.g. ESD) is not
disturbing the current regulation.
To detect shorted loads or low inductance loads in all three regulation modes a timer is started when a channel is
turned on (tli). If the first rising edge of the load current reaches the programmed current level (peak or hold current
depending on the configured current control mode) within this time a overload fault is reported (see Chapter 7.3).
Figure 5 Simplified Functional Block Diagram
TLE6288R
Description
Data Sheet 12 Rev. 2.5, 2010-10-11
Figure 6 Current Forms of the Different Current Control Modes of Channel 1-3
Peak and Hold
with set peak time
Hold only
Peak & Hold
with min. peak time
Ihd
Ihd
Ipk
Ipk
tp
tfo
No Regulation Current defined only by load
Input Signal
Ihd
tfo
tfo
tfo
Data Sheet 13 Rev. 2.5, 2010-10-11
TLE6288R
Description
4.2 Protection
The TLE6288R has integrated protection functions1) for overload and short circuit (active current limitation),
overtemperature, ESD at all pins and overvoltage at the power outputs (zener clamping).
Overtemperature Behavior
Each channel has an overtemperature sensor and is individually protected against overtemperature.
As soon as overtemperature occurs the channel is immediately turned off. In this case there are two different
behaviors of the affected channel that can be selected by SPI (for all channels generally):
Autorestart: as long as the input signals of the channel remains on (e.g. parallel input high) the channel turns
automatically on again after cooling down.
Latching: After overtemperature shutdown the channel stays off until the this overtemperature latch is reset by a
new L → H transition of the input signal.
Note: These overtemperature sensors of the channels are only active if the channel is turned on.
An additional overtemperature sensor is located in the logic of the device. It monitors permanently the IC
temperature. As soon as the IC temperature reaches a specified level an overtemperature fault will be indicated.
1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous
repetitive operation.
TLE6288R
Description
Data Sheet 14 Rev. 2.5, 2010-10-11
4.3 Diagnostic
The TLE6288R has a parallel diagnosis via 6 output pind (DIAG1 - DIAG6) and a serial diagnosis functionallity via
SPI.
4.3.1 Parallel Diagnostic Functions
Parallel diagnostic pins (push-pull) change state according to the input signal of the corresponding channel. As
soon as an error occurs at the corresponding channel (overload and overtemperature is detected in on state and
open load/switch bypass in off state) the DIAG output shows the inverted input signal. An fault is detected only if
it lasts for longer than the fault filter time. The fault information is not latched in a register.
If DIAG6 is configured as Overtemperature Flag: This is a general fault pin which shows a high to low transition
as soon as an overtemperature error occurs for any one of the six channels (for longer than the fault filter time) or
the IC logic. This fault indication can be used to differ between overload and overtemperature errors in one of the
six channels or to detect a general IC overtemperature.
4.3.2 Electrical Characteristics: Diagnostic Functions
Electrical Characteristics: Diagnostic Functions
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
4.3.1 Open Load Detection Voltage VDS(OL) –5.5–V– lowside
configuration,
VB = 12 V
4.3.2 Open Load Detection Voltage VDS(OL) – 4.5 – V – highside
configuration,
VB = 12 V
4.3.3 Output Open Load diagnosis
Current
Id(OL) -500 -100 -20 μA– VB = Vout = 12
V
4.3.4 Fault Filter Time tf(fault) 50 100 200 μs– –
4.3.5 Switch Bypass Detection
Current
Id(SB) ––250μA– –
4.3.6 Overload Detection Threshold
(Channel 1 to 3)
IDd(lim1-3) 4 – 6 A – no regulation
mode
4.3.7 Overload / low inductance
load Detection time
(Channel 1 to 3)
tli ––tfo μssee
Chapter 7.3
current
control mode
4.3.8 Overload Detection Threshold
(Channel 4 to 6)
IDd(lim 4-6) 3–6A– –
Data Sheet 15 Rev. 2.5, 2010-10-11
TLE6288R
SPI
5SPI
The SPI is a Serial Peripheral Interface with 4 digital pins and a 16-bit shift register. The SPI is used to configure
and program the device, turn on and off channels and to read detailed diagnostic information.
Figure 7 Serial Peripheral Interface
5.1 SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE6288R by means of the CS pin. Whenever the pin is
in a logic low state, data can be transferred from the μC and from the TLE6288R to the µC.
•CS = H: Any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state.
•CS = H → L:
– diagnostic information is transferred from the diagnosis register into the SPI shift register
– serial input data can be clocked into the SPI shift register from then on
– SO changes from high impedance state to logic high or low state corresponding to the SO bits
Figure 8
•CS = L: SPI is working like a shift register. With each clock signal the state of the SI is read into the SPI shift-
register and one diagnosis bit is written out of SO.
•CS = L → H:
– transfer of SI bits from SPI shift register into the internal logic registers
– reset of diagnosis register if sent command was valid
To avoid any false clocking the serial clock input pin SCLK should be logic high state (if CLKProg = L; low state if
CLKProg = H) during high to low transition of CS.
SCLK - Serial Clock. The serial clock pin clocks the internal SPI shift register of the TLE6288R. The serial input
(SI) accepts data into the input SPI shift register on the rising edge of SCLK (if CLKProg = L; falling edge if
CLKProg = H) while the serial output (SO) shifts diagnostic information out of the SPI shift register on the falling
SPI
CS
SCLK
SI
SO
internal logic registers
diagnosis register
16 bit SPI shift register
SI SO
CS
CS
MSB
MSB
LSB
LSB
Serial input
data MSB first
Serial output
(diagnosis)
MSB first
TLE6288R
SPI
Data Sheet 16 Rev. 2.5, 2010-10-11
edge (if CLKProg = L; rising edge if CLKProg = H) of serial clock. It is essential that the SCLK pin is in a logic high
state (if CLKProg = L; low state if CLKProg = H) whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read
in on the rising edge of SCLK (if CLKProg = L; falling edge if CLKProg = H). Input data is latched in the SPI shift
register and then transferred to the internal registers of the logic.
The input data consists of 16 bits, made up of 4 control bits and 12 data bits. The control word is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 5.5).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO
is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO
pin following the falling edge of SCLK (if CLKProg = L; rising edge if CLKProg = H).
5.2 Electrical Characteristics: SPI Timing
Electrical Characteristics: SPI Timing
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
5.2.1 Serial Clock Frequency
(depending on SO load)
fSCLK DC – 5 MHz – –
5.2.2 Serial Clock Period (1/fSCLK)tp(SCLK) 200––ns– –
5.2.3 Serial Clock High Time tSCLKH 50––ns– –
5.2.4 Serial Clock Low Time tSCLKL 50––ns– –
5.2.5 Enable Lead Time
(falling edge of CS to falling
edge of SCLK)
tleadL 200––ns– CLKProg = L
Enable Lead Time
(falling edge of CS to rising
edge of SCLK)
tleadH 200––ns– CLKProg = H
5.2.6 Enable Lag Time (rising edge
of SCLK to rising edge of CS)
tlagL 200––ns– CLKProg = L
Enable Lag Time (falling edge
of SCLK to rising edge of CS)
tlagH 200––ns– CLKProg = H
5.2.7 Data Setup Time (required
time SI to rising of SCLK)
tSUL 20––ns– CLKProg = L
Data Setup Time (required
time SI to falling of SCLK)
tSUH 20––ns– CLKProg = H
5.2.8 Data Hold Time (rising edge of
SCLK to SI)
tHL 20––ns– CLKProg = L
Data Hold Time (falling edge of
SCLK to SI)
tHH 20––ns– CLKProg = H
5.2.9 Disable Time1) tDIS ––200ns– –
Data Sheet 17 Rev. 2.5, 2010-10-11
TLE6288R
SPI
5.3 SPI Diagnostics
As soon as a fault occurs for longer than the fault filter time, the fault information is latched into the diagnosis
register (and the Fault pin will change from high to low state). A new error on the same channel will overwrite the
old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal,
all diagnosis bits can be shifted out serially. If the sent command was valid (see Note in Chapter 5.5) the rising
edge of CS will reset the diagnosis registers (except the channel OT flag) and restart the fault filter time. In case
of an invalid command the device will ignore the data bits and the diagnosis register will not be reset at the rising
CS edge.
Figure 9 Two Bits per Channel Diagnostic Feedback plus two Overtemperature Flags
For Full Diagnosis there are two diagnostic bits per channel configured as shown in Figure 9.
Diagnosis bit 0 and bit 1 are always set to 1.
5.2.10 Transfer Delay Time2)
(CS high time between two
accesses)
tdt 200––ns– –
5.2.11 Data Valid Time1)
CL = 50 pF to 100 pF
CL = 220 pF
tvalid
–
–
–
–
120
150
ns – –
1) Not subject to production test, specified by design.
2) To get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault filter time
tf(fault)max = 200 μs.
Electrical Characteristics: SPI Timing (cont’d)
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
Diagnostic Serial Data Out SO
HH Normal function
HL Overload, Shorted Load or Overtemperature
LH Open Load
LL Switch Bypassed
Ch.6 Ch.5 Ch.4 Ch.3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB
Ch.2 Ch.1
LSB
Channel Overtem-
perature Flag
IC Overtem-
perature Flag
Bit0 and Bit1
is always 1
TLE6288R
SPI
Data Sheet 18 Rev. 2.5, 2010-10-11
Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function.
Overload, Shorted Load or Overtemperature: HL is set when the current limitation gets active, i.e. there is a
overload, short to supply or overtemperature condition. The second reason for this bit combination is
overtemperature of the corresponding channel.
In current regulation mode HL is also set if the load current reaches the programmed current value in a time shorter
than the fixed off time (tfo). This detection is only performed at the first rising load current edge after a channel is
turned on (for channel 1 to 3). See Chapter 7.3.
Open load: LH is set when open load is detected (in off state of the channel).
Switch Bypassed:
•Short to GND: in lowside configuration LL is set when this condition is detected.
•Short to Battery: in highside configuration LL is set when this condition is detected.
Channel Overtemperature Flag: In case of overtemperature in any output channel in on state the
overtemperature Flag in the SPI diagnosis register is set (change bit 3 from 0 to 1). This bit can be used to
distinguish between Overload and Overtemperature (both HL combination) and is reset by switching OFF/ON the
affected channel.
In addition the DIAG6 / Overtemp pin is set low (if configured as Overtemp Flag).
IC Overtemperature Flag: When the IC logic temperature exceeds typ. 170 °C the non-latching IC
Overtemperature Flag will be set in the SPI diagnosis register (change bit 2 from 0 to 1).
In addition the DIAG6 / Overtemp pin is set low (if configured as Overtemp. Flag).
5.4 SPI Commands, Values and Parameters
The 16-bit SPI is used to program different IC functions and values, turn on and off the channels and to get detailed
diagnosis information. Therefore 4 command bits and 12 data bits are used.
Figure 10
Data Sheet 19 Rev. 2.5, 2010-10-11
TLE6288R
SPI
The following parameters and functional behavior can be programmed by SPI:
•Current regulation mode (mode): for each of the 3 highside channels individually the operation mode can be
set.
– “no current regulation”
– current regulation “hold only”
– current regulation “peak & hold with minimum peak time”
– current regulation “peak & hold with programmed peak time”
•Peak Current (Ipk): for each of the 3 highside channels individually the peak current value for P&H current
regulation can be programmed. The current range is 1.2 A to 3.6 A.
•Fixed off time of the current regulator (tfo): for each of the 3 highside channels (Ch1 to Ch3) individually the
fixed off time for all modes with current regulation can be programmed from 100 μs to 400 μs.
•Hold current (Ihd): for each of the 3 highside channels (Ch1 to Ch3) individually the hold current value for P&H
and hold only current regulation can be programmed. The current range is 0.7 A to 2.0 A.
•Peak time (tp): for each of the 3 highside channels (Ch1 to Ch3) individually the peak time value for P&H
current regulation can be programmed. The time range is 0.8 ms to 3.6 ms.
•Highside/Lowside configuration (H/L): Each of the 3 configurable channels (Ch4 to Ch6) can be
programmed for use as Highside switch or Lowside switch.
•Open load and switch bypassed detection activated or deactivated (OL+SB): For each of the 3
configurable channels (Ch4 to Ch6) the open load and switch bypassed diagnosis can be deactivated. In
lowside configuration the open load and the short to GND detection can be deactivated, in highside
configuration the open load and short to battery detection.
•Boolean operation (OR/AND): For all channels generally the Boolean operation of the parallel input signal
and the SPI bit of the corresponding channel can be defined.
•Overtemperature behavior (R/L): The overtemperature behavior of the channels can be programmed by SPI.
Autorestart or latching overtemperature shutdown can be selected (for all channels the same behavior).
•DIAG6 or overtemperature flag (D/F): With this SPI bit the function of the DIAG6 / Overtemp pin is defined.
This output can work as diagnosis output of channel 6 or as Overtemperature Flag.
5.5 SPI Commands
Table 3 Command Table
Command MSB14131211 10 9 8 7 6 5 4 3 2 1 LSB
Set all to Default 1 000XX XX XX X XX XXX
Config. Regulator 1 1 0 0 1 Mode Ipk tfo Ihd tpX
Config. Regulator 2 1 0 1 0 Mode Ipk tfo Ihd tpX
Config. Regulator 3 1 0 1 1 Mode Ipk tfo Ihd tpX
Config. Ch1 - Ch6 1 1 0 0 Ch6
H/L
Ch6
OL+
SB
Ch5
H/L
Ch5
OL+
SB
Ch4
H/L
Ch4
OL+
SB
all
OR/
AND
all
R/L
DIAG
6D/F
XXX
Channels on/off 1 1 0 1 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 X X X X X X
Diagnosis only 1 1 1 1 X X X X X X X X X X X X
TLE6288R
SPI
Data Sheet 20 Rev. 2.5, 2010-10-11
Legend of SPI Command Table
• Mode: Operation mode of the current regulator:
– no regulation
– hold only
– peak & hold with minimum peak time
– peak & hold with programmed peak time
•Ipk: Peak current values 1.2 A … 3.6 A
•Ihd: Hold current values 0.7 A … 2 A
•tp: Peak time value 0.8 ms … 3.6 ms
•tfo: Fixed off time value 100 μs … 400 μs
• H/L: Channel 4 to 6 in highside or lowside configuration
• OL+SB: open load detection and switch bypassed detection activated or deactivated
• OR/AND: Boolean Operation (parallel input and corresponding SPI Bit)
• R/L: Autorestart or Latching overtemperature behaviour
• D/F: DIAG6/Overtemp pin set as Diagnosis output of channel 6 or as Overtemperature Flag
• Ch1-Ch6: On/Off information of the output drivers (high active)
Command Description
Config. Regulator 1-3: With this command the values for the current regulation and the functional mode of the
channel is written into the internal logic registers.
Config. Ch1 to Ch6: This command writes the configuration data of the 3 configurable channels (4-6) and sets
the Boolean operation and overtemperature behavior of all channels. It also sets the DIAG6/Overtemp. pin to
Diagnosis of channel 6 or Overtemperature Flag.
Set all to default: This command sets all internal logic registers back to default settings.
Diagnosis only: When this command is sent the 12 data bits are ignored. The internal logic registers are not
changed.
Channels on/off: With this command the SPI bits for the ON/OFF information of the 6 Channels are set.
Note: Specified control words (valid commands) are executed and the diagnosis register is reset after the rising
CS edge.
Not specified control words are not executed (cause no function) and the diagnosis register is not reset after
the CS = L →H signal.
Data Sheet 21 Rev. 2.5, 2010-10-11
TLE6288R
SPI
5.6 Bit Assignment and Default Settings for Internal Logic Registers
Default Settings are in bold print.
Mode 00 no current regulation
01 hold only
10 P&H minimum peak time
11 P&H with programmed times
Peak Current (Ipk)1.2 A 1.8 A 2.4 A 3.6 A
2 Bits 00 01 10 11
Hold Current (Ihd)0.7 A 1.0 A 1.4 A 2.0 A
2 Bits 00 01 10 11
Fixed off Time (tfo)100 μs200 μs300 μs 400 μs
2 Bits 00 01 10 11
Peak Time (tp)0.8 ms 1.2 ms 1.6 ms 2.0 ms 2.4 ms 2.8 ms 3.2 ms 3.6 ms
3 Bits 000 001 010 011 100 101 110 111
Boolean operation OR AND
1 Bit 01
Overtemp. behavior Restart Latch
1 Bit 01
Diag6 / Overtemp Diag6 Overtemp. Flag
1 Bit 01
Highside / Lowside Highside Lowside
1 Bit 01
Open Load & SB (4-6) Yes No
1 Bit 01
Channels on / off off on
1 Bit 01
TLE6288R
SPI
Data Sheet 22 Rev. 2.5, 2010-10-11
5.7 SPI Timing Diagrams
Figure 11 Input Timing Diagram (CLKProg = L)
Figure 12 SO Valid Time Waveforms and Enable and Disable Time Waveforms (CLKProg = L)
Figure 13 Serial Interface
tleadL
tSCKH
0.2Vcc
tlagL
tHL
tSCKL
0.2 Vcc
tSUL
0.7Vcc
0.2Vcc
CS
SCLK
SI
0.7Vcc
tdt
0.7Vcc
tvalid
SCLK
CS
SO
tDis
0.2 Vcc
SO
0.2 Vcc
0.7 Vcc
0.2 Vcc
SO
0.7 Vcc
0.2 Vcc
4 control bit 12 data bit
C o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
SCLK
SI
SO
MSB LSB
Data Sheet 23 Rev. 2.5, 2010-10-11
TLE6288R
SPI
Figure 14 Input Timing Diagram (CLKProg = H)
Figure 15 SO Valid Time Waveforms and Enable and Disable Time Waveforms (CLKProg = H)
Figure 16 Serial Interface
tleadH
tSCKH
0.2Vcc
tlagH
tHH
tSCKL
0.2 Vcc
tSUH
0.7Vcc
0.2Vcc
CS
SCLK
SI
0.7Vcc
tdt
0.7V
cc
tvalid
SCLK
CS
SO
tDis
0.2 Vcc
SO
0.7 Vcc
0.7 Vcc
0.2 Vcc
SO
0.7 Vcc
0.2 Vcc
4 control bit 12 data bit
C o n t r o l word 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
SCLK
SI
SO
MSB LSB
TLE6288R
Electrical Characteristics Input / Output Pins
Data Sheet 24 Rev. 2.5, 2010-10-11
6 Electrical Characteristics Input / Output Pins
6.1 Power Supply, Reset
6.2 Power Outputs
Electrical Characteristics: Power Supply, Reset
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
6.1.1 Power Supply Current 1 IB– – 10 mA DOUT1-3 Ch1-Ch6: Off
6.1.2 Power Supply Current 2 ICC ––10mAVCC –
6.1.3 Power Supply Current in
Standby Mode
ICC + Ib––50μA DOUT1-3,
VCC
Reset = L
6.1.4 Minimum Reset Duration tReset,min 50 – – μs– –
6.1.5 Wake-up time after reset twakeup ––5ms– CCP = 10 nF
Electrical Characteristics: Power Outputs
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
6.2.1 On Resistance RDS(ON) ––350mΩDOUTx -
SOUTx
ID = 2.4 A
VB = 10 V
6.2.2 Forward Voltage Revers
Diode
VRDf ––2VSOUTx -
DOUTx
ID = -4 A
Tj = 150 °C
6.2.3 Peak Current range Ipk – 1.2 …
3.6
–A– –
6.2.4 Peak Current accuracy Ipka ––±15
±20
%
%
–Tj = 25, 150 °C
Tj = -40 °C
6.2.5 Hold Current range Ihd –0.7 … 2–A– –
6.2.6 Hold Current accuracy Ihda ––±15
±20
%
%
–Tj = 25, 150 °C
Tj = -40 °C
6.2.7 Peak time range tp– 0.8 …
3.6
–ms– –
6.2.8 Peak time accuracy tpa ––±20 % – –
6.2.9 Fixed off Time range tfo – 100 …
400
–μs– –
6.2.10 Fixed off Time accuracy tfoa ––±30 % – 100 μs
6.2.11 Fixed off Time accuracy tfoa ––±20 % – 200 μs -
400 μs
6.2.12 Output ON Delay time1 tdON ––10μs– see Figure 17
6.2.13 Output ON Rise time1 tr––10μs– see Figure 17
Data Sheet 25 Rev. 2.5, 2010-10-11
TLE6288R
Electrical Characteristics Input / Output Pins
6.3 Digital Inputs
6.2.14 Output OFF Delay time tdOFF ––20μs – HS- Mode
LS- Mode
see Figure 17
6.2.15 Output OFF Fall time tf––10μs– see Figure 17
6.2.16 Leakage Current – – – 10 μA – Reset = L
6.2.17 Leak Current in OFF
(highside configuration)
Iloff ––-250μASOUT1-6–
6.2.18 Leak Current in OFF
(lowside configuration)
Iloff ––500μADOUT4-6–
6.2.19 Output Clamp Voltage
(highside configuration)
Vclh -19 -14 -9 V SOUT1-6 Refers to GND
level
6.2.20 Output Clamp Voltage
(lowside configuration)
Vcll 40 – 55 V DOUT4-6 Refers to GND
level
6.2.21 Current limitation
(Channel 1 to 3)
IDlim1-3 4–6A– –
6.2.22 Current limitation
(Channel 4 to 6)
IDlim4-6 3–6A– –
6.2.23 IC Overtemp. Warning1)
Hysteresis
Tot
Thys
160
–
–
10
180
–
°C
°C
––
1) Not subject to production test, specified by design.
Electrical Characteristics: Digital Inputs
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
6.3.1 Input Low Voltage VINL ––1Vall digit.
inputs
–
6.3.2 Input High Voltage VINH 2––V all digit.
inputs
–
6.3.3 Input Voltage Hysteresis VINHys – 100 – mV all digit.
inputs
–
6.3.4 Input pull-down current Ipd 20 50 100 μAIN1-6;
CLKProg
VIN = 5 V
6.3.5 Input pull-up current Ipu -100 -50 -20 μAReset;
FSIN
VIN = GND
Electrical Characteristics: Power Outputs (cont’d)
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
TLE6288R
Electrical Characteristics Input / Output Pins
Data Sheet 26 Rev. 2.5, 2010-10-11
6.4 Digital Outputs
Figure 17 Turn on/off Timings with Resistive Load
6.3.6 SPI Input pull-down current Ipd 10 20 50 μA SI, SCLK
(CLKProg
= H)
VIN = 5 V
6.3.7 SPI Input pull-up current Ipu -50 -20 -10 μA CS, SCLK
(CLKProg
= L)
VIN = GND
Electrical Characteristics: Digital Outputs
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
6.4.1 SO Low State Output Voltage VSOL ––0.4VSO ISOL = 2.5 mA
6.4.2 SO High State Output Voltage VSOH VDO -
0.4 V
––VSO ISOH = -2 mA
6.4.3 DIAG Low State Output
Voltage
VDIAGL ––0.4VDIAG1-6IDIAGL = 50 μA
6.4.4 DIAG High State Output
Voltage
VDIAGH VDO -
0.4 V
––VDIAG1-6IDIAGH =
-50 μA
6.4.5 Fault Low Output Voltage Vol – – 0.4 V Fault Iout = 1 mA
6.4.6 Fault Output leak Current Ioh ––1μA Fault Output: OFF
V(fault) = 5 V
Electrical Characteristics: Digital Inputs (cont’d)
VCC = 4.5 V to 5.5 V, Tj = -40 ⋅C to +150 ⋅C, VB = 6 V to 16 V, Reset = H, VDO = VCC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Pin/
Comment
Conditions
Min. Typ. Max.
Input Voltage
Output Voltage
(Highside configuration)
70%
30%
tdON tdOFF
trtf
Data Sheet 27 Rev. 2.5, 2010-10-11
TLE6288R
Application Information
7 Application Information
7.1 Zthjc Diagram Junction - Case for Single channel operation
Figure 18 Zthjc Diagram
• Conditions for Figure 18
– Results based on FEM Simulations
–Tcase = 125 °C
–Single Channel operation, 0.8W power dissipation
7.2 Thermal Application Information
All thermal resistance values in this document are data from FEM (Finite Element Modelling). The boundary
conditions are chosen according to the JESD51 standard. Therefore, all values can be viewed as reliable and
reproducible.
The high effective thermal conductivity test PCB (2s2p) gives a near best case thermal performance value.
compared to the single layer low effective thermal conductivity PCB (1s). It should be emphasized that values
measured/simulated with these test boards cannot be used to directly predict any particular system application
performance.
In real applications, the RthjA can be influenced by the environment and PCB conditions. Thermal vias, application
specific multi layer PCBs and a direct thermal connection to the ECU metal-case are often used to improve the
thermal impedance RthjA.
0,01
0,1
1
10
0,000001 0,00001 0,0001 0,001 0,01 0,1
Pulse width [s]
Zth(D, Pulse width) [K/W
]
0,5
0,2
0,1
0,05
0,02
0,01
Dutycycle D
TLE6288R
Application Information
Data Sheet 28 Rev. 2.5, 2010-10-11
Figure 19 FE Model of the JEDEC 2s2p PCB
Figure 20 Thermal via layout
Figure 19 showes the Product TLE6288R on the 2s2p board used to specify the typical RthjA value in Chapter 3.2.
In Figure 20, the thermal via layout according to JESD51-5 is shown.
Data Sheet 29 Rev. 2.5, 2010-10-11
TLE6288R
Application Information
7.3 Overload/Low Inductance Load Detection in Current Regulation Mode
Figure 21
Load Current
normal condition
Ipk / Ihd
tfo
Input Signal
tli
Load Current
low-inductance load
Ipk / Ihd
tfo
tli
Overload / low inductance load detection
Load Current
normal condition
Ipk / Ihd
tfo
Input Signal
tli
Load Current
low-inductance load
Ipk / Ihd
tfo
tli
Overload / low inductance load detection
TLE6288R
Package Outlines
Data Sheet 30 Rev. 2.5, 2010-10-11
8 Package Outlines
Figure 22 PG-DSO-36-54 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Bottom View
Does not include plastic or metal protrusion of 0.15 max. per side
118
0.25
±0.1
1.1
36
+0.13 0.25
36x
19
M
(Heatslug)
15.74
0.65
±0.1
CAB
19
C
3.25
3.5 MAX.
+0.1
0
0.1
±0.1
36
2.8 B
11±0.15 1)
1.3
5˚
0.25
±3˚
-0.02
+0.07
6.3
14.2
(Mold)
±0.3 B
±0.15
0.25
Heatslug
0.95
Heatslug
±0.1
5.9
3.2
(Metal)
±0.1
(Metal)
13.7
(Metal)
10 1
-0.2
Index Marking
(Mold)
15.9 1)
±0.1 A
1 x 45˚
1)
GPS09181
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
Data Sheet 31 Rev. 2.5, 2010-10-11
TLE6288R
Revision History
9 Revision History
Revision Date Changes
2.2 2004-03-25 Preliminary Datasheet TLE6288R Vp2.2
2.3 2006-05-03 Formal changes, Thermal information added, Spec. values not changed
2.4 2007-08-08 RoHS-compliant version of the TLE6288R
Page 3:
“AEC qualified” and “RoHS” logo added, “Green Product (RoHS compliant)” and “AEC
qualified” statement added to feature list, package names changed to RoHS
compliant versions, package pictures updated
Page 30:
Package names changed to RoHS compliant versions, “Green Product” description
added
Revision History updated
Legal Disclaimer updated
2.5 2010-10-11 Updated package type
Edition 2010-10-11
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.