Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F eee CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION | 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION 5.1 Pinning 5.2 Pin description 6 FREQUENCY GENERATOR 6.1 Frequency generator derivative registers 6.2 Melody output (P1.7/MDY) 6.3 Frequency registers: 6.4 DTMF frequencies 6.5 Modem frequencies 6.6 Musical scale frequencies 7 EEPROM AND TIMER 2 ORGANIZATION 7.1 EEPROM registers 7.2 EEPROM latches 7.3 EEPROM flags 7.4 EEPROM macros 7.5 EEPROM access 7.6 Timer 2 8 DERIVATIVE INTERRUPTS 9 TIMING 10 RESET 11 IDLE MODE 12 STOP MODE 13 INSTRUCTION SET RESTRICTIONS 14 OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION 15 OTP PROGRAMMING 16 SUMMARY OF DERIVATIVE REGISTERS 17 HANDLING 18 LIMITING VALUES 19 DC CHARACTERISTICS 20 AC CHARACTERISTICS 21 PACKAGE OUTLINES 22 SOLDERING 22.1 Reflow soldering 22.2 Wave soldering 22.3 DIP 22.4 Repairing soldered joints 23 DEFINITIONS 24 LIFE SUPPORT APPLICATIONS 1997 Apr 16 1043Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F = FEATURES 8-bit CPU, ROM, RAM, EEPROM and I/O; in a single 28-lead or 32-lead package 8 kbytes user-programmable ROM (One-Time Programmable) * 128 bytes RAM 128 bytes Electrically Erasable Programmable Read-Only Memory (EEPROM) * Over 100 instructions (based on MAB8048) all of 1 or 2 cycles 20 quasi-bidirectional I/O port lines 8-bit programmable Timer/event counter 1 8-bit reloadable Timer 2 Three single-level vectored interrupts: external 8-bit programmable Timer/event counter 1 derivative; triggered by reloadable Timer 2 Two test inputs, one of which also serves as the external interrupt input e DTMF, modem, musical tone generator Reference for supply and temperature-independent tone output Filtering for low output distortion (CEPT compatible) Melody output for ringer application e Power-on-reset Stop and Idle modes Supply voltage: 1.8 to 6 V (DTMF tone output and EEPROM erase/write from 2.5 V) e Clock frequency: 1 to 16 MHz (3.58 MHz for DTMF suggested) e Operating temperature: 25 to +70 C Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION (see note 1) 2 GENERAL DESCRIPTION This data sheet details the specific properties of the PCD3755A, PCD3755E and PCD3755F. The devices differ in their Port and Power-on-reset configurations. References to PCD3755x apply to all three types. The devices are members of the PCD33xxA family of microcontrollers. The shared properties of the family are described in the PCD33xxA family data sheet, which should be read in conjunction with this publication. The PCD3755A, PCD3755E and PCD3755F are One-Time Programmable (OTP) microcontrollers designed primarily for telephony applications. They include an on-chip generator for dual tone multifrequency (DTMF), modem and musical tones. In addition to dialling, generated frequencies can be made available as square waves (P1.7/MDY) for melody generation, providing ringer operation. The PCD3755A, PCD3755E and PCD3755F also incorporate 128 bytes of EEPROM. The EEPROM can be used for storing telephone numbers, particularly for implementing redial! functions. The Power-on-reset circuitry is extra accurate to accommodate parallel telephones and fax equipment. The instruction set is similar to that of the MAB8048 and is a sub-set of that listed in the PCD33xxA family data sheet. PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCD3755xP DIP28 | plastic dual in-line package; 28 leads (600 mil) SOT117-1 PCD3755xT $028 | plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 PCD3755xH LQFP32 | plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4mm SOT358-1 Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and the ROM mask options. 1997 Apr 16 1044Product specification PCD3755A; PCD3755E Philips Semiconductors bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM 8 PCD3755F 4 BLOCK DIAGRAM wesBeip yooig 4 'Bi4 OLYTTIOSO SZITWLLUNI LdTdY3LNI ZWiX -WIX 138au O19 z101 NIALL ONY TOHLNOD I+ dous asnray TWAIDS0 6o90aN se1q ezt 183. AVE WY LINACISau Jug 900 oo > 91901 3YOLS vLVG AHO o ova HONVUB wawu >| AWNOLLIGNOS NYE HALSIOSY on/a0 >} GNOo3s TNO | 3 (aionaT aTaviewa) | 2 id wovis angie |S <= i waisioad 3 wagoos0 9 uaisIO3 a aNy $ HAlSIOae waisi9ay | | vualsiogy NOLLOMBLSNI euaisioay WAaLSIOay ZuaLSIOIY ssaucdy | YaLsioau Wve 0W31SIO30 Yad le yaruaqUr eLEKE 1aSay wind issaenowowe] IND 9107 seudq ez Woudaa OUSLY idnuewut eaneauep idnuew un | | Lyaisiogy zuaisiogd | | 0 winwnooy 91007 SdSNVEL gaisiead AuvHOdWAL | | AuVEOdWaL Ad nWUBLNI Woudsa 7 HaLSIOIY W3LSIDSY JOULNOD ee <7] avo wowd33 ZuSWL tt gf 0d 00d qHuOM wainnioo | | waiNnoo | | HaLNnoo [* tL snivis WyHOOud WVHODOUd AN3AZ WYYDOUd YaHOIH AB Zee aaoogd dO14-dI1s 0 1HOd Wana sovkay 8 O1YOd WOw-dLO INadIS3u Ht yaLsIoaY Yass 2oTN ae | AGOTSN Dhd WO yOLVYSNIS AWM Nis dod Z1uOd adane @LHOd Cad WOE 1045 1997 Apr 16Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 5 PINNING INFORMATION 5.1 Pinning Pot [7] U 28] PO.0 Po [2 | 27] P2.3 Pos [3 | [26] P2.2 Poa [4 | [25] P2.1 Pos [5 | [24] Yop Pos [6 | 23) TONE P07 [7 | pepszssxP]2] ss 11 [S| PCD3755xT [a7] P20 XTAL [9 | [20] P1.7/MDY xTAL2 [19] i9] P16 Reset [11] 18] P1.5 CEO [12] 17] P14 P10 [13] 16] P1.3 Pit [14] 15] P12 M8GE40 Fig.2 Pin configuration (SOT117-1 and SOT136-1). [32] P0.4 [31] P03 ne. Pos [2 | Pos [3 | Paz [4] 11 [5] XTAL1 [6 | xTa2 [7 | reser [6 | [30] P02 [29] Po.1 [28] nc. PCD3755xH [27] P0.0 [26] P2.3 [25] P2.2 [24] P21 23] Yop 22] TONE [21] Vgg [20] P2.0 49] P1.7/MDY 18] P1.6 n.c. P1.0 [70] Pid certo [9 | m P1.2|12 no. [13] P13 [14] p1.4 [15] p15 [16] Fig.3 Pin configuration (SOT358-1). MBG641 1997 Apr 16 1046Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM PCD3755A; PCD3755E; PCD3755F 5.2 Pin description Table 1. SOT117-1 and SOT136-1 packages (for information on parallel I/O ports, see Chapter 14) SYMBOL PIN TYPE DESCRIPTION P1.1 to P0.7 1to7 vo 7 bits of Port 0: 8-bit quasi-bidirectional I/O port T1 8 I Test 1 or count input of 8-bit Timer/event counter 1 XTAL1 9 t crystal oscillator or external clock input XTAL2 10 oO crystal oscillator output RESET 11 I reset input CE/TO 12 | Chip Enable or Test 0 P1.0 to P1.6 13 to 19 VO 7 bits of Port 1: 8-bit quasi-bidirectional /O port P1.7/MDY 20 VO 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output P2.0 21 VO 1 bit of Port 2: 4-bit quasi-bidirectional I/O port Vss 22 P ground TONE 23 Oo DTMF output Vpp 24 P positive supply voltage P2.1 to P2.3 25 to 27 VO 3 bits of Port 2: 4-bit quasi-bidirectionai /O port P0.0 28 VO 1 bit of Port 0: 8-bit quasi-bidirectional I/O port Table 2 SOT358-1 package (f or information on parallel /O ports, see Chapter 14) SYMBOL PIN TYPE DESCRIPTION nc. 1, 13, 17, 28 ~ not connected PO.5 to P0.7 2to04 VO 3 bits of Port 0: 8-bit quasi-bidirectional I/O port T1 5 I Test 1 or count input of 8-bit Timer/event counter 1 XTAL1 6 I crystal oscillator or external clock input XTAL2 7 Oo crystal oscillator output RESET 8 I reset input CE/TO 9g \ Chip Enable or Test 0 P1.0 to P1.6 10 to 12, VO 7 bits of Port 1: 8-bit quasi-bidirectional 1/O port 14 to 16, 18 P1.7/MDY 19 Vo 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output P2.0 20 VO 1 bit of Port 2: 4-bit quasi-bidirectional I/O port Vss 21 P ground TONE 22 0 DTMF output Vop 23 P positive supply voltage P2.1 to P2.3 24 to 26 VO 3 bits of Port 2: 4-bit quasi-bidirectional /O port PO.0 to PO.4 27, 29 to 32 ie) 5 bits of Port 0: 8-bit quasi-bidirectional |/O port 1997 Apr 16 4047Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 6 FREQUENCY GENERATOR A versatile frequency generator section is provided (see Fig.4). For norma! operation, use a 3.68 MHz quartz crystal or PXE resonator. The frequency generator includes precision circuitry for dual tone multifrequency (DTMF) signals, which is typically used for tone dialling telephone sets. The TONE output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. In addition to DTMF and modem frequencies, two octaves of musical scale in steps of semitones are available. In case no tones are generated the TONE output is in 3-state mode. Their frequencies are provided in purely sinusoidal form on the TONE output or as square waves on the P1.7/MDY output. 6.1 Frequency generator derivative registers 6.1.1 Table 3 gives the addresses, mnemonics and access types of the High Group Frequency (HGF) and Low Group Frequency (LGF) registers. HIGH AND Low GROUP FREQUENCY REGISTERS Table 3. Hexadecimal! addresses, mnemonics, access types and bit mnemonics of the frequency registers REGISTER | REGISTER | ACCESS BIT MNEMONICS ADDRESS | MNEMONIC TYPE 7 6 5 4 3 2 1 0 11H HGF WwW H7 H6 H5 H4 H3 H2 H1 HO 12H LGF Ww L7 L6 L5 L4 L3 L2 L1 LO 6.1.2 | MELODY CONTROL REGISTER (MDYCON) MDYCON is a R/W register. Table 4 Melody Control Register (address 13H) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 EMO Table 5 Description of MDYCON bits BIT MNEMONIC DESCRIPTION 7to1 - 0 EMO These bits are set to a logic 0. Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line. If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY must remain set to avoid conflicts between melody and port outputs. When the HGF contents are zero while EMO = 1, P1.7/MDY is in the logic HIGH state. 1997 Apr 16Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F L 8 ELODY CONTRO A oL_ Mpasren SSeS Br square wave 8 DIGITAL SYNTHESIZER +] SWITCHED SWITCHED C. CIT 8 INTERNAL BUS BANDGAP_ b.. OW PASS | of RC ems +-> TONE VOLTAGE FILTER AEFERENCE | oa c| MLC4IE ITAL ame J) otis | SYNTHESIZER Fig.4 Block diagram of the frequency generator and melody output (P1.7/MDY) section. 1997 Apr 16 1049Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 6.2 Melody output (P1.7/MDY) The melody output (P1.7/MDY) is very useful for generating musical tones when a purely sinusoidal signal is not required, such as for ringer applications. The square wave (duty cycle = 1343 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the HGF register (Table 3). However, even higher frequency tones may be produced since the low-pass filtering on the TONE output is not applied to the P1.7/MDY output. This results in the minimum decimal value x in the HGF register being 2 for the P1.7/MDY output, rather than 60 for the TONE output - the value shown in equation (1). A sinusoidal TONE auiput is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves with x < 60 will not appear at the TONE output. Since the melody output is shared with P1.7, the port flip-flop of P1.7 has to be set HIGH before using the melody output. This is to avoid conflicts between melody and port outputs. The melody output drive depends on the configuration of port P1.7/MDY; see Chapter 14, Tabie 24. 6.3 Frequency registers The two frequency registers HGF and LGF define two frequencies. From these, the digital sine synthesizers together with the Digital-to-Analog Converters (DACs) construct two sine waves. Their amplitudes are precisely scaled according to the bandgap voltage reference. This ensures tone output levels independent of supply voltage and temperature. 1997 Apr 16 The amplitude of the Low group frequency sine wave is attenuated by 2 dB compared to the amplitude of the High group frequency sine wave. The two sine waves are summed and then filtered by an on-chip switched capacitor and RC low-pass filters. These guarantee that all DTMF tones generated fulfil the CEPT recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. The value 00H in a frequency register stops the corresponding digital sine synthesizer. If both frequency registers contain OOH, the whole frequency generator is shut off, resulting in lower power consumption. The frequency of the sine wave generated f' is dependent on the clock frequency fia and the decimal value x held in the frequency registers (HGF and LGF). The variables are related by the equation: F ta f = [23 (x+2)] where 60<x<255 = (1) The frequency limitation given by x > 60 is due to the low-pass filters which would attenuate higher frequency sine waves. 1050Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 6.4 DTMF frequencies 6.5 Modem frequencies Assuming an oscillator frequency fy1a) = 3.58 MHz, the DTMF standard frequencies can be implemented as shown in Table 6. Again assuming an oscillator frequency fyi = 3.58 MHz, the standard modem frequencies can be implemented as in Table 8. It is suggested to define the frequency by the HGF register while the LGF register contains OOH, The relationships between telephone keyboard symbols, disabling Low Group Frequency generation. DTMF frequency pairs and the frequency register contents are given in Table 7. Table 8 Standard modem frequencies and their Table 6 DTMF standard frequencies and their implementation implementation; value = LGF, HGF contents HGF FREQUENCY (Hz) DEVIATION VALUE FREQUENCY (Hz) DEVIATION \HEX) MODEM | GENERATED | (%) | (Hz) (HEX) | STANDARD | GENERATED | (%) | (Hz) 9D 980") 978.82 ~0.12 1-118 DD 697 97.90 0.13 | 0.90 82 | 11800) 1179.03 ~0.08 | -0.97 cs 770 770.46 0.06 | 0.46 8F | 10702) 1073.33 0.31 | 3.33 BS 852 850.45 0.18 | -1.55 79 =| 1270) 1265.30 -0.37 | -4.70 A3 941 943.23 0.24 | 2.23 80 | 12000) 1197.17 0.24 | -2.83 7F 1209 1206.45 -0.21 | -2.55 45 | 22000) 2192.01 -0.36 | -7.99 72 1336 1341.66 0.42 | 5.66 76 43004) 1296.94 -0.24 | -3.06 67 1477 1482.21 0.35 | 5.21 48 21004 2103.14 0.15 | 3.14 5D 1633 1638.24 0.32 | 5.24 5c 11650 1655.66 0.34 | 5.66 _ 52 1185001) 1852.77 0.15 | 2.77 Table 7 Dialling symbols, corresponding DTMF frequency pairs and frequency register contents 4B 2.025%) 2021.20 0.19 | -3.80 44 | 22250) 2223.32 ~0.08 | -1.68 TELEPHONE | DTMF FREQ.| LGF HGF KEYBOARD PAIRS VALUE VALUE Notes SYMBOLS (Hz) (HEX) (HEX) 1. Standard is V.21. 0 (941, 1336) A3 72 2. Standard is Bell 103. 1 (697, 1209) DD 7F 3. Standard is Bell 202. 2 (697, 1336) DD 72 4. Standard is V.23. 3 (697, 1477) DD 67 4 (770, 1209) C8 7F 5 (770, 1336) C8 72 6 (770, 1477) C8 67 7 (852, 1209) BS 7F 8 (852, 1336) BS 72 g (852, 1477) BS 67 A (697, 1633) DD 5D B (770, 1633) C8 5D fo (852, 1633) BS 5D D (941, 1633) A3 5D * (941, 1209) A3 7F # (941, 1477) A3 67 1997 Apr 16 1051Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 6.6 Musical scale frequencies Finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency fxta = 3.58 MHz (Table 9). It is suggested to define the frequency by the HGF register while the LGF contains OOH, disabling Low Group Frequency generation. Table 9 Musical scale frequencies and their implementation : HGF FREQUENCY (Hz) NOTE | VALUE (HEX) STANDARD") | GENERATED D#5 F8 622.3 622.5 E5 EA 659.3 659.5 F5 DD 698.5 697.9 F#5 DO 740.0 741.1 G5 C5 784.0 782.1 G#5 Bg 830.6 832.3 A5 AF 880.0 879.3 A#5 AS 923.3 931.9 BS 9C 987.8 985.0 c 93 4046.5 1044.5 C#6 8A 1108.7 4111.7 D6 82 1174.7 1179.0 D#6 7B 1244.5 1245.1 E6 74 1318.5 1318.9 F6 6D 1396.9 1402.1 F#E 67 1480.0 1482.2 G6 61 1568.0 1572.0 G# 5C 1661.2 1655.7 A6 56 1760.0 1768.5 A#6 51 1864.7 1875.1 B6 4D 1975.5 1970.0 C7 48 2093.0 2103.3 C#7 44 2217.5 2223.3 D7 40 2349.3 2358.1 D#7 3D 2489.0 2470.4 Note 1. Standard scale based on A4 @ 440 Hz. 1997 Apr 16 7 EEPROM AND TIMER 2 ORGANIZATION The PCD3755A, PCD3755E and PCD3755F have 128 bytes of Electrically Erasable Programmable Read-Only Memory (EEPROM). Such non-volatile storage provides data retention without the need for battery backup. In telecom applications, the EEPROM is used for storing redial numbers and for short dialling of frequently used numbers. More generally, EEPROM may be used for customizing microcontrollers, such as to include a PIN code or a country code, to define trimming parameters, to select application features from the range stored in ROM. The most significant difference between a RAM and an EEPROM is that a bit in EEPROM, once written to a logic 1, cannot be cleared by a subsequent write operation. Successive write accesses actually perform a logical OR with the previously stored information. Therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. Thus, an erase-and-write operation is the EEPROM equivalent of a RAM write operation. Whereas read access times to an EEPROM are comparable to RAM access times, write and erase accesses are much slower at 5 ms each. To make these operations more efficient, several provisions are available in the PCD3755A, PCD3755E and PCD3755F. First, the EEPROM array is structured into 32 four-byte pages (see Fig.5) permitting access to 4 bytes in paraliel (write page, erase/write page and erase page). It is also possible to erase and write individual bytes. Finally, the EEPROM address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. To simplify the erase and write timing, the derivative 8-bit down-counter (Timer 2) with reload register is provided. In addition to EEPROM timing, Timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths. 1052Philips Semiconductors . Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM PCD3755A; PCD3755E; PCD3755F + 5 8 EEPROM ADDRESS REGISTER . co i 2:4 DECODER \ / 5 : 82 DECODER \ EEPROM LATCH 0 8 EEPROM LATCH 1 EEPROMLATCH 2] [F2] EEPROMLATCH 3] [F3] 128-byte EEPROM ARRAY (32 4-byte PAGES) 8 8 , EEPROM TEST REGISTER 8 EEPROM CONTROL REGISTER TIMER 2 RELOAD REGISTER 8 TIMER 2 REGISTER (T2) T2F set on underflow MGBE24 1 _ f. INTERNAL 480 Xtal BUS Fig.5 Block diagram of the EEPROM and Timer 2. 1997 Apr 16 1053Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PPCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 7.1. EEPROM registers 7.1.1. EEPROM ConTROL REGISTER (EPCR) The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register. Table 10 EEPROM Control Register (address 04H, access type R/W) . 7 6 5 4 3 2 1 STT2 ET2! T2F EWP MC3 MC2 MC1 Table 11 Description of EPCR bits BIT MNEMONIC DESCRIPTION 7 STT2 Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2 decrements from reload value. 6 ET21 Enable T2 interrupt. if ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1, then T2F event can request interrupt. 5 T2F Timer 2 flag. Set when T2 underflows (or by program); reset by program. 4 EWP Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or write and Timer 2). Reset at the end of EEPROM erase and/or write. 3 MC3 Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as 2 MC2 shown in Table 12. 1 MC1 0 - This bit is set to a logic 0. Table 12 Mode selection; X = dont care EWP MC3 MC2 MC1 DESCRIPTION 0 0 0 0 read byte 0 0 1 0 increment mode 1 0 1 x write page 1 1 0 0 erase/write page 1 1 1 1 erase page xX 0 0 1 not allowed x 1 0 1 x 1 1 0 1997 Apr 16 1054Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM PCD3755A; PCD3755E; : PCD3755F 7.1.2 EEPROM ADDRESS REGISTER (ADDR) The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed. As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero. Table 13 EEPROM Address Register (address 01H, access type R/W) 7 6 5 4 3 2 1 0 0 AD6 AD5 AD4 AD3 AD2 AD1 ADO Table 14 Description of ADDR bits BIT MNEMONIC DESCRIPTION 7 - This bit is set to a logic 0. 6to2 AD6 to AD2 | AD2 to AD6 select one of 32 pages. 1toO AD1 to ADO | AD1 and ADO are irrelevant during erase and write cycles. For read accesses, ADO and AD1 indicate the byte location within an EEPROM page. During page setup, finally, ADO and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. lf increment mode (Table 12) is active during page setup, the subcounter consisting of ADO and AD1 increments after every write to an EEPROM latch, thus enhancing access to sequential EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when ADO and AD1 are both a logic 1. 7.1.3. EEPROM Data REGISTER (DATR) Table 15 EEPROM Data Register (address 03H; access type R/W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 DO Table 16 Description of DATR bits BIT MNEMONIC DESCRIPTION 7toO D7toDO |The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits ADO . and AD1 of ADDR. 7.1.4 EEPROM TEST REGISTER (TST) The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the device user. 1997 Apr 16 1055Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 7.2. EEPROM latches The four EEPROM latches (EEPROM Latch 0 to 3; Fig.5) cannot be read by user software. Due to their construction, the latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of any EEPROM cycle. 7.3. EEPROM flags The four EEPROM flags (FO to F3; Fig.5) cannot be directly accessed by user software. An EEPROM fiag is set as a side-effect when the corresponding EEPROM latch is written through DATR. The EEPROM flags are reset at the conclusion of any EEPROM cycle. 7.4. EEPROM macros The instruction sequence used in an EEPROM access should be treated as an indivisible entity. Erroneous programs resutt if ADDR, DATR, RELR or EPCR are inadvertently changed during an EEPROM cycle or its setup. Special care should be taken if the program may asynchronously divert due to an interrupt. Particularly, a new access to the EEPROM may only be initiated when no write, erase or erase/write cycles are in progress. This can be verified by reading bit EWP (register EPCR). For write, erase and erase/write cycles, it is assumed that the Timer 2 Reload Register (RELR) has been loaded with the appropriate value for a 5 ms delay, which depends on fxta (see Table 23). The end of a write, erase or erase/write cycle will be signalled by a cleared EWP and by a Timer 2 interrupt provided that ET21 = 1 and that the derivative interrupt is enabled. 7.5 EEPROM access One read, one write, one erase/write and one erase access are defined by bits EWP and MC1 to MC3 in the EPCR register; see Table 10. Read byte retrieves the EEPROM byte addressed by ADDR when DATR is read. Read cycies are instantaneous. Write and erase cycles take 5 ms, however. Erase/write is a combination of an erase and a subsequent write cycle, consequenily taking 10 ms. As their names imply, write page, erase page and erase/write page are applied to a whole EEPROM page. Therefore, bits ADO and AD1 of register ADDR (see Table 13), defining the byte location within an EEPROM 1997 Apr 16 page, are irrelevant during write and erase cycles. However, write and erase cycles need not affect all bytes of the page. The EEPROM flags FO to F3 (see Fig.5) determine which bytes within the EEPROM page are affected by the erase and/or write cycles. A byte whose corresponding EEPROM flag is zero remains unchanged. With erase page, a byte is erased if its corresponding EEPROM flag is set. With write page, data in EEPROM Latch 0 to 3 (Fig.5) are ORed to the individual page bytes if and only if the corresponding EEPROM flags are set. In an erase/write cycle, FO to F3 select which page bytes are erased and ORed with the corresponding EEPROM latches. . ORing, in this event, means that the EEPROM latches are copied to the selected page bytes. The described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. This advantage necessitates a preparation step, called page setup, before the actual erase and/or write cycle can be executed. Page setup controls EEPROM latches and EEPROM flags. This will be described in the Sections 7.5.1 to 7.5.5. 7.5.1 PAGE SETUP Page setup is a preparation step required before write page, erase page and erase/write page cycles. As previously described, these page operations include single-byte write, erase and erase/write as a special event. EEPROM flags FO to F3 determine which page bytes will be affected by the mentioned page operations. EEPROM Latch 0 to 3 must be preset through DATR to specify the write cycle data to EEPROM and to set the EEPROM flags as a side-effect. Obviously, the actual preset value of the EEPROM latches is irrelevant for erase page. Preset of one, two, three or all four EEPROM latches and the corresponding EEPROM flags can be performed by repeatedly defining ADDR and writing to DATR (see Table 17). Jf more than one EEPROM latch must be preset, the subcounter consisting of ADO and AD1 can be induced to auto-increment after every write to DATR, thus stepping through all EEPROM latches. For this purpose, increment mode (Table 12) must be selected. Auto-incrementing stops at EEPROM Latch 3. It is not mandatory to start at EEPROM Latch 0 as in shown in Table 18. Note that AD2 to AD6 are irrelevant during page setup. They will usually specify the intended EEPROM page, anticipating the subsequent page cycle. 1056Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F From now on, it will be assumed that AD2 to AD6 will contain the intended EEPROM page address after page setup. Table 17 Page setup; preset INSTRUCTION RESULT MOV A, #addr address of EEPROM latch MOV ADDR, A_ | send address to ADDR MOV A, #data load write, erase/write or erase data MOV DATR, A _ | send data to addressed EEPROM latch Table 18 Page setup; auto-incrementing INSTRUCTION RESULT MOV A, #MC2 increment mode control word MOV EPCR, A_ | select increment mode MOV A, #baddr EEPROM Latch 0 address (ADO = AD1 = 0) MOV ADDR, A_ | send EEPROM Latch 0 address to ADDR MOV A, RO load 18 byte from Register 0 MOV DATR, A_ | send 15* byte to EEPROM Latch 0 MOV A, R11 load 2" byte from Register 1 MOV DATR, A send 2 byte to EEPROM Latch 1 MOV A, R2 load 3" byte from Register 2 MOV DATR, A_ | send 3 byte to EEPROM Latch 2 MOV A, R3 load 4'" byte from Register 3 MOV DATR, A_ | send 4" byte to EEPROM Latch 3 7.5.2 READ BYTE Since ADDR auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. Table 19 Read byte INSTRUCTION RESULT MOV A, #RDADODR | load read address MOV ADDR, A send address to ADDR MOV A, DATR read EEPROM data 7.5.3 WRITE PAGE The write cycle performs a logical OR between the data in the EEPROM latches and that in the addressed EEPROM page. 1997 Apr 16 To actually copy the data from the EEPROM latches, the corresponding bytes in the page should previously have been erased. The EEPROM latches are preset as described in Section 7.5.1. The actual transfer to the EEPROM is then performed as shown in Table 20. The last instruction also starts Timer 2. The data in the EEPROM latches are ORed with that in the corresponding page bytes within 5 ms. A single-byte write is simply a special case of write page. ADDR auto-increments after the write cycle. If ADO and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by bits AD2 to AD6) and to EEPROM Latch 0 (by bits ADO and AD1). This allows efficient coding of multi-page write operations. Table 20 Write page INSTRUCTION RESULT MOV A, #EWP + MC2_ | write page control word MOV EPCR, A start write page cycle 7.5.4 ERASE/WRITE PAGE The EEPROM latches are preset as described in Section 7.5.1. The page byte corresponding to the asserted flags (among FO to F3) are erased and re-written with the contents of the respective EEPROM latches. The last instruction also starts Timer 2. Erasure takes 5 ms upon which Timer Register T2 reloads for another 5 ms cycle for writing. The top cycles together take 10 ms. A single-byte erase/write is simply a special event of erase/write page. ADDR auto-increments after the write cycle. If ADO and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by AD2 to AD6) and to EEPROM Latch 0 (by ADO and AD1). This allows efficient coding of multi-page erase/write operations. Table 21 Erase/write page INSTRUCTION RESULT MOV A, #EWP + MC3_| erase/write page control word MOV EPCR, A start erase/write page cycle 1057Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM. PCD3755A; PCD3755E; PCD3755F 7.5.5 The EEPROM flags are set as described in Section 7.5.1. The corresponding page bytes are erased. ERASE PAGE The {ast instruction also starts Timer 2. Erasure takes 5 ms. Asingle-byte erase is simply a special case of erase page. Note that ADDR does not auto-increment after an erase cycle. Table 22 Erase page The second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding EEPROM cycle. Timer 2 is stopped, T2F is set whereas EWP and MC1 to MC3 are cleared. Table 23 Reload values as a function of fai INSTRUCTION RESULT MOV A, #EWP + MC3 + MC2 + MC1 | erase page control word MOV EPCR, A start erase page cycle 7.6 Timer2 Timer 2 is a 8-bit down-counter decremented at a rate of Vago x fat. It may be used either for EEPROM timing or as a general purpose timer. Conflicts between the two applications should be carefully avoided. 7.6.1 TIMER 2 FOR EEPROM TIMING When used for EEPROM timing, Timer 2 serves to generate the 5 ms intervals needed for erasing or writing the EEPROM. At the decrement rate of 439 x faa, the reload value for a 5 ms interval is a function of faa. Table 23 summarizes the required reload vaiues for a number of oscillator frequencies. Timer 2 is started by setting bit EWP in the EPCR. The Timer Register T2 is loaded with the reload value from RELR. T2 decrements to zero. For an erase/write cycle, underflow of T2 indicates the end of the erase operation. Therefore, Timer Register T2 is reloaded from RELR for another 5 ms interval during which the flagged EEPROM latches are copied to the corresponding bytes in the page addressed by ADDR. 1997 Apr 16 fxtat RELOAD VALUE() . (MHz) (HEX) 4 OA 2 14 3.58 25 6 3E 10 68 16 AG Note 1. The reload value is (5 x 1073 x Vago x faal) 15 fetal in MHz. 7.6.2 TIMER 2 AS A GENERAL PURPOSE TIMER When used for purposes other than EEPROM timing, Timer 2 is started by setting STT2. The Timer Register T2 (see Table 26) is loaded with the reload value from RELR. T2 decrements to zero. On underflow, T2 is reloaded from RELR, T2F is set and T2 continues to decrement. Timer 2 can be stopped at any time by clearing STT2. The value of T2 is then held and can be read out. After setting STT2 again, Timer 2 decrements from the reload value. Alternatively, it is possible to read T2 on the fly i.e. while Timer 2 is operating. 1058Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 8 DERIVATIVE INTERRUPTS One derivative interrupt event is defined. It is controlled by bits T2F and ET2I in the EPCR (see Tables 10 and 11). The derivative interrupt event occurs when T2F is set. This request is honoured under the following circumstances: e No interrupt routine proceeds e No external interrupt request is pending e The derivative interrupt is enabled ET2lis set. The derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing T2F. If the derivative interrupt is not used, T2F may directly be tested by the program. Obviously, T2F can also be asserted under program control, e.g. to generate a software interrupt. 9 TIMING Although thePCD3755A, PCD3755E and PCD3755F operate over a clock frequency range from 1 to 16 MHz, fital = 3.58 MHz will usually be chosen to take full advantage of the frequency generator section. 10 RESET In addition to the conditions given in the PCD33xxA Family data sheet, all derivative registers are cleared in the reset state. 11 IDLE MODE In Idle mode, the frequency generator, the EEPROM and the Timer 2 sections remain operative. Therefore, the IDLE instruction may be executed while an erase and/or write access to EEPROM is in progress. 12 STOP MODE Since the oscillator is switched off, the frequency generator, the EEPROM and the Timer 2 sections receive no clock. It is suggested to clear both the HGF and the LGF registers before entering Stop mode. This will cut off the biasing of the internal amplifiers, considerably reducing current requirements. The Stop mode must not be entered while an erase and/or write access to EEPROM is in progress. The STOP instruction may only be executed when EWP in EPCR is zero. The Timer 2 section is frozen during Stop mode. After exit from Stop mode by a HIGH level on CE/TO, Timer 2 proceeds from the held state. 13 INSTRUCTION SET RESTRICTIONS As RAM space is restricted to 128 bytes, care should be taken to avoid accesses to non-existing RAM locations. 14 OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION Table 24 Port and Power-on-reset configuration See note 1 and 2. PORT 0 TYPE PORT 1 PORT 2 Oo;71/;2;3);/4)/5)/6)7)0)1 Vv, 21l3|/alsle6| 7 f[o]/1l2/13|" PCD3755A 118/15] 18/1S)18]18]1S 18]1S 18/1S|1S8)1S]iR|1R@ }2S }2S |2S [2S }1.3V PCD3755E |1S/1S]18]1S]18/1S]18 28 | 2S 28 | 2S] 2S|28]1S]18@) /2S5 |1R | 1R |1R ]20V PCD3755F | 1S] 1S} 1S)1S]18]1S]1S 18]1S 16/18]1S8]1S]1R|1RA@) }2S | 2S }2S8 |28 |20v Notes 1. Port output drive: 1 = standard I/O; 2 = open-drain V/O, see PCD33xxA Family data sheet. 2. Port state after reset: S = Set (HIGH) and R = Reset (LOW). 3. The Melody Output drive type is push-pull. 1997 Apr 16 1059Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 15 OTP PROGRAMMING Thus, the complete OTP memory cannot be tested by the factory, but only partially via a special test array. The programming of the PCD3755x and PCD3756x OTPs The average expected yield is 97%. is based on the OM4260 programmer (Ceibo MP-51), available from Philips. The OM4260 works in conjunction Detailed information on the OTP programming is available with various adapters supporting the different package in the PCD3755x Application Note, which is available via types available as listed in Table 25. your Philips Sales office. The low-voltage OTP program memory used is of Anti-Fuse-PROM type and can not be erased after programming. Table 25 OTP programming overview . DEVICE PHILIPS TYPE NUMBER CEIBO TYPE NUMBER | SUPPORTED PACKAGE Ceibo MP-51 OM4260 MP-51 programmer base = PCD3755x/56x | OM5007 PCD3755A / 56A adapter DIP DIP28 PCD3755x/56x | OM5030 PCD3755A / 56A adapter SO $028 PCD3755x/56x | OM5037!") PCD3755A / 56A adapter QFP32 | LQFP32 Note 1. As the OM5037 is only a socket converter, the OM5007 is also needed to program the PCD3755x/56x in the LQFP32 package. 1997 Apr 16 1060Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 16 SUMMARY OF DERIVATIVE REGISTERS Table 26 Register map ADDR. (HEX) REGISTER 7 6 5 4 3 2 1 0 R/iw 00 not used 01 EEPROM Address Register 0 AD6 | ADS | AD4 | AD3 | AD2 | AD1 | ADO | RAW (ADDR) 02 not used 03 EEPROM Data Register D7 D6 DS D4 D3 D2 D1 DO RAW (DATR) 04 EEPROM Control Register STT2 | ET21 | TF2 | EWP | MC3 | MC2 | MC1 0 RAW (EPCR) 05 Timer 2 Reload Register R7 R6 R5 R4 R3 R2 R1 RO RAW (RELR) 06 Timer 2 Register 72.7 | 72.6 | T2.5 | 72.4 | 72.3 | 72.2 | T2.1 | 72.0 R (T2) o7 sn only for test purposes; not to be accessed by the device user 08 to 10 | not used 11 High Group Frequency Register H7 H6 HS H4 H3 H2 H1 HO Ww (HGF) 12 Low Group Frequency Register L7 L6 L5 L4 L3 L2 ui Lo WwW (LGF) 13 Melody Control Register 0 0 0 0 0 0 0 EMO | R/W (MDYCON) 14 to FF | not used 17 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see Data Handbook IC 14, Section: Handling MOS devices"). 18 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT Vop supply voltage 0.8 +7.0 Vv Vi all input voltages -0.5 Vop + 0.5 Vv hy DC input current -10 +10 mA lo DC output current -10 +10 mA Prot total power dissipation - 125 mW Po power dissipation per output - 30 mW Isg ground supply current -50 +50 mA Tstg storage temperature -65 +150 C Tj operating junction temperature - 30 C 1997 Apr 16 1061Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 19 DC CHARACTERISTICS Vop = 1.8 to 6 V; Vgsg = 0 V; Tamp = 25 to +70 C; all voltages with respect to Vs; fxta) = 3.58 MHz; unless otherwise specified. SYMBOL PARAMETER | CONDITIONS | min. | TYP. | MAX. | UNIT Supply Vop supply voltage see Fig.6 operating note 1 1.8 - 6 Vv RAM data retention in Stop 1.0 - 6 Vv mode Ipp operating supply current see Figs 7 and 8; note 2 Vop = 3 V; value HGF or LGF + 0 | - 0.8 1.6 mA Vop=3V - 0.35 0.7 mA Vop = 5 V3 fal = 10 MHz ~ 1.5 4.0 mA Vop = 5 V3 frat = 16 MHz - 2.4 6.0 mA IpDiidie) supply current (Idle mode) see Figs 9 and 10; note 2 Vop = 3 V; value HGF or LGF #0 | - 0.7 1.4 mA Vop=3V - 0.25 0.5 mA Vop = 5 V3 fia = 10 MHz - 1.1 3.4 mA Vop = 5 V; fal = 16 MHz - 1.7 5.0 mA lppistp) supply current (Stop mode) see Fig.11; note 3 Vop = 1.8 V; Tamb = 25 C - 1.0 5.5 LA Vpp =1.8V; Tamb =70C - - 10 LA Inputs Vit LOW level input voltage 0 ~ 0.3Vpp | V Vin HIGH level input voltage 0.7Vpp | - Vpp Vv lu input leakage current Vss < Vi < Vop -1 - +1 pA Port outputs lo. LOW level port sink current Vop = 3 V; Vo = 0.4 V; see Fig.12 | 0.7 3.5 = mA lou HIGH level pull-up output source | Vpp = 3 V; Vo = 2.7 V; see Fig.13 | -10 ~30 - pA current Vpp = 3 V; Vo = 0 V; see Fig.13 - ~140 |-300 |paA lout HIGH level push-pull output Vop = 3 V; Vo = 2.6 V; see Fig.14 | -0.7 -3.5 ~ mA source current Tone output (see Fig.15; note 4) Via(RMs) HGF voltage (RMS) 158 181 205 mV Viaiams) | LGF voltage (RMS) 125 142 160 mV At/t frequency deviation 0.6 - +0.6 % Voc DC voltage level - 0.5Vpp | - Vv IZo| output impedance - 100 |500 |Q Gy pre-emphasis of group 1.5 2.0 2.5 dB THD total harmonic distortion Tamb = 25 C; note 5 - 25 - dB 1997 Apr 16 1062Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM PCD3755A; PCD3755E; PCD3755F SYMBOL | PARAMETER CONDITIONS | min. | TYP. | MAX. | UNIT EEPROM (notes 1 and 6) CY ww endurance (erase/write cycles) | note 7 105 - - tret data retention time 10 - - years Power-on-reset (see Fig. 16) Vpor Power-on-reset level PCD3755A 0.8 1.3 1.8 Vv PCD3755E 1.5 2.0 2.5 Vv PCD3755F 1.5 2.0 2.5 Vv Oscillator (see Fig.17) Om transconductance Vop = 5 V 0.2 0.4 1.0 mS Re feedback resistor 0.3 1.0 3.0 MQ Notes 1. TONE output, EEPROM erase and write require Vpp 2 2.5 V. 2. Vit = Vssi Vin = Vop; open-drain outputs connected to Vsg; all other outputs open; value HGF = LGF = 0, unless otherwise specified. a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit. b) Typical values: Tamp = 25 C; crystal connected between XTAL1 and XTAL2. 3. Vit =Vss; Vin = Vop; RESET, T1 and CE/TO at Vsg; crystal connected between XTAL1 and XTAL2; pins T1 and CE/TO at Veg. NQOn > Verified on sampling basis. 1997 Apr 16 Values are specified for DTMF frequencies only (CEPT). Related to the Low Group Frequency (LGF) component (CEPT). After final testing the value of each EEPROM bit is a logic 1, but this cannot be guaranteed after board assembly. 1063Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 18 MLA493 6 MGB627 Saal (MHz) 'bb (mA) J 46 MHz / HGF or LGF + 0 2 TT OS +10 MHz i _ |_| 3.58 " F 3 5 Vop ) 7 Vop () Fig.6 Maximum clock frequency (fa) as a function of supply voltage (Vpp). Measured with crystal between XTAL1 and XTAL2. Fig.7 Typical operating supply current (ipp) as a function of supply voltage (Vpp). MGB828 6 Dp {mA) 4 5v 2 yr L+| ett | Sv 9 TI ; 1 10 tat (MHz) 10 Measured with function generator on XTAL1. Fig.8 Typical operating supply current (Ipp) as a function of clock frequency (fai). MGBB29 6 lop (idtey (mA) 4 16 MHz A YA 3.58 MHz 1 HGF or L@F #0 2 a | J | 10 MHz i | | 4 3.58 MHz 0 1 3 5 Vpp (Vv) 7 Measured with crystal between XTAL1 and XTAL2. Fig.9 Typical supply current in Idle mode (Ippiiaie)) as a function of supply voltage (Vpp). 1997 Apr 16 1064Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 6 MGB850 6 MGB826 'DD(stp) 'DD{idle) (A) (mA) 4 4 3 2 ev 2 LH 1} ___] | ety 3V 0 et 0 1 10 fyxtal (MHz) 107 1 3 5 Vop (V) 7 Measured with function generator on XTAL1. Fig.10 Typical supply current in Idle mode (Ippiidie)) as a function of clock frequency (fyta). Fig.11 Typical supply current in Stop mode (Ipp(stp)) aS a function of supply voltage (Vpp). MGB831 12 lo. (mA) 8 | a fA o 1 3 5 Vop () 7 Vo = 0.4 V. Fig.12 Typical LOW level output sink current (lot) as a function of supply voltage (Vpp). MGB832 -300 'ou (nA) 1 Vo=OV 200 -100 of VQ =9.9Vpp aa Le Ww] 0 8 5 Ypp) 7 Fig.13 Typical HIGH fevel pull-up output source current (lo) as a function of supply voltage (Vpp). 1997 Apr 16 1065Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, PCD3755A; PCD3755E; 8 kbytes OTP and 128 bytes EEPROM PCD3755F 12 MGB633 on Yop . | TBF DEVICE TYPE NUMBER | TONE | Leer) 10kQ 4 4 Vss MGB835 0 1 3 5 Vppw) 7 Vo = Vpp - 0.4 V. Fig.14 Typical HIGH level push-pull output source current (loy41) as a function of supply voltage (1) Device type number: PCD3755A, PCD3755E or PCD3755F. Fig.16 Typical Power-on-reset level (VpoRr) as function of ambient temperature (Tamp). (Vpp). Fig.15 TONE output test circuit. 6 MGD495 MGB834 Vpp I Wy) | 4 t | | Vpor = 2.0 2 Ss ! Vpon=13V | | ( ( 9 1 3 5 7 -25 25 175 Tc) 128 Vpp (Vv) 70 amb (C) Fig.17 Typical transconductance (g,) as a function of supply voltage (Vpp). 1997 Apr 16 1066Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator, 8 kbytes OTP and 128 bytes EEPROM PCD3755A; PCD3755E; PCD3755F 20 AC CHARACTERISTICS Vpp = 1.8 to 6 V; Vgs = 0 V; Tamb = -25 to +70 C; all voltages with respect to Vsg; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT t, rise time all outputs Vop = 5 V; Tamb = 25 C; CL = 50 pF |- 30 - ns ty fall time all outputs - 30 - ns ftal clock frequency see Fig.6 1 - 16 MHz 1997 Apr 16