PIN CONFIGURATION
32 PDIP
FEATURES
• 1M x 8 organization
• Single +5V pow er supply
• Fast access time : 100/120/150/200ns
• Totally static oper ation
• Completely TTL compatib le
1
P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
8M-BIT [1M x 8] CMOS MASK ROM
• Operating current : 40mA
• Standby current : 100uA
• P ackage
- 32 pin plastic DIP
- 32 pin plastic SOP
- 32 pin plastic PLCC
- 32 pin plastic TSOP
GENERAL DESCRIPTION
The MX23C8000 is a 5V only, 8M-bit, Read Only
Memory. It is organized as 1M words by 8 bits, oper-
ates from a single +5V supply , has a static standby mode,
and has an access time of 100/120/150/200ns. It is
designed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design con-
siderations.
MX23C8000 offers automatic power-down, with power-
down controlled by the chip enable (CE) input. When
CE goes high, the device automatically powers down
and remains in a low-pow er standb y modes as long as
CE remains high.
MX23C8000 pin 24 may also be programmed either ac-
tive HIGH or LOW in order to eliminate bus contention
in multiple-b us microprocessor systems.
32 SOP
MX23C8000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A18
A17
A14
A13
A8
A9
A11
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
32 PLCC 32 TSOP
1
4
5
9
13
14 17 20
21
25
29
32 30 A14
A13
A8
A9
A11
OE/OE
A10
CE/CE
Q7
A7
A6
A5
A4
A3
A2
A1
A0
DQ
Q1
Q2
VSS
Q3
Q4
Q5
Q6
A12
A15
A16
A19
VCC
A18
A17
MX23C8000
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
10
19
18
17
A19
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
VCC
A18
A17
A14
A13
A8
A9
A11
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
MX23C8000
A11
A9
A8
A13
A14
A17
A18
VCC
A19
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE/OE
A10
CE/CE
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX23C8000
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P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
ABSOLUTE MAXIMUM RATINGS*
RATING VALUE
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 125°C
Applied Input V oltage -0.5V to VCC+0.5
Applied Output V oltage -0.5V to VCC+0.5
VCC to Ground P otential -0.5V to 7.0V
P ower Dissipation 1.0W
*Note:
Stress greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device . This
is a stress rating only and functional operation of the device
at these or any other conditions abo v e those indicated in the
operational sections of this specification is not implied. Ex-
posure to absolute maximum rating conditions for extended
period may affect reliability.
CAPACITANCE (Ta = 25°C, f=1.0MHz (Note 2))
Item Symbol MIN. MAX. UNIT Conditions
Input Capacitance CIN - 10 pF VIN=0V
Output Capacitance COUT - 10 pF V OUT=0V
PIN DESCRIPTION
Symbol Pin Function
A0~A19 Address Inputs
Q0~Q7 Data Outputs
CE/CE Chip Enable Input
OE/OE Output Enable Input
VCC P o wer Supply Pin (+5V)
VSS Ground Pin
BLOCK DIAGRAM
CONTROL
LOGIC OUTPUT
BUFFERS Q0~Q7
CE/CE
OE/OE
A0~A19
ADDRESS
INPUTS
Y-DECODER
X-DECODER
Y-SELECT
8M BIT
ROM ARRAY
VCC
VSS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 5.0V ± 10%)
Item Symbol MIN. MAX. Conditions
Output High Voltage V OH 2.4V - IOH = -1.0mA
Output Low Voltage V OL - 0.4V IOL = 2.1mA
Input High Voltage VIH 2.2V VCC+0.3V
Input Low Voltage VIL -0.3V 0.8V
Input Leakage Current ILI - 10uA VIN=0 to 5.5V
Output Leakage Current ILO - 10uA VOUT=0 to 5.5V
P ow er-Down Supply Current ICC3 - 100uA CE>VCC-0.2V
Standby Supply Current ICC2 - 1.0mA CE=VIH
Operating Supply Current ICC1 - 40mA Note 1
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P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
AC Test Conditions
Input Pulse Lev els 0.4V~2.4V
Input Rise and F all Times 10ns
Input Timing Level 1.5V
Output Timing Le v el 0.8V and 2.0V
Output Load See Figure
TIMING DIAGRAM
PROPAGATION DELAY FROM ADDRESS (CE/OE=ACTIVE)
VALID DATA
VALID ADDRESS
ADDRESS
INPUTS
tCYC
tAA
DATA OUT
tOH
Note:
1. Measured with device selected at f=5MHz and output unloaded.
2. This parameter is per iodically sampled and is not 100% teseted.
3. Output low-impedance delay (tLA) is measured from CE going low.
4. Output high-impedance delay (tHZ) is measured from CE going high.
AC CHARA CTERISTICS (Ta = -10°C ~ 70°C , VCC = 5.0V ± 10%)
23C8000-10 23C8000-12 23C8000-15 23C8000-20
PARAMETER SYMBOL MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. CONDITIONS
Cycle Time tCYC 100ns - 120ns - 150ns - 200ns -
Address Access Time tAA - 100ns - 120ns - 150ns - 200ns
Output Hold Time After tOH 0ns - 0ns - 0ns - 0ns -
Address Change
Chip Enable Access Time tACE - 100ns - 120ns - 150ns - 200ns
Output Enable/Chip Select t AOE - 80ns - 80ns - 80ns - 100ns
Access Time
Output Low Z Delay tLZ 0ns - 0ns - 0ns - 0ns - Note 3
Output High Z Delay tHZ 20ns - 20ns - 20ns - 20ns Note 4
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P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
ORDER INFORMATION
Part No. Access Time Operating Current MAX. STANDBY CURRENT MAX. Pack ag e
MX23C8000PC-10 100ns 40mA 100uA 32 pin DIP
MX23C8000MC-10 100ns 40mA 100uA 32 pin SOP
MX23C8000QC-10 100ns 40mA 100uA 32 pin PLCC
MX23C8000TC-10 100ns 40mA 100uA 32 pin TSOP
MX23C8000PC-12 120ns 40mA 100uA 32 pin DIP
MX23C8000MC-12 120ns 40mA 100uA 32 pin SOP
MX23C8000QC-12 120ns 40mA 100uA 32 pin PLCC
MX23C8000TC-12 120ns 40mA 100uA 32 pin TSOP
MX23C8000PC-15 150ns 40mA 100uA 32 pin DIP
MX23C8000MC-15 150ns 40mA 100uA 32 pin SOP
MX23C8000QC-15 150ns 40mA 100uA 32 pin PLCC
MX23C8000TC-15 150ns 40mA 100uA 32 pin TSOP
MX23C8000PC-20 200ns 40mA 100uA 32 pin DIP
MX23C8000MC-20 200ns 40mA 100uA 32 pin SOP
MX23C8000QC-20 200ns 40mA 100uA 32 pin PLCC
MX23C8000TC-20 200ns 40mA 100uA 32 pin TSOP
PR OPAGATION DELAY FR OM CHIP ENABLE (ADDRESS VALID)
tHZ
tACE
tAOE
tLZ
OE
DATA OUT
CE
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P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
PACKAGE INFORMATION
32-PIN PLASTIC DIP (600 mil)
6
P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
32-PIN PLASTIC SOP (450 mil)
7
P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
32-PIN PLASTIC LEADED CHIP CHARRIER (PLCC)
8
P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
32-PIN PLASTIC TSOP
9
P/N:PM0137 REV. 3.8, JUL. 16, 2001
MX23C8000
REVISION HISTORY
REVISION DESCRIPTION PAGE DATE
3.4 tHZ:70ns max. ---> 20ns max. SEP/25/1997
3.5 A C CHARA CTERISTICS tOH 10ns-->0ns P3 JAN/29/1999
3.6 Modify PIN CONFIGUTATION of 32SOP P1 JUN/08/2000
30pin A19-->A17 ; 24pin CE/CE-->OE/OE
3.7 Modify Pin Configuration--32TSOP P1 NO V/08/2000
3.8 Modify P ackage Inf ormation P5~8 JUL/16/2001
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MX23C8000
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
