TLC2555CDGKR - Texas Instruments High-Performance Analog

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DMaximum Throughput . . . 175/360 KSPS

DINL/DNL: ±1 LSB Max, SINAD: 72 dB,

SFDR: 85 dB, fi = 20 kHz

DSPI/DSP-Compatible Serial Interface

DSingle 5-V Supply

DRail-to-Rail Analog Input With 500 kHz BW

DThree Options Available:

– TLC2551: Single Channel Input

– TLC2552: Dual Channels With

Autosweep

– TLC2555: Single Channel With

Pseudo-Differential Input

DLow Power With Autopower Down

– Operating Current: 3.5 mA

Autopower Down: 8 µA

DSmall 8-Pin MSOP and SOIC Packages

TOP VIEW

TLC2551

VREF

GND

AIN

SDO

VDD

SCLK

VREF

GND

AIN0

SDO

SCLK

VDD

AIN1

VREF

GND

AIN(+)

SDO

SCLK

VDD

AIN(–)

TOP VIEW

TLC2552 TOP VIEW

TLC2555

description

The TLC2551, TLC2552, and TLC2555 are a family of high performance, 12-bit, low-power , miniature, CMOS

analog-to-digital converters (ADC). The TLC255x family uses a 5-V supply. Devices are available with single,

dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial clock (SCLK), and serial

data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors

(SPI interface). When interfaced with a TMS320 DSP, a frame sync signal (FS) can be used to indicate the

start of a serial data frame on CS for all devices or on FS for the TLC2551.

The TLC2551, TLC2552, and TLC2555 are designed to operate with very low power consumption. The power

saving feature is further enhanced with an autopower-down mode. This product family features a high-speed

serial link to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent

upon the mode of operation (see Table 1). The TLC255x family uses SCLK as the conversion clock, which

provides synchronous operation and a minimum conversion time of 1.5 µs using a 20-MHz SCLK.

AVAILABLE OPTIONS

PACKAGED DEVICES

TA8-MSOP

(DGK) 8-SOIC

(D)

TLC2551CDGK (AHF)

0°C to 70°CTLC2552CDGK (AHH)

0 C

70 C

TLC2555CDGK (AHJ)

TLC2551IDGK (AHG) TLC2551ID

–40°C to 85°CTLC2552IDGK (AHI) TLC2552ID

40 C

85 C

TLC2555IDGK (AHK) TLC2555ID

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TMS320 is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

S/H

SDO

VREF

LOW POWER

SAR ADC

VDD

CONTROL

LOGIC

Mux

S/H LOW POWER

12-BIT

SAR ADC

÷ 2

CONTROL

LOGIC

AIN

SCLK

VREF

AIN0

AIN1

SCLK

SDO

VDD

GNDGND

TLC2551 TLC2552

S/H LOW POWER

12-BIT

SAR ADC

CONTROL

LOGIC

VREF

AIN (+)

AIN (–)

SCLK

SDO

VDD

GND

TLC2555

÷ 2

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TLC2551

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

AIN 4 I Analog input channel

CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.

CS can be used as the FS pin when a dedicated DSP serial port is used.

FS 7 I DSP frame sync input. Indication of the start of a serial data frame. T ie this terminal to VDD if not used.

GND 3 I Ground return for the internal circuitry . Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge

or FS rising edge, whichever occurs first. The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO pin after CS falling edge

and output data is valid on the first falling edge of SCLK.

When CS and FS are both used (FS = 0 at the falling edge of CS), the MSB is presented to the SDO pin after the

falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after rising FS. Output data is valid on

the first falling edge of SCLK. (This is typically used with an active FS from a DSP.)

VDD 6 I Positive supply voltage

VREF 2 I External reference input

TLC2552/55

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

AIN0 /AIN(+) 4 I Analog input channel 0 for TLC2552—Positive input for TLC2555

AIN1/AIN (–) 5 I Analog input channel 1 for TLC2552—Inverted input for TLC2555

CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can

be connected to the FS output from a DSP on a dedicated serial port.

GND 3 I Ground return for the internal circuitry . Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high

and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO

returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.

VDD 6 I Positive supply voltage

VREF 2 I External reference input

detailed description

The TLC2551, TLC2552, and TLC2555 are successive approximation (SAR) ADCs utilizing a charge

redistribution DAC. Figure 1 shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

GND/AIN(–)

ADC Code

AIN

Charge

Redistribution

DAC

Control

Logic

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB LSB

D15–D4 D3–D0

Conversion result (OD11–OD0) Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero-scale code = 000h, Vcode = GND

Full-scale code = FFFh, Vcode = VREF – 1 LSB

pseudo-differential inputs

The TLC2555 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a

maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one

SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered

up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever

CS (pin 1) is high to assure proper operation.

TLC2551

DControl via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB

may be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of SCLK.

This is typically used for a microcontroller with an SPI interface, although it can also be used for a DSP. The

microcontroller SPI interface may be programmed for CPOL = 0 (serial clock referenced to ground) and

CPHA = 1 (data is valid on the falling edge of serial clock). At least one falling edge transition on SCLK is

needed whenever CS is brought high.

DControl via FS—The MSB is presented after the rising edge of FS. The falling edge of FS starts the cycle.

The MSB may be read on the first falling edge of SCLK after FS is low. This is the typical configuration when

the ADC is the only device on the DSP serial port.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

control and timing (continued)

DControl via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS starts

the sampling cycle. The MSB may be read on the first falling SCLK edge after FS is low. Output data changes

on the rising edge of SCLK. This control via CS and FS is typically used for multiple devices connected to

a TMS320 DSP.

TLC2552 and TLC2555

All control is provided using CS (pin 1) on the TLC2552 and TLC2555. The cycle starts on the falling edge

transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing

is similar to the TLC2551, with control via CS only.

TLC2552 channel MUX reset cycle

The TLC2552 uses CS to reset the analog input multiplexer (MUX). A short active CS cycle (4 to 7 SCLKs) resets

the MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as is the case for a complete

conversion cycle, (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel

(see Figure 4 for timing).

sampling

The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter

has received a high-to-low CS transition (or a high-to-low FS transition for the TLC2551).

conversion

The TLC2551, TLC2552, and TLC2555 completes conversion in the following manner. The conversion starts

after the 16th SCLK falling edge during the cycle and requires 28 SCLKs to complete. Enough time for

conversion should be allowed before a rising CS or FS edge so that no conversion is terminated prematurely.

TLC2552 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0

via CS as described earlier and in Figure 4. The input is sampled for 12 SCLKs and converted. The result is

presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to

avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is not complete.

The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous

cycle.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing diagrams/conversion cycles

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1 2 3 4 5 6 12 13 14 15 16 1

OD8 OD7 OD6 OD5 OD0

SDO

t(sample) tct(powerdown)

OD10OD11 OD9

Figure 2. TLC2551 Timing: Control via CS (FS = 1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1 2 3 4 5 6 12 13 14 15 16 1

OD9 OD8OD11 OD10 OD7 OD6 OD0

SDO

t(sample) tct(powerdown)

Figure 3. TLC2551 Timing: Control via CS and FS or FS Only

SCLK

2 3 4 5 1 12 16

ÎÎÎÎÎÎ

ÎÎÎ

SDO

t(powerdown)

1 4 161241

OD11 OD0

t(sample)

>8 SCLKs, MUX Toggles to AIN1

AIN0 Result

<8 SCLKs, MUX

Resets to AIN0

ÎÎÎÎÎÎÎ

t(sample)

Figure 4. TLC2552 Reset Timing

OD8

SCLK

1 2 3 4 5 6 12 13 14 15 16

OD7 OD6 OD5 OD0

ÎÎÎÎÎÎ

SDO

t(sample) tct(powerdown)

OD9

OD10 OD9OD11 OD10 OD11

Figure 5. TLC2552 and TLC2555 Timing

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

using CS as the FS input

When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This connection saves one output terminal from the DSP.

(Output data changes on the falling edge of SCLK. This is the default configuration for the TLC2552 and

TLC2555).

SCLK and conversion speed

The SCLK input can range in frequency from 100 kHz to 20 MHz. The required number of conversion clocks

is 14. The conversion clock for the ADC is SCLK/2 which translates to 28 SCLK cycles to perform a conversion.

For a 15-MHz SCLK, the minimum total cycle time is given by: 16x(1/15 M)+14x(1/7.5 M)+1 SCLK = 3.0 µs. An

additional SCLK is added to account for the required CS or FS high time. These times specify the minimum cycle

time for an active CS or FS signal. If violated, the conversion terminates, invalidating the next data output cycle.

Table 1 gives the maximum SCLK frequency for a given operational mode.

control via pin 1 (CS, SPI interface)

All devices are compatible with this mode of operation. A falling CS initiates the cycle. (For TLC2551, the FS

input is tied to VDD.) CS remains low for the entire cycle time (sample + convert + 1 SCLK) and can then be

released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high.

control via pin 1 (CS, DSP interface)

All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the

CS input of the ADC. A falling edge on the CS input initiates the cycle. (For TLC2551, the FS input can be tied

to VDD, although better performance can be achieved by using the FS input for control. Refer to the control via

pin 1 and pin 7 (CS and FS or FS only, DSP interface) section. The CS input should remain low for the entire

cycle time (sample + convert + 1 SCLK) and can then be released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high. This requirement is usually of little

consequence since SCLK is normally always present when interfacing with a DSP.

control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)

Only the TLC2551 is compatible with this mode of operation. The CS input to the ADC can be controlled via a

general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the

ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS

edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and

FS inputs should remain low for the entire cycle time (sample + convert + 1 SCLK) and can then be released.

reference voltage

An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the

analog inputs to produce a full-scale reading. The value of VREF and the analog input must not exceed the

positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output

is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal

to or lower than GND.

powerdown and powerup

Autopower down is built into these devices in order to reduce power consumption. The actual power savings

depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.

Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some

power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 8 µA

within 0.5 µs. To achieve the lowest power-down current (deep powerdown) of 1 µA requires 2-ms inactive time

between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately

at the next falling edge of CS or the rising edge of FS.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.5 µS

2 mS

3.5 mA

8 µA

1 µA

ICC

VDD = 5 V With 1-µF/0.1-µF Capacitor Between Supply and Ground

(

Powerdown

)

– Powerdown time – S

Table 1. Modes of Operation and Data Throughput

CONTROL PIN(s)/DEVICE MAX SCLK (MHz)

(50/50 duty cycle)

VDD = 4.5 V

APPROXIMATE CONVERSION

THROUGHPUT (ksps)

VDD = 4.5 V

CS control only (TLC2551 only)

For SPI†15 333

DSP interface‡8 175

CS and FS control (TLC2551 only)§

DSP interface 20 400

†See Figure 21(a).

‡See Figure 21(b).

§See Figure 21(c).

absolute maximum ratings over operating free-air temperature (unless otherwise noted)¶

Supply voltage range, GND to VDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to VDD+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA:C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

¶Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VDD 4.5 5 5.5 V

Positive external reference voltage input, VREFP (see Note 1) 2 VDD V

Analog input voltage (see Note 1) 0 VDD V

High level control input voltage, VIH 2.1 V

Low-level control input voltage, VIL 0.6 V

Setup time, CS falling edge before first SCLK falling edge,

tsu(CSL-SCLKL) VDD = REF = 4.5 V 40 ns

Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) 5 ns

Delay time, delay from CS falling edge to FS rising edge td(CSL-FSH) (TLC2551 only) 0.5 7 SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLC2551 only) 0.35 SCLKs

Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL) (TLC2551 only) 0.65 SCLKs

Pulse width CS high time, tw(H_CS) 100 ns

Pulse width FS high time, tw(H_FS) (TLC2551 only) 0.75 SCLKs

SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 50 10000 ns

Pulse width low time, tw(L_SCLK) 0.4 0.6 SCLKs

Pulse width high time, tw(H_SCLK) 0.4 0.6 SCLKs

Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion

time, tc)0.05 µs

Active CS cycle time to reset internal MUX to AIN0, t(Reset cycle) (TLC2552 only) 4 7 SCLKs

Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV) VDD = REF = 4.5 V, 25-pF load 40 ns

Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV)

(TLC2551 only) VDD = REF = 4.5 V, 25-pF load 1 ns

Delay time, delay from SCLK rising edge to SDO valid,

td(SCLKH-SDOV) VDD = REF = 4.5 V, 25-pF load 11 ns

Delay time, delay from 17th SCLK rising edge to SDO 3-state,

td(SCLK17H-SDOZ) VDD = REF = 4.5 V, 25-pF load 30 ns

Conversion time, tc28 SCLKs

Sampling time, t(sample) See Note 2 300 ns

erating free air tem

erature TA

TLC2551/2/5C 0 70

°C

Operating free-air temperature, TATLC2551/2/5I –40 85 °C

NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied

to GND convert as all zeros(000000000000).

2. Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

VDD = VREF = 4.5 V to 5.5 V, (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VOH High-level output voltage VDD = 5.5 V, IOH = –0.2 mA at 30-pF load 2.4 V

VOL Low-level output voltage VDD = 5.5 V, IOL = 0.8 mA at 30-pF load 0.4 V

Off-state output current VO = VDD

CS VDD

1 2.5

IOZ

Off

state

out ut

current

(high-impedance-state) VO = 0 CS = VDD –1–2.5 µA

IIH High-level input current VI = VDD 0.005 2.5 µA

IIL Low-level input current VI = 0 V –0.00

52.5 µA

ICC Operating supply current CS at 0 V, VDD = 4.5 V to 5.5 V 3 3.5 mA

Autopower-down current

t(powerdown) ≥ 0.5 µsFor all digital inputs,

0≤V≤03VorV ≥V03V

ICC(AUTOPWDN) Deep autopower-down current

t(powerdown) ≥ 2 ms

0≤ VI ≤ 0.3 V or VI ≥ VDD– 0.3 V,

SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref 1µA

Selected analo

input channel Selected channel at VDD 1

Selected

analog

in ut

channel

leakage current Selected channel at 0 V –1µA

Input capacitance

Analog inputs 20 45 50

CiInput capacitance Control Inputs 5 25 pF

Input on resistance VDD = 5.5 V 500 Ω

†All typical values are at VDD = 5 V, TA = 25°C.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ac specifications (fi = 20 kHz)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SINAD Signal-to-noise ratio + distortion 400 KSPS, VDD = VREF = 5 V 70 72 dB

THD Total harmonic distortion 400 KSPS, VDD = VREF = 5 V –84 –80 dB

ENOB Effective number of bits 400 KSPS, VDD = VREF = 5 V 11.8 bits

SFDR Spurious free dynamic range 400 KSPS, VDD = VREF = 5 V –84 –80 dB

Analog Input

Full-power bandwidth, –3 dB 1 MHz

Full-power bandwidth, –1 dB 500 kHz

external reference specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference input voltage VDD = 4.5 V to 5.5 V 2 VDD V

Reference input impedance

V55V

CS = 1, SCLK = 0 100 MΩ

Reference input impedance VDD = 5.5 V CS = 0, SCLK = 20 MHz 20 25 kΩ

Reference current VDD = VREF = 5.5 V 100 400 µA

Reference input capacitance

VV 55V

CS = 1, SCLK = 0 5 15

Reference input capacitance VDD = VREF = 5.5 V CS = 0, SCLK = 20 MHz 20 45 50 pF

VREF Reference voltage VDD = 4.5 V to 5.5 V VDD V

dc specification, VDD = VREF = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INL Integral linearity error (see Note 4) ±0.6 ±1 LSB

DNL Differential linearity error See Note 3 ±0.5 ±1 LSB

Offset error (see Note 5)

See Note 3

TLC2551/52 ±1.5

LSB

EOOffset error (see Note 5) See Note 3 TLC2555 ±2.5 LSB

Gain error (see Note 5)

See Note 3

TLC2551/52 ±2

LSB

EGGain error (see Note 5) See Note 3 TLC2555 ±5LSB

Total unadjusted error (see Note 6)

See Note 3

TLC2551/52 ±2

LSB

EtTotal unadjusted error (see Note 6) See Note 3 TLC2555 ±5LSB

NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111).

4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

6. Total unadjusted error comprises linearity, zero, and full-scale errors.

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎÎ

OD0

SCLK

VIH

OD11

SDO

t(sample)

4 12

tw(L_SCLK)

OD8

ÎÎÎÎÎ

VIL

tsu(CSL-SCLKL)

tw(H_SCLK)

th(EOC-CSH)

tw(H_CS)

t(powerdown)

th(SCLKL-FSL)

tsu(FSH-SCLKL)

tw(H_FS)

td(CSL-FSH)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

Figure 6. TLC2551 Critical Timing (Control via CS and FS or FS only)

OD10 OD0

SCLK

SDO

t(sample)

4 1612

OD9

td(SCLKH-SDOV)

td(CSL-SDOV)

OD11

ÎÎÎÎÎÎÎ

t(powerdown)

tsu(CSL–SCLKL)

th(EOC–CSH)

td(SCLK17H-SDOZ)

Figure 7. TLC2551 Critical Timing (Control via CS only, FS = 1)

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎ

SCLK

SDO

t(sample)

td(SCLK17H-SDOZ)

1 1 12 164

t(reset cycle)

MUX = AIN0

OD11 OD0

ÎÎÎÎÎ

OD11

td(CSL-SDOV)

th(EOC-CSH)

td(SCLKH-SDOV)

td(CSL-SDOV)

tw(H_CS)

Figure 8. TLC2552 Reset Cycle Critical Timing

OD11 OD0

SCLK

VIH

SDO

t(sample) tc

4 1612

tw(L_SCLK)

ÎÎÎÎÎ

VIL

tw(H_SCLK)

th(EOC-CSH)

t(powerdown)

th(SCLKL-CSL)

tsu(CSL-SCLKL)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

OD8

tw(H_CS)

Figure 9. TLC2552 and TLC2555 Conversion Cycle Critical Timing

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

0.6

–40 25

INL – Integral Nonlinearity – LSB

INTEGRAL NONLINEARITY

FREE-AIR TEMPERATURE

0.7

0.65

VDD = REF = 5.5 V

400 KSPS

TA – Free-Air Temperature – °C

Figure 11

0.35

0.3

–40 25

DNL – Differential Nonlinearity – LSB

0.4

DIFFERENTIAL NONLINEARITY

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

400 KSPS

TA – Free-Air Temperature – °C

Figure 12

0.45

0.4

–40 25

Offset Error – LSB

0.5

OFFSET ERROR

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

400 KSPS

TA – Free-Air Temperature – °C

Figure 13

0.85

0.7

–40 25

Gain Error – LSB

0.9

GAIN ERROR

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

400 KSPS

0.8

0.75

TA – Free-Air Temperature – °C

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 14

–40 25

Supply Current – mA

3.1

SUPPLY CURRENT

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

400 KSPS

3.05

TA – Free-Air Temperature – °C

–0.5

–11

DNL – Differential Nonlinearity – LSB

0.5

Digital Output Codes

DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODES

4094

VDD = REF = 5 V

400 KSPS

Figure 15

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–0.5

–11

INL – Integral Nonlinearity – LSB

0.5

Digital Output Codes

INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODES

4094

VDD = REF = 5 V

400 KSPS

Figure 16

–60

–80

0 20 40 60 80 100

Magnitude – dB

–40

–20

f – Input Frequency – KHz

2048 POINTS FAST FOURIER TRANSFORM (FFT)

–120

–140

–100

–160 120 140 160 180 200

VDD = REF = 5.5 V

400 KSPS

fi = 20 kHz

Figure 17

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

65080

SINAD – Signal-To-Noise and Distortion – dB

f – Input Frequency – KHz

SIGNAL-TO-NOISE AND DISTORTION

INPUT FREQUENCY

120

20 40 60 100 140 160

VDD = REF = 5.5 V

400 KSPS

180 200

Figure 19

11.5

ENOB – Effective Number of Bits – Bits

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY

10.5

VDD = REF = 5.5 V

400 KSPS

080

f – Input Frequency – KHz

12020 40 60 100 140 160 180 200

Figure 20

–70

–90 0

THD – Total Harmonic Distortion – dB

f – Input Frequency – KHz

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

–80

VDD = REF = 5.5 V

400 KSPS

–65

–75

–85

80 12020 40 60 100 140 160 180 200

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

SPI PORT

TLC2551

AIN

10 kΩ

VDD

SDO VDD

SCLK

EXT

Reference

VREF

GND

VDD

MISO

SCLK

(a)

DSP

TLC2551

AIN

10 kΩ

VDD

SDO VDD

SCLK

EXT

Reference

VREF

GND

VDD

FSX

CLKR

(b)

DSP

TLC2551

AIN

SDO

VDD

SCLK

EXT

Reference

VREF

GND

VDD

FSX

CLKX

(c)

GPIO

CLKX

FSR

CLKR

Figure 21. Typical TLC2551 Interface to a TMS320 DSP

TLC2551, TLC2552, TLC2555

5-V, LOW-POWER, 12-BIT, 175/360 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276D – MARCH 2000 – REVISED MAY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLC2552/55

TMS320

CLKR

AIN 0/AIN (+)†

10 kΩ

VDD

SDO

SCLK

VDD

GND

10 kΩEXT

Reference

VREF

AIN 1/AIN (–)†

†For TLC2555 onl

FSR

FSX

CLKX

DSP

Figure 22. Typical TLC2552/55 Interface to a TMS320 DSP

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLC2551CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2551IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2551IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2551IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2551IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2552CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2552CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2552ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2552IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2552IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2552IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2555ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLC2555IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLC2555IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLC2555IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLC2551CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLC2551IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLC2551CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

TLC2551IDR SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

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