0 VirtexTM-E 1.8 V Field Programmable Gate Arrays R DS022-2 (v2.3) November 9, 2001 0 0 Preliminary Product Specification Architectural Description Virtex-E Array The Virtex-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). * CLBs provide the functional elements for constructing logic * IOBs provide the interface between the package pins and the CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlockTM that also provides local routing resources to connect the CLB to the GRM. Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Input/Output Block The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and outputs that support a wide variety of I/O signalling standards, see Table 1. T TCE D Q CE Weak Keeper SR DLLDLL DLLDLL O OCE PAD D Q CE OBUFT VersaRing SR I IQ Q D CE Programmable Delay CLBs BRAMs CLBs BRAMs CLBs CLBs BRAMs BRAMs Vref IOBs IOBs IBUF SR SR CLK ICE ds022_02_091300 Figure 2: Virtex-E Input/Output Block (IOB) The three IOB storage elements function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. VersaRing DLLDLL DLLDLL ds022_01_121099 Figure 1: Virtex-E Architecture Overview The VersaRingTM I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex-E architecture also includes the following circuits that connect to the GRM. * Dedicated block memories of 4096 bits each * Clock DLLs for clock-distribution delay compensation and clock domain control * 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 1 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Input Path Table 1: Supported I/O Standards I/O Output Input Input Board Termination Standard VCCO VCCO VREF Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A SSTL3 I & II 3.3 N/A 1.50 1.50 SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 HSTL I 1.5 N/A 0.75 0.75 HSTL III & IV 1.5 N/A 0.90 1.50 CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/A An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in close proximity to each other. <Link>See "I/O Banking" on page 2. There are optional pull-up and pull-down resistors at each input for use after configuration. Their value is in the range 50 - 100 kW. Output Path The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides synchronous enable and disable. In addition to the CLK and CE control signals, the three flip-flops share a Set/Reset (SR). For each flip-flop, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asynchronous Clear. The output buffer and all of the IOB control signals have independent polarity controls. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. When PCI 3.3 V compliance is required, a conventional clamp diode is connected to the output supply voltage, VCCO. Optional pull-up, pull-down and weak-keeper circuits are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but I/Os can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins are in a high-impedance state. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex-E IOBs support IEEE 1149.1-compatible boundary scan testing. Module 2 of 4 2 The Virtex-E IOB input path routes the input signal directly to internal logic and/ or through an optional input flip-flop. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. <Link>See "I/O Banking" on page 2. An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Since the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provision of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. The VCCO and VREF pins for each bank appear in the device pin-out tables and diagrams. The diagrams also show the bank affiliation of each I/O. Bank 1 GCLK3 GCLK2 Bank 2 Bank 7 Bank 0 Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a super set of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. Bank 3 Bank 6 VirtexE Device GCLK1 GCLK0 Bank 5 In Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards are supplied by VCCO rather than VCCINT. For these standards, only input and output buffers that have the same VCCO can be mixed together. Bank 4 In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. ds022_03_121799 Figure 3: Virtex-E I/O Banks Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Table 2: Compatible Output Standards VCCO Compatible Standards 3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+, LVPECL 2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+, BLVDS, LVDS 1.8 V LVCMOS18, GTL, GTL+ 1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+ Configurable Logic Blocks The basic building block of the Virtex-E CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex-E CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex-E CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. Approximately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification Virtex-E function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. www.xilinx.com 1-800-255-7778 Module 2 of 4 3 R VirtexTM-E 1.8 V Field Programmable Gate Arrays COUT COUT YB Y G4 G3 G2 LUT SP D Q CE Carry & Control YB Y G4 G3 YQ G1 LUT G2 SP D Q CE Carry & Control YQ G1 RC BY RC BY XB X F4 F3 LUT F2 SP D Q CE Carry & Control F1 XB F3 XQ LUT F2 SP D Q CE Carry & Control XQ F1 RC BX X F4 RC BX Slice 1 Slice 0 CIN CIN ds022_04_121799 Figure 4: 2-Slice Virtex-E CLB COUT YB CY G4 G3 G2 G1 I3 I2 I1 I0 Y O LUT DI WE 0 INIT D Q CE 1 REV YQ BY XB F5IN F6 CY CK WE A4 WSO I3 I2 I1 I0 WE WSH BX X DI INIT DQ CE BX F4 F3 F2 F1 F5 F5 BY DG XQ DI REV O LUT 0 1 SR CLK CE CIN ds022_05_092000 Figure 5: Detailed View of Virtex-E Slice Storage Elements The storage elements in the Virtex-E slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D inputs can be driven either by Module 2 of 4 4 the function generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to operate asynchronously. All of the control signals are independently invertible, and are shared by the two flip-flops within the slice. Additional Logic The F5 multiplexer in each slice combines the function generator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. Each CLB has four direct feedthrough paths, two per slice. These paths provide extra data input lines or additional local routing that does not consume logic resources. Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions. BUFTs Each Virtex-E CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. <Link>See "Dedicated Routing" on page 7. Each Virtex-E BUFT has an independent 3-state control pin and an independent input pin. Block SelectRAM Virtex-E FPGAs incorporate large block SelectRAM memories. These complement the Distributed SelectRAM memories that provide shallow RAM structures implemented in CLBs. Block SelectRAM memory blocks are organized in columns, starting at the left (column 0) and right outside edges and inserted every 12 CLB columns (see notes for smaller devices). Each memory block is four CLBs high, and each memory column extends the full height of the chip, immediately adjacent (to the right, except for column 0) of the CLB column locations indicated in Table 3. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification Table 3: CLB/Block RAM Column Locations XCV Device /Col. 0 12 24 36 48 60 72 84 96 50E Columns 0, 6, 18, & 24 100E Columns 0, 12, 18, & 30 200E Columns 0, 12, 30, & 42 300E O O O 400E O O 600E O O O 1000E O O O 1600E O O O O 2000E O O O O 2600E O O O O 3200E O O O O 108 120 138 156 O O O O O O O O O O O O O O O O O O O O O O O O O Table 4 shows the amount of block SelectRAM memory that is available in each Virtex-E device. Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XCV50E 16 65,536 XCV100E 20 81,920 XCV200E 28 114,688 XCV300E 32 131,072 XCV400E 40 163,840 XCV600E 72 294,912 XCV1000E 96 393,216 XCV1600E 144 589,824 XCV2000E 160 655,360 XCV2600E 184 753,664 XCV3200E 208 851,968 As illustrated in Figure 6, each block SelectRAM cell is a fully synchronous dual-ported (True Dual PortO) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. www.xilinx.com 1-800-255-7778 Module 2 of 4 5 R VirtexTM-E 1.8 V Field Programmable Gate Arrays RAMB4_S#_S# WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] To Adjacent GRM DOA[#:0] To Adjacent GRM DOB[#:0] Direct Connection To Adjacent CLB Direct Connection To Adjacent CLB XCVE_ds_007 General Purpose Routing Table 5 shows the depth and width aspect ratios for the block SelectRAM. The Virtex-E block SelectRAM also includes dedicated routing to provide an efficient interface with both CLBs and other block SelectRAMs. Table 5: Block SelectRAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 1 4096 ADDR<11:0> DATA<0> 2 2048 ADDR<10:0> DATA<1:0> 4 1024 ADDR<9:0> DATA<3:0> 8 512 ADDR<8:0> DATA<7:0> 16 256 ADDR<7:0> DATA<15:0> Most Virtex-E signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hierarchy. General-purpose routing resources are located in horizontal and vertical routing channels associated with the CLB rows and columns and are as follows: * * * Programmable Routing Matrix It is the longest delay path that limits the speed of any worst-case design. Consequently, the Virtex-E routing architecture and its place-and-route software were defined in a joint optimization process. This joint optimization minimizes long-path delays, and consequently, yields the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times. Local Routing The VersaBlock provides local routing resources (see Figure 7), providing three types of connections: Interconnections among the LUTs, flip-flops, and GRM Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM. Module 2 of 4 6 CLB Figure 7: Virtex-E Local Routing ds022_06_121699 * To Adjacent GRM To Adjacent GRM Figure 6: Dual-Port Block SelectRAM * * GRM * Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. 72 buffered Hex lines route GRM signals to another GRMs six-blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines are driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are uni-directional. 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device. I/O Routing Virtex-E devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Dedicated Routing Clock Routing Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedicated routing resources are provided for two classes of signal. Clock Routing resources distribute clocks and other signals with very high fanout throughout the device. Virtex-E devices include two tiers of clock routing resources referred to as global and local clock routing resources. * Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. * Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB.Global Clock Distribution Network * DLL Location * * The global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and block RAM clock pins. The global nets can be driven only by global buffers. There are four global buffers, one for each global net. The local clock routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. These local resources are more flexible than the global resources since they are not restricted to routing only to clock pins. Tri-State Lines CLB CLB CLB CLB buft_c.eps Figure 8: BUFT Connections to Dedicated Horizontal Bus LInes Global Clock Distribution Virtex-E provides high-speed, low-skew clock distribution through the global routing resources described above. A typical clock distribution net is shown in Figure 9. GCLKPAD3 GCLKPAD2 GCLKBUF3 GCLKBUF2 Global Clock Column Global Clock Rows Four global buffers are provided, two at the top center of the device and two at the bottom center. These drive the four global nets that in turn drive any clock pin. Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is selected either from these pads or from signals in the general purpose routing. Digital Delay-Locked Loops Global Clock Spine GCLKBUF1 GCLKBUF0 GCLKPAD1 GCLKPAD0 XCVE_009 Figure 9: Global Clock Distribution Network DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification There are eight DLLs (Delay-Locked Loops) per device, with four located at the top and four at the bottom, Figure 10. The DLLs can be used to eliminate skew between the clock input pad and the internal clock input pins throughout the device. Each DLL can drive two global clock networks.The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element. Additional delay is introduced such that clock edges arrive at internal flip-flops synchronized with clock edges arriving at the input. In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. The DLL provides four quadrature phases of the source clock, and can double the clock or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. www.xilinx.com 1-800-255-7778 Module 2 of 4 7 R VirtexTM-E 1.8 V Field Programmable Gate Arrays The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to de-skew a board level clock among multiple devices. To guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. For more information about DLL functionality, see the Design Consideration section of the data sheet. DLLDLL Primary DLLs DLLDLL Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including un-bonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. Before the device is configured, all instructions except USER1 and USER2 are available. After configuration, all instructions are available. During configuration, it is recommended that those operations using the boundary-scan register (SAMPLE/PRELOAD, INTEST, EXTEST) not be performed. DLLDLL XCVE_0010 Figure 10: DLL Locations In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Boundary Scan Virtex-E devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS, IDCODE, USERCODE, and HIGHZ instructions. The TAP Module 2 of 4 8 The JTAG input pins (TDI, TMS, TCK) do not have a VCCO requirement and operate with either 2.5 V or 3.3 V input signalling levels. The output pin (TDO) is sourced from the VCCO in bank 2, and for proper operation of LVTTL 3.3 V levels, the bank should be supplied with 3.3 V. Table 6 lists the boundary-scan instructions supported in Virtex-E FPGAs. Internal signals can be captured during EXTEST by connecting them to un-bonded or unused IOBs. They can also be connected to the unused outputs of IOBs defined as unidirectional input pins. Secondary DLLs Secondary DLLs DLLDLL also supports two internal scan chains and configuration/readback of the device. Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays DATA IN IOB.T 0 1 0 IOB IOB IOB IOB sd D Q D Q 1 LE IOB IOB IOB IOB IOB IOB IOB IOB IOB 1 sd D Q D Q 0 LE 1 IOB.I 0 1 IOB IOB IOB IOB IOB 0 D Q D Q LE 1 0 IOB.Q IOB BYPASS REGISTER sd IOB.T INSTRUCTION REGISTER TDI 0 M TDO U X 1 0 sd D Q D Q 1 LE 1 0 sd D Q D Q LE 1 IOB.I 0 DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER UPDATE EXTEST X9016 Figure 11: Virtex-E Family Boundary Scan Logic Table 6: Boundary Scan Instructions (Continued) Instruction Set The Virtex-E Series boundary scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). The complete instruction set is coded as shown in Table 6.. Boundary-Scan Command Binary Code(4:0) CFG_IN 00101 Access the configuration bus for write operations. INTEST 00111 Enables boundary-scan INTEST operation Table 6: Boundary Scan Instructions Boundary-Scan Command Binary Code(4:0) Description Description EXTEST 00000 Enables boundary-scan EXTEST operation USERCODE 01000 Enables shifting out USER code SAMPLE/ PRELOAD 00001 Enables boundary-scan SAMPLE/PRELOAD operation IDCODE 01001 Enables shifting out of ID Code HIGHZ 01010 3-states output pins while enabling the Bypass Register JSTART 01100 Clock the start-up sequence when StartupClk is TCK BYPASS 11111 Enables BYPASS USER1 00010 Access user-defined register 1 USER2 00011 Access user-defined register 2 CFG_OUT 00100 Access the configuration bus for read operations. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification RESERVED www.xilinx.com 1-800-255-7778 All other codes Xilinx reserved instructions Module 2 of 4 9 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Data Registers The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out, and 3-State Control. Non-IOB pins have appropriate partial bit population if input-only or output-only. Each EXTEST CAPTURED-OR state captures all In, Out, and 3-state pins. The other standard data register is the single flip-flop BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA supports up to two additional internal scan chains that can be specified using the BSCAN macro. The macro provides two user pins (SEL1 and SEL2) which are decodes of the USER1 and USER2 instructions respectively. For these instructions, two corresponding pins (T DO1 and TDO2) allow user scan data to be shifted out of TDO. Likewise, there are individual clock pins (DRCK1 and DRCK2) for each user register. There is a common input pin (TDI) and shared output pins that represent the state of the TAP controller (RESET, SHIFT, and UPDATE). BSDL (Boundary Scan Description Language) files for Virtex-E Series devices are available on the Xilinx web site in the File Download area. Identification Registers The IDCODE register is supported. By using the IDCODE, the device connected to the JTAG port can be determined. The IDCODE register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (05 for Virtex-E family) a = the number of CLB rows (ranges from 16 for XCV50E to 104 for XCV3200E) c = the company code (49h for Xilinx) The USERCODE register is supported. By using the USERCODE, a user-programmable identification code can be loaded and shifted out for examination. The identification code (see Table 7) is embedded in the bitstream during bitstream generation and is valid only after configuration. Bit Sequence The order within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA IDCODE XCV50E v0A10093h XCV100E v0A14093h XCV200E v0A1C093h XCV300E v0A20093h XCV400E v0A28093h XCV600E v0A30093h Left half of top-edge IOBs (Right to Left) XCV1000E v0A40093h Left-edge IOBs (Top to Bottom) XCV1600E v0A48093h M1 M0 M2 XCV2000E v0A50093h XCV2600E v0A5C093h XCV3200E v0A68093h From a cavity-up view of the chip (as shown in EPIC), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 12. Bit 0 ( TDO end) Bit 1 Bit 2 Right half of top-edge IOBs (Right to Left) GCLK2 GCLK3 Left half of bottom-edge IOBs (Left to Right) GCLK1 GCLK0 Right half of bottom-edge IOBs (Left to Right) Note: Attempting to load an incorrect bitstream causes configuration to fail and can damage the device. DONE PROG Right-edge IOBs (Bottom to Top) (TDI end) Including Boundary Scan in a Design CCLK 990602001 Figure 12: Boundary Scan Bit Sequence Since the boundary scan pins are dedicated, no special element needs to be added to the design unless an internal data register (USER1 or USER2) is desired. If an internal data register is used, insert the boundary scan symbol and connect the necessary pins as appropriate. Module 2 of 4 10 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Development System Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation (for example, Synopsys FPGA Express), while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xilinx Design Manager (XDMTM) software, providing designers with a common user interface regardless of their choice of entry and verification tools. The XDM software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to Placement and Routing (PAR) can be accessed through the XDM software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Virtex-E design. RPMs, for example, are schematic-based macros with relative location constraints to guide their placement. They help ensure optimal implementation of common functions. For HDL design entry, the Xilinx FPGA Foundation development system provides interfaces to the following synthesis design environments. * * * Synopsys (FPGA Compiler, FPGA Express) Exemplar (Spectrum) Synplicity (Synplify) For schematic design entry, the Xilinx FPGA Foundation and Alliance development system provides interfaces to the following schematic-capture design environments. * * Mentor Graphics V8 (Design Architect, QuickSim II) Viewlogic Systems (Viewdraw) Third-party vendors support many other environments. A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Virtex-E FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. The "soft macro" portion of the library contains detailed descriptions of common logic functions, but does not contain any partitioning or placement information. The performance of these macros depends, therefore, on the partitioning and placement obtained during implementation. RPMs, on the other hand, do contain predetermined partitioning and placement information that permits optimal DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification implementation of these functions. Users can create their own library of soft macros or RPMs based on the macros and primitives in the standard library. The design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. Design Implementation The place-and-route tools (PAR) automatically provide the implementation flow described in this section. The partitioner takes the EDIF net list for the design and maps the logic into the architectural resources of the FPGA (CLBs and IOBs, for example). The placer then determines the best locations for these blocks based on their interconnections and the desired performance. Finally, the router interconnects the blocks. The PAR algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing information is optionally specified during the design-entry process. The implementation of highly structured designs can benefit greatly from basic floor planning. The implementation software incorporates Timing Wizard(R) timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines in PAR then recognize these user-specified requirements and accommodate them. Timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary. Design Verification In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. The development system supports both software simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the net list for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the TRCE(R) static timing analyzer. www.xilinx.com 1-800-255-7778 Module 2 of 4 11 R VirtexTM-E 1.8 V Field Programmable Gate Arrays For in-circuit debugging, an optional download and readback cable is available. This cable connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes. Configuration Virtex-E devices are configured by loading configuration data into the internal configuration memory. Note that attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Some of the pins used for configuration are dedicated pins, while others can be re-used as general purpose inputs and outputs once configuration is complete. Virtex-E supports the following four configuration modes. * * * * Slave-serial mode Master-serial mode SelectMAP mode Boundary-scan mode (JTAG) The Configuration mode pins (M2, M1, M0) select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration. The selection codes are listed in Table 8. The following are dedicated pins: * * * * * Configuration Modes Mode pins (M2, M1, M0) Configuration clock pin (CCLK) PROGRAM pin DONE pin Boundary-scan pins (TDI, TDO, TMS, TCK) Depending on the configuration mode chosen, CCLK can be an output generated by the FPGA, or can be generated externally and provided to the FPGA as an input. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. For correct operation, these pins require a VCCO of 3.3 V or 2.5 V. At 3.3 V the pins operate as LVTTL, and at 2.5 V they operate as LVCMOS. All affected pins fall in banks 2 or 3. Table 8: Configuration Codes M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups Master-serial mode 0 0 0 Out 1 Yes No Boundary-scan mode 1 0 1 N/A 1 No No SelectMAP mode 1 1 0 In 8 No No Slave-serial mode 1 1 1 In 1 Yes No Master-serial mode 1 0 0 Out 1 Yes Yes Boundary-scan mode 0 0 1 N/A 1 No Yes SelectMAP mode 0 1 0 In 8 No Yes Slave-serial mode 0 1 1 In 1 Yes Yes Configuration Mode Module 2 of 4 12 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Table 9 lists the total number of bits required to configure each device. up at the DIN input pin a short time before each rising edge of an externally generated CCLK. Table 9: Virtex-E Bitstream Lengths For more information on serial PROMs, see the PROM data sheet at http://www.xilinx.com/partinfo/ds026.pdf. Device # of Configuration Bits XCV50E 630,048 XCV100E 863,840 XCV200E 1,442,016 XCV300E 1, 875,648 XCV400E 2,693,440 XCV600E 3,961,632 XCV1000E 6,587,520 XCV1600E 8,308,992 XCV2000E 10,159,648 XCV2600E 12,922,336 XCV3200E 16,283,712 Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular FPGA has been configured, the data for the next device is routed to the DOUT pin. The data on the DOUT pin changes on the rising edge of CCLK. The change of DOUT on the rising edge of CCLK differs from previous families, but does not cause a problem for mixed configuration chains. This change was made to improve serial configuration rates for Virtex and Virtex-E only chains. Figure 13 shows a full master/slave system. A Virtex-E device in slave-serial mode should be connected as shown in the right-most device. Slave-Serial Mode Slave-serial mode is selected by applying <111> or <011> to the mode pins (M2, M1, M0). A weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. Figure 14 shows slave-serial configuration timing. In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data. The serial bitstream must be set Table 10 provides more detail about the characteristics shown in Figure 14. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High. Table 10: Master/Slave Serial Mode Programming Switching Figure References Symbol Values Units DIN setup/hold, slave mode 1/2 TDCC/TCCD 5.0 / 0.0 ns, min DIN setup/hold, master mode 1/2 TDSCK/TCKDS 5.0 / 0.0 ns, min DOUT 3 TCCO 12.0 ns, max High time 4 TCCH 5.0 ns, min Low time 5 TCCL 5.0 ns, min FCC 66 MHz, max Description CCLK Maximum Frequency Frequency Tolerance, master mode with respect to nominal +45% -30% . N/C 3.3V 4.7 K M0 M1 M2 N/C DOUT VIRTEX-E MASTER SERIAL CCLK DIN PROGRAM DONE INIT M0 M1 M2 DIN DOUT CCLK XC1701L CLK DATA CEO CE RESET/OE VIRTEX-E, XC4000XL, SLAVE PROGRAM DONE INIT (Low Reset Option Used) PROGRAM XCVE_ds_013 Figure 13: Master/Slave Serial Mode Circuit Diagram DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 13 R VirtexTM-E 1.8 V Field Programmable Gate Arrays DIN 1 TDCC 2 TCCD 5 TCCL CCLK 4 TCCH 3 TCCO DOUT (Output) X5379_a Figure 14: Slave-Serial Mode Programming Switching Characteristics Master-Serial Mode In master-serial mode, the CCLK output of the FPGA drives a Xilinx Serial PROM that feeds bit-serial data to the DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. devices operate in slave-serial mode. The SPROM RESET pin is driven by INIT, and the CE input is driven by DONE. There is the potential for contention on the DONE pin, depending on the start-up sequence options chosen. The sequence of operations necessary to configure a Virtex-E FPGA serially appears in Figure 15. Apply Power The interface is identical to slave-serial except that an internal oscillator is used to generate the configuration clock (CCLK). A wide range of frequencies can be selected for CCLK, which always starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the remainder of the configuration. Switching to a lower frequency is prohibited. FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished. In a full master/slave system (Figure 13), the left-most device operates in master-serial mode. The remaining Low INIT? High The CCLK frequency is set using the ConfigRate option in the bitstream generation software. The maximum CCLK frequency that can be selected is 60 MHz. When selecting a CCLK frequency, ensure that the serial PROM and any daisy-chained FPGAs are fast enough to support the clock rate. On power-up, the CCLK frequency is approximately 2.5 MHz. This frequency is used until the ConfigRate bits have been loaded when the frequency changes to the selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz. If used to delay configuration Release INIT Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. If no CRC errors found, FPGA enters start-up phase causing DONE to go High. End of Bitstream? No Yes Configuration Completed ds009_15_111799 Figure 15: Serial Configuration Flowchart Figure 16 shows the timing of master-serial configuration. Master-serial mode is selected by a <000> or <100> on the mode pins (M2, M1, M0). Table 10 shows the timing information for Figure 16. CCLK (Output) TCKDS 2 1 TDSCK Serial Data In Serial DOUT (Output) DS022_44_071201 Figure 16: Master-Serial Mode Programming Switching Characteristics Module 2 of 4 14 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays At power-up, VCC must rise from 1.0 V to VCC Min in less than 50 ms, otherwise delay configuration by pulling PROGRAM Low until VCC is valid. SelectMAP Mode The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the FPGA with a BUSY flag controlling the flow of data. An external data source provides a byte stream, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read using the SelectMAP mode. If WRITE is not asserted, configuration data is read out of the FPGA as part of a readback operation. After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively, the port can be retained to permit high-speed 8-bit readback. Retention of the SelectMAP port is selectable on a design-by-design basis when the bitstream is generated. If retention is selected, PROHIBIT constraints are required to prevent the SelectMAP-port pins from being used as user I/O. Write Write operations send packets of configuration data into the FPGA. The sequence of operations for a multi-cycle write operation is shown below. Note that a configuration packet can be split into many such sequences. The packet does not have to complete within one assertion of CS, illustrated in Figure 17. 1. Assert WRITE and CS Low. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or de-asserted. Otherwise, an abort is initiated, as described below. 2. Drive data onto D[7:0]. Note that to avoid contention, the data source should not be enabled while CS is Low and WRITE is High. Similarly, while WRITE is High, no more that one CS should be asserted. 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead occurs on the first clock after BUSY goes Low, and the data must be held until this has happened. 4. Repeat steps 2 and 3 until all the data has been sent. 5. De-assert CS and WRITE. Multiple Virtex-E FPGAs can be configured using the SelectMAP mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. See Table 11 for SelectMAP Write Timing Characteristics. Table 11: SelectMAP Write Timing Characteristics Description CCLK Symbol Units D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.0 ns, min CS Setup/Hold 3/4 TSMCSCC/TSMCCCS 7.0 / 1.0 ns, min WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.0 ns, min 7 TSMCKBY 12.0 ns, max FCC 66 MHz, max FCCNH 50 MHz, max BUSY Propagation Delay Maximum Frequency Maximum Frequency with no handshake DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 15 R VirtexTM-E 1.8 V Field Programmable Gate Arrays CCLK CS WRITE 3 4 5 6 1 2 DATA[7:0] 7 BUSY No Write Write No Write Write DS022_45_071201 Figure 17: Write Operations A flowchart for the write operation is shown in Figure 18. Note that if CCLK is slower than fCCNH, the FPGA never asserts BUSY, In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases INIT when finished. Abort During a given assertion of CS, the user cannot switch from a write to a read, or vice-versa. This action causes the current packet command to be aborted. The device remains BUSY until the aborted operation has completed. Following an abort, data is assumed to be unaligned to word boundaries, and the FPGA requires a new synchronization word prior to accepting any new packets. If used to delay configuration Release INIT INIT? Low High Set WRITE = Low Enter Data Source Sequence A On first FPGA Set CS = Low To initiate an abort during a write operation, de-assert WRITE. At the rising edge of CCLK, an abort is initiated, as shown in Figure 19. Apply Configuration Byte Once per bitstream, FPGA checks data using CRC and pulls INIT Low on error. Busy? High Low End of Data? If no errors, first FPGAs enter start-up phase releasing DONE. If no errors, later FPGAs enter start-up phase releasing DONE. No Yes Set CS = High Repeat Sequence A On first FPGA For any other FPGAs Disable Data Source Set WRITE = High When all DONE pins are released, DONE goes High and start-up sequences complete. Configuration Completed ds009_18_111799 Figure 18: SelectMAP Flowchart for Write Operations Module 2 of 4 16 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays CCLK CS WRITE DATA[7:0] BUSY Abort DS022_46_071201 Figure 19: SelectMAP Write Abort Waveforms Boundary-Scan Mode In the boundary-scan mode, no non-dedicated pins are required, configuration being done entirely through the IEEE 1149.1 Test Access Port. Configuration through the TAP uses the CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. The following steps are required to configure the FPGA through the boundary-scan port (when using TCK as a start-up clock). 1. Load the CFG_IN instruction into the boundary-scan instruction register (IR). 2. Enter the Shift-DR (SDR) state. 3. Shift a configuration bitstream into TDI. 4. Return to Run-Test-Idle (RTI). 5. Load the JSTART instruction into IR. Configuration and readback via the TAP is always available. The boundary-scan mode is selected by a <101> or <001> on the mode pins (M2, M1, M0). Configuration Sequence The configuration of Virtex-E devices is a three-phase process. First, the configuration memory is cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a start-up process. Configuration is automatically initiated on power-up unless it is delayed by the user, as described below. The configuration process can also be initiated by asserting PROGRAM. The end of the memory-clearing phase is signalled by INIT going High, and the completion of the entire process is signalled by DONE going High. The power-up timing of configuration signals is shown in Figure 20. 6. Enter the SDR state. 7. Clock TCK through the startup sequence. 8. Return to RTI. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 17 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Vcc TPOR PROGRAM TPL INIT TICCK CCLK OUTPUT or INPUT M0, M1, M2 (Required) VALI ds022_020_071201 Figure 20: Power-Up Timing Configuration Signals The corresponding timing characteristics are listed in Table 12. Table 12: Power-up Timing Characteristics Description Symbol Value Units Power-on Reset1 TPOR 2.0 ms, max Program Latency TPL 100.0 ms, max CCLK (output) Delay TICCK 0.5 ms, min 4.0 ms, max Program Pulse Width TPROGRAM 300 ns, min Notes: 1. TPOR delay is the initialization time required after VCCINT and VCCO in Bank 2 reach the recommended operating voltage. Start-Up Sequence The default Start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addition, the GTS, GSR, and GWE events can be made dependent on the DONE pins of multiple devices all going High, forcing the devices to start synchronously. The sequence can also be paused at any stage until lock has been achieved on any or all DLLs. Delaying Configuration INIT can be held Low using an open-drain driver. An open-drain is required since INIT is a bidirectional open-drain pin that is held Low by the FPGA while the configuration memory is being cleared. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded. Readback The configuration data stored in the Virtex-E configuration memory can be readback for verification. Along with the configuration data it is possible to readback the contents all flip-flops/latches, LUT RAMs, and block RAMs. This capa- Module 2 of 4 18 bility is used for real-time debugging. For more detailed information, see application note XAPP138 "Virtex FPGA Series Configuration and Readback". www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Design Considerations This section contains more detailed design information on the following features. * * * Delay-Locked Loop . . . see page 19 BlockRAM . . . see page 23 SelectI/O . . . see page 30 In order to guarantee the system clock establishes prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL achieves lock. By taking advantage of the DLL to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, high-performance clocks. Using DLLs The Virtex-E FPGA series provides up to eight fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits which improve and simplify system level design. Introduction As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance and the task of managing clock skew and clock delay with conventional clock trees becomes more difficult in large devices. The Virtex-E series of devices resolve this potential problem by providing up to eight fully digital dedicated on-chip DLL circuits, which provide zero propagation delay and low clock skew between output clock signals distributed throughout the device. Library DLL Symbols Figure 21 shows the simplified Xilinx library DLL macro symbol, BUFGDLL. This macro delivers a quick and efficient way to provide a system clock with zero propagation delay throughout the device. Figure 22 and Figure 23 show the two library DLL primitives. These symbols provide access to the complete set of DLL features when implementing more complex applications. I ds022_25_121099 Figure 21: Simplified DLL Macro Symbol BUFGDLL Each DLL can drive up to two global clock routing networks within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DLL output clock, the DLL can compensate for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device. CLKDLL CLKIN CLKFB CLKDV RST LOCKED ds022_26_121099 Figure 22: Standard DLL Symbol CLKDLL Clock multiplication gives the designer a number of design alternatives. For instance, a 50 MHz source clock doubled by the DLL can drive an FPGA design operating at 100 MHz. This technique can simplify board design because the clock path on the board no longer distributes such a high-speed signal. A multiplied clock also provides designers the option of time-domain-multiplexing, using one circuit twice per clock cycle, consuming less area than two copies of the same circuit. Two DLLs in can be connected in series to increase the effective clock multiplication factor to four. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification CLK0 CLK90 CLK180 CLK270 CLK2X In addition to providing zero delay with respect to a user source clock, the DLL can provide multiple phases of the source clock. The DLL can also act as a clock doubler or it can divide the user source clock by up to 16. The DLL can also act as a clock mirror. By driving the DLL output off-chip and then back in again, the DLL can be used to de-skew a board level clock between multiple devices. O 0ns CLKDLLHF CLKIN CLKFB CLK0 CLK180 CLKDV RST LOCKED ds022_027_121099 Figure 23: High Frequency DLL Symbol CLKDLLHF www.xilinx.com 1-800-255-7778 Module 2 of 4 19 R VirtexTM-E 1.8 V Field Programmable Gate Arrays BUFGDLL Pin Descriptions Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic DLL application as shown in Figure 24. IBUFG I O CLKDLL CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 BUFG I O DLLs. This makes a total of eight usable input pins for DLLs in the Virtex-E family. Feedback Clock Input -- CLKFB The DLL requires a reference or feedback signal to provide the delay-compensated output. Connect only the CLK0 or CLK2X DLL outputs to the feedback clock input (CLKFB) pin to provide the necessary feedback to the DLL. The feedback clock input can also be provided through one of the following pins. IBUFG - Global Clock Input Pad CLK2X IO_LVDS_DLL - the pin adjacent to IBUF CLKDV RST LOCKED If an IBUFG sources the CLKFB pin, the following special rules apply. 1. An external input port must source the signal that drives the IBUFG I pin. ds022_28_121099 Figure 24: BUFGDLL Schematic This symbol does not provide access to the advanced clock domain controls or to the clock multiplication or clock division features of the DLL. This symbol also does not provide access to the RST, or LOCKED pins of the DLL. For access to these features, a designer must use the library DLL primitives described in the following sections. Source Clock Input -- I The I pin provides the user source clock, the clock signal on which the DLL operates, to the BUFGDLL. For the BUFGDLL macro the source clock frequency must fall in the low frequency range as specified in the data sheet. The BUFGDLL requires an external signal source clock. Therefore, only an external input port can source the signal that drives the BUFGDLL I pin. Clock Output -- O The clock output pin O represents a delay-compensated version of the source clock (I) signal. This signal, sourced by a global clock buffer BUFG symbol, takes advantage of the dedicated global clock routing resources of the device. The output clock has a 50-50 duty cycle unless you deactivate the duty cycle correction property. 2. The CLK2X output must feedback to the device if both the CLK0 and CLK2X outputs are driving off chip devices. 3. That signal must directly drive only OBUFs and nothing else. These rules enable the software determine which DLL clock output sources the CLKFB pin. Reset Input -- RST When the reset pin RST activates the LOCKED signal deactivates within four source clock cycles. The RST pin, active High, must either connect to a dynamic signal or tied to ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock output pins. Furthermore, the DLL output clocks no longer de-skew with respect to one another. For these reasons, rarely use the reset pin unless re-configuring the device or changing the input frequency. 2x Clock Output -- CLK2X The library CLKDLL primitives provide access to the complete set of DLL features needed when implementing more complex applications with the DLL. The output pin CLK2X provides a frequency-doubled clock with an automatic 50/50 duty-cycle correction. Until the CLKDLL has achieved lock, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty cycle. This behavior allows the DLL to lock on the correct edge with respect to source clock. This pin is not available on the CLKDLLHF primitive. Source Clock Input -- CLKIN Clock Divide Output -- CLKDV The CLKIN pin provides the user source clock (the clock signal on which the DLL operates) to the DLL. The CLKIN frequency must fall in the ranges specified in the data sheet. A global clock buffer (BUFG) driven from another CLKDLL, one of the global clock input buffers (IBUFG), or an IO_LVDS_DLL pin on the same edge of the device (top or bottom) must source this clock signal. There are four IO_LVDS_DLL input pins that can be used as inputs to the The clock divide output pin CLKDV provides a lower frequency version of the source clock. The CLKDV_DIVIDE property controls CLKDV such that the source clock is divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16. CLKDLL Primitive Pin Descriptions Module 2 of 4 20 This feature provides automatic duty cycle correction such that the CLKDV output pin always has a 50/50 duty cycle, with the exception of noninteger divides in HF mode, where the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays 1x Clock Outputs -- CLK[0|90|180|270] The 1x clock output pin CLK0 represents a delay-compensated version of the source clock (CLKIN) signal. The CLKDLL primitive provides three phase-shifted versions of the CLK0 signal while CLKDLLHF provides only the 180 phase-shifted version. The relationship between phase shift and the corresponding period shift appears in Table 13. Table 13: Relationship of Phase-Shifted Output Clock to Period Shift Phase (degrees) Period Shift (percent) 0 0% 90 25% 180 50% 270 75% 90 180 270 0 90 180 270 t To achieve lock, the DLL might need to sample several thousand clock cycles. After the DLL achieves lock, the LOCKED signal activates. The DLL timing parameter section of the data sheet provides estimates for locking times. To guarantee that the system clock is established prior to the device "waking up," the DLL can delay the completion of the device configuration process until after the DLL locks. The STARTUP_WAIT property activates this feature. DLL Properties Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction). Duty Cycle Correction Property CLKIN The 1x clock outputs, CLK0, CLK90, CLK180, and CLK270, use the duty-cycle corrected default, exhibiting a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (by default TRUE) controls this feature. To deactivate the DLL duty-cycle correction for the 1x clock outputs, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. When duty-cycle correction deactivates, the output clock has the same duty cycle as the source clock. CLK2X CLKDV_DIVIDE=2 CLKDV DUTY_CYCLE_CORRECTION=FALSE CLK0 CLK90 Clock Divide Property CLK180 The CLKDV_DIVIDE property specifies how the signal on the CLKDV pin is frequency divided with respect to the CLK0 pin. The values allowed for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16; the default value is 2. CLK270 DUTY_CYCLE_CORRECTION=TRUE CLK0 Startup Delay Property CLK90 This property, STARTUP_WAIT, takes on a value of TRUE or FALSE (the default value). When TRUE the device configuration DONE signal waits until the DLL locks before going to High. CLK180 CLK270 ds022_29_121099 Virtex-E DLL Location Constraints Figure 25: DLL Output Characteristics The DLL provides duty cycle correction on all 1x clock outputs such that all 1x clock outputs by default have a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (TRUE by default), controls this feature. In order to deactivate the DLL duty cycle correction, attach the DUTY_CYCLE_CORRECTION=FALSE property to the DLL symbol. When duty cycle correction deactivates, the output clock has the same duty cycle as the source clock. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification Locked Output -- LOCKED Until the LOCKED signal activates, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. In particular the CLK2X output appears as a 1x clock with a 25/75 duty cycle. The timing diagrams in Figure 25 illustrate the DLL clock output characteristics. 0 The DLL clock outputs can drive an OBUF, a BUFG, or they can route directly to destination clock pins. The DLL clock outputs can only drive the BUFGs that reside on the same edge (top or bottom). As shown in Figure 26, there are four additional DLLs in the Virtex-E devices, for a total of eight per Virtex-E device. These DLLs are located in silicon, at the top and bottom of the two innermost block SelectRAM columns. The location constraint LOC, attached to the DLL symbol with the identifier DLL0S, DLL0P, DLL1S, DLL1P, DLL2S, DLL2P, DLL3S, or DLL3P, controls the DLL location. The LOC property uses the following form: LOC = DLL0P www.xilinx.com 1-800-255-7778 Module 2 of 4 21 R VirtexTM-E 1.8 V Field Programmable Gate Arrays DLL-3S DLL-3P DLL-2P DLL-2S B R A M B R A M B R A M B R A M DLL-1S DLL-1P DLL-0P DLL-0S In a similar manner, a phase shift of the input clock is also possible. The phase shift propagates to the output one to four clocks after the original shift, with no disruption to the CLKDLL control. Output Clocks Bottom Right Half Edge x132_14_100799 Figure 26: Virtex Series DLLs Design Factors Use the following design considerations to avoid pitfalls and improve success designing with Xilinx devices. Input Clock The output clock signal of a DLL, essentially a delayed version of the input clock signal, reflects any instability on the input clock in the output waveform. For this reason the quality of the DLL input clock relates directly to the quality of the output clock waveforms generated by the DLL. The DLL input clock requirements are specified in the data sheet. In most systems a crystal oscillator generates the system clock. The DLL can be used with any commercially available quartz crystal oscillator. For example, most crystal oscillators produce an output waveform with a frequency tolerance of 100 PPM, meaning 0.01 percent change in the clock period. The DLL operates reliably on an input waveform with a frequency drift of up to 1 ns -- orders of magnitude in excess of that needed to support any crystal oscillator in the industry. However, the cycle-to-cycle jitter must be kept to less than 300 ps in the low frequencies and 150 ps for the high frequencies. As mentioned earlier in the DLL pin descriptions, some restrictions apply regarding the connectivity of the output pins. The DLL clock outputs can drive an OBUF, a global clock buffer BUFG, or they can route directly to destination clock pins. The only BUFGs that the DLL clock outputs can drive are the two on the same edge of the device (top or bottom). In addition, the CLK2X output of the secondary DLL can connect directly to the CLKIN of the primary DLL in the same quadrant. Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. Useful Application Examples The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip Standard Usage The circuit shown in Figure 27 resembles the BUFGDLL macro implemented to provide access to the RST and LOCKED pins of the CLKDLL. CLKDLL IBUFG CLKIN CLKFB Input Clock Changes CLK2X Changing the period of the input clock beyond the maximum drift amount requires a manual reset of the CLKDLL. Failure to reset the DLL produces an unreliable lock signal and output clock. It is possible to stop the input clock with little impact to the DLL. Stopping the clock should be limited to less than 100 ms to keep device cooling to a minimum. The clock should be stopped during a Low phase, and when restored the full High period should be seen. During this time, LOCKED stays High and remains High when the clock is restored. When the clock is stopped, one to four more clocks are still observed as the delay line is flushed. When the clock is restarted, the output clocks are not observed for one to four clocks as the delay line is filled. The most common case is two or three clocks. Module 2 of 4 22 BUFG CLK0 CLK90 CLK180 CLK270 CLKDV OBUF IBUF RST LOCKED ds022_028_121099 Figure 27: Standard DLL Implementation Board Level De-skew of Multiple Non-Virtex-E Devices The circuit shown in Figure 28 can be used to de-skew a system clock between a Virtex-E chip and other non-Virtex-E chips on the same board. This application is commonly used when the Virtex-E device is used in conjunction with other standard products such as SRAM or DRAM devices. While designing the board level route, ensure that the return net delay to the source equals the delay to the other chips involved. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. Virtex-E Device CLKDLL IBUFG CLKIN OBUF CLK0 CLK90 CLK180 CLK270 CLKFB IBUFG The dll_2x files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit. CLK2X Virtex-E 4x Clock CLKDV RST Two DLLs located in the same half-edge (top-left, top-right, bottom-right, bottom-left) can be connected together, without using a BUFG between the CLKDLLs, to generate a 4x clock as shown in Figure 30. Virtex-E devices, like the Virtex devices, have four clock networks that are available for internal de-skewing of the clock. Each of the eight DLLs have access to two of the four clock networks. Although all the DLLs can be used for internal de-skewing, the presence of two GCLKBUFs on the top and two on the bottom indicate that only two of the four DLLs on the top (and two of the four DLLs on the bottom) can be used for this purpose. LOCKED BUFG CLKDLL CLKIN CLK0 CLK90 CLK180 CLK270 CLKFB CLK2X CLKDV RST LOCKED Non-Virtex-E Chip CLKDLL-S IBUFG Non-Virtex-E Chip CLKIN CLKFB Other Non_Virtex-E Chips CLK0 CLK90 CLK180 CLK270 ds022_029_121099 CLK2X Figure 28: DLL De-skew of Board Level Clock CLKDV RST Board-level de-skew is not required for low-fanout clock networks. It is recommended for systems that have fanout limitations on the clock network, or if the clock distribution chip cannot handle the load. INV LOCKED CLKDLL-P CLKIN CLKFB Do not use the DLL output clock signals until after activation of the LOCKED signal. Prior to the activation of the LOCKED signal, the DLL output clocks are not valid and can exhibit glitches, spikes, or other spurious movement. CLK0 CLK90 CLK180 CLK270 BUFG CLK2X CLKDV RST OBUF LOCKED The dll_mirror_1 files in the xapp132.zip file show the VHDL and Verilog implementation of this circuit. De-Skew of Clock and Its 2x Multiple ds022_031_041901 The circuit shown in Figure 29 implements a 2x clock multiplier and also uses the CLK0 clock output with a zero ns skew between registers on the same chip. Alternatively, a clock divider circuit can be implemented using similar connections. CLKDLL IBUFG CLKIN CLKFB Figure 30: DLL Generation of 4x Clock in Virtex-E Devices The dll_4xe files in the xapp132.zip file show the DLL implementation in Verilog for Virtex-E devices. These files can be found at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip BUFG CLK0 CLK90 CLK180 CLK270 Using Block SelectRAM+ Features BUFG CLK2X CLKDV IBUF RST OBUF LOCKED ds022_030_121099 Figure 29: DLL De-skew of Clock and 2x Multiple DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification The Virtex FPGA Series provides dedicated blocks of on-chip, true dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the block SelectRAM+ memory can be independently configured as a read/write port, a read port, a write port, and can be configured to a specific data width. The block SelectRAM+ memory offers new capabilities allowing the FPGA designer to simplify designs. www.xilinx.com 1-800-255-7778 Module 2 of 4 23 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Operating Modes RAMB4_S#_S# VIrtex-E block SelectRAM+ memory supports two operating modes: * * WEA ENA RSTA CLKA ADDRA[#:0] DIA[#:0] Read Through Write Back Read Through (one clock edge) The read address is registered on the read port clock edge and data appears on the output after the RAM access time. Some memories might place the latch/register at the outputs, depending on whether a faster clock-to-out versus set-up time is desired. This is generally considered to be an inferior solution, since it changes the read operation to an asynchronous function with the possibility of missing an address/control line transition during the generation of the read pulse clock. WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] Figure 31: Dual-Port Block SelectRAM+ Memory RAMB4_S# WE EN RST The write address is registered on the write port clock edge and the data input is written to the memory and mirrored on the output. * * * * All inputs are registered with the port clock and have a set-up to clock timing specification. All outputs have a read through or write back function depending on the state of the port WE pin. The outputs relative to the port clock are available after the clock-to-out timing specification. The block SelectRAMs are true SRAM memories and do not have a combinatorial path from the address to the output. The LUT SelectRAM+ cells in the CLBs are still available with this function. The ports are completely independent from each other (i.e., clocking, control, address, read/write function, and data width) without arbitration. A write operation requires only one clock edge. A read operation requires only one clock edge. The output ports are latched with a self timed circuit to guarantee a glitch free read. The state of the output port does not change until the port executes another read or write operation. Library Primitives Figure 31 and Figure 32 show the two generic library block SelectRAM+ primitives. Table 14 describes all of the available primitives for synthesis and simulation. DO[#:0] CLK ADDR[#:0] DI[#:0] Block SelectRAM+ Characteristics * DOB[#:0] ds022_032_121399 Write Back (one clock edge) * DOA[#:0] ds022_033_121399 Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available Library Primitives Primitive Port A Width N/A RAMB4_S1 RAMB4_S1_S1 RAMB4_S1_S2 RAMB4_S1_S4 1 1 2 4 RAMB4_S1_S8 8 RAMB4_S1_S16 16 RAMB4_S2 N/A RAMB4_S2_S2 RAMB4_S2_S4 2 2 4 RAMB4_S2_S8 8 RAMB4_S2_S16 16 RAMB4_S4 N/A RAMB4_S4_S4 RAMB4_S4_S8 4 4 8 RAMB4_S4_S16 16 RAMB4_S8 N/A RAMB4_S8_S8 8 RAMB4_S8_S16 RAMB4_S16 RAMB4_S16_S16 Module 2 of 4 24 Port B Width www.xilinx.com 1-800-255-7778 8 16 16 N/A 16 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Port Signals Data Output Bus--DO[A|B]<#:0> Each block SelectRAM+ port operates independently of the others while accessing the same set of 4096 memory cells. The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus reflects the data in bus. The width of this bus equals the width of the port. The allowed widths appear in Table 15. Table 15 describes the depth and width aspect ratios for the block SelectRAM+ memory. Table 15: Block SelectRAM+ Port Aspect Ratios Inverting Control Pins Width Depth ADDR Bus Data Bus 1 4096 ADDR<11:0> DATA<0> 2 2048 ADDR<10:0> DATA<1:0> The four control pins (CLK, EN, WE and RST) for each port have independent inversion control as a configuration option. 4 1024 ADDR<9:0> DATA<3:0> Address Mapping 8 512 ADDR<8:0> DATA<7:0> 16 256 ADDR<7:0> DATA<15:0> Each port accesses the same set of 4096 memory cells using an addressing scheme dependent on the width of the port. Clock--CLK[A|B] Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The data output bus has a clock-to-out time referenced to the CLK pin. Enable--EN[A|B] The enable pin affects the read, write and reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Write Enable--WE[A|B] Activating the write enable pin allows the port to write to the memory cells. When active, the contents of the data input bus are written to the RAM at the address pointed to by the address bus, and the new data also reflects on the data out bus. When inactive, a read operation occurs and the contents of the memory cells referenced by the address bus reflect on the data out bus. The physical RAM location addressed for a particular width are described in the following formula (of interest only when the two ports use different aspect ratios). Start = ((ADDRport +1) * Widthport) -1 End = ADDRport * Widthport Table 16 shows low order address mapping for each port width. Table 16: Port Address Mapping Port Port Width Addresses 1 4095... 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2 2047... 07 4 1023... 8 511... 16 255... 06 05 03 04 03 02 02 01 01 01 00 00 00 00 Creating Larger RAM Structures Reset--RST[A|B] The reset pin forces the data output bus latches to zero synchronously. This does not affect the memory cells of the RAM and does not disturb a write operation on the other port. The block SelectRAM+ columns have specialized routing to allow cascading blocks together with minimal routing delays. This achieves wider or deeper RAM structures with a smaller timing penalty than when using normal routing channels. Address Bus--ADDR[A|B]<#:0> Location Constraints The address bus selects the memory cells for read or write. The width of the port determines the required width of this bus as shown in Table 15. Block SelectRAM+ instances can have LOC properties attached to them to constrain the placement. The block SelectRAM+ placement locations are separate from the CLB location naming convention, allowing the LOC properties to transfer easily from array to array. Data In Bus--DI[A|B]<#:0> The data in bus provides the new data value to be written into the RAM. This bus and the port have the same width, as shown in Table 15. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification The LOC properties use the following form. LOC = RAMB4_R#C# RAMB4_R0C0 is the upper left RAMB4 location on the device. www.xilinx.com 1-800-255-7778 Module 2 of 4 25 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Conflict Resolution The block SelectRAM+ memory is a true dual-read/write port RAM that allows simultaneous access of the same memory cell from both ports. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. The following lists specifics of port and memory cell write conflict resolution. * * If both ports write to the same memory cell simultaneously, violating the clock-to-clock setup requirement, consider the data stored as invalid. If one port attempts a read of the same memory cell the other simultaneously writes, violating the clock-to-clock setup requirement, the following occurs. - The write succeeds - The data out on the writing port accurately reflects the data written. - The data out on the reading port is invalid. Conflicts do not cause any physical damage. Single Port Timing Figure 33 shows a timing diagram for a single port of a block SelectRAM+ memory. The block SelectRAM+ AC switching characteristics are specified in the data sheet. The block SelectRAM+ memory is initially disabled. At the first rising edge of the CLK pin, the ADDR, DI, EN, WE, and RST pins are sampled. The EN pin is High and the WE pin is Low indicating a read operation. The DO bus contains the contents of the memory location, 0x00, as indicated by the ADDR bus. At the second rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN and WE pins are High indicating a write operation. The DO bus mirrors the DI bus. The DI bus is written to the memory location 0x0F. At the third rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is High and the WE pin is Low indicating a read operation. The DO Module 2 of 4 26 bus contains the contents of the memory location 0x7E as indicated by the ADDR bus. At the fourth rising edge of the CLK pin, the ADDR, DI, EN, WR, and RST pins are sampled again. The EN pin is Low indicating that the block SelectRAM+ memory is now disabled. The DO bus retains the last value. Dual Port Timing Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A has a longer period than the clock on Port B. The timing parameter TBCCS, (clock-to-clock set-up) is shown on this diagram. The parameter, TBCCS is violated once in the diagram. All other timing parameters are identical to the single port version shown in Figure 33. TBCCS is only of importance when the address of both ports are the same and at least one port is performing a write operation. When the clock-to-clock set-up parameter is violated for a WRITE-WRITE condition, the contents of the memory at that location are invalid. When the clock-to-clock set-up parameter is violated for a WRITE-READ condition, the contents of the memory are correct, but the read port has invalid data. At the first rising edge of the CLKA, memory location 0x00 is to be written with the value 0xAAAA and is mirrored on the DOA bus. The last operation of Port B was a read to the same memory location 0x00. The DOB bus of Port B does not change with the new value on Port A, and retains the last read value. A short time later, Port B executes another read to memory location 0x00, and the DOB bus now reflects the new memory value written by Port A. At the second rising edge of CLKA, memory location 0x7E is written with the value 0x9999 and is mirrored on the DOA bus. Port B then executes a read operation to the same memory location without violating the TBCCS parameter and the DOB reflects the new memory values written by Port A. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays TBPWH TBPWL CLK TBACK ADDR 00 0F 7E 8F CCCC BBBB 2222 TBDCK DDDD DIN TBCKO DOUT MEM (00) CCCC MEM (7E) TBECK EN RST TBWCK WE DISABLED READ WRITE READ DISABLED ds022_0343_121399 Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory TBCCS VIOLATION CLK_A PORT A ADDR_A 00 EN_A 7E 0F 0F 7E TBCCS TBCCS WE_A DI_A AAAA DO_A 9999 AAAA AAAA 1111 0000 9999 AAAA UNKNOWN 2222 CLK_B PORT B ADDR_B 00 00 7E 0F 0F 7E 1A 1111 1111 1111 BBBB 1111 2222 FFFF EN_B WE_B DI_B DO_B MEM (00) AAAA 9999 BBBB UNKNOWN 2222 FFFF ds022_035_121399 Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory At the third rising edge of CLKA, the TBCCS parameter is violated with two writes to memory location 0x0F. The DOA and DOB busses reflect the contents of the DIA and DIB busses, but the stored value at 0x0F is invalid. At the fourth rising edge of CLKA, a read operation is performed at memory location 0x0F and invalid data is present DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification on the DOA bus. Port B also executes a read operation to memory location 0x0F and also reads invalid data. At the fifth rising edge of CLKA a read operation is performed that does not violate the TBCCS parameter to the previous write of 0x7E by Port B. THe DOA bus reflects the recently written value by Port B. www.xilinx.com 1-800-255-7778 Module 2 of 4 27 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Initialization Design Examples The block SelectRAM+ memory can initialize during the device configuration sequence. The 16 initialization properties of 64 hex values each (a total of 4096 bits) set the initialization of each RAM. These properties appear in Table 17. Any initialization properties not explicitly set configure as zeros. Partial initialization strings pad with zeros. Initialization strings greater than 64 hex values generate an error. The RAMs can be simulated with the initialization values using generics in VHDL simulators and parameters in Verilog simulators. Creating a 32-bit Single-Port RAM The true dual-read/write port functionality of the block SelectRAM+ memory allows a single port, 128 deep by 32-bit wide RAM to be created using a single block SelectRAM+ cell as shown in Figure 35. RAMB4_S16_S16 Initialization in VHDL and Synopsys The block SelectRAM+ structures can be initialized in VHDL for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the VHDL code uses a generic to pass the initialization. Synopsys FPGA compiler does not presently support generics. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the generic statements. The following code illustrates a module that employs these techniques. Table 17: RAM Initialization Properties Property Memory Cells INIT_00 255 to 0 INIT_01 511 to 256 INIT_02 767 to 512 INIT_03 1023 to 768 INIT_04 1279 to 1024 INIT_05 1535 to 1280 INIT_06 1791 to 2047 INIT_07 2047 to 1792 INIT_08 2303 to 2048 INIT_09 2559 to 2304 INIT_0a 2815 to 2560 INIT_0b 3071 to 2816 INIT_0c 3327 to 3072 INIT_0d 3583 to 3328 INIT_0e 3839 to 3584 INIT_0f 4095 to 3840 WEA ENA RSTA CLKA ADDRA[7:0] DIA[15:0] WE EN RST CLK ADDR[6:0], GND DI[15:0] WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] DOA[15:0] DO[31:16] DOB[15:0] DO[15:0] ds022_036_121399 Figure 35: Single Port 128 x 32 RAM Interleaving the memory space, setting the LSB of the address bus of Port A to 1 (VCC), and the LSB of the address bus of Port B to 0 (GND), allows a 32-bit wide single port RAM to be created. Creating Two Single-Port RAMs The true dual-read/write port functionality of the block SelectRAM+ memory allows a single RAM to be split into two single port memories of 2K bits each as shown in Figure 36. RAMB4_S4_S16 WE1 EN1 RST1 CLK1 V CC , ADDR1[8:0] DI1[3:0] WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0] WE2 EN2 RST2 CLK2 GND, ADDR2[6:0] DI2[15:0] WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] DOA[3:0] DO1[3:0] DOB[15:0] DO2[15:0] ds022_037_121399 Figure 36: 512 x 4 RAM and 128 x 16 RAM In this example, a 512K x 4 RAM (Port A) and a 128 x 16 RAM (Port B) are created out of a single block SelectRAM+. The address space for the RAM is split by fixing the MSB of Port A to 1 (VCC) for the upper 2K bits and the MSB of Port B to 0 (GND) for the lower 2K bits. Initialization in Verilog and Synopsys The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a defparam to pass the initialization. The Synopsys FPGA compiler does not presently support defparam. The initialization values instead attach as attributes to the RAM by a built-in Synopsys dc_script. The translate_off statement stops synthesis translation of the defparam statements. The following code illustrates a module that employs these techniques. Module 2 of 4 28 WE EN RST CLK ADDR[6:0], V CC DI[31:16] Block Memory Generation The CoreGen program generates memory structures using the block SelectRAM+ features. This program outputs VHDL or Verilog simulation code templates and an EDIF file for inclusion in a design. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE of MYMEM is signal logic0, logic1: std_logic; component RAMB4_S8 --synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"); --synopsys translate_on port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; --synopsys dc_script_begin --set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string --set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string --synopsys dc_script_end begin logic0 <='0'; logic1 <='1'; ram0: RAMB4_S8 --synopsys translate_off generic map ( INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF", INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210") --synopsys translate_on port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); end BEHAVE; DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 29 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string //synopsys dc_script_end assign logic0 = 1'b0; assign logic1 = 1'b1; RAMB4_S8 ram0 (.WE(WE), .EN(logic1), .RST(logic0), .CLK(CLK), .ADDR(ADDR), .DI(DIN), .DO(DOUT)); //synopsys translate_off defparam ram0.INIT_00 = 256h'0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF; defparam ram0.INIT_01 = 256h'FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210; //synopsys translate_on endmodule Using SelectI/O The Virtex-E FPGA series includes a highly configurable, high-performance I/O resource, called SelectI/OTM to provide support for a wide variety of I/O standards. The SelectI/O resource is a robust set of features including programmable control of output drive strength, slew rate, and input delay and hold time. Taking advantage of the flexibility and SelectI/O features and the design considerations described in this document can improve and simplify system level design. Introduction As FPGAs continue to grow in size and capacity, the larger and more complex systems designed for them demand an increased variety of I/O standards. Furthermore, as system clock speeds continue to increase, the need for high performance I/O becomes more important. While chip-to-chip delays have an increasingly substantial impact on overall system speed, the task of achieving the desired system performance becomes more difficult with the proliferation of low-voltage I/O standards. SelectI/O, the revolutionary input/output resources of Virtex-E devices, resolve this potential problem by providing a highly configurable, high-performance alternative to the I/O resources of more conventional programmable devices. Virtex-E SelectI/O features combine the flexibility and time-to-market advantages of programmable logic with the high performance previously available only with ASICs and custom ICs. Module 2 of 4 30 Each SelectI/O block can support up to 20 I/O standards. Supporting such a variety of I/O standards allows the support of a wide variety of applications, from general purpose standard applications to high-speed low-voltage memory busses. SelectI/O blocks also provide selectable output drive strengths and programmable slew rates for the LVTTL output buffers, as well as an optional, programmable weak pull-up, weak pull-down, or weak "keeper" circuit ideal for use in external bussing applications. Each Input/Output Block (IOB) includes three registers, one each for the input, output, and 3-state signals within the IOB. These registers are optionally configurable as either a D-type flip-flop or as a level sensitive latch. The input buffer has an optional delay element used to guarantee a zero hold time requirement for input signals registered within the IOB. The Virtex-E SelectI/O features also provide dedicated resources for input reference voltage (VREF) and output source voltage (VCCO), along with a convenient banking system that simplifies board design. By taking advantage of the built-in features and wide variety of I/O standards supported by the SelectI/O features, system-level design and board design can be greatly simplified and improved. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Fundamentals Overview of Supported I/O Standards Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored specifically to the needs of that application. The bus I/O standards provide specifications to other vendors who create products designed to interface with these applications. Each standard often has its own specifications for current, voltage, I/O buffering, and termination techniques. This section provides a brief overview of the I/O standards supported by all Virtex-E devices. The ability to provide the flexibility and time-to-market advantages of programmable logic is increasingly dependent on the capability of the programmable logic device to support an ever increasing variety of I/O standards LVTTL -- Low-Voltage TTL The SelectI/O resources feature highly configurable input and output buffers which provide support for a wide variety of I/O standards. As shown in Table 18, each buffer type can support a variety of voltage requirements. Table 18: Virtex-E Supported I/O Standards While most I/O standards specify a range of allowed voltages, this document records typical voltage values only. Detailed information on each specification can be found on the Electronic Industry Alliance Jedec website at: http://www.jedec.org The Low-Voltage TTL, or LVTTL standard is a general purpose EIA/JESDSA standard for 3.3V applications that uses an LVTTL input buffer and a Push-Pull output buffer. This standard requires a 3.3V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a termination voltage (VTT). LVCMOS2 -- Low-Voltage CMOS for 2.5 Volts The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2 standard is an extension of the LVCMOS standard (JESD 8.-5) used for general purpose 2.5V applications. This standard requires a 2.5V output source voltage (VCCO), but does not require the use of a reference voltage (VREF) or a board termination voltage (VTT). Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS18 -- 1.8 V Low Voltage CMOS LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A SSTL3 I & II 3.3 N/A 1.50 1.50 This standard is an extension of the LVCMOS standard. It is used in general purpose 1.8 V applications. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 HSTL I 1.5 N/A 0.75 0.75 The Peripheral Component Interface, or PCI standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses a LVTTL input buffer and a Push-Pull output buffer. This standard does not require the use of a reference voltage (VREF) or a board termination voltage (VTT), however, it does require a 3.3V output source voltage (VCCO). HSTL III & IV 1.5 N/A 0.90 1.50 GTL -- Gunning Transceiver Logic Terminated CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/A I/O Standard PCI -- Peripheral Component Interface The Gunning Transceiver Logic, or GTL standard is a high-speed bus standard (JESD8.3) invented by Xerox. Xilinx has implemented the terminated variation for this standard. This standard requires a differential amplifier input buffer and a Open Drain output buffer. GTL+ -- Gunning Transceiver Logic Plus The Gunning Transceiver Logic Plus, or GTL+ standard is a high-speed bus standard (JESD8.3) first used by the Pentium Pro processor. HSTL -- High-Speed Transceiver Logic The High-Speed Transceiver Logic, or HSTL standard is a general purpose high-speed, 1.5V bus standard sponsored by IBM (EIA/JESD 8-6). This standard has four variations or classes. SelectI/O devices support Class I, III, and IV. This DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 31 R VirtexTM-E 1.8 V Field Programmable Gate Arrays standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 -- Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 standard is a general purpose 3.3V memory bus standard also sponsored by Hitachi and IBM (JESD8-8). This standard has two classes, I and II. SelectI/O devices support both classes for the SSTL3 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer. SSTL2 -- Stub Series Terminated Logic for 2.5V The Stub Series Terminated Logic for 2.5V, or SSTL2 standard is a general purpose 2.5V memory bus standard sponsored by Hitachi and IBM (JESD8-9). This standard has two classes, I and II. SelectI/O devices support both classes for the SSTL2 standard. This standard requires a Differential Amplifier input buffer and an Push-Pull output buffer. Library Symbols The Xilinx library includes an extensive list of symbols designed to provide support for the variety of SelectI/O features. Most of these symbols represent variations of the five generic SelectI/O symbols. * * * * * IBUF (input buffer) IBUFG (global clock input buffer) OBUF (output buffer) OBUFT (3-state output buffer) IOBUF (input/output buffer) IBUF Signals used as inputs to the Virtex-E device must source an input buffer (IBUF) via an external input port. The generic Virtex-E IBUF symbol appears in Figure 37. The extension IBUF I CTT -- Center Tap Terminated The Center Tap Terminated, or CTT standard is a 3.3V memory bus standard sponsored by Fujitsu (JESD8-4). This standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. AGP-2X -- Advanced Graphics Port The Intel AGP standard is a 3.3V Advanced Graphics Port-2X bus standard used with the Pentium II processor for graphics applications. This standard requires a Push-Pull output buffer and a Differential Amplifier input buffer. LVDS -- Low Voltage Differential Signal LVDS is a differential I/O standard. It requires that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has an inherent noise immunity over single-ended I/O standards. The voltage swing between two signal lines is approximately 350mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. LVDS requires the use of two pins per input or output. LVDS requires external resistor termination. BLVDS -- Bus LVDS This standard allows for bidirectional LVDS communication between two or more devices. The external resistor termination is different than the one for standard LVDS. LVPECL -- Low Voltage Positive Emitter Coupled Logic LVPECL is another differential I/O standard. It requires two signal lines for transmitting one data bit. This standard specifies two pins per input or output. The voltage swing between these two signal lines is approximately 850 mV. The use of a reference voltage (VREF) or a board termination voltage (VTT) is not required. The LVPECL standard requires external resistor termination. Module 2 of 4 32 O x133_01_111699 Figure 37: Input Buffer (IBUF) Symbols to the base name defines which I/O standard the IBUF uses. The assumed standard is LVTTL when the generic IBUF has no specified extension. The following list details the variations of the IBUF symbol: * * * * * * * * * * * * * * * * * * IBUF IBUF_LVCMOS2 IBUF_PCI33_3 IBUF_PCI66_3 IBUF_GTL IBUF_GTLP IBUF_HSTL_I IBUF_HSTL_III IBUF_HSTL_IV IBUF_SSTL3_I IBUF_SSTL3_II IBUF_SSTL2_I IBUF_SSTL2_II IBUF_CTT IBUF_AGP IBUF_LVCMOS18 IBUF_LVDS IBUF_LVPECL When the IBUF symbol supports an I/O standard that requires a VREF, the IBUF automatically configures as a differential amplifier input buffer. The VREF voltage must be supplied on the VREF pins. In the case of LVDS, LVPECL, and BLVDS, VREF is not required. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUF placement restrictions require that any differential amplifier input signals within a bank be of the same standard. How to specify a specific location for the IBUF via the LOC property is described below. Table 19 summarizes the Virtex-E input standards compatibility requirements. An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element by default activates to ensure a zero hold-time requirement. The NODELAY=TRUE property overrides this default. When the IBUF does not drive a flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. Table 19: Xilinx Input Standards Compatibility Requirements Standards with the same input VCCO, output VCCO, and VREF can be placed within the same bank. Bank 7 Bank 0 Bank 1 GCLK3 GCLK2 Bank 2 Rule 1 Bank 5 Bank 3 Bank 6 GCLK0 Bank 4 ds022_42_012100 Figure 38: Virtex-E I/O Banks IBUFG Signals used as high fanout clock inputs to the Virtex-E device should drive a global clock input buffer (IBUFG) via an external input port in order to take advantage of one of the four dedicated global clock distribution networks. The output of the IBUFG symbol can drive only a CLKDLL, DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification IBUFG I O x133_03_111699 Figure 39: Virtex-E Global Clock Input Buffer (IBUFG) Symbol The extension to the base name determines which I/O standard is used by the IBUFG. With no extension specified for the generic IBUFG symbol, the assumed standard is LVTTL. The following list details variations of the IBUFG symbol. * * * * * * * * * * * * * * * * * * IBUFG IBUFG_LVCMOS2 IBUFG_PCI33_3 IBUFG_PCI66_3 IBUFG_GTL IBUFG_GTLP IBUFG_HSTL_I IBUFG_HSTL_III IBUFG_HSTL_IV IBUFG_SSTL3_I IBUFG_SSTL3_II IBUFG_SSTL2_I IBUFG_SSTL2_II IBUFG_CTT IBUFG_AGP IBUFG_LVCMOS18 IBUFG_LVDS IBUFG_LVPECL When the IBUFG symbol supports an I/O standard that requires a differential amplifier input, the IBUFG automatically configures as a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. Virtex-E Device GCLK1 CLKDLLHF, or BUFG symbol. The generic Virtex-E IBUFG symbol appears in Figure 39. The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IBUFG placement restrictions require any differential amplifier input signals within a bank be of the same standard. The LOC property can specify a location for the IBUFG. As an added convenience, the BUFGP can be used to instantiate a high fanout clock input. The BUFGP symbol www.xilinx.com 1-800-255-7778 Module 2 of 4 33 R VirtexTM-E 1.8 V Field Programmable Gate Arrays represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in a global clock pad location. The LOC property can specify a location for the BUFGP. OBUF An OBUF must drive outputs through an external output port. The generic output buffer (OBUF) symbol appears in Figure 40. The extension to the base name defines which I/O standard the OBUF uses. With no extension specified for the generic OBUF symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength. OBUF I Figure 40: Virtex-E Output Buffer (OBUF) Symbol The LVTTL OBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL output buffers have selectable drive strengths. The format for LVTTL OBUF symbol names is as follows: OBUF_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16, or 24). The following list details variations of the OBUF symbol. OBUF OBUF_S_2 OBUF_S_4 OBUF_S_6 OBUF_S_8 OBUF_S_12 OBUF_S_16 OBUF_S_24 OBUF_F_2 OBUF_F_4 OBUF_F_6 OBUF_F_8 OBUF_F_12 OBUF_F_16 OBUF_F_24 OBUF_LVCMOS2 OBUF_PCI33_3 Module 2 of 4 34 OBUF_PCI66_3 OBUF_GTL OBUF_GTLP OBUF_HSTL_I OBUF_HSTL_III OBUF_HSTL_IV OBUF_SSTL3_I OBUF_SSTL3_II OBUF_SSTL2_I OBUF_SSTL2_II OBUF_CTT OBUF_AGP OBUF_LVCMOS18 OBUF_LVDS OBUF_LVPECL The Virtex-E series supports eight banks for the HQ and PQ packages. The CS packages support four VCCO banks. O x133_04_111699 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OBUF placement restrictions require that within a given VCCO bank each OBUF share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within any VCCO bank. Table 20 summarizes the Virtex-E output compatibility requirements. The LOC property can specify a location for the OBUF. Table 20: Output Standards Compatibility Requirements Rule 1 Only outputs with standards that share compatible VCCO can be used within the same bank. Rule 2 There are no placement restrictions for outputs with standards that do not require a VCCO. VCCO Compatible Standards 3.3 LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL, GTL+, PCI33_3, PCI66_3 2.5 SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+ 1.5 HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+ OBUFT The generic 3-state output buffer OBUFT (see Figure 41) typically implements 3-state outputs or bidirectional I/O. The extension to the base name defines which I/O standard OBUFT uses. With no extension specified for the generic OBUFT symbol, the assumed standard is slew rate limited LVTTL with 12 mA drive strength. The LVTTL OBUFT additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays LVTTL 3-state output buffers have selectable drive strengths. The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. The format for LVTTL OBUFT symbol names is as follows: The SelectI/O OBUFT placement restrictions require that within a given VCCO bank each OBUFT share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. OBUFT_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16, or 24). T 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the OBUFT (PULLUP, PULLDOWN, or KEEPER). OBUFT O I x133_05_111699 Figure 41: 3-State Output Buffer Symbol (OBUFT) The following list details variations of the OBUFT symbol. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OBUFT OBUFT_S_2 OBUFT_S_4 OBUFT_S_6 OBUFT_S_8 OBUFT_S_12 OBUFT_S_16 OBUFT_S_24 OBUFT_F_2 OBUFT_F_4 OBUFT_F_6 OBUFT_F_8 OBUFT_F_12 OBUFT_F_16 OBUFT_F_24 OBUFT_LVCMOS2 OBUFT_PCI33_3 OBUFT_PCI66_3 OBUFT_GTL OBUFT_GTLP OBUFT_HSTL_I OBUFT_HSTL_III OBUFT_HSTL_IV OBUFT_SSTL3_I OBUFT_SSTL3_II OBUFT_SSTL2_I OBUFT_SSTL2_II OBUFT_CTT OBUFT_AGP OBUFT_LVCMOS18 OBUFT_LVDS OBUFT_LVPECL DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification The LOC property can specify a location for the OBUFT. The weak "keeper" circuit requires the input buffer within the IOB to sample the I/O signal. So, OBUFTs programmed for an I/O standard that requires a VREF have automatic placement of a VREF in the bank with an OBUFT configured with a weak "keeper" circuit. This restriction does not affect most circuit design as applications using an OBUFT configured with a weak "keeper" typically implement a bidirectional I/O. In this case the IBUF (and the corresponding VREF) are explicitly placed. The LOC property can specify a location for the OBUFT. IOBUF Use the IOBUF symbol for bidirectional signals that require both an input buffer and a 3-state output buffer with an active high 3-state pin. The generic input/output buffer IOBUF appears in Figure 42. The extension to the base name defines which I/O standard the IOBUF uses. With no extension specified for the generic IOBUF symbol, the assumed standard is LVTTL input buffer and slew rate limited LVTTL with 12 mA drive strength for the output buffer. The LVTTL IOBUF additionally can support one of two slew rate modes to minimize bus transients. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. LVTTL bidirectional buffers have selectable output drive strengths. The format for LVTTL IOBUF symbol names is as follows: IOBUF_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast) or S (Slow), and <drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16, or 24). www.xilinx.com 1-800-255-7778 Module 2 of 4 35 R VirtexTM-E 1.8 V Field Programmable Gate Arrays T I The voltage reference signal is "banked" within the Virtex-E device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38, page 33 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. IOBUF IO O x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * IOBUF IOBUF_S_2 IOBUF_S_4 IOBUF_S_6 IOBUF_S_8 IOBUF_S_12 IOBUF_S_16 IOBUF_S_24 IOBUF_F_2 IOBUF_F_4 IOBUF_F_6 IOBUF_F_8 IOBUF_F_12 IOBUF_F_16 IOBUF_F_24 IOBUF_LVCMOS2 IOBUF_PCI33_3 IOBUF_PCI66_3 IOBUF_GTL IOBUF_GTLP IOBUF_HSTL_I IOBUF_HSTL_III IOBUF_HSTL_IV IOBUF_SSTL3_I IOBUF_SSTL3_II IOBUF_SSTL2_I IOBUF_SSTL2_II IOBUF_CTT IOBUF_AGP IOBUF_LVCMOS18 IOBUF_LVDS IOBUF_LVPECL The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. Additional restrictions on the Virtex-E SelectI/O IOBUF placement require that within a given VCCO bank each IOBUF must share the same output source drive voltage. Input buffers of any type and output buffers that do not require VCCO can be placed within the same VCCO bank. The LOC property can specify a location for the IOBUF. An optional delay element is associated with the input path in each IOBUF. When the IOBUF drives an input flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Override this default with the NODELAY=TRUE property. In the case when the IOBUF does not drive an input flip-flop within the IOB, the delay element de-activates by default to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. 3-state output buffers and bidirectional buffers can have either a weak pull-up resistor, a weak pull-down resistor, or a weak "keeper" circuit. Control this feature by adding the appropriate symbol to the output net of the IOBUF (PULLUP, PULLDOWN, or KEEPER). SelectI/O Properties Access to some of the SelectI/O features (for example, location constraints, input delay, output drive strength, and slew rate) is available through properties associated with these features. Input Delay Properties An optional delay element is associated with each IBUF. When the IBUF drives a flip-flop within the IOB, the delay element activates by default to ensure a zero hold-time requirement. Use the NODELAY=TRUE property to override this default. When the IOBUF symbol used supports an I/O standard that requires a differential amplifier input, the IOBUF automatically configures with a differential amplifier input buffer. The low-voltage I/O standards with a differential amplifier input require an external reference voltage input VREF. Module 2 of 4 36 IOBUF placement restrictions require any differential amplifier input signals within a bank be of the same standard. In the case when the IBUF does not drive a flip-flop within the IOB, the delay element by default de-activates to provide higher performance. To delay the input signal, activate the delay element with the DELAY=TRUE property. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays IOB Flip-Flop/Latch Property Design Considerations The Virtex-E series I/O Block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. The design implementation software automatically takes advantage of these registers when the following option for the Map program is specified. Reference Voltage (VREF) Pins map -pr b <filename> Alternatively, the IOB = TRUE property can be placed on a register to force the mapper to place the register in an IOB. Location Constraints Specify the location of each SelectI/O symbol with the location constraint LOC attached to the SelectI/O symbol. The external port identifier indicates the value of the location constrain. The format of the port identifier depends on the package chosen for the specific design. The LOC properties use the following form: LOC=P37 Output Slew Rate Property As mentioned above, a variety of symbol names provide the option of choosing the desired slew rate for the output buffers. In the case of the LVTTL output buffers (OBUF, OBUFT, and IOBUF), slew rate control can be alternatively programed with the SLEW= property. By default, the slew rate for each output buffer is reduced to minimize power bus transients when switching non-critical signals. The SLEW= property has one of the two following values. SLEW=SLOW SLEW=FAST Output Drive Strength Property The desired output drive strength can be additionally specified by choosing the appropriate library symbol. The Xilinx library also provides an alternative method for specifying this feature. For the LVTTL output buffers (OBUF, OBUFT, and IOBUF, the desired drive strength can be specified with the DRIVE= property. This property could have one of the following seven values. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification The voltage reference signal is "banked" within the device on a half-edge basis such that for all packages there are eight independent VREF banks internally. See Figure 38 for a representation of the Virtex-E I/O banks. Within each bank approximately one of every six I/O pins is automatically configured as a VREF input. After placing a differential amplifier input signal within a given VREF bank, the same external source must drive all I/O pins configured as a VREF input. Within each VREF bank, any input buffers that require a VREF signal must be of the same type. Output buffers of any type and input buffers can be placed without requiring a reference voltage within the same VREF bank. Output Drive Source Voltage (VCCO) Pins LOC=A42 DRIVE=2 DRIVE=4 DRIVE=6 DRIVE=8 DRIVE=12 (Default) DRIVE=16 DRIVE=24 Low-voltage I/O standards with a differential amplifier input buffer require an input reference voltage (VREF). Provide the VREF as an external signal to the device. Many of the low voltage I/O standards supported by SelectI/O devices require a different output drive source voltage (VCCO). As a result each device can often have to support multiple output drive source voltages. The Virtex-E series supports eight banks for the HQ and PQ packages. The CS package supports four VCCO banks. Output buffers within a given VCCO bank must share the same output drive source voltage. Input buffers for LVTTL, LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the VCCO voltage for Input VCCO voltage. Transmission Line Effects The delay of an electrical signal along a wire is dominated by the rise and fall times when the signal travels a short distance. Transmission line delays vary with inductance and capacitance, but a well-designed board can experience delays of approximately 180 ps per inch. Transmission line effects, or reflections, typically start at 1.5" for fast (1.5 ns) rise and fall times. Poor (or non-existent) termination or changes in the transmission line impedance cause these reflections and can cause additional delay in longer traces. As system speeds continue to increase, the effect of I/O delays can become a limiting factor and therefore transmission line termination becomes increasingly more important. Termination Techniques A variety of termination techniques reduce the impact of transmission line effects. The following are output termination techniques: * * * * None Series Parallel (Shunt) Series and Parallel (Series-Shunt) www.xilinx.com 1-800-255-7778 Module 2 of 4 37 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Input termination techniques include the following. Simultaneous Switching Guidelines * * Ground bounce can occur with high-speed digital ICs when multiple outputs change states simultaneously, causing undesired transient behavior on an output, or in the internal logic. This problem is also referred to as the Simultaneous Switching Output (SSO) problem. None Parallel (Shunt) These termination techniques can be applied in any combination. A generic example of each combination of termination methods appears in Figure 43. Ground bounce is primarily due to current changes in the combined inductance of ground pins, bond wires, and ground metallization. The IC internal ground level deviates from the external system ground level for a short duration (a few nanoseconds) after multiple outputs change state simultaneously. Double Parallel Terminated Unterminated VTT VTT Z=50 Z=50 VREF Unterminated Output Driving a Parallel Terminated Input Series Terminated Output Driving a Parallel Terminated Input VTT VTT Ground bounce affects stable Low outputs and all inputs because they interpret the incoming signal by comparing it to the internal ground. If the ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input can be interpreted as a short pulse with a polarity opposite to the ground bounce. Z=50 Z=50 VREF VREF Series-Parallel Terminated Output Driving a Parallel Terminated Input VTT Series Terminated Output VTT Z=50 Z=50 VREF VREF x133_07_111699 Figure 43: Overview of Standard Input and Output Termination Methods Table 21 provides guidelines for the maximum number of simultaneously switching outputs allowed per output power/ground pair to avoid the effects of ground bounce. See Table 22 for the number of effective output power/ground pairs for each Virtex-E device and package combination. Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair Package Standard BGA, CS, FGA HQ PQ, TQ LVTTL Slow Slew Rate, 2 mA drive 68 49 36 LVTTL Slow Slew Rate, 4 mA drive 41 31 20 LVTTL Slow Slew Rate, 6 mA drive 29 22 15 LVTTL Slow Slew Rate, 8 mA drive 22 17 12 LVTTL Slow Slew Rate, 12 mA drive 17 12 9 LVTTL Slow Slew Rate, 16 mA drive 14 10 7 LVTTL Slow Slew Rate, 24 mA drive 9 7 5 LVTTL Fast Slew Rate, 2 mA drive 40 29 21 LVTTL Fast Slew Rate, 4 mA drive 24 18 12 LVTTL Fast Slew Rate, 6 mA drive 17 13 9 LVTTL Fast Slew Rate, 8 mA drive 13 10 7 LVTTL Fast Slew Rate, 12 mA drive 10 7 5 LVTTL Fast Slew Rate, 16 mA drive 8 6 4 LVTTL Fast Slew Rate, 24 mA drive 5 4 3 LVCMOS2 10 7 5 PCI 8 6 4 GTL 4 4 4 GTL+ 4 4 4 Module 2 of 4 38 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair (Continued) Package Standard BGA, CS, FGA HQ PQ, TQ HSTL Class I 18 13 9 HSTL Class III 9 7 5 HSTL Class IV 5 4 3 SSTL2 Class I 15 11 8 SSTL2 Class II 10 7 5 SSTL3 Class I 11 8 6 SSTL3 Class II 7 5 4 CTT 14 10 7 AGP 9 7 5 Note: This analysis assumes a 35 pF load for each output. Table 22: Virtex-E Equivalent Power/Ground Pairs Pkg/Part XCV100E XCV200E CS144 12 12 PQ240 20 20 XCV300E XCV400E 20 20 HQ240 BG352 20 32 BG432 32 20 FG456 FG676 XCV1000E XCV1600E XCV2000E 20 20 56 58 60 56 56 56 58 60 64 32 BG560 FG256(1) XCV600E 24 24 40 40 40 40 40 40 54 56 FG680(2) 46 FG860 FG900 56 FG1156 58 96 60 104 120 Notes: 1. Virtex-E devices in FG256 packages have more VCCO than Virtex series devices. 2. FG680 numbers are preliminary. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 39 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Application Examples GTL+ Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termination techniques required for each I/O standard. A sample circuit illustrating a valid termination technique for GTL+ appears in Figure 45. DC voltage specifications appear in Table 24. GTL+ VTT = 1.5V VTT = 1.5V This section describes some common application examples illustrating the termination techniques recommended by each of the standards supported by the SelectI/O features. 50 VCCO = N/A Termination Examples GTL A sample circuit illustrating a valid termination technique for GTL is shown in Figure 44. GTL Z = 50 VREF = 1.0V Circuit examples involving typical termination techniques for each of the SelectI/O standards follow. For a full range of accepted values for the DC voltage specifications for each standard, refer to the table associated with each figure. The resistors used in each termination technique example and the transmission lines depicted represent board level components and are not meant to represent components on the device. 50 x133_09_012400 Figure 45: Terminated GTL+ Table 24: GTL+ Voltage Specifications Parameter Min Typ Max - - - 0.88 1.0 1.12 VTT 1.35 1.5 1.65 VIH = VREF + 0.1 0.98 1.1 - VIL = VREF - 0.1 - 0.9 1.02 VCCO VREF = N VTT 1 VTT = 1.2V VTT = 1.2V VOH - - - 50 50 VOL 0.3 0.45 0.6 - - - IOLat VOL (mA) at 0.6V 36 - - IOLat VOL (mA) at 0.3V - - 48 VCCO = N/A IOH at VOH (mA) Z = 50 VREF = 0.8V x133_08_111699 Figure 44: Terminated GTL Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. Table 23 lists DC voltage specifications. Table 23: GTL Voltage Specifications Parameter Min Typ Max - N/A - VREF = N VTT1 0.74 0.8 0.86 VTT 1.14 1.2 1.26 VIH = VREF + 0.05 0.79 0.85 - VIL = VREF - 0.05 - 0.75 0.81 VOH - - - VOL - 0.2 0.4 IOH at VOH(mA) - - - IOLat VOL(mA) at 0.4V 32 - - IOLat VOL(mA) at 0.2V - - 40 VCCO Notes: 1. N must be greater than or equal to 0.653 and less than or equal to 0.68. Module 2 of 4 40 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays HSTL HSTL Class III A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. 50 Z = 50 Table 25: HSTL Class I Voltage Specification Parameter VTT= 1.5V VCCO = 1.5V VREF = 0.9V Min Typ Max VCCO 1.40 1.50 1.60 VREF 0.68 0.75 0.90 VTT - VCCO 0.5 - A sample circuit illustrating a valid termination technique for HSTL_IV appears in Figure 48. VIH VREF + 0.1 - - Table 27: HSTL Class IV Voltage Specification VIL - - VREF - 0.1 VOH VCCO - 0.4 - 0.4 x133_11_111699 VOL Figure 47: Terminated HSTL Class III Parameter Min Typ Max VCCO 1.40 1.50 1.60 VREF - 0.90 - IOH at VOH (mA) -8 - - VTT - VCCO - IOLat VOL (mA) 8 - - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VTT= 0.75V VOL - - 0.4 50 IOH at VOH (mA) -8 - - IOLat VOL (mA) 48 - - HSTL Class I VCCO = 1.5V Z = 50 VREF = 0.75V Note: Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user. x133_10_111699 Figure 46: Terminated HSTL Class I Table 26: HSTL Class III Voltage Specification Parameter HSTL Class IV Min Typ Max 1.40 1.50 1.60 VREF (1) - 0.90 - VTT - VCCO - VIH VREF + 0.1 - - VIL - - VREF - 0.1 VOH VCCO - 0.4 - - VOL - - 0.4 IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - VCCO VCCO = 1.5V VTT= 1.5V VTT= 1.5V 50 50 Z = 50 VREF = 0.9V x133_12_111699 Figure 48: Terminated HSTL Class IV Note: Per EIA/JESD8-6, "The value of VREF is to be selected by the user to provide optimum noise margin in the use conditions specified by the user." DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 41 R VirtexTM-E 1.8 V Field Programmable Gate Arrays SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class I VTT= 1.5V VCCO = 3.3V 50 25 Z = 50 VREF = 1.5V Table 29: SSTL3_II Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF = 0.45 VCCO 1.3 1.5 1.7 VTT = VREF 1.3 1.5 1.7 VIH = VREF + 0.2 1.5 1.7 3.9(1) VIL= VREF - 0.2 -0.3(2) 1.3 1.5 VOH = VREF + 0.8 2.1 - - VOL= VREF - 0.8 - - 0.9 IOH at VOH (mA) -16 - - IOLat VOL (mA) 16 - - x133_13_111699 Figure 49: Terminated SSTL3 Class I Table 28: SSTL3_I Voltage Specifications Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF = 0.45 VCCO 1.3 1.5 1.7 VTT = VREF 1.3 1.5 1.7 VIH = VREF + 0.2 1.5 1.7 3.9(1) VIL = VREF - 0.2 -0.3(2) 1.3 1.5 VOH = VREF + 0.6 1.9 - - VOL = VREF - 0.6 - - 1.1 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula SSTL2_I A sample circuit illustrating a valid termination technique for SSTL2_I appears in Figure 51. DC voltage specifications appear in Table 30. SSTL2 Class I VTT= 1.25V VCCO = 2.5V 50 25 Z = 50 VREF = 1.25V Notes: 1. VIH maximum is VCCO + 0.3 2. VIL minimum does not conform to the formula xap133_15_011000 Figure 51: Terminated SSTL2 Class I SSTL3_II Table 30: SSTL2_I Voltage Specifications A sample circuit illustrating a valid termination technique for SSTL3_II appears in Figure 50. DC voltage specifications appear in Table 29. Parameter VCCO VREF = 0.5 VCCO 25 Typ Max 2.3 2.5 2.7 1.15 1.25 1.35 N(1) 1.11 1.25 1.39 VTT= 1.5V VTT= 1.5V VIH = VREF + 0.18 1.33 1.43 3.0(2) 50 VIL = VREF - 0.18 -0.3(3) 1.07 1.17 VOH = VREF + 0.61 1.76 - - VOL= VREF - 0.61 - - 0.74 IOH at VOH (mA) -7.6 - - IOLat VOL (mA) 7.6 - - VTT = VREF + SSTL3 Class II VCCO = 3.3V Min 50 Z = 50 VREF = 1.5V x133_14_111699 Figure 50: Terminated SSTL3 Class II Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. Module 2 of 4 42 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class II VCCO = 2.5V 25 VTT= 1.25V VTT= 1.25V 50 50 Z = 50 VREF = 1.25V x133_16_111699 Figure 52: Terminated SSTL2 Class II Table 31: SSTL2_II Voltage Specifications Parameter VCCO VREF = 0.5 VCCO Min Typ Max 2.3 2.5 2.7 Table 32: CTT Voltage Specifications Parameter Min Typ Max VCCO 2.05(1) 3.3 3.6 VREF 1.35 1.5 1.65 VTT 1.35 1.5 1.65 VIH = VREF + 0.2 1.55 1.7 - VIL = VREF - 0.2 - 1.3 1.45 VOH = VREF + 0.4 1.75 1.9 - VOL= VREF - 0.4 - 1.1 1.25 IOH at VOH (mA) -8 - - IOLat VOL (mA) 8 - - Notes: 1. Timing delays are calculated based on VCCO min of 3.0V. 1.15 1.25 1.35 N(1) 1.11 1.25 1.39 PCI33_3 & PCI66_3 VIH = VREF + 0.18 1.33 1.43 3.0(2) VIL = VREF - 0.18 -0.3(3) PCI33_3 or PCI66_3 require no termination. DC voltage specifications appear in Table 33. 1.07 1.17 VOH = VREF + 0.8 1.95 - - VOL = VREF - 0.8 - - 0.55 IOH at VOH (mA) -15.2 - - IOLat VOL (mA) 15.2 - - VTT = VREF + Table 33: PCI33_3 and PCI66_3 Voltage Specifications Min Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH = 0.5 VCCO 1.5 1.65 VCCO + 0.5 VIL = 0.3 VCCO -0.5 0.99 1.08 VOH = 0.9 VCCO 2.7 - - CTT VOL= 0.1 VCCO - - 0.36 A sample circuit illustrating a valid termination technique for CTT appear in Figure 53. DC voltage specifications appear in Table 32. IOH at VOH (mA) Note 1 - - IOLat VOL (mA) Note 1 - - Notes: 1. N must be greater than or equal to -0.04 and less than or equal to 0.04. 2. VIH maximum is VCCO + 0.3. 3. VIL minimum does not conform to the formula. Parameter Notes: 1. Tested according to the relevant specification. CTT VCCO = 3.3V VTT = 1.5V 50 Z = 50 VREF= 1.5V x133_17_111699 Figure 53: Terminated CTT DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 43 R VirtexTM-E 1.8 V Field Programmable Gate Arrays LVTTL LVCMOS18 LVTTL requires no termination. DC voltage specifications appears in Table 34. LVCMOS18 does not require termination. Table 36 lists DC voltage specifications. Table 34: LVTTL Voltage Specifications Table 36: LVCMOS18 Voltage Specifications Min Typ Max VCCO 1.70 1.80 1.90 - VREF - - - - - VTT - - - 2.0 - 3.6 VIH 0.7 x VCCO - 1.95 VIL -0.5 - 0.8 VIL - 0.5 - 0.2 x VCCO VOH 2.4 - - VOH VCCO - 0.4 - - VOL - - 0.4 VOL - - 0.4 IOH at VOH (mA) -24 - - IOH at VOH (mA) -8 - - IOLat VOL (mA) 24 - - IOLat VOL (mA) 8 - - Parameter Min Typ Max VCCO 3.0 3.3 3.6 VREF - - VTT - VIH Notes: 1. Note: VOLand VOH for lower drive currents sample tested. LVCMOS2 LVCMOS2 requires no termination. DC voltage specifications appear in Table 35. Parameter AGP-2X The specification for the AGP-2X standard does not document a recommended termination technique. DC voltage specifications appear in Table 37. Table 37: AGP-2X Voltage Specifications Parameter Table 35: LVCMOS2 Voltage Specifications Parameter Min Typ Max VCCO VREF = N VCCO (1) Min Typ Max 3.0 3.3 3.6 1.17 1.32 1.48 - - - VCCO 2.3 2.5 2.7 VREF - - - VTT VTT - - - VIH = VREF + 0.2 1.37 1.52 - VIH 1.7 - 3.6 VIL = VREF - 0.2 - 1.12 1.28 VIL -0.5 - 0.7 VOH = 0.9 VCCO 2.7 3.0 - VOH 1.9 - - VOL = 0.1 VCCO - 0.33 0.36 VOL - - 0.4 IOH at VOH (mA) Note 2 - - IOH at VOH (mA) -12 - - IOLat VOL (mA) Note 2 - - IOLat VOL (mA) 12 - - Module 2 of 4 44 Notes: 1. N must be greater than or equal to 0.39 and less than or equal to 0.41. 2. Tested according to the relevant specification. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays LVDS LVPECL Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrating a valid termination technique for transmitting LVDS signals appears in Figure 54. A sample circuit illustrating a valid termination for receiving LVDS signals appears in Figure 55. Table 38 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40. Depending on whether the device is transmitting or receiving an LVPECL signal, two different circuits are used for LVPECL termination. A sample circuit illustrating a valid termination technique for transmitting LVPECL signals appears in Figure 56. A sample circuit illustrating a valid termination for receiving LVPECL signals appears in Figure 57. Table 39 lists DC voltage specifications. Further information on the specific termination resistor packs shown can be found on Table 40. Table 39: LVPECL Voltage Specifications 1/4 of Bourns Part Number CAT16-LV4F12 Virtex-E FPGA Q 2.5V RS Parameter Z0 = 50 to LVDS Receiver 165 DATA Transmit RS Q RDIV 140 Z0 = 50 to LVDS Receiver 165 VCCO = 2.5V LVDS Output x133_19_122799 Figure 54: Transmitting LVDS Signal Circuit Q Z0 = 50 from LVDS Driver VIRTEX-E FPGA LVDS_IN Z0 = 50 Q DATA Receive - Typ Max VCCO 3.0 3.3 3.6 VREF - - - VTT - - - VIH 1.49 - 2.72 VIL 0.86 - 2.125 VOH 1.8 - - VOL - - 1.57 Notes: 1. For more detailed information, see LVPECL DC Specifications + RT 100 Min 1/4 of Bourns Part Number CAT16-PC4F12 LVDS_IN Virtex-E FPGA Q x133_29_122799 3.3V Figure 55: Receiving LVDS Signal Circuit DATA Transmit RS Table 38: LVDS Voltage Specifications Parameter VCCO VICM (2) VOCM (1) VIDIFF (1) VODIFF VOH (1) VOL(1) (1) Min Typ RS Z0 = 50 LVPECL_OUT to LVPECL Receiver 100 Q RDIV 187 Z0 = 50 100 to LVPECL Receiver LVPECL_OUT Max 2.375 2.5 2.625 0.2 1.25 2.2 1.125 1.25 1.375 0.1 0.35 - 0.25 0.35 0.45 1.25 - - - - 1.25 x133_20_122799 Figure 56: Transmitting LVPECL Signal Circuit Q VIRTEX-E FPGA Z0 = 50 LVPECL_IN + from LVPECL Driver RT 100 Z0 = 50 Q - DATA Receive LVPECL_IN x133_21_122799 Figure 57: Receiving LVPECL Signal Circuit Notes: 1. Measured with a 100 W resistor across Q and Q. 2. Measured with a differential input voltage = +/- 350 mV. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 45 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Termination Resistor Packs Creating LVDS Global Clock Input Buffers Resistor packs are available with the values and the configuration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at http://www.bourns.com. Global clock input buffers can be combined with adjacent IOBs to form LVDS clock input buffers. P-side is the GCLKPAD location; N-side is the adjacent IO_LVDS_DLL site. Table 41: Global Clock Input Buffer Pair Locations Table 40: Bourns LVDS/LVPECL Resistor Packs I/O Standard Term. for: Pairs/ Pack Pins CAT16-LV2F6 LVDS Driver 2 8 CAT16-LV4F12 LVDS Driver 4 16 CAT16-PC2F6 LVPECL Driver 2 8 CAT16-PC4F12 LVPECL Driver 4 16 CAT16-PT2F2 LVDS/LVPECL Receiver 2 8 CAT16-PT4F4 LVDS/LVPECL Receiver 4 16 Part Number LVDS Design Guide The SelectI/O library elements have been expanded for Virtex-E devices to include new LVDS variants. At this time all of the cells might not be included in the Synthesis libraries. The 2.1i-Service Pack 2 update for Alliance and Foundation software includes these cells in the VHDL and Verilog libraries. It is necessary to combine these cells to create the P-side (positive) and N-side (negative) as described in the input, output, 3-state and bidirectional sections. IBUF_LVDS I O OBUF_LVDS I O IOBUF_LVDS T I IBUFG_LVDS I O OBUFT_LVDS T I IO O O x133_22_122299 Figure 58: LVDS elements GCLK 3 GCLK 2 GCLK 1 GCLK 0 Pkg P N P N P N P N CS144 A6 C6 A7 B7 M7 M6 K7 N8 PQ240 P213 P215 P210 P209 P89 P87 P92 P93 HQ240 P213 P215 P210 P209 P89 P87 P92 P93 BG352 D14 A15 B14 A13 AF14 AD14 AE13 AC13 BG432 D17 C17 A16 B16 AK16 AL17 AL16 AH15 BG560 A17 C18 D17 E17 AJ17 AM18 AL17 AM17 FG256 B8 A7 C9 A8 R8 T8 N8 N9 FG456 C11 B11 A11 D11 Yll AA11 W12 U12 FG676 E13 B13 C13 F14 AB13 AF13 AA14 AC14 FG680 A20 C22 D21 A19 AU22 AT22 AW19 AT21 FG860 C22 A22 B22 D22 AY22 AW21 BA22 AW20 FG900 C15 A15 E15 E16 AK16 AH16 AJ16 AF16 FG1156 E17 C17 D17 J18 Al19 AL17 AH18 AM18 HDL Instantiation Only one global clock input buffer is required to be instantiated in the design and placed on the correct GCLKPAD location. The N-side of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire to the differential input buffer located in the GCLKIOB. The output of this buffer then drives the output of the GCLKIOB cell. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation gclk0_p : IBUFG_LVDS port map (I=>clk_external, O=>clk_internal); Verilog Instantiation IBUFG_LVDS gclk0_p (.I(clk_external), .O(clk_internal)); Location constraints All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. NET clk_external LOC = GCLKPAD3; GCLKPAD3 can also be replaced with the package pin name such as D17 for the BG432 package. Module 2 of 4 46 www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Verilog Instantiation Optional N-side Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side IBUFG connection has a net connected to it. Since the N-side IBUFG does not have a connection in the EDIF net list, it is trimmed from the design in MAP. IBUF_LVDS data0_p (.I(data[0]), .O(data_int[0])); Location Constraints All LVDS buffers must be explicitly placed on a device. For the input buffers this can be done with the following constraint in the .ucf or .ncf file. NET data<0> LOC = D28; # IO_L0P VHDL Instantiation gclk0_p : IBUFG_LVDS port map (I=>clk_p_external, O=>clk_internal); gclk0_n : IBUFG_LVDS port map (I=>clk_n_external, O=>clk_internal); Verilog Instantiation IBUFG_LVDS gclk0_p (.I(clk_p_external), .O(clk_internal)); IBUFG_LVDS gclk0_n (.I(clk_n_external), .O(clk_internal)); Location Constraints All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. Optional N-side Some designers might prefer to also instantiate the N-side buffer for the input buffer. This allows the top-level net list to include net connections for both PCB layout and system-level integration. In this case, only the output P-side IBUF connection has a net connected to it. Since the N-side IBUF does not have a connection in the EDIF net list, it is trimmed from the design in MAP. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data_p(0), O=>data_int(0)); data0_n : IBUF_LVDS port map (I=>data_n(0), O=>open); Verilog Instantiation IBUF_LVDS data0_p (.I(data_p[0]), .O(data_int[0])); NET clk_p_external LOC = GCLKPAD3; NET clk_n_external LOC = C17; IBUF_LVDS data0_n (.I(data_n[0]), .O()); GCLKPAD3 can also be replaced with the package pin name, such as D17 for the BG432 package. Location Constraints Creating LVDS Input Buffers All LVDS buffers must be explicitly placed on a device. For the global clock input buffers this can be done with the following constraint in the .ucf or .ncf file. An LVDS input buffer can be placed in a wide number of IOB locations. The exact location is dependent on the package that is used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side where # is the pair number. HDL Instantiation Only one input buffer is required to be instantiated in the design and placed on the correct IO_L#P location. The N-side of the buffer is reserved and no other IOB is allowed to be placed on this location. In the physical device, a configuration option is enabled that routes the pad wire from the IO_L#N IOB to the differential input buffer located in the IO_L#P IOB. The output of this buffer then drives the output of the IO_L#P cell or the input register in the IO_L#P IOB. In EPIC it appears that the second buffer is unused. Any attempt to use this location for another purpose leads to a DRC error in the software. VHDL Instantiation data0_p : IBUF_LVDS port map (I=>data(0), O=>data_int(0)); DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N Adding an Input Register All LVDS buffers can have an input register in the IOB. The input register is in the P-side IOB only. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries available to explicitly create these structures. The input library macros are listed in Table 42. The I and IB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 Module 2 of 4 47 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Verilog Instantiation Table 42: Input Library Macros Name OBUF_LVDS data0_p .O(data_p[0])); (.I(data_int[0]), Inputs Outputs I, IB, C Q IBUFDS_FDE_LVDS I, IB, CE, C Q IBUFDS_FDC_LVDS I, IB, C, CLR Q I, IB, CE, C, CLR Q I, IB, C, PRE Q I, IB, CE, C, PRE Q I, IB, C, R Q I, IB, CE, C, R Q NET data_p<0> LOC = D28; # IO_L0P I, IB, C, S Q NET data_n<0> LOC = B29; # IO_L0N I, IB, CE, C, S Q Synchronous vs. Asynchronous Outputs I, IB, G Q IBUFDS_LDE_LVDS I, IB, GE, G Q IBUFDS_LDC_LVDS I, IB, G, CLR Q I, IB, GE, G, CLR Q If the outputs are synchronous (registered in the IOB) then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or COLUMN in the device. I, IB, G, PRE Q I, IB, GE, G, PRE Q IBUFDS_FD_LVDS IBUFDS_FDCE_LVDS IBUFDS_FDP_LVDS IBUFDS_FDPE_LVDS IBUFDS_FDR_LVDS IBUFDS_FDRE_LVDS IBUFDS_FDS_LVDS IBUFDS_FDSE_LVDS IBUFDS_LD_LVDS IBUFDS_LDCE_LVDS IBUFDS_LDP_LVDS IBUFDS_LDPE_LVDS INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUF_LVDS data0_n .O(data_n[0])); Location Constraints All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. Creating LVDS Output Buffers LVDS output buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both output buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). Failure to follow these rules leads to DRC errors in software. data0_p : OBUF_LVDS port map (I=>data_int(0), O=>data_p(0)); port map O=>data_n_int(0)); data0_n : OBUF_LVDS port map (I=>data_n_int(0), O=>data_n(0)); Module 2 of 4 48 The LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous-capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at some point in the product lifetime, then only the common pairs for all packages should be used. Adding an Output Register All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The clock pin (C), clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. VHDL Instantiation data0_inv: INV (I=>data_int(0), (.I(data_n_int[0]), To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The output library macros are listed in Table 43. The O and OB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays VHDL Instantiation Table 43: Output Library Macros Name data0_p: OBUFT_LVDS port map (I=>data_int(0), T=>data_tri, O=>data_p(0)); Inputs Outputs D, C O, OB OBUFDS_FDE_LVDS DD, CE, C O, OB OBUFDS_FDC_LVDS D, C, CLR O, OB D, CE, C, CLR O, OB D, C, PRE O, OB D, CE, C, PRE O, OB D, C, R O, OB D, CE, C, R O, OB D, C, S O, OB D, CE, C, S O, OB D, G O, OB OBUFDS_LDE_LVDS D, GE, G O, OB OBUFDS_LDC_LVDS D, G, CLR O, OB D, GE, G, CLR O, OB D, G, PRE O, OB Synchronous vs. Asynchronous 3-State Outputs D, GE, G, PRE O, OB If the outputs are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the outputs are asynchronous (no output register), then they must use one of the pairs that are part of the same IOB group at the end of a ROW or COLUMN in the device. This applies for either the 3-state pin or the data out pin. OBUFDS_FD_LVDS OBUFDS_FDCE_LVDS OBUFDS_FDP_LVDS OBUFDS_FDPE_LVDS OBUFDS_FDR_LVDS OBUFDS_FDRE_LVDS OBUFDS_FDS_LVDS OBUFDS_FDSE_LVDS OBUFDS_LD_LVDS OBUFDS_LDCE_LVDS OBUFDS_LDP_LVDS OBUFDS_LDPE_LVDS Creating LVDS Output 3-State Buffers LVDS output 3-state buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both output 3-state buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one High and one Low). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software. data0_inv: INV port map (I=>data_int(0), O=>data_n_int(0)); data0_n: OBUFT_LVDS port map (I=>data_n_int(0), T=>data_tri, O=>data_n(0)); Verilog Instantiation OBUFT_LVDS data0_p (.I(data_int[0]), .T(data_tri), .O(data_p[0])); INV data0_inv (.I(data_int[0], .O(data_n_int[0]); OBUFT_LVDS data0_n (.I(data_n_int[0]), .T(data_tri), .O(data_n[0])); Location Constraints All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N LVDS pairs that can be used as asynchronous outputs are listed in the Virtex-E pinout tables. Some pairs are marked as "asynchronous capable" for all devices in that package, and others are marked as available only for that device in the package. If the device size might be changed at some point in the product lifetime, then only the common pairs for all packages should be used. Adding Output and 3-State Registers All LVDS buffers can have an output register in the IOB. The output registers must be in both the P-side and N-side IOBs. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE) and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 49 R VirtexTM-E 1.8 V Field Programmable Gate Arrays The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The input library macros are listed below. The 3-state is configured to be 3-stated at GSR and when the PRE,CLR,S or R is asserted and shares it's clock enable with the output register. If this is not desirable then the library can be updated by the user for the desired functionality. The O and OB inputs to the macros are the external net connections. Creating a LVDS Bidirectional Buffer LVDS bidirectional buffers can be placed in a wide number of IOB locations. The exact locations are dependent on the package used. The Virtex-E package information lists the possible locations as IO_L#P for the P-side and IO_L#N for the N-side, where # is the pair number. HDL Instantiation Both bidirectional buffers are required to be instantiated in the design and placed on the correct IO_L#P and IO_L#N locations. The IOB must have the same net source the following pins, clock (C), set/reset (SR), 3-state (T), 3-state clock enable (TCE), output (O), output clock enable (OCE). In addition, the output (O) pins must be inverted with respect to each other, and if output registers are used, the INIT states must be opposite values (one HIGH and one LOW). If 3-state registers are used, they must be initialized to the same state. Failure to follow these rules leads to DRC errors in the software. VHDL Instantiation data0_p: IOBUF_LVDS port map (I=>data_out(0), T=>data_tri, IO=>data_p(0), O=>data_int(0)); data0_inv: INV (I=>data_out(0), port map O=>data_n_out(0)); data0_n : IOBUF_LVDS port map (I=>data_n_out(0), T=>data_tri, IO=>data_n(0), O=>open); Verilog Instantiation IOBUF_LVDS data0_p(.I(data_out[0]), .T(data_tri), .IO(data_p[0]), .O(data_int[0]); INV data0_inv (.I(data_out[0], .O(data_n_out[0]); IOBUF_LVDS data0_n(.I(data_n_out[0]),.T(data_tri),. IO(data_n[0]).O()); Module 2 of 4 50 Location Constraints All LVDS buffers must be explicitly placed on a device. For the output buffers this can be done with the following constraint in the .ucf or .ncf file. NET data_p<0> LOC = D28; # IO_L0P NET data_n<0> LOC = B29; # IO_L0N Synchronous vs. Asynchronous Bidirectional Buffers If the output side of the bidirectional buffers are synchronous (registered in the IOB), then any IO_L#P|N pair can be used. If the output side of the bidirectional buffers are asynchronous (no output register), then they must use one of the pairs that is a part of the asynchronous LVDS IOB group. This applies for either the 3-state pin or the data out pin. The LVDS pairs that can be used as asynchronous bidirectional buffers are listed in the Virtex-E pinout tables. Some pairs are marked as asynchronous capable for all devices in that package, and others are marked as available only for that device in the package. If the device size might change at some point in the product's lifetime, then only the common pairs for all packages should be used. Adding Output and 3-State Registers All LVDS buffers can have an output and input registers in the IOB. The output registers must be in both the P-side and N-side IOBs, the input register is only in the P-side. All the normal IOB register options are available (FD, FDE, FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE, LDC, LDCE, LDP, LDPE). The register elements can be inferred or explicitly instantiated in the HDL code. Special care must be taken to insure that the D pins of the registers are inverted and that the INIT states of the registers are opposite. The 3-state (T), 3-state clock enable (CE), clock pin (C), output clock enable (CE), and set/reset (CLR/PRE or S/R) pins must connect to the same source. Failure to do this leads to a DRC error in the software. The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the "map -pr [i|o|b]" where "i" is inputs only, "o" is outputs only and "b" is both inputs and outputs. To improve design coding times VHDL and Verilog synthesis macro libraries have been developed to explicitly create these structures. The bidirectional I/O library macros are listed in Table 44. The 3-state is configured to be 3-stated at GSR and when the PRE,CLR,S or R is asserted and shares its clock enable with the output and input register. If this is not desirable then the library can be updated be the user for the desired functionality. The I/O and IOB inputs to the macros are the external net connections. www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification R VirtexTM-E 1.8 V Field Programmable Gate Arrays Table 44: Bidirectional I/O Library Macros Name Inputs Bidirectional Outputs D, T, C IO, IOB Q IOBUFDS_FDE_LVDS D, T, CE, C IO, IOB Q IOBUFDS_FDC_LVDS D, T, C, CLR IO, IOB Q D, T, CE, C, CLR IO, IOB Q D, T, C, PRE IO, IOB Q D, T, CE, C, PRE IO, IOB Q D, T, C, R IO, IOB Q D, T, CE, C, R IO, IOB Q D, T, C, S IO, IOB Q D, T, CE, C, S IO, IOB Q D, T, G IO, IOB Q IOBUFDS_LDE_LVDS D, T, GE, G IO, IOB Q IOBUFDS_LDC_LVDS D, T, G, CLR IO, IOB Q D, T, GE, G, CLR IO, IOB Q D, T, G, PRE IO, IOB Q D, T, GE, G, PRE IO, IOB Q IOBUFDS_FD_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS IOBUFDS_LD_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for this document. Date Version Revision 12/7/99 1.0 Initial Xilinx release. 1/10/00 1.1 Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL, Select RAM and SelectI/O information. 1/28/00 1.2 Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54, & 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote references. 2/29/00 1.3 Updated pinout tables, VCC page 20, and corrected Figure 20. 5/23/00 1.4 Correction to table on p. 22. 7/10/00 1.5 * * * Numerous minor edits. Data sheet upgraded to Preliminary. Preview -8 numbers added to Virtex-E Electrical Characteristics tables. 8/1/00 1.6 * * Reformatted entire document to follow new style guidelines. Changed speed grade values in tables on pages 35-37. DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 Module 2 of 4 51 R VirtexTM-E 1.8 V Field Programmable Gate Arrays Date Version 9/20/00 1.7 Revision * * * * * * * 11/20/00 1.8 * * * * * 2/12/01 1.9 Min values added to Virtex-E Electrical Characteristics tables. XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics tables (Module 3). Corrected user I/O count for XCV100E device in Table 1 (Module 1). Changed several pins to "No Connect in the XCV100E" and removed duplicate VCCINT pins in Table ~ (Module 4). Changed pin J10 to "No connect in XCV600E" in Table 74 (Module 4). Changed pin J30 to "VREF option only in the XCV600E" in Table 74 (Module 4). Corrected pair 18 in Table 75 (Module 4) to be "AO in the XCV1000E, XCV1600E". Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to Preliminary. Updated minimums in Table 13 and added notes to Table 14. Added to note 2 to Absolute Maximum Ratings. Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF. * Changed all minimum hold times to -0.4 under Global Clock Set-Up and Hold for LVTTL Standard, with DLL. Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters. * Changed GCLK0 to BA22 for FG860 package in Table 46. * * * Revised footnote for Table 14. Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices. * * 4/02/01 2.0 * * Updated numerous values in Virtex-E Switching Characteristics tables. Converted data sheet to modularized format. See the Virtex-E Data Sheet section. 4/19/01 2.1 * Modified Figure 30 "DLL Generation of 4x Clock in Virtex-E Devices." 07/23/01 2.2 * * Made minor edits to text under Configuration. Added CLB column locations for XCV2600E anbd XCV3200E devices in Table 3. 11/09/01 2.3 * Added warning under Configuration section that attempting to load an incorrect bitstream causes configuration to fail and can damage the device. Virtex-E Data Sheet The Virtex-E Data Sheet contains the following modules: * DS022-1, Virtex-E 1.8V FPGAs: * Introduction and Ordering Information (Module 1) * DS022-2, Virtex-E 1.8V FPGAs: Functional Description (Module 2) Module 2 of 4 52 DS022-3, Virtex-E 1.8V FPGAs: DC and Switching Characteristics (Module 3) * DS022-4, Virtex-E 1.8V FPGAs: Pinout Tables (Module 4) www.xilinx.com 1-800-255-7778 DS022-2 (v2.3) November 9, 2001 Preliminary Product Specification