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August 2014

FSA880 / FSA881 • Rev. 1.0.7

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

FSA880 / FSA881 – USB Port 2:1 Switch with Accessory

and Charger Detection

Features

Switch Type 2:1 USB

Switch Mechanism Automatic switching with Available

Interrupt

Accessory Detection

USB Data Cable

Chargers (CDP , DCP, Travel Adapter,

Car Kit-CEA-936-A)

Factory-Mode Cables

USB FS and HS 2.0 Compliant

USB Charging Battery Charg ing 1.1 Compliant

Charger Detect, DCD, OVT (28 V)

UART RxD and TxD

VBAT 3.0 to 4.4 V

Programmability I

ESD 15kV IEC 61000-4-2 Air Gap

Operating

Temperature -40°C to 85°C

Package 16-Lead UMLP

1.8x2.6x0.55 mm, 0.4 mm Pitch

JIG Opt ion FSA880 – Active LOW

FSA881 – Active HIGH

Ordering Infor mat ion FSA880UMX

FSA881UMX

Description

The FSA88x is a high-performance switch featuring

automatic switching and accessory detection for a USB port.

The FSA88x allows sharing of a common USB port to pass

USB data, as well as factory programmability. In addition,

the FSA88x integrates accessory detection of devices such

as USB chargers and factory data cables. The FSA88x can

be programm ed for manual switching or automatic switching

of data paths. VBUS_IN has 28 V over-voltage tolerance.

The difference between the FSA880 and the FSA881 is that

FSA880 JIG output is an open-drain, active-LOW output,

while FSA881 JIG is an active-HIGH, C MOS output.

Applications

 Cellular Phones, Smart Phones

 MP3 and PMP

Related Resources

 FSA880 / FSA881 Demonstration Board

Typical Applica tion

Figure 1. Mobile Phone Example

FSA9280A

FSA88x

USB CHARGING

USB Data

FACTORY TES T

OVT

PROTECTION

FSA880 / FSA881 • Rev. 1.0.7 2

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Ordering Information

Part Number Operating Tempe rature Range Top Mark Package

FSA880UMX -40 to +85°C KU 16-Lead, Ultrathin Molded Leadless Package (UMLP),

1.8 mm x 2.6 mm x 0.55 mm, 0.4 mm Pitch

FSA881UMX -40 to +85°C KX 16-Lead, Ultrathin Molded Leadless Package (UMLP),

1.8 mm x 2.6 mm x 0.55 mm, 0.4 mm Pitch

Block Diagram

Figure 2. Block Diagram

Baseband

Processor

USB

INTB

I2C_SCL

I2C_SDA

DM_HOST1

DP_HOST1

HS USB

or UART

Interrupt

Float

Detect

Charger

Detect BC1. 1

Switch

Control

and

Slave

Detection

28V OVT

2:1

MUX

BAT

ADC ID

Detect

JIG

BOOT

100k

DDIO

Phone

Power

USB Port

BUS_IN

DM_CON

DP_CON

GND

ID_CON

FSA880

DM_HOST

DP_HOST

FSA880 / FSA881 • Rev. 1.0.7 3

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Pin Configuration

Figure 3. Pin Assignment (Through View)

5 6 7 8

112

16 15 14 13

ID_CON DP_CON DM_CON V

BUS_IN

GND

I2C_SDA

I2C_SCL

INTB

BAT

BOOT JIG V

DDIO

DM_HOST

DP_HOST

DM_HOST1

DP_HOST1

FSA880 / FSA881 • Rev. 1.0.7 4

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Pin Descriptions

Name Pin # Type Default

State Description

USB/UART Interface

DP_HOST 2 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the

resident USB / UAR T on the phone. Default port for all USB

accessories and USB factory modes.

DM_HOST 1 Signal Path Open D- signal switch path, dedicated USB port to be c onnected to the

resident USB / UART on the phone. Default port for all USB

accessories and USB factory modes.

VBUS_IN 13 Input N/A Input voltage supply pin to be connected to the VBUS pi n of the USB

connector

USB/UART Interface 1

DM_HOST1 3 Signal Path Open D- signal switch path, dedicated USB port to be c onnected to the

secondary resident USB / UART on the phone. Default port for UART

factory modes.

DP_HOST1 4 Signal Path Open D+ signal switch path, ded icated USB port to be connected to the

secondary resident USB / UART on the phone. Default port for UART

factory modes.

Connector Interface

GND 12 Ground N/A Ground

ID_CON 16 Signal Path Open Connected to the USB connector ID pin and used for detecting

accessories

DP_CON 15 Signal Path Open Connected to the USB connector D+ pin; depending on the signaling

mode, this pin can be switched to DP_HOST or RxD_HOST pins.

DM_CON 14 Signal Path Open Connected to the USB connector D- pin; depen ding on the signaling

mode, this pin can switched to DM_HOST or TxD_HOST pins.

Power Interface

VDDIO 8 Power N/A Input baseband interface I/O supply pin

VBAT 5 Power N/A Input voltage supply pin to be connected to the mobile phone battery

output or to an internal regulator on the phone

Factory Interface

JIG 7

FSA880:

Open-Drain

Output

FSA881:

CMOS

Output

FSA880:Hi-Z

FSA881:

LOW

Output control signal and used by the processor for factory test modes

FSA880: Active LOW open-drain output

FSA881: Active HIGH CMOS output

BOOT 6 CMOS

Output LOW Output control signal and used by the processor for factory test modes

I2C Interface

I2C_SCL 10 Input Hi-Z I2C serial clock signal to be connected to the phone-based I2C master

I2C_SDA 11 Open-Drain

I/O Hi-Z I2C serial data signal to be connect ed to the phone-based I2C master

INTB 9 CMOS

Output LOW Interrupt active LOW output used to prompt the phone baseband

processor to read the I2C register bits, i ndicate a change in ID_CON

pin status or accessories’ attach status

Note:

1. LOW = VOL or VIL; HIGH = VOH or VIH.

FSA880 / FSA881 • Rev. 1.0.7 5

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

1. Functionality

The FSA88x is USB port accessory detector and switch with

integrated 28 V over-voltage tolerance. Fully controlled using

I2C, FSA88x enables high-speed USB 2.0 Standard

Downstream Port (SDP), USB Charging Downstream Port

(CDP) battery charger, USB Dedicated Charging Port (DCP)

charger data cables to use a common connector micro or

mini USB 2.0 port. Factory-mode cables can be detected

and switched to use either the UART or USB data path. The

FSA88x can be programmed for manual switching or

automatic swit c hing of data paths.

The architecture uses ID pin detection for convenient factory

testing. Figure 9 - Figure 13 show the FSA88x passing the

USB eye compliance test w ith ampl e margi n.

1.1. Functional Overview

The FSA88x is designed for minimal software requirements

for proper operation. The flow diagram in Figure 4 walks

through the fundamental steps of operation and contains

reference s to more detailed information.

Flow Diagram State Datasheet

Section Description

Figure 4. Basic Operation Flow

Power-Up & Reset Section 2 Applies power to the device and resets state

of the device

I2C Section 3 Communication with device through I2C

Configuration Section 4 Configures the device using I2C and the

internal registers (which c an be bypassed

during power-up)

Detection Section 5 Manages accessory detection, including

attachment and detachment

Processor

Communication Section 6 How the detection of the accessory is

indicated to the processor

Switch

Configuration Section 7 Configuration of switches based on detection

Active Signal Section 8 Signal performance of selected configuration

Power-up &

Reset

Accessory

Plug-in

I2C

Detection

Processor

Communication

Switch

Configuration

Active Signals

Accessory

Detached

Configuration

FSA880 / FSA881 • Rev. 1.0.7 6

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

2. Power-Up & Reset

The FSA88x does not need special power sequencing for

correct operation. The main power is provided by VBAT only.

VDDIO is only used for I2C interface and interr upt pr oc es sing.

Table 1 summarizes the enabled features of each power

state. The valid voltages levels for each power supply can be

found in Section 9.

Table 1. Power States Summary

Notes:

1. VDDIO is expected to be the same supply used by the baseband I/Os.

2. Typically VDDIO is only present when VBAT is valid.

3. X = Don’t care.

2.1. Reset

When the device is reset, all the registers are initialized to

the default values shown in Section 9.9 and all switch paths

are open. After reset or power up, FSA88x enters Standby

Mode and is ready to detect accessories sensed on its

VBUS_IN and / or ID_CON pins.

2.1.1. Hardware Reset

Power-on reset is caused by the initial rising edge of VBAT

2.1.2. Software Reset

The device can be reset through software by writing to the

Reset bit in the Register (1BH).

Valid

VBUS_IN Valid VBAT Valid

VDDIO(1) Power State

Enabled Functionality

Processor

Communication

(I2C & Interr u p ts) Detection

X N N Power Down NO

X N Y(2) Not Typical Illegal State

X Y N Powered from VBAT NO YES

X Y Y Powered from VBAT YES YES

FSA880 / FSA881 • Rev. 1.0.7 7

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

3. I2C

The FSA88x integrates a full fast-mode I2C slave controller

compliant with the I2C s pecification version 2.1. The FSA88x

I2C interface runs up to 400 kHz.

The slave address is shown in Table 2. Status information

and configuration occurs via the I2C interface. Please see

Table 7 for more information.

Table 2. I2C Slave Address

Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Slave Address 8 0 1 0 0 1 0 1 Read / Write

8bits

Slave

Address

Address K

Write

Data

Write

Data

K+1

Write

Data

K+2

Write Data

K+N-1

Note:

Single-byte write is initiated by Master with P immediately fol lowing first data byte.

Figure 5. I2C Write Sequence

Figure 6. I2C Read Sequence

4. Configuration

FSA88x requires minimal configuration for proper detection

and reporting. The following steps provide full configuration.

1. Write Control register (02h) to configure manual or

automatic switching modes.

a. If using manual switching modes, write Manual SW

1 register (13h) to configure switches.

2. Write Control register (02h) to clear INT Mask bit.

This enables interrupts to the baseband.

SWR A A S RD A A A NA P

Note:

8bits

If Register is not specified Master will begin read from current register. In this case only sequence showing in Red

bracket is needed

Single or multi byte read executed from current register location (Single Byte read is

initiated by Master with NA immediately following first data byte)

Read Data K+1

Read Data K+N-1

8bits

Slave Address

Read Data K

Slave Address

From Master to Slave SStart Condition NA NOT Acknowledge (SDA High) RD Read =1

From Slave to Master AAcknowledge (SDA Low) WR Write=0 P

Stop Condition

FSA880 / FSA881 • Rev. 1.0.7 8

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

5. Detection

The FSA88x monitors both VBUS_IN and ID_CON to detect

accessories . The ID_CON detection is a “resistive detection”

that reads the resistance to GND on the ID_CON pin to

determine the accessory attached. Table 3 shows the

assignment of accessories based on resistor values.

FSA88x can also detect accessories with ID resistances

outside the specified ranges. The FSA88x detects these

unknown accessories in the same manner as the defined

accessories and interrupts the baseband processor and

provides the c orrect ADC value, as shown in Table 3.

Table 3. ID_CON Accessory Detection

ADC Code Equivalent RID Description

4 3 2 1 0 Min. Target Max.

1 0 1 0 1 117.4 kΩ 121 kΩ 124.6 kΩ Unknown Accessory

1 0 1 1 0 145.5 kΩ 150 kΩ 154.5 kΩ Unknown Accessory

1 0 1 1 1 176.4 kΩ 200 kΩ(4) 206 kΩ Travel Adapter (TA) or Car Kit T y pe 1 Charger

1 1 0 0 0 247.3 kΩ 255 kΩ 262.7 kΩ Factory Mode Boot OFF-USB

1 1 0 0 1 291.9 kΩ 301 kΩ 310.1 kΩ Factory Mode Boot ON-USB

1 1 0 1 0 354 kΩ 365 kΩ 375.9 kΩ Unknown Accessory

1 1 0 1 1 428.7 kΩ 442 kΩ

(4)

455.3 kΩ Unknown Accessory

1 1 1 0 0 507.3 kΩ 523 kΩ 538.7 kΩ Factory Mode Boot OFF-UART

1 1 1 0 1 600.4 kΩ 619 kΩ 637.6 kΩ Factory Mode Boot ON-UART

1 1 1 1 0 750 kΩ 1000 kΩ 1030 kΩ Unknown Accessory

Not ‘h1F or any code above 3 MΩ None of the above ranges Unknown Accessory

Note:

4. These accessories need VBUS to be valid in order to be detected since they are charger accessories.

5.1. Factory Cable Detection

Factory modes are initiated with the attachment of special

test hardware, called a “JIG box” for factory testing. The

FSA88x automatically configures switch paths to any of the

factory-mode accessories when the appropriate resistor is

sensed on the ID_CON pin. A change of resistor on the

ID_CON pin dynamically switches between factory modes

and auto-configures the appropriate switch paths without

detaching and attaching the c able.

The different factory mode accessories with the associated

resistor values (1% standard resistors) on the ID_CON pin

and the JIG and BOOT logic states are listed in Table 4. The

FSA88x allows both HS USB and FS USB in addition to

UART signals to be passed on both ports with matched

performance. This allows greater flexibility when designing

with the FSA88x.

JIG output signals when a factory mode accessory is plugged

in and BOOT output signals the mobile phone to boot up. The

switch paths for factor y modes are shown in Table 4.

Table 4. ID_ CON Factory Cable Detecti o n

Configura tion Type DP_CON DM_CON ID_CON BOOT FSA880

JIG FSA881

JIG

Factory Mode

Jig: UART Boot_On DP_HOST1 DM_HOST1 600kΩ 619kΩ 637kΩ HIGH LOW HIGH

Boot_Off DP_HOST1 DM_HOST1 507kΩ 523kΩ 538kΩ LOW LOW HIGH

Factory Mode

Jig: USB Boot_On DP_Host DM_Host 292kΩ 301kΩ 310kΩ HIGH LOW HIGH

Boot_Off DP_Host DM_Host 247kΩ 255kΩ 262kΩ LOW LOW HIGH

The FSA88x detection algorithms monitor both the VBUS and

ID pins of the USB interface. Based on the detec tion results,

multiple registers are updated and the INTB pin is asserted

to indicate to the baseband processor that an accessory was

detected and to read the registers for the complete

information. The detection algorithm allows the application to

control the timing of the detection algorithm and the

configuration of the internal switches. The flow diagram in

Figure 7 shows the operatio n of the det ect ion algor ith m.

FSA880 / FSA881 • Rev. 1.0.7 9

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Figure 7. Factory Cable Detection Flow Chart (FSA880)

Factory JIG Box

Attached

FSA880 Detects

Attachment

INTB Asserted and

Switch Paths Auto-

Configured

FSA880 Writes

Device Register

and Asserts JIG

FSA880 Enters

Standby

µP Reads Interrupt

Registers

ID Change?

Rid=Factory

Mode

YES

ID Float >70ms

Exit Factory Mode

Accessory Flow

YES

VDDIO

HIGH?

YES

FSA880 / FSA881 • Rev. 1.0.7 10

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

5.2. USB Port Detection

The multiple types of USB 2.0 ports the FSA88x can detect are summarized in Table 5.

Table 5. ID_CON and VBUS Detection Table for USB Devices

VBUS_IN DP_CON DM_CON ID_CON resistance to GND Accessory Detected(5)

Min. Typ. Max.

5V Not Checked Not Checked 174.6 kΩ 200 kΩ 206 kΩ TA (travel adapter) Charger (180 kΩ) and

Car Kit Charger Type 1 only (200 kΩ)(6)

5V Shorted to

DM_CON Shorted to

DP_CON 3 MΩ Open Open USB Dedicated Charging Port, Travel

Adapter or Dedicated Charger (DCP)(6)

5V DP_HOST DM_HOST 3 MΩ Open Open USB Charging Downstream Port (CDP)(6)

5V DP_HOST DM_HOST 3 MΩ Open Open USB Standard Downstream Port (SDP)

(6)

Notes:

5. The accessory type is reported in the Device Type 1 (0Ah) register for each valid accessory detected.

6. The FSA88x follows the Battery Charging 1.1 specification, which uses DP_CON and DM_CON to determ ine the USB

accessory attached. Refer to Battery Charg ing 1.1 spe cif ica tion for further details.

For SDP and CDP USB accessories, the following pin mapping is automatically configured:

 DP_HOST = DP_CON

 DM_HOST = DM_CON

For DCP charger, the DP_HOST and DM_HOST switches are open. For all USB accessories VBUS_IN is Over-Voltage

Tolerance (OVT) up to 28 V.

6. Processor Communication

Typical communication steps between the processor and the

FSA88x during accessory detection are:

1. INTB is asserted LOW, indicating change in accessory

detection.

2. Processor reads Interrupt 1 (03h) register to determine if

an attach or detach event was detected.

3. Processor reads Status registers to determine the exact

accessory detected.

a. Device Type 1 (0Ah): Indicates which USB, Car Kit

CDP, or DCP accessory was detected.

b. Device Type 2 (0Bh): Indicates whi ch fac tor y mode or

unknown accessory was detected.

FSA880 / FSA881 • Rev. 1.0.7 11

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

7. Switch Configuration

FSA88x devices have two modes of operation when

configuring the internal switches. The FSA88x can auto-

configure the switches or the switches can be configured

manually by the processor. Typical applications use Auto-

Configuration Mode and do not require interaction with the

baseband to configure the switches correctly.

7.1. Configurations

USB Accessor ies an d

Factory Cables:

DP_CON=DP_HOST

DM_CON=DM_HOST

UART Factory

Cables:

DP_CON=DP_HOST1

DM_CON=DM_HOST1

Figure 8. Switch Configurations

7.2. Manual Switching

Manual switching is enabled by writing the foll owing registers:

 Manual Switch 1 (13h): Configures the switches for DM_CON, and DP_CON.

 Manual Switch 2 (14h): Configures the BOOT, and JIG pins.

Baseband

Processor

HS USB

INTB

I2C_SCL

I2C_SDA

DM_HOST1

DP_HOST1

HS USB

or UART

Interrupt

Float

Detect

Charger

Detect BC1.1

Switch

Control

and

Slave

Detection

28V OVT

2:1

MUX

BAT

ADC I D

Detect

JIG

BOOT

100k

DDIO

Phone

Power

USB Po rt

BUS_IN

DM_CON

DP_CON

GND

ID_CON

FSA880

DM_HOST

DP_HOST

Baseband

Processor

HS USB

INTB

I2C_SCL

I2C_SDA

DM_HOST1

DP_HOST1

I2C

Interrupt

Float

Detect

Charger

Detect BC1.1

Switch

Control

and

I2C

Slave

Detection

28V OVT

VBAT

ADC I D

Detect

JIG

BOOT

100k

VDDIO

Phone

Power

USB Po rt

VBUS_IN

DM_CON

DP_CON

GND

ID_CON

FSA880

DM_HOST

DP_HOST

HS USB

or UART 2:1

MUX

FSA880 / FSA881 • Rev. 1.0.7 12

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

8. Active Signal Performance

8.1. HS USB Data

8.1.1. DP_HOST/DM_HOST

Figure 9. Pass Through Eye Compliance Testing

Input Signal

Figure 10. USB 2.0 Eye Compliance Test Results

at Output

8.1.2. DP_HOST1/DM_HOST1

Figure 11. Pass-Through Eye Compliance Testing

Input Signal

Figure 12. USB 2.0 Eye Compliance Test Result s

at Output

FSA880 / FSA881 • Rev. 1.0.7 13

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

8.2. Full-Speed USB

8.2.1. DP_HOST/DM_HOST

Figure 13. USB FS Eye Compliance Testing

8.2.2. DP_HOST1/DM_HOST1

Figure 14. USB FS Eye Compliance Testing

FSA880 / FSA881 • Rev. 1.0.7 14

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

9. Product Specifications

9.1. Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable

above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,

extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute

maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VBAT Supply Voltage from Bat tery -0.5 6.0 V

VBUS_IN Supply Voltage from USB Connector -0.5 28.0 V

VSW Switch I/O Voltage USB -1.0 6.0 V

UART -1.0 6.0

IIK Input Clamp Diode Current -50 mA

ISW Switch I/O Current (Continuous) USB at TA=85°C 25 mA

UART at TA=85°C 12

ISWPEAK Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) 150 mA

TSTG Storage Temperature Range -65 +150 °C

TJ Maximum Junction Temperature +150 °C

TL Lead Temperature (Soldering, 10 Seconds) +260 °C

ESD IEC 61000-4-2 System ESD USB Connector Pins

(DP_CON, DM_CON,

VBUS_IN, ID_CON) to GND

Air Gap 15

Contact 8

Human Body Model, JEDEC JESD22-A114 All Pins 4

Charged Device Model , JEDEC JESD22-C101 All Pins 2

9.2. Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend

exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

VBAT Battery Supply Voltage 3.0 4.4 V

VBUSIN VBUS_IN Voltage 4.0 5.5 V

VDDIO Processor Supply Voltage 1.8 3.6 V

VSW Switch I/O Voltage USB Path Active 0 3.6 V

UART Path Active 0 3.6

IDCAP Capacitive Load on ID_CON Pin for Reliable Accessory Detection 1.0 nF

TA Operating Temperature -40 +85 ºC

FSA880 / FSA881 • Rev. 1.0.7 15

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

9.3. Switch Path DC Electrical Characteristics

All typical values are at TA=25° C unless otherwise specified.

Symbol Parameter VBAT (V) Conditions TA = -40 to +85°C Unit

Min. Typ. Max.

Host Interface Pins (BOOT, JIG, INTB)

VOH Output High Voltage (FSA881 JIG

Output) 3.0 to 4.4 IOH=-2 mA 0.8•VBAT V

VOH Output High Voltage (just BOOT &

INTB Outputs)(7) 3.0 to 4.4 IOH=-2 mA 0.7•VDDIO V

VOL Output Low Voltage (INTB, JIG &

BOOT Outputs) 3.0 to 4.4 IOL=3 mA 0.4 V

I2C Interface Pins – Fast Mode (I2C_SDA, I2C_SCL)

VIL Low-Level Input Voltage 3.0 to 4.4 0.3•VDDIO V

VIH High-Level Input Voltage 3.0 to 4.4 0.7•VDDIO V

VHYS Hysteresis of Schmitt Trigger Inputs 3.0 to 4.4 VDDIO>2 V 0.05 VDDIO

VDDIO<2 V 0.1 VDDIO V

VOL1 Low-Level Output Voltage at 3 mA

Sink Current (Open-Drain) 3.0 to 4.4 VDDIO>2 V 0.4

VDDIO<2 V 0.2•VDDIO V

II2C Input Current of I2C_SDA and

I2C_SCL Pins 3.0 to 4.4 Input Voltage 0.26 V to

2.34 V -10 10 µA

Switch OFF Characteristics

IOFF Power-Off Leakage Current 0 All Data Ports VSW=0 V to

4.4 V 10 µA

INO(OFF) Off Leakage Current 3.0 to 4.4 VBAT=4.4 V; I/O

Pins=0.3 V, 4.1 V, or

Floating -0.100 0.001 0.100 µA

IIDSHRT Short-Circuit Current 3.0 to 4.4 Current Limit if

ID_CON=0 V 1 mA

USB Switch ON Path

RONUSB USB Switch On Resistance(8) 3.0 to 4.4 VD+/D-=0 V, 0.4 V; ION=8 mA 8 10 Ω

VSW=0 V, 3.6 V; ION=30 mA 25 30 Ω

VBUS Path

VBUSIN VBUS_IN Valid Threshold 0.8 4.0 V

RBUS VBUS_IN Resistance to GND 3 MΩ

UART Switc h ON Paths

VASR_UART Analog Signal Range 3.0 to 4.4 0 3.6 V

RONUART UART Switch On Resistance 3.0 to 4.4 VD+/D-=0 V, 0.4 V; ION=8 mA 8 10 Ω

VSW=0 V, 3.6 V; ION=30 mA 25 30

Total Current Consumption

ICCSL Battery Supply Standby Mode

Current (No Accessory Attached) 3.0 to 4.4 No Accessory, Static

Current During Standby

Mode 15 25 µA

ICCSLWA Battery Supply Standby Mode

Current with Accessory Attac hed(7) 3.0 to 4.4

With non-Factory Mode

Accessories Attached 30 40 µA

With Factory Mode

Accessories Attached(9) 100 120 µA

Notes:

7. Limits based on electr ic al characterization data.

8. On resistance is the voltage drop between the two terminals at the indicated current through the switch.

9. Factory mode accessories leave the detection circuitry activ e after attach to allow detection of ID changes w ithout an at tach.

FSA880 / FSA881 • Rev. 1.0.7 16

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

9.4. Capacitance

Symbol Parameter VBAT (V) Conditions TA = -4 0 to +85°C Unit

Min. Typ. Max.

CON DP_CON, DM_CON On Capacitance 3.8 VBIAS=0.2 V, f=1 MHz 6 pF

CI Capacitance for Each I/O Pin 3.8 5 pF

9.5. I2C DC Electrical Characteristics

Symbol Parameter VBAT (V) Conditions TA = -40 to +85°C Unit

Min. Max.

Fast Mode (I2C_SDA, I2C_SCL)

VIL Low-Level Input Voltage 3.0 to 4.4 0.3•VDDIO V

VIH High-Level Input Voltage 3.0 to 4.4 0.7•VDDIO V

Vhys Hysteresis of Schmitt Trigger Inputs 3.0 to 4.4 VDDIO>2 V 0.05 VDDIO V

VDDIO<2 V 0.1 VDDIO V

VOL1 Low-Level Output Voltage at 3 mA

Sink Current (Open-Drain) 3.0 to 4.4 VDDIO>2 V 0.4

VDDIO<2 V 0.2•VDDIO V

Ii2C Input Current of I2C_SDA and

I2C_SCL Pins 3.0 to 4.4 Input Voltage 0.26 V to

2.34 V -10 10 µA

9.6. I2C AC Electrical Characteristics

Symbol Parameter Fast Mode Unit

Min. Max.

fSCL I2C_SCL Clock Frequen cy 0 400 kHz

tHD;STA Hold Time (Repeated) START Condition 0.6 µs

tLOW LOW Period of I2C_SCL Clock 1.3 µs

tHIGH HIGH Period of I2C_SCL Clock 0.6 µs

tSU;STA Set-up Time for Repeated START Condition 0.6 µs

tHD;DAT Data Hold Tim e 0 0.9 µs

tSU;DAT Data Set-up Time

(10)

100 ns

tr Rise Time of I2C_SDA and I2C_SCL Signals(10,11) 20+0.1Cb 300 ns

tf Fall Time of I2C_SDA and I2C_SCL Signals(10,11) 20+0.1Cb 300 ns

tSU;STO Set-up Time for STOP Condition 0.6 µs

tBUF BUS-Free Time between STOP and START Conditions 1.3 µs

tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns

Notes:

10. A fast-mode I2C Bus® device can be used in a Standard-Mode I2C Bus system, but the requirement tSU;DAT ≥ 250 ns must

be met. This is autom atically the cas e if the device does not stretc h the LOW period of the I2C_SCL signal. If a device

does stretch the LOW period of the I2C_SCL signal, it must out put the next data bit to the I2C_SDA line tr_max + tSU;DAT =

1000 + 250 = 1250 ns (according to the Standard-Mode I2C bus specification) before the I2C_SCL line is released.

11. Cb equals the total capacitance of one bus line in pF. If mixed with high-speed devices, faster fall times are allowed by the

I2C specification.

FSA880 / FSA881 • Rev. 1.0.7 17

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Figure 15. Definition of Timing for Full-Speed Mode Devices on the I2C Bus®

Table 6. I2C Slave Address

Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Slave Address 8 0 1 0 0 1 0 1 R/W

9.7. Switch Path AC Electrical Characteristics

All typical values are for VBAT=3.8 V at TA=25°C unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Unit

Xtalk Active Channel Crosstalk

DP_CON to DM_CON USB Mode f=1 MHz, RT=50 Ω, CL=0 pF -60 dB

f=240 MHz, RT=50 Ω,

CL=0 pF -30

OIRR Off Isolation USB Mode f=1 MHz, RT=50 Ω, CL=0 pF -60 dB

tSK(P) Skew of Opposite Transitions of the Same

Output (USB Mode) tr=tf=750 ps (10-90%) at

240 MHz, CL=0 pF, RL=50 Ω 35 ps

tSW Time after INT Ma sk Cleared to “0” until INTB

Goes LO W to Signal the Interrupt after

Interruptible Event while INT Mask Bit Set to “1” See Fi gur e 16 and Figure 17 10 ms

tSDPDET Time from VBUS_IN Valid to USB Switches Closed

for USB Standard Downstream Port See Figure 17 130 ms

tCHGOUT Time from VBUS_IN Valid to USB Switches Closed

for USB Charging Downstream Port (CDP) See Figure 18 170 ms

tJIGVBUS Time from VBUS_IN Valid to JIG LO W for Factory

Mode Operation with VBUS_IN Present See Figure 20 200 ms

tJIGVBUS Time from VBUS_IN Valid to JIG LOW for Factory

Mode Operation without VBUS_IN Present See Figure 21 200 ms

FSA880 / FSA881 • Rev. 1.0.7 18

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

9.8. Timing Diagrams

Figure 16. INT Mask to INTB Interrupt at Power-Up Tim ing Diagram

Figure 17. INT Mask to INTB Interrupt During Operation Timing Diagram

Figure 18. USB Stand ard Downstream Port Attach T i ming

Figure 19. USB Charging Ports (DCP & CDP) Attach T iming

VBUS Voltage

INTB Asserted and

Registers Written

VBUS

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

FLOAT

ID Resistance

DCD

CHG DETECTION

150

INTB Pin

Switch State

170

Closed

(

CDP Only

)

130

VBUS

USB Switch State

USB Switches Closed

VBUS

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

FLOAT

ID Resistance

Closed

Open

DCD Checkin g

ID Detection Time

110

BAT

DDIO

INTB Mask

Bit

INTB Event

INTB

Don’t Car e

(

High or Low

)

INTB Event

BAT

Internal Reset

INTB Mask

Bit

400

µs

INTB event

Standby Mode

Interrupt

Registers Read

INTB

FSA880 / FSA881 • Rev. 1.0.7 19

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Figure 20. Jig Box Attach Timing (VBUS_IN Valid)

Figure 21. JIG Box Attach Timing without VBUS_IN

ID Resistance

XXXXXX

FLOAT

JIG Pin

BOOT Pin

ID Detection Time

200

Switch State

Closed

Open

VBUS_iN

BUS

ID Resistance

XXXXXXXX

FLOAT

JIG Pin

BOOT Pin

ID Detection Time

200

Switch State

Closed

Open

FSA880 / FSA881 • Rev. 1.0.7 20

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

9.9. Programmability Tables

Table 7. I2C Register Map

Address

Type

Reset

Value(12,13) Bit 7(14) Bit 6(14) Bit 5(14) Bit 4(14) Bit 3(14) Bit 2(14) Bit 1(14) Bit 0(14)

01H Device ID R N/A Revision Number Vendor ID

02H Control R/W xxx0x1x1 Switch

Open Auto

Config INT

Mask

03H Interrupt R/C xxxxxx00 Detach Attach

07H ADC R xxx11111 ADC Value

0AH Device

Type 1 R x000x0xx

Dedicated

Charger

(DCP)

USB

Charger

(CDP)

Car Kit

Type 1

& TA

Charger

Standard

USB

(SDP)

0BH Device

Type 2 R 0xxx0000 Unknown

Accessory Jig UART

Off

Jig

UART

Jig USB

Off Jig USB

13H Manual

SW 1 R/W 000000xx D- Switching D+ Switching

14H Manual

SW 2 R/W xxxx00xx BOOT

SW JIG ON

1BH Reset R/W xxxxxxx0 Reset

Notes:

12. Write “0” to undefined register bits.

13. Values read from undefined register bits are not defined and invalid.

14. Do not use undefined register locations.

Table 8. Device ID

Address: 01h

Type: Read

Bit # Name Size (Bits) Description

7:3 Revision Number 5 Rev 0.0 = 00000

2:0 Vendor ID 3 000: Fairc hild Semiconductor

Table 9. Control

Address: 02h

Reset Value: xxx0x1x1

Type: Read/Write

Bit # Name Size (Bits) Description

7:5 DoNotUse 3 N/A

4 Switch Open 1 1: Open all switches

0: Automatic switching by accessory status

3 DoNotUse 1 N/A

2 Auto Config 1 1: Automatic switching (also called auto-configuration)

0: Manual switching

1 DoNotUse 1 N/A

0 I N T Ma sk 1 1: Mask interrupt – do not interrupt baseband processor

0: Unmask interrupt – interrupt baseband processor on change of state in

Interrupt register

FSA880 / FSA881 • Rev. 1.0.7 21

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Table 10. Interrupt

Address: 03h

Reset Value: xxxxxx00

Type: Read/Clear

Bit # Name Size (Bits) Description

7:2 DoNotUse 6 N/A

1 Detach 1 1: Accessory detached

0: Accessory not detached

0 Attach 1 1: Accessory attached

0: Accessory not attached

Table 11. Device Type 1

Address: 07h

Reset Value: xxx11111

Type: Read

Bit # Name Size (Bits) Description

7:5 Reserved 3 NA

4:0 ADC Value 5 ADC value read from ID

Table 12. Device Type 1

Address: 0Ah

Reset Value: x00x00xx

Type: Read

Bit # Name Size (Bits) Description

7 DoNotUse 1 N/A

6 Dedicated Charger

(DCP) 1 1: USB dedicated charging port (DCP) charger detected

0: USB dedicated charging port (DCP) charger not detected

5 USB Charger (CDP) 1 1: USB charging downstream port (CDP) charger detected

0: USB charging downstream port (CDP) charger not detected

4 Ca r Kit Type 1 & TA

Charger 1 1: Car Kit Type 1 or Travel Adapter (TA) detected

0: Car Kit Type 1 or Travel Adapter (TA) not detected

3 DoNotUse 1 N/A

2 Standard USB

(SDP) 1 1: USB standard downstream port (SDP) detected

0: USB standard downstream port (SDP) not detected

1:0 DoNotUse 2 N/A

Table 13. Device Type 2

Address: 0Bh

Reset Value: 0xxx0000

Type: Read

Bit # Name Size (Bits) Description

7 Unknown Accessory 1 1: Any accessory detected as unknown or an accessory that cannot be

detected as being valid even though ID_CON is not floating

0: Unknown accessory not detected

6:4 DoNotUse 4 N/A

3 JIG_UART_OFF 1 1: Factory mode BOOT-OFF-UART detected

0: Factory mode BOOT-OFF-UART not detected

FSA880 / FSA881 • Rev. 1.0.7 22

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

Bit # Name Size (Bits) Description

2 JIG_UART_ON 1 1: Factory mode cable UART path with BOOT ON detected

0: Factory mode cable UART path with BOOT ON not detected

1 JIG_USB_OFF 1 1: Factory mode cable USB path with BOOT OFF detected

0: Factory mode cable USB path with BOOT OFF not detected

0 JIG_USB_ON 1 1: Factory mode cable USB path with BOOT ON detected

0: Factory mode cable USB path with BOOT ON not detected

Table 14. Manual S/W 1(15)

Address: 13h

Reset Value: 000000xx

Type: Read/Write

Bit # Name Size (Bits) Description

7:5 DM_CON Switching 3

000: Open switch

001: DM_CON connected to DM_HOST of USB port

011: DM_CON connected to DM_HOST1 of UART port

All other values: DoNotUse

4:2 DP_CON Switching 3

000: Open switch

001: DP_CON connected to DP_HOST of USB port

011: DP_CON connected to DP_HOST1 of UART port

All other values: DoNotUse

1:0 DoNotUse 2 N/A

Note:

15. When switching between manual switch configurations on a single attach, the access ory must pass through an “000:

Open Switc h” state between configurations. Manual Modes m ust have an accessory attached prior to operation.

The FSA88x does not configure per the Manual Modes register if an accessory has not been previously attached.

Table 15. Manual S/W 2

Address: 14h

Reset Value: xxxx00xx

Type: Read/Write

Bit # Name Size (Bits) Description

7:4 DoNotUse 4 N/A

3 BOOT_SW 1 1: HIGH

0: LOW

2 JIG_ON 1 1: JIG output=GND (FSA880) or JIG output=HIGH (FSA881)

0: JIG output=High impedance (FSA880) or JIG output=LOW (FSA881)

1:0 DoNotUse 2 N/A

Table 16. Reset

Address: 1Bh

Reset Value: xxxxxx0

Type: Read/Write

Bit # Name Size (Bits) Description

7:1 DoNotUse 6 N/A

0 Reset 1 1: Resets the FSA88x

0: Does not reset the FSA88x

FSA880 / FSA881 • Rev. 1.0.7 23

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

10. Layout Guidel i nes

10.1. PCB Layout Guidelines for H igh-Speed

USB Signal Integrity

1. Place FSA88x as close to the USB controller as

possible. Shorter traces mean less loss, less chance of

picking up s tray noise, and less radiated EMI.

a) Keep the distance between the USB controller and

the device less than 25 mm (< one inch).

b) For best results, this distance should be <18mm.

This keeps it less than one quarter (¼) of the

transmissi on ele ctrical length.

2. Use an impedance calculator to ens ure 90 Ω differential

impedance for DP_CON and DM_CON lines.

3. Select the best transmission line for the application.

a) For example, for a densely populated board, select

an edge-coup led differential stripline.

4. Minimize the use of vias and keep HS USB lines on

same plane in the sta ck.

a) Vias are an interruption in the impedance of the

transmission line and should be avoided.

b) Try to avoid routing schemes that generally force

the use of at least two vias: one on each end to get

the signal to and from the surface.

5. Cross lines, only if necessary, orthogonally to avoid

noise coupling (traces running in parallel couple).

6. If possible, separate HS USB lines with GND to improve

isolation.

a) Routing GND, power, or components close to the

transmission lines can create impedance

discontinuities.

7. Match transmission line pairs as much as possible to

improve skew perform anc e.

8. Avoid sharp bends in PCB traces; a chamfer or

rounding is gener ally preferr e d .

9. Place decoupling for power pins as close to the device

as possible.

a) Use low-ESR capacitor s for decoupling if possible.

b) A tuned PI filter should be used to negate the

effects of switching power supplies and other noise

sources if needed.

10.2. Layout for GSM / TDMA Buzz Reduction

There are two possible mechanisms for TDMA / GSM noise

to negatively impact FSA88x performance. The first is the

result of large current draw by the phone transmitter during

active signaling when the transmitter is at full or almost-full

power. With the phone transmitter dumping large amounts of

current in the phone GND plane; it is possible for there to be

temporary voltage excursions in the GND plane if not

properly designed. This noise can be coupled back through

the GND plane into the FSA88x device and, although the

FSA88x has very good isolation; if the GND noise amp litude

is large enough, it can result in noise coupling to the

FSA88x. The second path for GSM noise is through

electromagnetic coupling onto the signal lines themselves.

In most cases, the noise introduced as a result is on the VBAT

and / or GND supply rails. Following are recommendations

for PCB board design that help address these two sources of

TDMA / GSM noise.

1. Provide a wide, low-impedance GND return path to both

the FSA88x and to the power amplifier that sources the

phone trans mit block.

2. Provide separate GND connections to PCB GND plane

for each device. Do not share GND return paths among

devices.

3. Add as large a decoupling capacitor as possible (≥1µF)

between the VBAT pin and GND to shunt any power

supply noise away from the FSA88x. Also add

decoupling capacitance at the PA (see the reference

application schematic in Figure 22 for recommended

decoupling cap ac itor val ues).

4. Add 33 pF shunt capacitors on any PCB nodes with the

potential to collect radiated energy from the phone

transmitter.

5. Add a series RBAT resistor prior to the decoupling

capacitor on the VBAT pin to attenuate noise prior to

reaching the FSA88x.

FSA880 / FSA881 • Rev. 1.0.7 24

FSA880 / FSA881 — USB Port 2:1 Switch with Accessory and Charger Detection

11. Reference Schematic

Baseband

Processor

BUS_IN

Micro

USB

GND

HS USB

or UART

I2C_SDA

I2C_SCL

INTB

DM_HOST1

DP_HOST1

I2C

HS USB

or UART

Interrupt

Float

Detect

Charger

Detect BC1.1

Switch

Control

and

Slave

Detection

28V OVT

2:1

MUX

ADC ID

Detect

JIG

BOOT

DDIO

Phone

Power

PU_JIG

VDDIO

PU_I2C

VDDIO

VBAT

BAT

DP/DM

DP_CON

DM_CON

TVS

TVS_OPT

VBUS

ID_CON

DM_HOST

DP_HOST

Figure 22. Reference Schematic

Table 17. Reference Schematic Component Values

Symbol Parameter Recommended Value Unit Notes

Min. Typ. Max.

CVBUS VBUS_IN Decoupling 1.0 4.7 10.0 µF This is the recommended capacitance i n the

USB standard (for the downstream port VBUS

capacitance specification).

CVBAT VBAT Decoupling Capacitance 1 10 µF Increasing this capacitance can help reduce

GSM / TDMA noise.

RBAT VBAT Series Resistance 50 100 Ω

Adding series resistance can help reduce

GSM / TDMA noise. Ensure that resistance

is small enough to not reduce VBAT levels

under normal opera tion .

RPU_I2C I2C Pull-up Resistance 4.7 kΩ The actual value used must allow

complianc e to I2C specification based on

VDDIO and bus capacitance.

RPU_JIG JIG Pull -up Resistance

(FSA880 ONLY) 100 kΩ Pull-up resistance for open-dr ain JIG pin.

RDP/DM DP_CON/DM_CON Series

Resistance 2.2 Ω Series resistance to improve surge

performanc e of high-speed USB path.

TVS High-Speed TVS Diodes 1 pF Recommended high-speed TVS diodes to

improve ESD perfor man ce.

TVS_OPT Optional High-Speed TVS

Diodes 1 pF Optional high-speed TVS diodes to improve

ESD performance.

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