1
FEATURES APPLICATIONS
1
2
3
45
6OUT2
OC1
OUT 1
EN1
GND
IN
TPS2062A/TPS2066A
DPACKAGE
(TOP VIEW)
7
8
EN2 OC2
5
6
TPS2062A/TPS2066A
DRBPACKAGE
(TOP VIEW)
7
8
PAD
1
2
3
4
EN1
GND
IN
EN2
OUT2
OC1
OUT1
OC2
Enableinputsareactivelowforall TPS2062A
andactivehighforall TPS2066A
DESCRIPTION
TPS2014600mA
TPS20151 A
TPS2041B500mA
TPS2051B500mA
TPS2045A 250mA
TPS2049100mA
TPS2055A 250mA
TPS20611 A
TPS20651 A
TPS20681.5 A
TPS20691.5 A
TPS201xA 0.2 A -2 A
TPS202x0.2 A -2 A
TPS203x0.2 A -2 A
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
TWO CHANNEL, CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES
•Heavy Capacitive Loads2
•70-m ΩHigh-Side MOSFET
•Short-Circuit Protection•1-A Continuous Current•Thermal and Short-Circuit Protection•Accurate Current-Limit
(1.2 A min, 2 A max)•Operating Range: 2.7 V to 5.5 V•0.6-ms Typical Rise Time•Undervoltage Lockout•Deglitched Fault Report ( OCx)•No OCx Glitch During Power Up•1- µA Maximum Standby Supply Current•Bidirectional Switch•Ambient Temperature Range: – 40 ° C to 85 ° C•Built-in Soft-Start•UL Listed -- File No. E169910, Both Single andGanged Channel Configuration
The TPS206xA power-distribution switches are intended for applications where heavy capacitive loads andshort-circuits are likely to be encountered. The TPS206xA family is pin-for-pin compatible with the TPS206xfamily with a tighter overcurrent tolerance. This family of devices incorporates two 70-m ΩN-channel MOSFETpower switches for power-distribution systems that require multiple power switches in a single package. Eachswitch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed tocontrol the power-switch rise and fall times to minimize current surges during switching. The charge pumprequires no external components and allows operation from supplies as low as 2.7 V.
Each device limits the output current to a safe level by switching into a constant-current mode when the outputload exceeds the current-limit threshold or a short is present. Individual channels indicate the presence of anovercurrent condition by asserting its corresponding OCx output (active low). Thermal protection circuitrydisables the device during overcurrent or short-circuit events to prevent permanent damage. The device recoversfrom thermal shutdown automatically once the device has cooled sufficiently. The device provides undervoltagelockout to disable the device until the input voltage rises above 2.0 V. The TPS206xA is designed to current limitat 1.6 A typically per channel.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according toMIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher thanmaximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted togetheror the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logicvoltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publicationGuidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
AVAILABLE OPTION AND ORDERING INFORMATION
PACKAGE
(1)RECOMMENDED
TYPICALMAXIMUM D-8 DRB-8T
A
ENABLE SHORT-CIRCUITCONTINUOUS LOAD (SOIC) (SON)LIMITCURRENT
PART # STATUS PART # STATUS
Active
TPS2062AD AVAILABLE TPS2062ADRB AVAILABLElow– 40 ° C to
1 A 1.6 A85 ° C
Active
TPS2066AD AVAILABLE TPS2066ADRB AVAILABLEhigh
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
over operating temperature range unless otherwise noted
(1) (2)
VALUE UNIT
V
I
Input voltage range IN – 0.3 to 6 VV
O
Output voltage range OUTx – 0.3 to 6 VInput voltage range ENx, ENx – 0.3 to 6 VV
I
Voltage range OCx – 0.3 to 6 VI
O
Continuous output current OUTx Internally limitedContinuous total power dissipation See " Dissipation Rating Table "T
J
Operating junction temperature range – 40 to 125 ° CT
stg
Storage temperature range – 65 to 150 ° CHuman body model MIL-STD-883C 2 kVElectrostatic dischargeESD
protection
Charge device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 ° C DERATING T
A
= 70 ° C T
A
= 85 ° CTHERMAL POWER FACTOR POWER POWERBOARD PACKAGE
RESISTANCE θ
JA
RATING ABOVE T
A
= RATING RATING25 ° C
Low-K
(1)
D-8 170 ° C/W 586 mW 5.86 mW/ ° C 320 mW 234 mWHigh-K
(2)
D-8 97.5 ° C/W 1025 mW 10.26 mW/ ° C 564 mW 410 mWLow-K
(3)
DRB
(4)
270 ° C/W 370 mW 3.71 mW/ ° C 203 mW 148 mWHigh-K
(5)
DRB
(4)
60 ° C/W 1600 mW 16.67 mW/ ° C 916 mW 666 mW
(1) The JEDEC low-K (1s) board used to dervie this data was a 3in x 3in, two-layer board with 2-ounce copper traces on top of the board.(2) The JEDEC high-K (2s2p) board used to dervive this data was a 3in x 3in, multilayer board with 1-ounce internal power and groundplanes and 2-ounce copper traces on top and bottom of the board.(3) Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.(4) See Recommended Operating Conditions Table for PowePad connection guidelines to meet qualifying conditions for CB Certificate(5) Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.
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Product Folder Link(s): TPS2062A TPS2066A
RECOMMENDED OPERATING CONDITIONS
(1)
ELECTRICAL CHARACTERISTICS
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
MIN MAX UNIT
Input voltage, IN 2.7 5.5 VV
I
Input voltage, ENx, ENx 0 5.5 VI
O
Continuous output current, OUTx 0 1 AT
J
Operating virtual junction temperature – 40 125 ° C
(1) The PowePad must be connected externally to GND pin to meet qualifying conditions for CB Certificate (DRB package only)
over recommended operating junction temperature range, V
I
= 5.5 V, I
O
= 1 A, V
/ENx
= 0 V (TPS2062A) or V
ENx
= 5.5 V(unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
T
J
= 25 ° C 70 100r
DS(on)
Static drain-source on-state resistance 2.7 V ≤V
I
≤5.5 V, I
O
= 1 A m Ω– 40 ° C ≤T
J
≤125 ° C 135
V
I
= 5.5 V 0.6 1.5t
r
Rise time, output
V
I
= 2.7 V 0.4 1C
L
= 1 µF,
msR
L
= 5 Ω, T
J
= 25 ° CV
I
= 5.5 V 0.05 0.5t
f
Fall time, output
V
I
= 2.7 V 0.05 0.5
ENABLE INPUT EN OR EN
V
IH
High-level input voltage 22.7 V ≤V
I
≤5.5 V VV
IL
Low-level input voltage 0.8
I
I
Input current -0.5 0.5 µA
t
on
Turnon time 3C
L
= 100 µF, R
L
= 5 Ωmst
off
Turnoff time 3
CURRENT LIMIT
T
J
= 25 ° C 1.2 1.6 2.0Short-circuit output current per V
I
= 5 V, OUTx connected to GND,I
OS
Achannel device enabled into short-circuit
– 40 ° C ≤T
J
≤125 ° C 1.1 1.6 2.1
I
OC
Overcurrent trip threshold V
IN
= 5 V I
OS
2.1 2.45 A
T
J
= 25 ° C 2.4 3.2 4.0V
I
= 5 V, OUT1 & OUT2 connected toI
OS_G
Ganged short-circuit output current
GND, device enabled into short-circuit
– 40 ° C ≤T
J
≤125 ° C 2.2 3.2 4.2 A
I
OC_G
Ganged overcurrent trip threshold V
I
= 5 V, OUT1 & OUT2 tied together I
OS_G
4.2 4.9
SUPPLY CURRENT
T
J
= 25 ° C 0.5 1I
IL
Supply current, device disabled No load on OUT µA– 40 ° C ≤T
J
≤125 ° C 0.5 5
T
J
= 25 ° C 50 60I
IH
Supply current, device enabled No load on OUT µA– 40 ° C ≤T
J
≤125 ° C 50 75
I
lkg
Leakage current, device disabled OUT connected to ground – 40 ° C ≤T
J
≤125 ° C 1 µA
Reverse leakage current V
O
= 5.5 V, V
I
= 0 V T
J
= 25 ° C 0.2 µA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN V
I
rising 2 2.5 V
Hysteresis, IN V
I
falling 75 mV
OVERCURRENT FLAG
V
OL
Output low voltage, OC I
/OCx
= 5 mA 0.4 V
Off-state current V
/OCx
= 5.0 V or 3.3 V 1 µA
OC deglitch OCx assertion or de-assertion 4 8 15 ms
THERMAL SHUTDOWN
(2)
Thermal shutdown threshold 135 ° C
Recovery from thermal shutdown 125 ° C
Hysteresis 10 ° C
(1) Pulsed load testing used to maintain junction temperature close to ambient(2) The thermal shutdown only reacts under overcurrent conditions.
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DEVICE INFORMATION
Charge
Pump
Driver Current
Limit
Thermal
Sense
Deglitch
IN
GND
EN2
OUT2
FAULT 2
CS
Current
Sense
CS
Driver Current
Limit
UVLO
Charge
Pump
Thermal
Sense
Deglitch
FAULT 1
OUT1
EN1
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME TPS2062A TPS2066A
EN1 3 — I Enable input, logic low turns on power switch IN-OUT1EN2 4 — I Enable input, logic low turns on power switch IN-OUT2EN1 — 3 I Enable input, logic high turns on power switch IN-OUT1EN2 — 4 I Enable input, logic high turns on power switch IN-OUT2GND 1 1 GroundIN 2 2 I Input voltageOC1 8 8 O Channel 1 over-current indicator; the output is open-drain, active low typeOC2 5 5 O Channel 2 over-current indicator; the output is open-drain, active low typeOUT1 7 7 O Power-switch output, IN-OUT1OUT2 6 6 O Power-switch output, IN-OUT2PowerPAD™
(1)
PAD PAD Connect PowerPAD to GND for proper operation (DRB package only)
(1) See the Recommended Operating Conditions Table for PowePad connection guidelines to meet qualifying conditions for CB Certificate.
FUNCTIONAL BLOCK DIAGRAM
A. Current senseB. Active low ( ENx) for TPS2062A. Active high (ENx) for TPS2066A.
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PARAMETER MEASUREMENT INFORMATION
RLCL
OUT
TEST CIRCUIT
trtf
10%
90%
10%
90%
VOUT
ton toff
10%
90%
50%50%
VEN
VOUT
VEN
VOUT
ton
toff
50% 50 %
10%
90%
VOLTAGEWAVEFORMS
VI(EN)
5V/div
VO(OUT)
2V/div
RL=5W,
CL=1 mF
TA=25°C
t − Time − 500 ms/div
VI(EN)
5V/div
VO(OUT)
2V/div
t − Time − 500 ms/div
R =5 ,
C =1 F,
T =25°C
L
L
A
W
m
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 1- µF Load Figure 3. Turnoff Delay and Fall Time With 1- µF Load
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VI(EN)
5V/div
VO(OUT)
2V/div
t − Time − 500 ms/div
R =5 ,
C =100 F,
T =25°C
L
L
A
W
m
VO(OUT)
2V/div
VI(EN)
5V/div
t − Time − 500 ms/div
R =5 ,
C =100 F,
T =25°C
L
L
A
W
m
VI(EN)
5V/div
IO(OUT)
500mA/div
t − Time − 500 ms/div
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time With 100- µF Load Figure 5. Turnoff Delay and Fall Time With 100- µF Load
Figure 6. Short-Circuit Current, Figure 7. Inrush Current With DifferentDevice Enabled Into Short Load Capacitance
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VO(OC)
2V/div
IO(OUT)
1A/div
t − Time − 2ms/div
VO(OC)
2V/div
IO(OUT)
1A/div
t − Time − 2ms/div
POWER-SUPPLY CONSIDERATIONS
IN
OC1
EN1
OC2
2
8
5
7
0.1 Fm22 Fm
0.1 Fm22 Fm
Load
Load
OUT1
OUT2
PowerSupply
2.7Vto5.5V
6
EN2
3
4
GND
0.1 Fm
TPS2062A
1
DETAILED DESCRIPTION
OVERVIEW
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. 2- ΩLoad Connected to Enabled Device Figure 9. 1- ΩLoad Connected to Enabled Device
Figure 10. Typical Application
The devices are current-limited, power distribution switches using N-channel MOSFETs for applications whereshort-circuits or heavy capacitive loads will be encountered. These devices have a minimum fixed current-limitthreshold above 1.1 A allowing for continuous operation up to 1 A per channel. Overtemperature protection is anaddtional device shutdown feature. Each device incorporates an internal charge pump and gate drive circuitrynecessary to drive the N-channel MOSFETs. The charge pump supplies power to the driver circuit and providesthe necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from inputvoltages as low as 2.7 V and requires little supply current. The driver controls the gate voltage of the powerswitch. The driver incorporates circuitry that controls the rise and fall times of the output voltage to provide"soft-start" and to limit large current and voltage surges.
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OVERCURRENT
OCx RESPONSE
UNDERVOLTAGE LOCKOUT (UVLO)
Enable ( ENx or ENx)
THERMAL SENSE
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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When an overcurrent condition is detected, the device maintains a constant output current and reduces theoutput voltage accordingly. Three possible overload conditions can occur.
In the first condition, the output has been shorted before the device is enabled or before voltage is applied to IN.The device senses the short and immediately switches into a constant-current output. In the second condition, ashort or an overload occurs while the device is enabled. At the instant the overload occurs, high currents mayflow for several microseconds before the current-limit circuit can react. The device operates in constant-currentmode after the current-limit circuit has responded. In the third condition, the load is increased gradually beyondthe recommended operating current. The current is permitted to rise until the current-limit threshold is reached.The devices are capable of delivering current up to the current-limit threshold without damage. Once thethreshold is reached, the device switches into constant-current mode.
Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. The device willremain off until the junction temperature cools approximately 10 ° C and will then re-start. The device will continueto cycle on/off until the overcurrent condition is removed.
Each OCx open-drain output is asserted (active low) during an overcurrent or overtemperature condition on thatchannel. The output remains asserted until the fault condition is removed. The TPS206xA eliminates false OCxreporting by using internal delay circuitry after entering or leaving an overcurrent condition. This "deglitch" time isapproximately 8-ms. This ensures that OCx is not accidentally asserted due to normal operation such as startinginto a heavy capacitive load. Overtemperature conditions are not deglitched and assert and de-assert the OCxsignal immediately.
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLOturn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from largecurrent surges.
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce thesupply current. The supply current is reduced to less than 5 µA when a logic high is present on ENx, or when alogic low is present on ENx. A logic low input on ENx or a logic high input on ENx enables the driver, controlcircuits, and power switch for that channel.
The TPS206xA monitors the operating temperature of both power distribution switches with individual thermalsensors. The junction temperature of each channel rises during an overcurrent or short-circuit condition. Whenthe die temperature of a particular channel rises above a minimum of 135 ° C in an overcurrent condition, theinternal thermal sense circuitry disables the individual channel in overtemperature to prevent damage. Hysteresisis built into the thermal sensor and re-enables the power switch individually after it has cooled approximately10 ° C. The power switch cycles on and off until the fault is removed. This topology allows one channel to continuenormal operation even if the other channel is in an overtemperature condition. The open-drain overcurrent flag( OCx) is asserted (active low) corresponding to the channel that is in an overtemperature or overcurrentcondition.
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TYPICAL CHARACTERISTICS
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
23456
TurnonTime − ms
VI− InputVoltage − V
CL=100 mF,
RL=5W,
TA=25 °C
1.5
1.6
1.7
1.8
1.9
2
23456
CL=100 mF,
RL=5W,
TA=25 °C
TurnoffTime − mS
VI− InputVoltage − V
0
0.1
0.2
0.3
0.4
0.5
0.6
2 3 4 5 6
RiseTime − ms
VI− InputVoltage − V
CL=1 mF,
RL=5W,
TA=25 °C
0
0.05
0.1
0.15
0.2
0.25
2 3 4 5 6
CL=1mF,
RL=5W,
TA=25°C
FallTime − ms
VI− InputVoltage − V
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
TURNON TIME TURNOFF TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 11. Figure 12.
RISE TIME FALL TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 13. Figure 14.
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0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI=5.5V
VI=5V
VI=3.3V
VI=2.7V
TJ− JunctionTemperature − °C
−SupplyCurrent,OutputDisabled −
II(IN) Am
0
10
20
30
40
50
60
70
−50 0 50 100 150
VI=5.5V
VI=5V
VI=3.3V
VI=2.7V
TJ− JunctionTemperature − °C
−SupplyCurrent,OutputEnabled −
II(IN) Am
1.34
1.36
1.38
1.4
1.42
1.44
1.48
1.5
1.52
1.54
1.56
−50 0 50 100 150
1.46
VI=3.3V
VI=5V
VI=3.3V
VI=5.5V
TJ− JunctionTemperature −°C
−Short-CircuitOutputCurrent −A
IOS
VI=2.7V
0
20
40
60
80
100
120
−50 0 50 100 150
Out1=5V
Out1=3.3V
Out1=2.7V
IO=0.5A
TJ− JunctionTemperature −°C
rDS(on) − StaticDrain-Source
On-StateResistance − mΩ
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
TPS2062A, TPS2066A TPS2062A, TPS2066ASUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 15. Figure 16.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 17. Figure 18.
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2.1
2.14
2.18
2.22
2.26
2.3
−50 0 50 100 150
UVLORising
UVLOFalling
UVOL − UndervoltageLockout − V
TJ− JunctionTemperature − °C
1.5
1.7
1.9
2.1
2.3
2.5
2.5 3 3.5 4 4.5 5 5.5 6
TA=25°C
LoadRamp=1A/10ms
ThresholdT
ripCurrent −A
VI− InputVoltage − V
0
50
100
150
200
0 2.5 5 7.5 10 12.5
Current-LimitResponse − sm
PeakCurrent − A
VI=5V,
TA=25°C
TPS2062A
TPS2066A
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........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS (continued)
THRESHOLD TRIP CURRENT UNDERVOLTAGE LOCKOUTvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 19. Figure 20.
CURRENT-LIMIT RESPONSE
vsPEAK CURRENT
Figure 21.
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APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
POWER DISSIPATION AND JUNCTION TEMPERATURE
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
www.ti.com
Input and output capacitance improve the performance of the device; the actual capacitance should be optimizedfor the particular application. For all applications, a 0.01 µF to 0.1 µF ceramic bypass capacitor between IN andGND is recommended and should be placed as close to the device as possible for local noise de-coupling. Thisprecaution reduces ringing on the input due to power-supply transients . Additional input capacitance may beneeded on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the deviceduring heavy transients.
Placing a high-value electrolytic capacitor on the output pin is recommended when the output load is heavy.Additionally, bypassing the output with a 0.01 µF to 0.1 µF ceramic capacitor improves the immunity of thedevice to short-circuit transients.
The low on-resistance of the N-channel MOSFETs allows the small surface-mount packages to pass largecurrents. It is good design practice to check power dissipation to ensure that the junction temperature of thedevice is within the recommended operating conditions. The below analysis gives an approximation forcalculating junction temperature based on the power dissipation in the package. However, it is important to notethat thermal analysis is strongly dependent on additional system level factors. Such factors include air flow,board layout, copper thickness and surface area, and proximity to other devices dissipating power. Good thermaldesign practice must include all system level factors in addition to individual component analysis.
The following procedure shows how to approximate the junction temperature rise due to power dissipation in asingle channel. The TPS2062A/66A devices contain two channels, so the total device power must sum the powerin each power switch.
Begin by determining the r
DS(on)
of the N-channel MOSFET relative to the input voltage and operatingtemperature. Use the highest operating ambient temperature of interest and read r
DS(on)
from the typicalcharacteristics graph as an initial estimate. Power dissipation is calculated by:P
D
= r
DS(on)
× I
OUT
2
P
T
= 2 x P
D
Where:
P
D
= Power dissipation/channel (W)P
T
= Total power dissipation for both channels (W)r
DS(on)
= Power switch on-resistance ( Ω)I
OUT
= Maximum current-limit threshold (A)
Finally, calculate the junction temperature:T
J
= P
T
x R
ΘJA
+ T
A
Where:
T
A
= Ambient temperature ° CR
ΘJA
= Thermal resistance ( ° C/W)P
T
= Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeatthe calculation using the "refined" r
DS(on)
from the previous calculation as the new estimate. Two or threeiterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependenton thermal resistance R
θJA
, and thermal resistance is highly dependent on the individual package and boardlayout. The "Dissipation Rating Table" at the begginng of this document provides example thermal resistances forspecific packages and board layouts.
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2062A TPS2066A
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
SELF-POWERED AND BUS-POWERED HUBS
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
TPS2062A
TPS2066A
www.ti.com
........................................................................................................................................... SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008
One application for this device is for current-limiting in universal serial bus (USB) applications. The original USBinterface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PCperipherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, theUSB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface isconceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where poweris distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 Vfrom the 5-V input or its own internal power supply. The USB specification classifies two different classes ofdevices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA asdefined by the standard. A device classified as high-power can draw up to 500 mA. It is important that theminimum current limit threshold of the current-limiting power switch exceed the maximum current limit draw of theintended application. The latest USB standard should always be referenced when considering the current-limitthreshold.
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that containsmultiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). Afunction is a USB device that is able to transmit or receive data or control information over the bus. A USBfunction can be embedded in a USB hub. A USB function can be one of three types included in the list below.•Low-power, bus-powered function•High-power, bus-powered function•Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS206x6A has higher currentcapability than required for a single USB port allowing it to power multiple downstream ports.
A SPH has a local power supply that powers embedded functions and downstream ports. This power supplymust provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions.SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller.Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up withless than 100 mA. The BPH usually has one embedded function, and power is always available to the controllerof the hub. If the embedded function and hub require more than 100 mA on power up, the power to theembedded function may need to be kept off until enumeration is completed. This is accomplished by removingpower or by shutting off the clock to the embedded function. Power switching the embedded function is notnecessary if the aggregate power draw for the function and controller is less than 100 mA. The total currentdrawn by the bus-powered device is the sum of the current to the controller, the embedded function, and thedownstream ports, and it is limited to 500 mA from an upstream port.
Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-powerfunctions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and candraw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ωand 10 µF at power up, the device must implement inrush current limiting.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2062A TPS2066A
USB POWER-DISTRIBUTION REQUIREMENTS
TPS2062A
TPS2066A
SLVS798F – JANUARY 2008 – REVISED NOVEMBER 2008 ...........................................................................................................................................
www.ti.com
USB can be implemented in several ways regardless of the type of USB device being developed. Severalpower-distribution features must be implemented.•SPHs must:– Current-limit downstream ports– Report overcurrent conditions•BPHs must:– Enable/disable power to downstream ports– Power up at < 100 mA– Limit inrush current ( < 44 Ωand 10 µF)•Functions must:– Limit inrush currents– Power up at < 100 mA
The feature set of the TPS2062A/66A meets each of these requirements. The integrated current-limiting andovercurrent reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet theneed of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2062A TPS2066A
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2062AD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADRBR ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADRBT ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2062ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066AD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADRBR ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADRBT ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2066ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2008
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2062ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2062ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2062ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2066ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2066ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2066ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2062ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2062ADRBR SON DRB 8 3000 370.0 355.0 55.0
TPS2062ADRBT SON DRB 8 250 195.0 200.0 45.0
TPS2066ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2066ADRBR SON DRB 8 3000 370.0 355.0 55.0
TPS2066ADRBT SON DRB 8 250 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jul-2008
Pack Materials-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2062ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2062ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2066ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2066ADRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS2066ADRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2062ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2062ADRBR SON DRB 8 3000 346.0 346.0 35.0
TPS2066ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2066ADRBR SON DRB 8 3000 346.0 346.0 35.0
TPS2066ADRBT SON DRB 8 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2011
Pack Materials-Page 2
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