m@ DESCRIPTION PF734-04 SRM2AL256LLM 256K-Bit Static RAM @ Extended Supply Voltage Range @ Extremely Low Standby Current @ Access Time 150ns (2.7V) /85ns (4.5V) @ 32,768 WordsxX8-Bit Asynchronous The SRM2AL256LLM is a low voltage operating 32,768 words X 8-bit asynchronous, static, random access memory fabricated using an advanced CMOS technology. Its very low standby power consumption makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refresh circuit. Output ports are 3-state output allows easy expansion of memory capacity. These features makes the SRM2AL256LLM usable for wide range of applications from microprocesser systems to terminal devices. m@ PIN CONFIGURATION ml FEATURES sas @ Extended supply voltage range ............. 2.7 to 5.5V @ Fast access time ............ ees 150ns (8V+10%) a 85ns (5V+10%) z : > @ Extremely low standby current .............. LL Version S oO @ Completely static 0.0.0.0 no clock required E @ 3-state output @ Battery back-up operation @ Package ............e. SRM2AL256LLM SOP2-28pin (plastic) TSOP SRM2AL256LLTM TSOP (I)-28pin (plastic) xde shave SRM2AL256LLRM TSOP(I)-28pin-R1 (plastic) | 4114428 2ofics. A8 [25 18007 A131 26 170/06 We 1.27,-.. 160 05 vin C3 * SRM2AL256LLTM 5 BCA BLOCK DIAGRAM arel2 303 as 4 41001 A5 5 10P Ao A4d6 9 at a3 07 8 Paz AO x - (TSOP-R1) (Reverse bending) o A3 3 a3 q7 8 a2 AA _ 9 8 512 Memory Cell Array mds 9 HAI AS 2 a 512x648 Ms C 8 oH A 5 6 ne *< a7 3 12Evo2 Aa 3 A202 130/03 AS 3 Aid i) SRM2AL256LLRM 4B loa At0 64x8 we Cf 27 teh vos Att _ A13q] 26 170 vos At2 6 S| os As Tj 25 130 v07 A13 > 8 | Column Gate Ag Oj 24 19H vos A14 A11G] 23 20Cs f OE Cj 22 21) A10 cs SB, aes m@ PIN DESCRIPTION 88 | AO to A14 Address Input OE i 5 WE Write Enable _ gs ) VO Butfer OE Output Enable wey Lee cs Chip Select 1/01 to /O8 Data Input/Output VbD Power Supply(2.7 to 5.5V) VO1 OZ VO3 /O4 VO5 VO6 07 08 y p Supply(OV) ss ower SEIKO EPSON CORPORATIONEPSON m@ ABSOLUTE MAXIMUM RATINGS (Vss=0V) Parameter Symbol Ratings Unit Supply voltage Vop 0.5 to 7.0 Vv Input voltage Vi 0.5* to 7.0 Vv Input/Output voltage Vio 0.5* to Vpp+0.3 Vv Power dissipation Pp 1.0 Ww Operating temperature Topr 0 to 70 C Storage temperature Tsig 65 to 150 C Soldering temperature and time Tsol 260C, 10s(at lead) = * V), Vio (Min)=-3.0V when pulse width is less or equal to 50ns m DG RECOMMENDED OPERATING CONDITIONS (Vsg=0V, Ta=0 to 70C) Vpp=2.7V~5.5V Vpp=5V+10% Parameter Symbol Min. Typ. Max Min. Typ. Max. Unit V 2.7 = 5.5 45 5.0 5.5 Vv Supply voltage BD py von Vss 0 0 0 0 0 V Vin 2.2 _- Vpp+0.3 2.2 3.5 Vpp+0.3 Vv Input voltage Vib 0.3% 04 -0.3% 0 08 V * V_ (Min)= 3V when pulse width is less or equal to 50ns mM ELECTRICAL CHARACTERISTICS @ DC Electrical Characteristics (Vgg=0V, Ta=0 to 70C) ye Vpp=3V+10% Vpp=5V+10% . Parameter Symbol Conditions Min. [Typ*"| Max. | Min. [Typ2] Max. Unit Input leakage lu Vi=0 to Vpp -1 - 1 1 - 1 pA Standby supply current lops CS=VIH 2 8 mA lopst CS Vpp-0.2V = 06 | 30 | - 1.0 | 50 yA VieViL, V lopa lyox0mMA toyow Min. - | 10 | 20 | - | 30 | 6o | mA Average operating current 2 VieVit, Vin _ _ 5 _ _ 10 mA DDA1 lyo=OmA_ teyc=1p15 VieViL, V Operating supply current lnpa o-OmA. - - 5 - - 10 mA CS=Vin or WE=V Output leakage | VO= NIH IL - - - _ P g ro or OE=Viy_ Vyo=0 to Vpp 1 1 1 1 HA High level output voltage Vou lon=-1.OmMA, 0.5mA*? 2.4 - - 2.4 |Vpp-O.1) - Vv Low level output voltage VoL lo.=2.1mMA, 1.0mA*? - - 0.4 - 0.2 0.4 V *1 Typical values are measured at Ta=25C and Vpp=3.0V #2 Typical values are measured at Ta=25C and Vpp=5.0V *3 Vn p=3Vt10% @ Terminal Capacitance (fe1MHz, Ta=25C) Parameter Symbol Conditions Min. Typ. Max. Unit Address Capacitance Capp Vapp=0V - - 8 pF Input Capacitance C, V\=0V - - 8 pF 1/0 Capacitance Cro Viyo=0V - _ 10 pF @ AC Electrical Characteristics O Read Cycle (Vgg=0V, Ta=0 to 70C) we Vpp=3V+10% Vpp=5V+10% . Parameter Symbol Conditions Min, Max Min. Max Unit Read cycle time tro 150 - 85 - ns Address access time tacc - 150 - 85 ns CS access time tacs 4 - 150 - 85 ns OE access time toe - 100 - 45 ns CS output set time teLz 10 - 10 - ns CS output floating touz P - 60 - 30 ns CE output set time towz 2 5 - 5 - ns 2 | OE output floating tonz _ 60 _ 30 ns Output hold time tou *4 10 - 10 - nsSRM2AL256LLM O Write Cycle (Vgg-0V, Ta=0 to 70C) p t Symbol Condit Vpp=3V+10% Vpp=5V+10% Unit arameter ymbo onaltlons Min. Max. Min. Max. nl Write cycle time two 150 - 85 - ns Chip select time tow 140 - 70 - ns Address valid to end of write taw 140 - 70 = ns Address setup time tas 0 = 0 = ns - - *1 Write pulse width twe 130 = 65 = ns Address hold time twr 0 = 0 - ns Input data set time tow 80 - 35 - ns Input data hold time tou 0 - 0 - ns Write to Output floating twuz "O - 60 - 30 ns Output Active from end to wirte tow 5 - 5 - ns %*1 = Test Conditions %*2 Test Conditions 1. Input pulse level: 0.6V to 2.4V(5V)/0.4V to 2.2V(3V) 1. Input pulse level : 0.6V to 2.4V(5v)/0.4V to 2.2V(3v) 2. tr=t=5ns 2. tr=tt5ns 3. Input and output timing reference levels : 1.5V 3. Input timing reference levels: 1.5V 4. Outputload CL=100pF 4. Output timing reference levels: +200mV (the level displaced from stable output voltage level) 5. Output load CL=5pF 1TTL 1TTL /O0 tT | 0 /O90 Tr | oO L L CL=100pF (Includes Jig Capacitance) CL=5pF(Includes Jig Capacitance) @ Timing chart O Read Cycle*' O Write Cycle (1) (CS Control)*? ADDRESS ADDRESS as cs OE We Dour Dour Din Note : O Write Cycle(2)(WE Control)*? *1 During read cycle time, WE is to be "H" level. ADDRESS cs Dout Din *2 %*3 During write cycle time that is controlled by CS, Output Buffer is in high impedance state, whether OE level is "H" or "L" During write cycle time that is controlled by WE, Output Buffer is in high impedance state if OE is "H" level.EPSON @ DATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (Vgg=0V, Ta=0 to 70C) Parameter Symbol Conditions Min. Typ.*1| Max. | Unit Data retention Supply voltage Vppr 2.0 - 5.5 Vv Data retention current IDpR Vop-3V, 2 - * CS2Vpp_0.2V 0.5 | 25(4%)) HA Chip select data hold time tcpr - - ns Operation recovery time tr - - ms *1 > Typical values are measured at 25C %*2 Typical values are measured at 40C Data retention timing Data hold mode Voo 27V 27 VoprR22.0V tcpr iR Cs Vin CS>Vpp-0.2V Vin Note: During standby mode in which the data is retentive, the supply voltage (Vp, can) be in low voltage until Voo.=Voor. At this mode data reading and writing are impossible. mM FUNCTIONS @ Truth Table os) OE WE AO to A14 DATA I/O Mode lbp H X xX - Hi-Z Standby Ipps. Ipps1 L X L Stable Din Write lppa. !ppat L L H Stable Dout Read lppa. !ppat L H H Stable Hi-Z Output disable Ippa. Ippad xX : "hye or "LN : "H", op" or "Hi-Z" @ Read Mode The data appear when the address is setted while holding CS="L", OE="L" and WE="H".When OE="H", DATA I/ O terminals are in high impedance state, that makes circuit design and bus control easy. @ Write Mode There are the following 3 ways of writing data into memory. (1) Hold CS="L" and WE="L", set address (2) Hold CS="L" then set address and give "L"pulse to WE. (3) After setting addresses, give "L" pulse to both CS and WE. In above any case data on the DATA I/O terminals are latched up into the chip when CS or WE is in positive- going. Since DATA I/O terminals are high impedance when CS or OE="H", bus contention between data driver and memory outputs can be avoided. @ Standby Mode When CS is "H" the chip become in the stand-by mode. In this mode, DATA I/O terminals are high impedance and all inputs of addresses, WE and data can be any "H" or "L". When CS is over than VpD-9.2V, the chip is in the data retention battery back-up mode, in this case, there is a small current in the chip which flow through the high resistances of the memory cells.m@ PACKAGE DIMENSIONS SRM2AL256LLM Plastic TSOP( | )-28pin 13.4108 0.828351 11.8292 (0.456338) ie 8 nN INDEX S a8 DDO TTT Te ~ Ico 7 gio2 (0.315#0007) Plastic TSOP (| )-28pin-R1 ~ o INDEX he Ba M00 TOTO TTT gio2 (0.315#0007) ie 8 Unit : mm (inch) Plastic SOP2-28pin (.Fi2me) (0.701 8B) LODO 0 N00 01 D DODTIOOOO OTL [ \ TO @ o%) (0 16388) Unit : mm (inch) @ CHARACTERISTICS CURVES Normalized Ippa-Ta Normalized Ippateyc Normalized IlppaVop Ta 0 10 20 30 40 50 60 70 80 (C) .0 10 50 100 200 teyc Taa25C 4 teyc=Min. 2.5 | LL 2.0 Re 1.5 A Ll Abn 150ns 1.0 3.0 05 Fo 0.0 5001000 2000 2 3 4 5 6 7 8 (ns) Vopp (V)EPSON SRM2AL256LLM Normalized IppsiTa Vop=5.5V CS=Vpp-0.2V 10.0 = 5.0 1.0 0.5 0.1 Normalized Ipbps1Vpp loH-VoH (mA) -14 Voo=4.5V Normalized tacc, tacs-Ta 0.7 0 10 20 30 40 50 60 708 Ta (C) Normalized tacc, tacs-VDD 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Vpp 7) lo--VoL 0.0 0.2 0.4 0.6 0.8 VoL So NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. Seiko Epson Corporation 1997 All right reserved. SEIKO EPSON CORPORATION [ELECTRONIC DEVICE MARKETING DEPARTMENT | IC Marketing & Engineering Group 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5816 FAX: 0425-87-5624 International Marketing Derpartment | (Europe, U.S.A.) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5812 International Marketing Derpartment II (Asia) 421-8 Hino, Hino-shi, Tokyo 191, JAPAN Phone: 0425-87-5814 FAX: 0425-87-5564 FAX: 0425-87-5110 First issue December, 1994) Revised January, 1997