SDLS032G − DECEMBER 1983 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DConvert TTL Voltage Levels to MOS Levels
DHigh Sink-Current Capability
DInput Clamping Diodes Simplify System
Design
DOpen-Collector Driver for Indicator Lamps
and Relays
DInputs Fully Compatible With Most TTL
Circuits
description/ordering information
These TTL hex buffers/drivers feature
high-voltage open-collector outputs for interfacing
with high-level circuits (such as MOS) or for
driving high-current loads (such as lamps or
relays) and also are characterized for use as
buffers for driving TTL inputs. The SN5407 and
SN7407 have minimum breakdown voltages of
30 V, and the SN5417 and SN7417 have
minimum breakdown voltages of 15 V. The
maximum sink current is 30 mA for the SN5407
and SN5417 and 40 mA for the SN7407 and
SN7417.
These devices perform the Boolean function
Y = A in positive logic.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
Tube SN7407D
7407
SOIC − D
Tape and reel SN7407DR 7407
SOIC − D Tube SN7417D
7417
0°C to 70°C
Tape and reel SN7417DR 7417
0°C to 70°C
PDIP − N
Tube
SN7407N SN7407N
PDIP − N Tube SN7417N SN7417N
SOP − NS
Tape and reel
SN7407NSR SN7407
SOP − NS Tape and reel SN7417NSR SN7417
CDIP − J
Tube
SNJ5407J SNJ5407J
−55°C to 125°C
CDIP − J Tube SNJ5417J SNJ5417J
−55°C to 125°CCFP − W Tube SNJ5407W SNJ5407W
LCCC − FK Tube SNJ5407FK SNJ5407FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN5407, SN5417 ...J OR W PACKAGE
SN7407, SN7417 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
SN5407 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
3212019
910111213
4
5
6
7
8
18
17
16
15
14
6Y
NC
5A
NC
5Y
2A
NC
2Y
NC
3A
1Y
1A
NC
4Y
4A 6A
3Y
GND
NC VCC
*"!-('%& '!#*,$% %! 4565 $,, *$"$#)%)"& $") %)&%)-
(,)&& !%/)"1&) !%)-. $,, !%/)" *"!-('%& *"!-('%!
*"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&.
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize
transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average
propagation delay time is 14 ns.
logic diagram, each buffer/driver (positive logic)
AY
schematic
Resistor values shown are nominal.
6 kΩ
Input A
Output Y
GND
VCC
3.4 kΩ1.6 kΩ
100 Ω
1 kΩ
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN5417, SN7417 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN NOM MAX UNIT
VCC
Supply voltage
SN5407, SN5417 4.5 5 5.5
V
VCC Supply voltage SN7407, SN7417 4.75 5 5.25 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VOH
High-level output voltage
SN5407, SN7407 30
V
VOH High-level output voltage SN5417, SN7417 15 V
IOL
Low-level output current
SN5407, SN5417 30
mA
IOL Low-level output current SN7407, SN7417 40 mA
TA
Operating free-air temperature
SN5407, SN5417 −55 125
°C
TAOperating free-air temperature SN7407, SN7417 0 70 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIK VCC = MIN, II = −12 mA −1.5 V
IOH
VCC = MIN,
VIH = 2 V
VOH = 30 V (SN5407, SN7407) 0.25
mA
IOH VCC = MIN, VIH = 2 V VOH = 15 V (SN5417, SN7417) 0.25 mA
IOL = 16 mA 0.4
V
OL
V
CC
= MIN, V
IL
= 0.8 V IOL = 30 mA (SN5407, SN5417) 0.7 V
VOL
VCC = MIN,
VIL = 0.8 V
IOL = 40 mA (SN7407, SN7417) 0.7
V
IIVCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VIH = 2.4 V 40 µA
IIL VCC = MAX, VIL = 0.4 V −1.6 mA
ICCH VCC = MAX 29 41 mA
ICCL VCC = MAX 21 30 mA
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tPLH
A
Y
RL = 110 Ω,
CL = 15 pF
6 10
ns
tPHL A
Y
R
L
= 110
Ω
,
C
L
= 15 pF
20 30 ns
tPLH
A
Y
RL = 150 Ω,
CL = 50 pF
15
ns
tPHL A
Y
R
L
= 150
Ω
,
C
L
= 50 pF
26 ns
SDLS032G − DECEMBER 1983 − REVISED MAY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
RL
Test Point
VCC
LOAD CIRCUIT
1.5 V 1.5 V
High-Level
Pulse
1.5 V 1.5 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE WIDTHS
NOTES: A. CL includes probe and jig capacitance.
B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf≤ 7 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
1.5 V 1.5 V
Input
tPLH
In-Phase
Output
3 V
0 V
1.5 V 1.5 V VOH
VOL
tPHL
1.5 V 1.5 V VOH
VOL
tPHL tPLH
Out-of-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2007, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
JM38510/00803BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
JM38510/00803BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN5407J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SN5417J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SN7407D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407J OBSOLETE CDIP J 14 TBD Call TI Call TI
SN7407N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7407N3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN7407NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7407NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7407NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7417N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7417N3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN7417NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SNJ5407FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ5407J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ5407W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SNJ5417J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN7407DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7407DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7407NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN7417DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7407DR SOIC D 14 2500 346.0 346.0 33.0
SN7407DR SOIC D 14 2500 333.2 345.9 28.6
SN7407NSR SO NS 14 2000 346.0 346.0 33.0
SN7417DR SOIC D 14 2500 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
