100-MHz Pentium® II Clock Synt hesizer/Driver with
Spread S pectrum for Mo bile or Desktop PCs
CY2280
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
A pril 10, 2000, Rev. *D
Features
• Mixed 2.5V and 3.3V operatio n
• Clock sol uti on for P entium® II , and oth er similar pr o-
cessor-based motherboards
— Four 2.5V CP U cl o cks u p t o 10 0 M H z
—E ight 3.3V sync. PCI cloc ks, one free-runn ing
—Two 3.3V 48-MHz USB clocks
—Three 3. 3V Ref. c locks at 14.3 18 MHz
—Two 2.5V APIC clocks at 14.318 MHz or PCI/2
• EMI control
—S pread spec trum clocking
—Factory-EPROM programm able sprea d spectrum
margin
—Factory-EPROM programmable output drive and
sl ew ra te
• Factory-EPROM programmable CPU clock frequencies
for custom confi gurations
• Available in space-saving 48-pin SSOP package
Functional Descri pti on
The CY2280 i s a Spread Spect rum clock s ynthesiz er/driv er f or
a Pentium II, or other similar processor-based PC requiring
100-MHz support. All of the r equired sy stem cloc ks are provi d-
ed in a spac e-sa vi ng 48-pi n SSOP pac kage. The CY228 0 can
be used with the CY231x for a total solution for systems with
SDRAM.
The CY2280 provides the option of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percent age is int roduced when th e SEL_ SS input i s asserted.
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreadi ng is
EPR OM-programmable to opt imize EMI-redu ction.
The CY2280 has power-down, CPU stop, and PCI stop pins
for power man agem ent control. The signals are synchr onized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock out-
puts are dr iven LOW. When the PCI_STOP input is ass e rted,
the PCI clock outputs (except the free-running PCI clock) are
driven LOW. When the PWR_DWN pin is asser ted, the refer-
ence oscillator and PLLs are shut down, and all outputs are
driv en LOW.
CY2280 Selector Guide CY2280 Configuration Options
Clock Outputs -1 -11S -12S -13S -21S - 31S
CPU (66.6, 100 MHz) 4 4 4 4 4 4
PCI (CPU/2, CPU/3) 888888
USB (48 MHz) 222222
APIC (14.318 MHz) 2 2 2 2 -- 2
APIC (PCI/2) --------2--
Reference (14.318 MHz)333333
CPU-PCI delay 1.5−4.0 ns 1.5−4.0 ns 1.5−4.0 ns 1.5−4.0 ns 1. 5−4.0 ns 0 ns
CPU-APIC delay -- -- -- -- 2.0–4. 5 ns --
Spread Spectrum
(Downspread) N/A −0.6% −1.0% −1.5% −0.6% −0.6%
Pen tium is a registered trademark of Intel Co rporation .
Logic Bloc k Diagram
EPROM
XTALOUT
XTALIN
APIC [0:1]
14.318
MHz
OSC.
SEL0
V
DDAPIC
CPU
PLL
SEL100
Delay
REF [0-2]
CPUCLK [0-3]
V
DDCPU
PCI [1-7]
PCICLK_F
STOP
STOP
LOGIC
LOGIC
SEL1
USBCLK [0:1]
SYS PLL
CPU_STOP
PWR_DWN
Divider
PCI_STOP V
DDPCI
V
DDPCI
V
DDREF
V
DDUSB
-1
-2
SEL_SS
2
CY2280
Pin Sum mar y
Name Pins Description
VDDPCI 15, 9 3.3V Digital voltage suppl y for PCI cloc ks
VDDUSB 21 3.3V Di git al voltag e supply for USB clocks
VDDREF 48 3.3V Di git al voltage supply for REF clocks
VDDAPIC 46 2.5V Digital voltag e supply for APIC clocks
VDDCPU 41, 37 2.5V Di git al voltag e supply for CPU clocks
AVDD 33, 19 Analog voltage supply, 3.3V
VSS 3, 6, 12, 18, 20, 24, 32, 34, 38 , 43 Ground
XTALIN[1] 4Reference crystal i nput
XTALOUT[1] 5Reference crystal feedback
PCI_STOP 31 Acti ve LOW con t r ol i n pu t to st op P C I cl ocks
CPU_STOP 30 Active LOW control inp ut t o stop CPU clocks
PWR_DWN 29 Acti ve LOW control inp ut to pow er down device
SEL_SS 28 Spread spect rum select input (-11S, -12S, -13S, -21S , -31S options)
N/C 28 Spread spectr um select input (-1 opt ion)
SEL0 27 CPU frequency se lect input , bi t 0 (see Functio n Table)
SEL1 26 CPU frequency se lect input , bi t 1 (see Functio n Table)
SEL100 25 CPU frequency select input, selects bet ween 100 MHz and 66.6 MH z
(see Function Table)
CPUCLK[0:3] 40, 39, 36, 35 CPU clock outputs
PCICLK[1:7] 8, 10, 11, 13, 14, 16, 17 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz
or 100 M Hz respectively
PCICLK_F 7Free-running PCI clock output
APIC[0:1] 45, 44 APIC cl ock outputs
REF[0:2] 1, 2, 47 3.3V Reference clock outputs
USBCLK[0:1] 22, 23 USB clock outputs
RESERVED 42 Reserved
Note:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
Pin Configurations 1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
REF0
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF1
VSS
XTALIN
XTALOUT
PCICLK_F
VSS
PCICLK1
PCICLK2
VDDPCI
PCICLK3
VSS
PCICLK4
VDDPCI
PCICLK5
PCICLK7
VSS
AVDD
VSS
VDDUSB
USBCLK0
USBCLK1
VSS
VDDREF
REF2
VDDAPIC
APIC0
APIC1
VSS
RESERVED
VDDCPU
CPUCLK0
CPUCLK1
VSS
VDDCPU
CPUCLK2
CPUCLK3
VSS
AVDD
PCI_STOP
PWR_DWN
N/C
SEL0
SEL1
SEL100
CPU_STOP
VSS
PCICLK6
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
REF0
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF1
VSS
XTALIN
XTALOUT
PCICLK_F
VSS
PCICLK1
PCICLK2
VDDPCI
PCICLK3
VSS
PCICLK4
VDDPCI
PCICLK5
PCICLK7
VSS
AVDD
VSS
VDDUSB
USBCLK0
USBCLK1
VSS
VDDREF
REF2
VDDAPIC
APIC0
APIC1
VSS
RESERVED
VDDCPU
CPUCLK0
CPUCLK1
VSS
VDDCPU
CPUCLK2
CPUCLK3
VSS
AVDD
PCI_STOP
PWR_DWN
SEL_SS
SEL0
SEL1
SEL100
CPU_STOP
VSS
PCICLK6
CY2280-1
CY2280-11S
CY2280-12S
CY2280-13S
CY2280-21S
CY2280-31S
48-pin SSOP (Top View)
48-pin SSOP (Top View)
3
CY2280
Function Table (-11S, -12S, -13S, -31S Options)
SEL100 SEL1 SEL0 SEL_SS[2] CPU/PCI
Ratio CPUCLK PCICLK_F
PCICLK REF APIC USBCLK
0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 1 N /A 2 Reserved Reserved 14.318 MH z 14.318 MH z 48 MHz
0 1 0 N /A 2 Reserved Reserved 14.318 MH z 14.318 MH z 48 MHz
0 1 1 0 (downspr ead) 2 66.66 MHz 33.33 MHz 14.318 MH z 14.318 MH z 48 MHz
0 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MH z 14.318 MH z 48 MHz
1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK[3] TCLK/2
1 0 1 N /A 3 Reserved Reserved 14.318 MH z 14.318 MH z 48 MHz
1 1 0 N /A 3 Reserved Reserved 14.318 MH z 14.318 MH z 48 MHz
1 1 1 0 (downspr ead) 3 100 MHz 33.33 MHz 14.318 M H z 14.318 MH z 48 MHz
1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14. 318 MH z 14.318 MH z 48 MHz
Function Table (-21S Option)
SEL100 SEL1 SEL0 SEL_SS[2] CPU/PCI
Ratio CPUCLK PCICLK_F
PCICLK REF APIC USBCLK
0 0 0 N/A 2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 1 N /A 2 Reserved Reserved 14.318 M Hz Reserved 48 MHz
0 1 0 N /A 2 Reserved Reserved 14.318 M Hz Reserved 48 MHz
0 1 1 0 (downspr ead) 2 66.66 MHz 33.33 MHz 14.318 MH z 16.67 MHz 48 MHz
0 1 1 1 (no spread) 2 66.66 MHz 33.33 MHz 14.318 MH z 16.67 MHz 48 MHz
1 0 0 N/A 3 TCLK/2 TCLK/6 TCLK[3] TCLK/12[3] TCLK/2
1 0 1 N /A 3 Reserved Reserved 14.318 M Hz Reserved 48 MHz
1 1 0 N /A 3 Reserved Reserved 14.318 M Hz Reserved 48 MHz
1 1 1 0 (downspr ead) 3 100 MHz 33.33 MHz 14.318 M H z 16.67 MHz 48 MHz
1 1 1 1 (no spread) 3 100 MHz 33.33 MHz 14. 318 MH z 16.67 MHz 48 MHz
Actual Clock Frequency Values
Clock Output Target Frequency
(MHz) Actual Frequency
(MHz) PPM
CPUCLK 66.67 66.654 –195
CPUCLK 100 99.77 –2346
USBCLK 48.0 48.008 167
Power Management Logic
CPU_STOP PCI_STOP PWR_DWN CPUCLK PCICLK PCICLK_F Other
Clocks Osc. PLLs
X X 0 Low Low Low Low Off Off
0 0 1 Low Low Running Running Running Running
0 1 1 Low Running Running Running Running Running
1 0 1 Running Low Running Running Running Running
1 1 1 Running Running Running Running Running Running
Notes:
2. Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.
3. TCLK supplied on the XTALIN pin in Test Mode.
4
CY2280
Maximum Ratings
(Above which the usefu l l ife ma y be impaired. For user guide-
li nes, not tested .)
Su pply Vol ta g e.......... ..... ..... ....... ..... ..... ....... ..... .–0.5 to +7.0V
Input Voltage......... ..... .. ........ .................... ..–0.5V to VDD+0.5
Storage Tempera tur e (Non-Condensing)... –65°C to +150°C
Max. Solderi ng Temperature (10 sec. ).... .. ............ ... +260°C
Junction Temperature............................................... +150°C
P ackage Pow er Di ssipation........... .. ........ ................. ........1W
Static Discharge Voltage..... ..... ..... .. ..... ..... ..... .. ..... ....>2000V
(per MIL- STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[4]
Parameter Description Min. Max. Unit
AVDD, VDDPCI,
VDDUSB, VDDREF Analog and Digit al Supply Voltage 3.135 3.465 V
VDDCPU CPU Supply Vol tage 2.375 2.625 V
VDDAPIC APIC Supply Volt age 2.375 2.625 V
TAOperating Temperature, Ambient 0 70 °C
CLMax. Capacitive Load on
CPUCLK
PCICLK
APIC, REF
USB
20
30
20
20
pF
f(REF) Reference Frequency, Osci ll ator Nominal Value 14.318 14.318 MHz
Electrical Characteristics O ver the Operating Range
P arameter Desc ri ption Test Conditi ons Min. Max. Unit
VIH High-level Input Voltage Except Crystal Input s[5] 2.0 V
VIL Low-level Input Voltage Except Crystal Inputs[5] 0.8 V
VOH High -l evel Output Voltage [6] VDDCPU = VDDAPIC = 2.375V IOH = 12 mA CPUCLK 2.0 V
IOH = 18 mA APIC
VOL Low-level Output Voltage[6] VDDCPU = VDDAPIC = 2.375V I OL = 12 mA CPUCLK 0.4 V
IOL = 18 mA API C
VOH High -l evel Output Voltage [6] VDDPCI, AVDD, VDDREF
, VDDUSB = 3.135V IOH = 14.5 mA PCICLK 2.4 V
IOH = 16 mA USBCLK
IOH = 16 mA REF
VOL Low-level Output Voltage[6] VDDPCI, AVDD, VDDREF
, VDDUSB= 3.135V IOL = 9.4 mA PCICLK 0.4V V
IOL = 9 mA USBCLK
IOL = 9 mA REF
IIH Input High Curr ent VIH = VDD –10 +10 µA
IIL Input Lo w Curr ent VIL = 0V 10 µA
IOZ Output Leakage Current Three-state –10 +10 µA
IDD25 Po wer Supply Current for
2.5V Clocks[6] VDDCPU = 2.625 V , VIN = 0 or VDD, Lo aded Output s, CPU = 66 .6 MH z 70 mA
IDD25 Po wer Supply Current for
2.5V Clocks[6] VDDCPU = 2. 625V, VIN = 0 or VDD, Loaded Outp uts, CPU = 100 MHz 100 mA
IDD33 Po wer Supply Current for
3.3V Clocks[6] VDD = 3 .465V, VIN = 0 or VDD, Loaded Outputs 170 mA
IDDS Power-down Current[6] Current draw in power-down state 500 µA
Notes:
4. Electrical parameters are guaranteed with these operating conditions.
5. Crystal Inputs have CMOS thresholds.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
CY2280
Switching Characteristics[6, 7]
Parameter Output Description Test Conditions Min. Typ. Max. Unit
t1All O utput Duty Cycle[8] t1 = t1A ÷ t1B 45 50 55 %
t2CPUCLK,
APIC CPU and APIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V -1,-11S,
-12S,-13S,
-21S only
1.0 4.0 V/ns
-31S only 0.8 4.0 V/ns
t2PCICLK PCI Cloc k Rising and
Falling Edge Rate Between 0.4V and 2.4V -1,-11S,
-12S,-13S,
-21S only
1.0 4.0 V/ns
-31S only 0.9 4.0 V/ns
t2USBCLK,
REF USB, REF Rising and
Falling Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns
t3CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V -1,-11S,
-12S,-13S,
-21S only
0.4 1.6 ns
-31S only 0.4 2.0 ns
t4CPUCLK CPU Clock F al l Ti me Between 2. 0V and 0.4V -1,-11S,
-12S,-13S,
-21S only
0.4 1.6 ns
-31S only 0.4 2.0 ns
t5CPUCLK CPU-CPU Clock Skew Measured at 1.25V 100 175 ps
t6CPUCLK,
PCICLK CPU-PCI Clock Skew[9] Measured at 1.25 V for 2. 5V
clocks, and at 1.5V f or 3.3V
clocks
-1,-11S,
-12S,-13S,
-21S only
1.5 4.0 ns
-31S only –1 1 ns
t7PCICLK,
PCICLK PCI-PCI Clo ck Skew Measured at 1. 5V 250 ps
t8CPUCLK,
APIC CPU-APIC Clock
Skew[10] Measured at 1.25V for 2.5V
clocks -21S only 2.0 4.5 ns
t9APIC APIC-APIC Clock Skew Measured at 1.25V 100 175 ps
t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V -1,-11S,
-12S,-13S,
-21S only
200 250 ps
-31S only 250 350 ps
t11 PCICLK Cycle-Cycle Clock Jitt er Measured at 1.5V 250 500 ps
t12 CPUCLK,
PCICLK Po wer-up Time CPU, PCI cloc k stabiliz ati on from
power-up 3ms
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S, -12S, -13S, -14S, -21S options.
10. APIC lags CPU for -21S option.
6
CY2280
Swi tchi n g Wavef o rms
Duty Cycle Timing
t1A t1B
OUTPUT
All Outp uts Ri se/Fall Time
OUTPUT
t2
t3
VDD
0V
t2
t4
CPU-CPU Clock Skew
t5
CPUCLK
CPUCLK
CPU-PCI Clock Skew
t6
CPUCLK
PCICLK
t7
PCICLK
PCICLK
PCI-PCI Clock Skew
t8
CPUCLK
APIC
CPU-APIC Clock Skew (-2 1S only)
7
CY2280
Swi tchi n g Wavef o rms (continued)
t9
APIC
APIC
APIC-APIC Clock Skew
CPU_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
PCI_STOP
PCICLK
(External)
(Free-Running)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
PCICLK
CPUCLK
(External)
(External)
VCO
Crystal
Shaded section on the V CO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
8
CY2280
Frequency (MHz)
Amplitude (dB)
Spread Spectrum Enabled
Spread Spectrum Disabled
SPREAD SPECTRUM CLOCKING
Description Max. Unit
Outputs Min.
Down Spread Margin at the Fundamental Frequency −0.6 %
Modulati on Frequency
CPU, PCI
30.0 33.0 kHz
0.0
Configuration
Al l (except -1)
Down Spread Margi n at t he Fundam ental Frequency
Down Spread Margi n at t he Fundam ental Frequency
Down Spread Margi n at t he Fundam ental Frequency
CPU, PCI
CPU, PCI
CPU, PCI, APIC
−1.0 %
0.0
−1.5 %
0.0
−0.6 %
0.0
-11S, -3 1S
-12S
-13S
-21S
9
CY2280
Application Information
Clock traces must be t erminated with either ser ies or paralle l termination, as they are normally done.
Application Circuit
Summary
•A parallel- resonant crystal should be used as the reference to t he clock generator. The operati ng frequency and CLO AD of
this crystal should be as specified in the data sheet. O pti onal trimming capacitors m ay be needed if a crystal with a different
CL OAD is us e d. Footprin t s mus t b e laid ou t for flexibilit y.
•Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.
In some ca ses, smaller value capacitors may be requi red.
•The value of the series t erminating resi stor sati sfies the f ollow ing equation, where Rtrace is the loaded characterist ic imped-
ance of t he tr ace , Rout is the output i mped ance of t he cloc k generat or (sp eci fied in t he da ta sheet ), and Rs eries i s the series
terminating resistor.
Rseries > Rtrace – Rout
•F ootprints must be laid out for optional EM I-reducing capacitor s, which should be placed a s close to the terminating resistor
as is physicall y possible. Typical values of these ca pacitors range from 4.7 pF to 22 pF.
•A Fer rite Bead may be used to isol ate the Boar d VDD from the cloc k generato r VDD island . Ensure that the F errite Bead off ers
great er t han 50Ω impedance at the cloc k fr equency, under loaded DC conditions . Please ref er to the applicat ion note “Layout
and Termination Techniques for Cypress Clock Generators” f o r more de ta ils.
•If a F errite Bead is used, a 10 µF–22 µF tantal um by pass capacit or should be plac ed close to the F errite Bead. Thi s capacitor
prevents power supply droop during current surges.
10
CY2280
Document #: 38-00694-D
Test Circuit
3, 6, 12, 18, 20, 24, 32, 34, 38, 43
9, 15, 19, 21, 33, 48
VDDPCI, V DDCORE,
CLOAD
OUTPUTS
0.1 µF
0.1µF
VDDCPU, VDDAPIC
Notes:
CY2280
37, 41, 46
Each supply pin must have an individual decoupling capacit or
All capacitors m ust be placed as cl ose to the pins as is possible.
VDDUSB, VDDREF
Orde ring Information
Ordering Code P ackage Name Package Type Operati ng Range
CY2280PVC-1 O48 48-Pin SSOP Commercial
CY2280PVC-11S O48 48-Pin SSOP Commercial
CY2280PVC-12S O48 48-Pin SSOP Commercial
CY2280PVC-13S O48 48-Pin SSOP Commercial
CY2280PVC-14S O48 48-Pin SSOP Commercial
CY2280PVC-21S O48 48-Pin SSOP Commercial
CY2280PVC-31S O48 48-Pin SSOP Commercial
CY2280
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi condu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra m
48-Lead Shrunk Small Outline Package O48
51-85061-B
