18-Bit Registered Transceive
r
CY74FCT163500
SCCS066 - June 1997 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Low power, pin-compatible replacement for LCX and
LPT families
• 5V tolerant inputs and outputs
• 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.6 ns
• Latch-up performance exceeds JEDEC standard no. 17
• ESD > 2000V per MIL-STD-883D, Method 3015
• Typical output skew < 250ps
• Industrial temperature range of –40˚C to +85˚C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical Volp (ground bounce) performance exceeds Mil
Std 883D
•V
CC = 2.7V to 3.6V
Functional Description
The CY74FCT163500 is an 18-bit universal bus transceiver
that can be operated in transparent, latched, or clock modes
by combining D-type latches and D-type flip-flops. Data flow in
each direction is controlled by output-enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock inputs
(CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is HIGH. When
LEAB is LOW, the A data is latched if CLKAB is held at a HIGH
or LOW logic level. If LEAB is LOW, the A bus data is stored in
the latch/flip-flop on the HIGH-to-LOW transition of CLKAB.
OEAB performs the output enable function on the B port. Data
flow from B-to-A is similar to that of A-to-B and is controlled by
OEBA, LEBA, and CLKBA.
The CY74FCT163500 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce.The inputs
and outputs are capable of being driven by 5.0V busses,
allowing them to be used in mixed voltage systems as
translators. The outputs are also designed with a power off
disable feature enabling them to be used in applications
requiring live insertion.
GND
LogicBlockDiagram Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
OEAB
34
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
LEAB
A1
A2
A3
B1
B2
B3
GND
GND
GND
VCC
A6
A7
A4
A5
B4
B5
B6
B7
VCC
GND
A10
A11
A8
A9
B8
B9
B11
B12
GND
A12
VCC
A16
GND
A14
VCC
A15
A17
TO 17 OTHER CHANNELS
LEAB
OEBA
LEBA
CLKAB
CLKBA
OEAB
C
D
C
D
C
D
C
D
A1B1
25
26
27
28
49
52
51
50
A13
OEBA
LEBA
GND
A18
CLKAB
53
56
55
54
B10
GND
B14
B15
B13
B16
B17
GND
B18
CLKBA
CY74FCT163500
2
Maximum Ratings[5, 6]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ................................ −55°C to +125°C
Ambient Temperature with
Power Applied................................................. −55°C to +125°C
Supply Voltage Range..................................... 0.5V to +4.6V
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation..........................................................1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance. = HIGH-to-LOW Transition.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, andCLKBA.
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LO W bef ore LEAB went LO W.
5. Operation beyond the limits set forth may impair the useful life of the device. Unless noted, these limits are over the operating free-air temperature range.
6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
Pin Summary
Name Description
OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input (Active LOW)
CLKBA B-to-A Clock Input (Active LOW)
A A-to-B Data Inputs or B-to-A Three-State Outputs
B B-to-A Data Inputs or A-to-B Three-State Outputs
Function Table[1, 2]
Inputs Outputs
OEAB LEAB CLKAB A B
L X X X Z
H H X L L
H H X H H
H L L L
H L H H
H L H X B[3]
H L L X B[4]
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 2.7V to 3.6V
CY74FCT163500
3
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter Description Test Conditions Min. Typ.[7] Max. Unit
VIH Input HIGH Voltage All Inputs 2.0 5.5 V
VIL Input LOW Voltage 0.8 V
VHInput Hysteresis[8] 100 mV
VIK Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=5.5V ±1µA
IIL Input LOW Current VCC=Max., VI=GND. ±1µA
IOZH High Impedance Output Current
(Three-State Output pins) VCC=Max., V OUT=5.5V ±1µA
IOZL High Impedance Output Current
(Three-State Output pins) VCC=Max., V OUT=GND ±1µA
IODL Output LOW Current[9] VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V 45 180 mA
IODH Output HIGH Current[9] VCC=3.3V, VIN=VIH
or VIL, VOUT=1.5V –45 –180 mA
VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V
VCC=3.0V, IOH= –8 mA 2.4 3.0 V
VCC=3.0V, IOH= –24 mA 2.0 3.0 V
VOL Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V
VCC=Min., IOL= 24 mA 0.3 0.5
IOS Short Circuit Current[9] VCC=Max., VOUT=GND –60 –135 –240 mA
IOFF Power-Off Disable VCC=0V, V OUT≤4.5V ±100 µA
Capacitance[8] (TA = +25˚C , f = 1.0 MHz)
Parameter Description Test Conditions Typ.[7] Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6.0 pF
COUT Output Capacitance VOUT = 0V 5.5 8.0 pF
Notes:
7. Typical values are at VCC=3.3V, TA = +25˚C ambient.
8. This parameter is specified but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
CY74FCT163500
4
Power Supply Characteristics
Parameter Description Test Conditions Typ.[7] Max. Unit
ICC Quiescent Power Supply Cur-
rent VCC=Max. VIN≤0.2V,
VIN≥VCC−0.2V 0.1 10 µA
∆ICC Quiescent Power Supply Cur-
rent (TTL inputs HIGH) VCC=Max. VIN=VCC–0.6V[10] 2.0 30 µA
ICCD Dynamic Power Supply
Current[11] VCC=Max.,OneInputToggling,
50%DutyCycle,OutputsOpen,
OEAB=OEBA=VCC or GND
VIN=VCC or
VIN=GND 50 75 µA/MHz
ICTotal Power Supply Current[12] VCC=Max., f0=10 MHz
(CLKAB), f1=5 MHz, 50% Duty
Cycle, Outputs Open,
One Bit Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND 0.5 0.8 mA
VIN=VCC–0.6V o r
VIN=GND 0.5 0.8 mA
VCC=Max., f0=10 MHz,
f1=2.5 MHz, 50% Duty
Cycle, Outputs Open,
Eighteen Bits Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND 2.5 3.8[13] mA
VIN=VCC–0.6V o r
VIN=GND 2.6 4.1[13] mA
Notes:
10. Per TTL driven input; all other inputs at V CC or GND .
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0NC/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
NC= Number of clock inputs changing at f1
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY74FCT163500
5
Switching Characteristics Over the Operating Range VCC = 3.0V to 3.6V[,14, 15]
CY74FCT163500A CY74FCT163500C
Fig. No.[16]
Parameter Description Min. Max. Min. Max. Unit
fMAX CLKAB or CLKBA frequency 150 150 MHz
tPLH
tPHL Propagation Delay
A to B or B to A 1.5 5.1 1.5 4.6 ns 1, 3
tPLH
tPHL Propagation Delay
LEBA to A, LEAB to B 1.5 5.6 1.5 5.3 ns 1, 5
tPLH
tPHL Propagation Delay
CLKBA to A, CLKAB to B 1.5 5.6 1.5 5.3 ns 1, 5
tPZH
tPZL Output Enable Time
OEBA to A, OEAB to B 1.5 6.0 1.5 5.4 ns 1, 7, 8
tPHZ
tPLZ Output Disable Time
OEBA to A, OEAB to B 1.5 5.6 1.5 5.2 ns 1, 7, 8
tSU Set-Up Time, HIGH or LOW
A to CLKAB, B to CLKBA 3.0 3.0 ns 9
tHHold Time, HIGH or LOW
A to CLKAB, B to CLKBA 0 0 ns 9
tSU Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA Clock HIGH 3.0 3.0 ns 4
Clock LOW 1.5 1.5 ns 4
tHHold Time, HIGH or LOW
A to LEAB, B to LEBA 1.5 1.5 ns 4
tWLEAB or LEBA Pulse Width HIGH 3.0 2.5 ns 5
tWCLKAB or CLKBA Pulse Width HIGH or LOW 3.0 3.0 ns 5
tSK(O) Output Skew[17] 0.5 0.5 ns
Ordering Information CY74FCT163500
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
4.6 CY74FCT163500CPACT Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT163500CPVC/PVCT O56 56-Lead (300-Mil) SSOP
5.1 CY74FCT163500APVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
CY74FCT163500
6
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
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Copyright 2000, Texas Instruments Incorporated
