SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 D Programmable Charging Current D Six Programmable Low-Dropout Linear features D Integrated, Single-Chip Solution for Battery D D D D D D Voltage Regulators Charge Control and Power Supply Management Linear Charger for Single-Cell Li-Ion or Li-Polymer Packs Integrated Control over Precharge, Constant-Current, and Constant-Voltage Charging Phases Programmable Charge Termination by Minimum Current and Time Battery Temperature Sensing Pack Wake-Up and Damaged Cell Detect Functions Safety Charge Timers During Precharge and Constant-Current Charging D Over 65-dB Power Supply Rejection Ratio D D D D D D D (PSRR) From 10 Hz to 10 kHz System Over- and Under-Voltage Shutdown Power On/Off and Reset Control Logic Three Individually Selectable LED Backlight Drivers Vibrator and Ringer Drivers Internal 8-Bit Analog-to-Digital Converter With Auxiliary Inputs I2C Control Interface and Three-Wire SPI Interface 48-Terminal Plastic TQFP (PFB) or MicroStar Junior BGA (GQE) Package description The TWL2214CA device is a single-chip battery and power management solution for wireless handsets, pagers, personal digital assistants (PDAs), and other battery-powered devices. For battery charging, the device incorporates a linear charger for single-cell Li-Ion and lithium polymer battery packs. Prior to charging, the TWL2214CA device initiates battery pack wake-up and damaged cell detect functions. For deeply discharged batteries, the device performs precharge conditioning by trickle charge to a user-defined current setting. Once an acceptable pack voltage is detected, the TWL2214CA device applies a constant-current fast charge at a current level that is determined by the combination of an external sense resistor and user-programmable sense voltage. When the battery reaches the selected charge regulation voltage, the TWL2214CA device maintains regulation until charging is terminated by a minimum current or a timer. During the entire charge cycle, the TWL2214CA device monitors temperature by external thermistor and suspends charging if temperature exceeds a programmed range. Three programmable safety timers limit the precharge, constant current, and total charge times. For power management, the TWL2214CA device includes six low-dropout linear voltage regulators. One regulator is driven from the device power-on/-off logic and incorporates a microcontroller reset function. Five low-noise regulators include individually programmable output voltage and enable-disable. The TWL2214CA device can be powered from a battery or from an ac adapter. When an adapter is present, it supplies power to the device, allowing the system to function without a battery. The TWL2214CA device also includes individually selectable drivers for three separate backlight LEDs, a ringer, and a vibrator motor. An internal 8-bit analog-to-digital converter (ADC) is accessible from external terminals. All TWL2214CA programming and status are accessed by the system microcontroller via the I2C/SPI serial interface. The TWL2214CA device is packaged in the Texas Instruments 48-terminal plastic thin quad flatpack (TQFP) (PFB) or the MicroStar Junior BGA (GQE) package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior BGA is a trademark of Texas Instruments Incorporated. Copyright 2002, Texas Instruments Incorporated ! "#$ ! %#&'" ( $) (#" ! " !%$"" ! %$ *$ $! $+! ! #$ ! ! (( , -) (#" %"$!!. ($! $"$!!'- "'#($ $! . '' %$ $!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 AVAILABLE OPTIONS OUTPUT VOLTAGE TA DEVICE NAME PACKAGE -40C to 85C TWL2214CAPFBR -40C to 85C TWL2214CAGQER INTERFACE REGULATOR 1 REGULATOR 6 TQFP 2.8 V 3V I2C MicroStar Junior BGA 2.8 V 3V I2C/SPI GQE PACKAGE (BOTTOM VIEW) J H G F E D C B A 2 3 4 5 6 7 8 9 IRQ CT GND RPRE VCHG ISENSE VG VG2 VDD VG3 VBAT REF 1 36 35 34 33 32 31 30 29 28 27 26 25 PWRKOUT PWRKIN PSH DATA CLK CD2 DGND VIOUT VDD5 RINGOUT RINGIN GND3 37 24 38 23 39 22 40 21 41 20 42 19 PFB PACKAGE (TOP VIEW) 43 18 44 17 45 16 46 15 47 14 13 48 2 3 4 5 6 7 8 9 10 11 12 IL0 IL1 IL2 SEL VDD1 VREG1 XRST AGND CD1 VREG6 VDD2 GND 1 TS ADCIN1 ADCIN2 CONT VREG5 VDD4 VREG4 BGRF GND2 VREG3 VDD3 VREG2 DISSIPATION RATING TABLE PACKAGE 2 TA = 25C POWER RATING OPERATING FACTOR ABOVE 25C TA = 70C POWER RATING TA = 85C POWER RATING GQE 1176 mW 11.8 mW/C 647 mW 471 mW PFB 1962 mW 15.7 mW/C 1256 mW 1020 mW POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 RPRE ADCIN2 TS ADCIN1 VBAT VG3 V DD ISENSE VG2 VG VCHG block diagram IRQ Battery Charger Control GND REF CT AGND VDD1 VREG1 GND REG1 Reference System BGRF Reset Control PWRKOUT XRST CD1 VDD2 PWRKIN REG6 Power On/Off Control PSH CD2 VREG6 CONT VDD3 REG2 CE VREG2 DATA I2C CLK REG3 DGND VREG3 VDD4 REG4 VREG4 LED Driver Ring Driver Vibrator Driver REG5 VREG5 POST OFFICE BOX 655303 VIOUT SEL RINGIN RINGOUT GND3 IL0 IL1 IL2 VDD5 GND2 * DALLAS, TEXAS 75265 3 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 Terminal Functions TERMINAL NAME ADCIN1 ADCIN2 GQE NO. PFB NO. J8 23 I/O DESCRIPTION I ADC input ADC input J7 22 I C4, D3, D4, E3, E4 8 I/O Regulator 1 ground BGRF J4 17 I/O Band gap output bypass capacitance CD1 F1 9 I/O XRST output delay adjustment capacitance CD2 A5 42 I/O Regulator 1 off delay adjustment capacitance CE A8 AGND I Clock enabled I2C/SPI bus serial clock input CLK B5 41 I CONT H6 21 I CT B9 35 I/O DATA A6 40 I/O External oscillator timing cap I2C/SPI bus serial address/data input output; this is a bidirectional terminal. DGND Regulator 6 is always on after power up except when CONT = H; regulator 6 is enabled through I2C interface. A4 43 I/O Digital ground GND C8, G2 12, 34 I/O Ground GND2 H4 16 I/O Ground for VREG2, VREG3, VREG4, and VREG5 GND3 B2 48 I/O Ground for vibrator, LED, and ringer IL0 B1 1 O 160-mA LED driver output IL1 C2 2 O 20-mA LED driver output IL2 C1 3 O 10-mA LED driver output IRQ B8 36 O Interrupt signal for external controller regarding to charger start/stop action ISENSE E9 31 I Current sense input for charger function PSH B6 39 I Power hold signal from controller PWRKIN A7 38 I Power-up start PWRKOUT B7 37 O Power-up signal for CPU REF H9 25 O Voltage reference during charge cycle, 3 V, IO = 3 mA RINGIN A2 47 I/O Input for ring driver RINGOUT B3 46 O Ring driver output RPRE C9 33 I/O Precharge current sense resistor SEL D2 4 I Input for vibrator output voltage change TS H8 24 I Battery temperature sense input voltage VBAT VCHG G8 26 I/O D9 32 I DC voltage input for charger VDD VDD1 Battery voltage sense input or output for precharge, wakeup F8 28 I Device dc supply feedback for charger function D1 5 I Device dc supply input and regulator 1 input VDD2 VDD3 G1 11 I Input to regulator 6 J2 14 I Input for regulators 2 and 3 VDD4 VDD5 J5 19 I Input for regulators 4 and 5 A3 45 I Input for vibrator, PN diode connection of ringer VG E8 30 O Gate control of an external P-FET for charger regulation VG2 F9 29 O Gate control of an external P-FET for battery blockage 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION GQE NO. PFB NO. VG3 G9 27 O Gate control of an external P-FET for charging action VIOUT B4 44 I/O Vibrator output VREG1 VREG2 E2 6 O Regulator 1 output H2 13 O Regulator 2 output J3 15 O Regulator 3 output H5 VREG3 VREG4 18 O Regulator 4 output VREG5 VREG6 J6 20 O Regulator 5 output F2 10 O Regulator 6 output XRST E1 7 O Reset output detailed description power-on/-off control The timing of the delayed power-on reset is controlled by the power-on/-off control circuit. There are two different conditions to power-on the device: manual power on and automatic power on. manual power on During the power-off state, after the power key is pressed, the PWRKIN signal becomes high and the output of VREG1 (regulator 1 output) is enabled. When the VREG1 output reaches 90% of its nominal output voltage, the TWL2214CA device starts the delayed reset process by charging the reset timing capacitor (CD1). When the voltage of CD1 reaches 1.2 V, the XRST signal is released by the TWL2214CA device and pulled high by an external pull-up resistor. The reset process is completed, and the external controller operates in normal condition. While PWRKIN remains high, the power-on condition remains active. Before PWRKIN goes low, the external controller must drive PSH high to retain power; otherwise, the TWL2214CA device starts the delay power-off process by charging timing capacitor CD2. After the voltage of CD2 reaches 1.2 V and no valid PSH signal is received, the device is powered off. automatic power on During the power-off state, after the adapter is attached, the output of VREG1 is automatically enabled. When VREG1 reaches 90% of its nominal output voltage, the TWL2214CA device starts the delayed reset process by charging the reset timing capacitor (CD1). When the voltage of the CD1 reaches 1.2 V, the XRST signal is released by the TWL2214CA device and pulled high by an external pull-up resistor. The reset process is completed and the external controller operates in normal condition. The external controller must drive PSH to high in time to retain power; otherwise, the TWL2214CA device starts the delay power-off process by charging timing capacitor CD2. After voltage of CD2 reaches 1.2 V and if no valid PSH signal is received, the device is powered off. During the on state, the device generates an output signal PWRKOUT with an inverted polarity to PWRKIN. An external controller can use PWRKOUT to sense whether the power key has been pressed. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 detailed description (continued) VG3 Battery Attachment VG2 VDD PWRKIN PWRKOUT 0.9 VOUT VREG1 CDI Delay CPU senses this falling edge and drives PSH to L CD1 XRST PSH CD2 Power Off Power On Figure 1. Power-On/-Off Sequence 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 detailed description (continued) Battery Attachment VG3 VG2 VDD A B A PWRKIN PWRKOUT VCHG Adapter Attachment 0.9 VOUT Adapter Attachment VREG1 CDI Delay CD1 XRST PSH CD2 A:VDD = VBAT B:VDD = 4.1 V or 4.2 V Auto power up with adapter insertion Figure 2. Adapter Powered (With Battery) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 detailed description (continued) VG3 VG2 VDD PWRKIN PWRKOUT VCHG Adapter Attachment 0.9 VOUT VREG1 CDI Delay CPU senses this falling edge and drives PSH to L CD1 XRST PSH CD2 Power down by power key insertion Auto power up with adapter insertion Figure 3. Adapter Powered (Without Battery) reset controller The reset controller performs two major functions: one is to control the timing of delayed power-on reset, and the other is to monitor the VREG1 level. The delay reset process is started when VREG1 reaches 90% of its nominal output voltage level. The delay time of the reset output (XRST) can be adjusted by an external timing capacitor (CD1). During the system active state when VREG1 drops below 0.9 x Vnominal - hysteresis, XRST is driven low. If VREG1 reaches 90% of its nominal output voltage level again, the delayed reset process is started over. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 detailed description (continued) VREG1 Hysteresis 0.9 VOUT XRST CD1 delay PSH CD1 CD2 To keep power-on condition PSH must be high within maximum CD2 delay. Figure 4. VREG1 Monitoring of Reset Control regulator 1 This regulator is automatically enabled after the power-on process is complete. It stays enabled until the power-off condition occurs. Regulator 1 supplies power to the microprocessor. The nominal output voltage is 2.8 V and the maximum output current is 150 mA. Regulator 1 requires an output capacitor in the range of 4.7 F to10 F with an ESR less than 6 . regulator 6 This regulator output voltage can be enabled by I2C by attaching CONT (terminal 21 or H6) to VDD. Attaching CONT to GND makes this regulator automatically enabled with power on. The output voltage is programmed by I2C. The maximum output current of 100 mA requires an output capacitor in range of 4.7 F to 10 F, with ESR in the range of 1 to 6 . The output voltage ranges from 2.5 V to 3 V. regulators 2, 3, 4, and 5 Regulators 2, 3, 4, and 5 are output voltages programmed and enabled by I2C. The output voltage ranges from 2.3 V to 3 V in 100-mV steps. The maximum output current for regulators 2 and 3 is 80 mA, for regulator 4 it is 120 mA, and for regulator 5 it is 150 mA. The default output voltage for all regulators is 3 V. These regulators have very low output noise (maximum 30 VRMS); they are suitable for powering up the RF block, which requires an output capacitor in the range of 4.7 F to 10 F with an ESR less than 6 . vibrator driver The TWL2214CA device has incorporated a vibrator driver with selectable output voltage and current. This integrated vibrator driver has the same features as the other LDO regulators. The vibrator is enabled by I2C. The output voltage can be selected by tying SEL (terminal 4 or D2) to VDD or GND. If SEL is tied to VDD, the output voltage is set to 3 V. If SEL is tied to GND, the output voltage is set to 1.3 V. LED driver The TWL2214CA device provides the capability of driving three LEDs. These drivers, enabled by I2C, can drive currents of 160 mA, 20 mA, and 10 mA individually with a maximum voltage drop of 0.8 V. ringer driver The TWL2214CA device provides the capability of driving a ringer. It is enabled by I2C and uses an N-channel FET with a maximum resistance of 3 . POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 dual-interface serial bus: DISB The DISB is a three-wire interface bus that incorporates both Phillips I2C and three-wire SPI. The SPI interface used here is different from the standard SPI interface; it combines both transmit and receive channels into one bidirectional port. It also incorporates the slave addressing topology to work like a bus and control many devices at the same time. The interface does not have a selection pin to choose between the two protocols. It uses the clock enable line to distinguish the communication format of the interface. When clock enable is high, the clock and data lines work as a standard I2C interface. However, on the falling edge of clock enable, the device expects the SPI protocol defined in the following section. The protocol includes a slave address identifier that allows the lines to be connected to many devices similar to that of I2C serial bus. Speed also improves when eliminating the master wait period to receive an acknowledge from the slave device. battery charger control This block provides the necessary signals to control the external circuits that perform the charger function. The charging activities include battery pack wake-up, precharge, fast charge, and battery temperature monitoring. This block also provides 2 ADC inputs for general measurement purposes. The input voltage level is from 0 V to 2 V. This block also includes an oscillator generator circuit, which generates the clocks for the device. The nominal frequency of the main clock is 500 kHz. It requires an external capacitor of 470 pF. reference system This block provides voltage reference and bias current for the internal circuitry. absolute maximum ratings over operating free-air temperature (unless otherwise noted) VCHG to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 12 V All other terminals relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6.5 V Operating ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 150C Storage temperature range, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Soldering temperature (for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN VCHG VDD1, VDD2, VDD3, VDD4, VDD5 High-level logic input, PWRKIN, SEL, CONT Low-level logic input, PWRKIN, SEL, CONT High-level logic input, PSH and CE Low-level logic input, PSH and CE MAX UNIT 4.5 6 V 3.3 4.3 V 0.7VDD1 GND VDD1 0.3VDD1 V 0.7VREG1 GND VREG1 0.3VREG1 V 100 mA 85 C Precharge current Operating free-air temperature, TA -40 V V logic level output PARAMETER TEST CONDITIONS MIN MAX UNIT 0.8VREG1 GND VREG1 0.22VREG1 V IOL = 2 mA IOH = -2 mA (open drain with 100 k internal pullup) GND 0.22VREG1 VREG1 V IOL = 2 mA (open drain 100 k internal pullup) GND 0.22VREG1 V VOH of terminals PWRKOUT, IRQ, CE VOL of terminals PWRKOUT, IRQ, CE IOH = -2 mA IOL = 2 mA VOL of DATA VOH of XRST VOL of XRST 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V V SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 electrical characteristics, TA = -25C to 85C (unless otherwise noted) regulator 1 (CO = 4.7 F with ESR = 2 ) PARAMETER VDD1 VREG1 Input voltage IO IOS Output current Output voltage Short circuit Load regulation Line regulation TEST CONDITIONS MIN TYP 3.3 IO = IMAX VDD1 = 3.8 V MAX 4.3 2.68 V 2.91 V 150 mA VDD1 = 3.8 V IO = 1 mA to IMAX, VDD1 = 3.8 V 550 mA 80 mV 20 mV 100 300 mV 65 120 A Dropout voltage VDD1 = 3.3 V to 4.3 V, IO = IMAX IO = IMAX PSRR Ripple rejection f = 10 Hz to 10 kHz, VDD1 = 3.8 V I(Standby) Standby current IO = 1.5 mA (regulator 1 and internal bias circuitry are active) 2.8 UNIT 105 dB regulator 6 (CO = 4.7 F with ESR = 2 ) This 100-mA LDO can be enabled with serial interface I2C or by CONT (terminal 21 or H6). The output range is from 2.5 V to 3 V. PARAMETER VDD2 Input voltage VREG6 O tp t voltage Output oltage IO Output current TEST CONDITIONS MIN TYP 3.3 CONT = Low CONT = High (see Note 1 and function register 4) VS Line regulation Dropout voltage PSRR Ripple rejection tON tOFF Turnon time See Note 2 Turnoff time See Note 3 V 2.88 3 3.12 V Vp 1.04Vp 100 V mA 330 mA 70 mV 20 mV 300 mV IO = 1 mA to IMAX, VDD2 = 3.8 V VDD2 = 3.3 V to 4.3 V, IO = IMAX IO = IMAX f = 10 Hz to 10 kHz, VDD2 = 3.8 V UNIT 4.3 0.96Vp Short circuit Load regulation MAX 100 65 2 dB 150 s 5 ms I(Quiescent) Quiescent current IO = 1.5 mA 15 30 A NOTES: 1. I2C/SPI programmable, V(p) is the programmed voltage. Refer to function registers 2 and 3 for programming information. 2. Output enable to output voltage = 0.9 x nominal value 3. Output disable to output voltage = 0.5 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 electrical characteristics, TA = -25C to 85C (unless otherwise noted) (continued) regulators 2, 3, 4, and 5 (CO = 4.7 F with ESR = 2 ) Regulators 2, 3, 4, and 5 provide programmable output. The output range, 2.3 V to 3 V, can be programmed in 100-mV steps. PARAMETER VI VO TEST CONDITIONS Input voltage Output voltage IO O tp t ccurrent Output rrent Short circ it ccurrent Short-circuit rrent Load regulation Line regulation MIN TYP MAX 3.3 UNIT 4.3 V V Regulator 2 1.04Vp 80 Regulator 3 80 Regulator 4 120 Regulator 5 150 Regulator 2 300 See Note 1 0.96Vp Vp Regulator 3 300 Regulator 4 400 Regulator 5 500 Regulator 2, IO = 1 mA to IMAX Regulator 4, IO = 1 mA to IMAX 70 Regulators 3 and 5, IO = 1 mA to IMAX 50 50 mA mA mV VDROPOUT PSRR Dropout voltage VI = 3.3 V to 4.3 V IO = IMAX 20 mV 300 mV Ripple rejection f = 10 Hz to 10 kHz, VDD3 = VDD4 = 3.8 V 65 dB N Output noise f = 10 Hz to 100 kHz, IO = IMAX, VI = 3.3 V 45 Vrms tON tOFF Turnon time See Note 2 Turnoff time No load, See Note 3 I(Quiescent) Quiescent current IO = 1 mA 80 s 1 5 ms 120 150 A regulator 1 voltage DET PARAMETER VO Voltage at XRST (see Note 4) VHY Hysteresis voltage TEST CONDITIONS MIN VREG1 VTH -VHY VREG1 VTH TYP MAX 0 UNIT 0.3 V 80 VREG1 100 Time delay voltage at CD1 1.15 1.2 1.25 V Time delay current at CD1 0.7 1 1.3 A 120 mV NOTE 4: VTH is 90% of the nominal VREG1. LED driver PARAMETER Output current at IL0 Output current at IL1 Output current at IL2 ILKG 12 Leakage current TEST CONDITIONS MIN TYP MAX UNIT VIL0 = 0.8 V VIL1 = 0.8 V 160 mA 20 mA VIL2 = 0.8 V Off 10 mA 1 A POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 electrical characteristics, TA = -25C to 85C (unless otherwise noted) (continued) vibrator driver PARAMETER TEST CONDITIONS VDD5 VO Input voltage Output voltage SEL = H IO VO Output current SEL = H Output voltage SEL = L IO VS Output current SEL = L Line regulation VDD5 = 3.3 V to 4.3 V, IOUT = IMAX IOUT = 1 mA to IMAX, VDD5 = 3.8 V Load regulation I(Quiescent) IL Quiescent current Current limit MIN TYP 3.3 MAX UNIT 4.3 V V 2.88 3 3.12 1.17 1.3 1.43 V 140 mA 20 mV 80 mV 85 IOUT = 0 VO = 0, VDD5 = 3.3 V to 4.3 V mA 80 A 490 mA ring driver PARAMETER On resistance ILKG Leakage current TEST CONDITIONS MIN TYP MAX IOUT = 100 mA at 25C Off UNIT 3 1 battery charger control PARAMETER TEST CONDITIONS VCHG input VDD1 S stem VDD System V(current sense) VG Current sense voltage Set maximum current, 100 to 200, 20-mV steps with I2C, See CSV register VGH IGH = 0 mA VGL IGL = 0 mA VG2 IG2 VG3 IG3 IGL MAX 6.5 4.059 4.1 4.141 4.158 4.2 4.242 2.91 3 3.09 VSENSE VG = 2 V V V V 149 178.5 197 214 218 226 IG2H = 0 mA VBAT 0 VG2L IG2L = 0 mA IG2H VG2 = VBAT - 0.3 V IG2L VG2 = 0.3 V VG3H IG3H = 0 mA VG3L IG3L = 0 mA IG3H VG3 = VDD1 - 0.3 V -2.7 -3.87 -4.65 IG3L VG3 = 0.3 V 2.95 4.43 5.3 A A V -2.8 -4.03 -4.65 3.2 5.02 5.70 VDD1 0 * DALLAS, TEXAS 75265 V V VG2H POST OFFICE BOX 655303 UNIT mV VCHG 0 IGH IG TYP 4.2 VBREG = 4.1 V VBREG = 4.2 V (see function control register) Required 0.1-F capacitor ESR of 2 , load = 1 mA maximum VREF MIN mA V mA 13 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 electrical characteristics, TA = -25C to 85C (unless otherwise noted) (continued) battery charger control (continued) PARAMETER VBAT regulation reg lation (CV) VBAT TEST CONDITIONS VBREG = 4.1 V VBREG = 4.2 V MIN TYP 4.1 4.141 4.158 4.2 4.242 Low voltage cutoff 1.9 High voltage cutoff 4.45 Fast charge voltage 3.2 Precharge voltage (see Note 5) Pack wake-up voltage MAX 4.059 V V 1.9 2.05 2.2 4.214 4.30 4.386 ICC Operating current VBREG is the regulated battery voltage programmed by setting bit 1 of CSV register. V NOTES: 5. Precharge current set by I + PRE 45 where V + 1.2 V " 10% PRE PRE R PR UNIT 20 mA ADC specification PARAMETER TEST CONDITIONS MIN TYP MAX 8 UNIT Resolution Output impedance <100 k Integral nonlinearity Confirm monotonous (see Note 6) -1 1 Low-level input ADC output = 00H 0 0.1 V High-level input ADC output = FFH 1.9 2 2.1 V 450 500 550 kHz Input capacitance bit 3 ADC CLK AD conversion time, tC From the start of SETUP Power-up time From the ADEN up selection LSB pF 16 CLK 10 s NOTE 6: LSB + 2V + 7.8 mV 255 DISB interface The TWL2214CA device supports both I2C bus and SPI bus serial interfaces. The interface uses serial data (DATA) and serial clock (CLK) to carry information between the devices. The CE terminal (A8) in the GQE package selects I2C or SPI. The device that initiates a transfer, generates clock signals, and terminates a transfer is the master. The TWL2214CA device operates as a slave device. The slave address for this device is fixed at E4h for write operations and E5h for read operations. The LSB of this slave address is simply an R/W flag. DATA is a bidirectional line connected to VREG1 via a 10-k pullup resistor. Data can be transferred at a rate up to 400K bits/s for I2C and up to 2M bits/s for SPI with one clock pulse generated for each data bit transferred. MSB is transferred first. When the bus is free, both DATA and CLK are high. Data transfer can only be initiated when the bus is free. The bus must return to the free state when the transfer is complete. Failure to return to the free state may cause an error. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 SPI bus protocols The TWL2214CA serial bus is SPI-compatible when a negative transition is generated on the CE input (A8) in the GQE package. Unlike I2C, in this mode, the slave device does not send an acknowledge bit for all data received. The data frame includes 2 start bits, 1 byte of slave address, 1 byte of register address, 1 byte of data, and half clock cycle of hold time. The total frame length, therefore, includes 26 full clock cycles and the rising edge of the 27th clock cycle. After the rising edge of the 27th clock cycle, CLK remains high. The following requirements must be satisfied for the interface: 1. CE goes low after the falling edge of CLK and remains low for no longer than 35 clock cycles. The data line must remain unchanged prior to the initial trailing edge of the CLK line. Failure to comply triggers the I2C start condition and the SPI interface fails. 2. Input data is sampled on the rising edge of the CLK when CE is set to low. 3. Input data is latched into the device on the last (26th) rising edge of the CLK. 4. If CE goes high before completing the transmission, data is ignored and the register is not updated. 5. Output data is updated on the falling edge of the CLK when CE is set to low. 6. The first two bits in the data line are dead bits to allow enough time for the communication mode option selection of the SPI. 7. During a read operation the direction of data line changes after the register address is received. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 SPI bus protocols (continued) t CLK t SUCE CLK CE t CLKH or t CLKL CLK DATA SPI1 t CE SPI0 CE t SUDIN t TD t HDIN CLK t HCE CE DATA DATA IN CLK t HDO CLK DATA DATA - MSB DATA OUT DATA Figure 5. SPI Protocol Timing CE CLK DATA DISB_SPI Format SPI[1-0] SA7 SA6 SA5 SA4 SA3 SA2 SA1 R/W A7 Start when CE goes low SPI[1-0] Slave Address [7-0] A6 A5 A4 A3 A2 Register Address [7-0] A1 A0 Data [7-0] One Cycle Figure 6. SPI Read and Write 16 POST OFFICE BOX 655303 D7 D6 * DALLAS, TEXAS 75265 D5 D4 D3 D2 Ignore data while CE is low D1 III III D0 Stop when CE goes high SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 SPI timing requirements (see Figure 5) PARAMETER MIN MAX UNIT tCLK tCLKL Clock period 500 ns Clock low time 200 ns tCLKH tTD Clock high time 200 ns Interframe transfer delay 5 tCE tSUCE CE low transition period 27 Clock enable setup time 50 ns tHCE tSUDIN Clock enable hold time 0 ns 50 ns tHDIN tHDO Input data hold time tr tf Input data setup time 35 50 Output data hold time tCLK-50 tCLK tCLK ns ns Clock or data rise time tCLK 20 Clock or data fall time 20 ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ns 17 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 I2C bus protocols For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TWL2214CA device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TWL2214CA device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TWL2214CA device must leave the data line high to enable the master to generate the stop condition. DATA CLK Data line stable; data valid Change of data allowed Figure 7. Bit Transfer on the I2C Bus 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 I2C bus protocols (continued) CE DATA CLK S P START Condition STOP Condition Figure 8. START and STOP Conditions CE CLK DATA A6 A5 A4 A0 R/W 0 ACK R7 R5 R0 ACK D7 D6 D5 D0 0 Slave Address Start R6 0 ACK 0 Register Address Stop Data NOTE: SLAVE = TWL2214CA Figure 9. I2C Bus Write to TWL2214CA Device CE CLK DATA Start A6 A5 A0 R/W ACK 1 Slave Address R7 R6 R0 ACK A6 A0 0 R/W ACK 1 Register Address D7 0 Slave Address Repeated Start D6 Slave Drives the Data D0 ACK Stop Master Drives ACK and Stop NOTE: SLAVE = TWL2214CA Figure 10. I2C Read From TWL2214CA Protocol A POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 I2C bus protocols (continued) CE CLK DATA A6 A5 A0 R/W ACK 1 Start R7 R6 R0 ACK 0 A6 A0 R/W ACK D7 A5 Stop Start Slave Address Register Address Slave Address NOTE: SLAVE = TWL2214CA D0 ACK Slave Drives the Data Stop Master Drives ACK and Stop Figure 11. I2C Read From TWL2214CA Protocol B I2C timing DATA t(BUF) th(STA) t(LOW) tr tf CLK th(STA) STO STA t(HIGH) th(DATA) tsu(STA) tsu(DATA) tsu(STO) STA STO MIN Clock frequency, fMAX MAX 400 Clock high time, twH(HIGH) 600 Clock low time, twL(LOW) DATA and CLK fall time, tF kHz ns 1300 DATA and CLK rise time, tR UNIT ns 300 ns 300 ns Hold time (repeated) START condition (after this period the first clock pulse is generated), th(STA) 600 ns Setup time for repeated START condition, th(DATA) 600 ns Data input hold time, th(DATA) Data input setup time, tsu(DATA) STOP condition setup time, tsu(STO) Bus free time, t(BUF) Figure 12. I2C Bus Timing Diagram 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 0 ns 100 ns 600 ns 1300 ns register map charger REGISTER PTR: Precharge timer register ADDRESS (HEX) 10h (R/W) Default CCTR: CC charge timer register 11h (R/W) Default 12h (R/W) Default VBOTRH+: Battery over temperature register at High+ VBOTRH-: Battery over temperature register at High High- CSV: Charge current sensing voltage and termination current ratio 0 0 = Disable 1 = Enable 0 D4 D3 D2 0 0 Don't care 0 0 0 00000 = 0 minutes L 11111 = 273 minutes in 8-minute steps 0 0 Don't care 0 0 0 0000 = 0 hours L 1111 = 15 hours in 1-hour steps 1 1 13h (R/W) Default 00h = 0 V 14h (R/W) 00h = 0 V L FFh = 2 V Default 00h = 0 V 15h (R/W) 00h = 0 V L FFh = 2 V Default 00h = 0 V 16h (R/W) Sensing voltage 000 = 100 mV L 101 = 200 mV in 20-mV steps 0 0 ADBV: Battery voltage 17h (R) VABV = 2 V x 2.5 x Value/256 ADBT: Battery temperature voltage 18h (R) VADBAT = 2 V x Value/256 ADCIN1: Voltage 19h (R) VADCIN1 = 2 V x Value/256 ADCIN2: Voltage 1Ah (R) VADCIN2 = 2 V x Value/256 D0 (LSB) D1 00000 = 0 minutes L 11111 = 136 minutes in 4-minute steps 00h = 0 V L FFh = 2 V Default D5 Don't Care 1 1 Termination current ratio 000 = 10% L 100 = 50% in 10% steps 0 0 0 0 = 4.1 V 1 = 4.2 V 0 0 Don't care 21 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 VBOTRL: Battery over temperature tem erature register at low 0 = Disable 1 = Enable D6 / / // / / / POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TCTR: Total charge timer (CC+CV) register D7 (MSB) 1Bh (R/W) Default SR: STATUS register POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 NOTES: 7. 8. 9. 10. 11. 1Ch (R) D7 (MSB) CHGSTR 0= 1 = Charger Start See Note 7 0 D6 ADC status 0 = Disable 1 = Enable See Notes 7 and 8 D5 ADC function 0 = Single 1 = Periodically See Notes 7 and 8 0 VEXT 1 = VCCHG in range 0 BATERR 1 = Battery error VBOT 1 = Battery overvoltage D4 ADBV 0 = Disable 1 = Enable See Notes 7 and 9 D3 VTS 0 = Disable 1 = Enable See Notes 7 and 10 D2 D0 (LSB) D1 ADCIN1 0 = Disable 1 = Enable See Notes 7 and 10 ADCIN2 0 = Disable 1 = Enable See Notes 7 and 10 0 0 0 0 CTERM 1 = Charge current goes below termination out NOCHG 1 = Charge condition, reset CHGSTR to 0. See Note 11 PCHG 1 = Precharge mode CCTO 1 = CC charge timeout D3 D2 D1 IRQ 0 = IRQ is L 1 = IRQ is H 0 TCTO 1 = Total charge time (CC+CV) out After the TWL2214CA device has finished charging, these values are set to 0. During CHGSTR H, ADC enables and periodically keeps functioning. During charging mode ADVB is enabled automatically. Charging mode is not necessary to set enable for function. External microprocessor must set CHGSTR bit to 0 when NOCHG = 1 regulator, LED, VIBRATOR REGISTER FCR2: Function register 2 ADDRESS (HEX) 20h (R/W) Default D7 (MSB) D6 D5 D4 REG2 0 = Disable 1 = Enable 0 REG3 000 = 3 V L 111 = 2.3 V in 100-mV steps 0 0 0 = Disable 1 = Enable 0 0 000 = 3 V L 111 = 2.3 V in 100-mV steps 0 0 REG4 FCR3: Function register 3 21h (R/W) Default 0 = Disable 1 = Enable 0 0 REG5 000 = 3 V L 101 = 2.5 V in 100-mV steps 0 D0 (LSB) 0 0 = Disable 1 = Enable 0 0 000 = 3 V L 101 = 2.5 V in 100-mV steps 0 0 0 REG6 FCR4: Function register 4 22h (R/W) Default FCR5: Function register 5 23h (R/W) Default 0 = Disable 1 = Enable See Note 12 000 = 3 V L 101 = 2.5 V in 100-mV steps Don't care 0 0 0 0 Vibrator Ringer IL2 IL1 0 = Disable 1 = Enable 0 = Disable 1 = Enable 0 0 0 = Disable 1 = Enable 0 0 = Disable 1 = Enable 0 IL0 0 = Disable 1 = Enable 0 VG3_EN 0 = Disable 1 = Enable Don't care 0 See Note 13 NOTES: 12. CONT = H, REG6 is dependent on D7 to enable. CONT = L, REG6 is independent of D7, always on after power up. 13. VG3_EN = 1, forces VG3 signal to Low. VG3_EN = 0, VG3 signal is at normal condition. Control of this bit is valid only when the adapter is connected. Template Release Date: 7-11-94 FCR1: Function control ADDRESS (HEX) / / // / / / REGISTER SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 22 charger (continued) SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION DC Input 4.5 V to 6.0 V Q1 R_SENSE1 0.2 ZXM64P02X 5 6 7 8 3 2 1 S R1 1 M C1 0.1 F D 4 G R2 100 k Q2:1 8D 7D SI9934DY R3 1 k Q2:2 S 1 D 6 D 5 SI9934DY G 2 4 G R4 1.2 k RT1 3.74 k C3 Battery Pack C2 1 F 470 pF RT2 6.19 k NTC C4 4.7 F D1 37 38 39 40 41 42 43 44 45 46 47 48 S1 R5 10 k PWRKOUT PWRKIN PSH DATA CLK U2 CD2 DGND TWL2214CA VIOUT VDD5 RINGOUT RINGIN GND3 TS ADCIN1 ADCIN2 CONT VREG5 VDD4 VREG4 BGRF GND2 VREG3 VDD3 VREG2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 IL0 IL1 IL2 SEL VDD1 VREG1 XRST AGND CD1 VREG6 VDD2 GND C13 0.001 F R6 10 k IRQ CT GND RPRE VCHG ISENSE VG VG2 VDD VG3 VBAT REF 36 35 34 33 32 31 30 29 28 27 26 25 - Vibrator + EXT_CONTROLLER GND C5 4.7 F C11 4.7 F C12 0.1 F RST C10 C9 4.7 F 0.1 F C6 0.1 F C8 C7 4.7 F 0.1 F C14 0.01 F IRQ PWRKOUT PSH DATA CLK VCC To VDD or GND To VDD or GND C17 0.1 F R9 100 k VREG1 VDD + Buzzer - To VDD or GND C15 4.7 F C18 0.1 F C16 4.7 F R7 R8 R10 C19 0.1 F Figure 13. Typical Application Circuit (PFB) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION DC Input 4.5 V to 6.0 V Q1 R_SENSE1 0.2 ZXM64P02X 5 6 7 8 3 2 1 S R1 1 M C1 0.1 F D 4 G R2 100 k Q2:1 8D 7D Q2:2 S 1 SI9934DY SI9934DY G 2 R3 1 k D 6 D 5 4 G R4 1.2 k RT1 3.74 k C3 Battery Pack C2 1 F 470 pF RT2 6.19 k NTC C4 4.7 F D1 B7 A7 B6 A6 B5 A5 A4 B4 A3 B3 A2 B2 S1 R5 10 k PWRKOUT PWRKIN PSH DATA CLK U2 CD2 DGND TWL2214CA VIOUT VDD5 RINGOUT RINGIN GND3 TS ADCIN1 ADCIN2 CONT VREG5 VDD4 VREG4 BGRF GND2 VREG3 VDD3 VREG2 H8 J8 J7 H6 J6 J5 H5 J4 H4 J3 J2 H2 A8 B1 C2 C1 D2 D1 E2 E1 C4 F1 F2 G1 G2 CE IL0 IL1 IL2 SEL VDD1 VREG1 XRST AGND CD1 VREG6 VDD2 GND C13 0.001 F R6 10 k IRQ CT GND RPRE VCHG ISENSE VG VG2 VDD VG3 VBAT REF B8 B9 C8 C9 D9 E9 E8 F9 F8 G9 G8 H9 - Vibrator + EXT_CONTROLLER GND VCC C5 4.7 F C11 4.7 F C12 0.1 F RST To VDD or GND C17 0.1 F R9 100 k VREG1 VDD + Buzzer - To VDD or GND C15 4.7 F C18 0.1 F C16 4.7 F R10 Figure 14. Typical Application Circuit (GQE) POST OFFICE BOX 655303 R7 R8 C19 0.1 F * DALLAS, TEXAS 75265 C10 C9 4.7 F 0.1 F C6 0.1 F C8 C7 4.7 F 0.1 F C14 0.01 F IRQ PWRKOUT PSH DATA CLK CE 24 To VDD or GND SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION device power supply control (VDD1) The TWL2214CA device receives device power by regulating the VCHG input to 4.1 V or 4.2 V, whenever VCHG is available; otherwise, the device uses the VBAT input directly as device dc supply. The regulated voltage from VCHG is programmable through the I2C interface. VCHG RS + VG BG VDD VG3 VG2 VBAT VDD + _ - Control Logic Decode R1 R2 VDD1 TWL2214CA BG: Band Gap Voltage R1: Fixed R2: Programmable Figure 15. Device Power Supply Condition 1: VCHG is on (VG = Active, VG2 = On, VG3 = Off) V DD1 + 4.1 V or 4.2 V The TWL2214CA device sets R2 value according to the programmed voltage level (4.1 V or 4.2 V). Condition 2: VCHG is off and VBAT applied (VG = High, VG2 = Off, VG3 = On) V DD1 + VBAT battery charger The TWL2214CA device provides a charger function for single cell Li-Ion battery packs. The charging activity starts with the battery pack wake-up cycle. If the wake-up cycle completes successfully, the charger starts the precharge function and slowly charges the battery to 3.2 V. If the battery is charged to 3.2 V within the time limit, the charger goes into the fast charge mode. The fast charge mode has two phases: 1) constant current (CC) mode and 2) constant voltage (CV) mode. The charger starts CC mode with the maximal charging current until the battery voltage reaches the regulated voltage level; the charger is then switched to CV mode. During the CV mode, the TWL2214CA device monitors the charging current; once it is below the programmed termination current level, the charger activity is terminated. The termination current level can be programmed at 10%, 20%, 30%, 40%, or 50% of the maximum charging current at the CC mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION Non-Charging Mode Power Up VCHG < 4.5 V or VCHG > 6.5 V 4.5 V VCHG 6.5 V XRST = Low or CHGSTR = Low Standby XRST = High and CHGSTR = High VBAT 4.3 V VBAT < 2.0 V or VBAT > 4.45 V Wake Up VBAT 3.2 V VBAT < 3.2 V VBAT < 3.2 V Temperature Out of Range Precharge Temperature In Range VBAT < 4.1 V or 4.2 V Time-Out or VBAT > 4.45 V VBAT 3.2 V Temperature Out of Range Charge Suspended Temperature In Range Fast-Charge CC Mode Temperature Out of Range Temperature In Range Temperature Out of Range ICHG > ITERMINATE and not CV Time-Out Fast-Charge CV Mode VBAT > 4.45 V ICHG ITERMINATE or CV Time-Out Figure 16. Charger State Diagram POST OFFICE BOX 655303 VBAT > 4.45 V VBAT 4.1 V or 4.2 V Charge Complete 26 CC Time-Out or * DALLAS, TEXAS 75265 Terminate Charge SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION control register--FCR1 (1BH) BIT NAME DESCRIPTION 7 CHGSTR Set this bit to 1 to start the charger operation. This bit is cleared if the charger is terminated. (Refer to status register table below for terminated conditions) 6 ADC ENABLE Set this bit to 1 to enable ADC operation, 0 to stop. 5 ADC FUNCTION Set this bit to 1 to have ADC operate continuously. Set to 0 to have ADC to operate one cycle only. 4 ADBV Set this bit to 1 to enable the VBAT input channel to ADC. Clear this bit to 0 to disable the input channel. 3 VTS Set this bit to 1 to enable the VTS input channel to ADC. Clear this bit to 0 to disable the input channel. 2 ADCIN1 Set this bit to 1 to enable the ADCIN1 input channel. 1 ADCIN2 Set this bit to 1 to enable the ADCIN2 input channel. 0 IRQ Status of IRQ terminal (refer to IRQ operation section). ADC has four input channels (ADBV, VTS, ADCIN1, and ADCIN2). Each channel can be enabled or disabled individually. The selected channel must be enabled before ADC FUNCTION and ADC ENABLE bits are enabled, the channel is included in the ADC operation. IRQ control/status The TWL2214CA device uses IRQ signal to inform the external controller about the exception condition of the VCHG input and the charger status. Bit 0 reflects the state of the IRQ signal. IRQ occurs in the following five conditions: 1. VCHG returns to operating range from nonoperating range. 2. VCHG goes out of range from operating range. 3. Battery error--occurs only during the charging cycle. 4. Battery temperature out of range--occurs only during the charging cycle. The charger is suspended temporarily. IRQ is cleared when the temperature returns to normal and the charger resumes automatically. 5. Charge complete. The controller must clear the IRQ signal by writing 0 to bit 0 in the interrupt service routine, except in the VBOT condition. The controller may miss the next interrupt if it fails to write the 0. In the VBOT condition, the TWL2214CA device clears the IRQ when the condition goes away. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION status register description--SR (1CH) SR shows the status of the charger. The external controller reads the SR to track the state of the charging condition. BIT 28 NAME DESCRIPTION 7 Vext When Vext = 1, the VCHG input is in the operating range. Otherwise the VCHG is out of range. 6 BATERR This bit is set to 1 indicating battery error. Four cases cause battery error: precharge timeout, constant-current mode timeout, VBAT < 2.9 V, or VBAT > 4.45 V. 5 VBOT During the charging cycle, if the battery temperature exceeds or falls below the nominal range, this sets to 1. The charger is suspended temporarily. VBOT is cleared when the temperature returns to nominal range and the charger function resumes automatically. 4 CTERM The charger is terminated normally because the charging current is below the preset termination current value. 3 NOCHG No charge condition. This condition is detected only during the wake-up state of the charging function. After the 8-second wake-up period expires, if VBAT is above 4.3 V, the NOCHG flag is set. The cause of this is a missing or completely charged battery. The TWL2214CA device does not deactivate the charger by setting CHGSTR = 0. The external processor must turn off the CHGSTR bit by setting it to 0. 2 PCHG Set to 1 to indicate the charger is in precharge state. 1 CCTO Set to 1 to indicate the charging time has exceeded the time limit allowed during CC mode. This is a fatal error. The TWL2214CA device clears CHGSTR bit, sets the BATERR flag, and makes IRQ go high to interrupt the external controller. 0 TCTO Set to 1 to indicate the charging time has exceeded the overall time limit allowed during CV mode. This is treated as normal termination of the charger function. The TWL2214CA device clears bit 7 (CHGSTR) of the control register and sets IRQ to 1 to interrupt the external controller. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION IRQ No VEXT=1 VCHG out of Bound Yes 1 Yes Display Error Message No BATTERR=1 Yes No NOCHG=1 1 Yes No VBOT Set CHGSTR to 0 No Yes Return CTERM Yes TCTO 1 Charge Complete No 1 1 1 Set IRQ1 to 0 Return Figure 17. Charger State Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION battery pack wake-up Li-Ion cells can be easily damaged by overcharging or overdischarging. To prevent damage, a pack-protector device is used within the battery pack. During the charging cycle, if the pack-protector senses an over-voltage condition, it disconnects the pack from the charger to prevent further charging but allows discharging. During the discharging cycle, if the protector senses an under-voltage condition, it disconnects the cell from the load to prevent further discharging. This phase of the charging cycle provides a wake-up capability for the battery pack with a pack-protector device. At the start of the charge cycle, the TWL2214CA device provides a wake-up signal of 1 mA and 4.3 V to the battery pack. At the end of the 8-second time limit, if the battery pack voltage remains at 4.3 V, a no-battery flag is set in the status register to signal the condition that the charging path is open. If the battery voltage is below 2.5 V, a BATTERR flag is set in the status register to signal a bad battery cell. In either case, the charging activity is halted. VCHG 1 mA BG VDD1 _ + _ No Battery + VBAT + R1 Wake-Up Enable Battery - R2 Control Logic TWL2214CA BG = 1.2 V R1 + R2 BG x = 4.3 V R2 Figure 18. Battery Pack Wake Up precharge The TWL2214CA device starts the precharge phase when the battery voltage is less than 3.2 V. The precharge time is limited by the PTR timer. The precharge current level is set by an external resistor. The maximum precharge current the charger can supply is 100 mA. Use the following equation to choose the external resistor value. V R PR + PRE 45, V PRE + 1.2V " 10% I PRE Where: RPR = External resistor IPRE = Desired precharge current VPRE = Voltage at RPRE terminal 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION Rsense Active DC Input ON VG VCHG OFF VG2 + - VBAT VG3 ISENSE VDD Voltage and Current Regulation Logic Constant Current Source Switch Control RPRE RPR Precharge Path TWL2214CA Figure 19. Precharge Functional Diagram fast charge constant current (CC mode) When the battery voltage is 3.2 V or higher, the TWL2214CA device starts the fast charge CC mode cycle. In CC mode, the charger regulates the charging current to its maximum level. The maximum charging current (IMAX) is determined by the external sense resistor, RSENSE, and the voltage, VSENSE. VSENSE, is programmable through the I2C interface (refer to CSV register for programming information). The range of VSENSE is from 100 mV to 200 mV, in 20-mV steps. The CC mode charge time is limited by the CCTR timer. I MAX + V SENSE R SENSE fast charge constant current (CV mode) When the cell reaches the constant voltage phase, the charger switches to the fast charge CV mode. The charging current begins tapering down while the charging voltage is regulated at the programmed voltage level (4.1 V or 4.2 V). The CV mode charging is limited by the TCTR timer. Fast Charge Path (CC, CV) Rsense DC Input Active ON ON + VCHG ISENSE VG VG2 VDD Voltage and Current Regulation Logic VG3 VBAT - Switch Control TWL2214CA Figure 20. Fast Charge Functional Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION current termination During the CV mode, the charge cycle is terminated when the charging current is under the programmed terminated level or when the total charge timer (TCTR) times out. The terminated current level can be programmed to 10%, 20%, 30%, 40%, or 50% of the charging current at CC mode. temperature monitoring The TWL2214CA device monitors the battery temperature throughout the charge cycle. The input for ADC reference voltage is generated by a negative temperature coefficient (NTC) thermistor. The TWL2214CA device compares the ADC input reference voltage to the programmed threshold voltages to determine if charging is allowed. Three required thresholds are: D VBOTRH+ Voltage for over-temperature cutoff; charging is suspended. D VBOTRH- Voltage to resume charging function for over-temperature cutoff. D VBOTRL Voltage for low-temperature cutoff; charging is suspended. Ts (V) 2V VBOTRL VBOTRH- VBOTRH+ 0V Charge Condition Enable Disabled Enabled Disabled Enabled Figure 21. Temperature Monitoring NOTE: The power-up default values are zero for these three thresholds. If the user opts not to use the temperature monitoring function during the charge cycle, the TS terminal of the device must be tied to GND to avoid an error signal. 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 APPLICATION INFORMATION maximum time out The TWL2214CA device provides three timers for maximal time allowed for charging. The time is programmable through I2C interface. TIMER DESCRIPTION RANGE STEP COMMENT PTR-Precharge timer 0-136 min 4 min During the precharge cycle, if the timer expires before the precharging activity is complete, a BATT_ERR flag is set in the status register, and the charge is terminated. CCTR-CC charge timer 0-274 min 8 min During the CC mode cycle, if the timer expires before the CC activity is complete, a BATT_ERR flag is set in the status register, and the charge is terminated. TCTR-total charge timer 0-15 hr 1 hr Total charge time is defined as the total charge time of CC mode and CV mode. TCTR time-out occurs only in the CV mode. If the timer expires before, the charge is complete. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 MECHANICAL DATA GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. 0,05 M 0,21 0,11 0,08 4200461/C 10/00 All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments. 34 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS321A - OCTOBER 2001 - REVISED JANUARY 2002 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0-7 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176/B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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