T3GE9WBG
2009-06-15
1
TOSHIBA Digital Integrated Circuit Silicon Monolithic
T3GE9WBG
Dual Supply Bus Transceiver for SD Card
The T3GE9WBG is a dual supply, advanced high-speed CMOS
dual supply voltage interface bus transceiver fabricated with
silicon gate CMOS technology.
Designed for use as an interface between a 1.8-V bus and a
2.9-V bus in mixed 1.8-V/2.9-V supply systems.
The A-port interfaces with the 1.8-V bus, the B-port with the
2.9-V bus.
The direction of data transmission is determined by the level of
the DIR input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
Bidirectional interface between 1.8-V and 2.9-V buses.
High-speed operation : tpd = 8.5 ns (max) (VCCA = 1.8 ± 0.15 V, VCCB = 2.9 ± 0.1 V)
Output current : IOHB/IOLB = ±6 mA (min) (VCCB = 2.8 V)
I
OHA/IOLA = ±6 mA (min) (VCCA = 1.65 V)
Regulator output current: 200mA (min)
Integrated EMI filter on B-port
Integrated Pull-up and Pull-down resistors on B-port
Latch-up performance : ±200 mA
ESD performance : Machine model > ±200 V
Human body model > ±2000 V
IEC61000-4-2 Level 4 (Contact) > ±8000 V ( SD card side )
Ultra-small package : WCSP24
Weight: 0.006 g (typ.)
T3GE9WBG
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Pin Assignment (top view)
Truth Table
Input Outputs
Clk.h Clk-f CLK-B
L L L
H H H
Inputs Function
CMD-dir CMD.h CMD-B
Outputs
L Output Input CMD.h = CMD-B
H Input Output CMD-B = CMD.h
Inputs Function
Dat0-dir Dat0.h Dat0-B
Outputs
L Output Input Dat0.h = Dat0-B
H Input Output Dat0-B = Dat0.h
Inputs Function
Dat123-dir Dat1.h –
Dat3.h
Dat1-B –
Dat3-B
Outputs
L Output Input Datn.h = Datn-B
H Input Output Datn-B = Datn.h
1 2 3 4 5
A Dat2.h CMD-dir Dat0-dir VBatt Dat2-B
B Dat3.h -- VCCA VCCB
O/P Dat3-B
C Clk.h Enable GND GND CLK-B
D Dat0.h CMD.h CD CMD-B Dat0-B
E Dat1.h Clk-f Dat123-dir WP Dat1-B
Input Output
Enable Regulator
L OFF
H ON
1 2 3 4 5
A
B
C
D
E
(
To
p
view
)
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Block Diagram
Clk-B
VCCA VCCB O/P
Clk.h
Logic
level
converter
Clk-f
R8 R9
C
VCCA
CMD-B
CMD-dir
CMD.h
Logic
level
converter
R2
R8 R9
C
VCCB O/P
Data0-B
VCCA
Data0-dir
Data0.h
Logic
level
converter
R3
R8 R9
C
VCCB O/P
VCCA
Data123-dir
Data1.h
Data2.h
Logic
level
converter
Data3.h
Data1-B
Data2-B
Data3-B
R4
R5
R8 R9
R8 R9
C
C
VCCB O/P
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Block Diagram
Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
VCCA −0.5 to 3.0
Power supply voltage
VBatt 5.5
V
DIR, Clk.h −0.5 to VCCA + 0.5
DC input voltage
Enable
VIN
−0.5 to 5.5
V
VI/OA −0.5 to VCCA + 0.5 (Note 2)
DC bus I/O voltage
VI/OB −0.5 to VCCB + 0.5 (Note 2)
V
DIR, Clk.h ±25
Input diode current
Enable
IIK −25
mA
Output diode current II/OK ±25 (Note 3) mA
IOUTA ±25
DC output current
IOUTB ±25
mA
DC VCC/ground current per supply pin ICCA ±50 mA
Power dissipation PD 400 mW
Storage temperature Tstg −55 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Note 2: High or Low stats. IOUT absolute maximum rating must be observed.
Note 3: VOUT < GND, VOUT > VCC
Symbol Value (typ)
R3, R4 70kΩ
R2 15kΩ
R5 470kΩ
R6, R7 100kΩ
R8 5Ω
R9 35Ω
C 35pF
VCCA
CD
VCCA
WP
R6 R7
LDO
VBatt
VCCB O/PEnable
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Operating Range (Note 1)
Characteristics Symbol Rating Unit
VCCA 1.65 to 1.95
Power supply voltage
VBatt 3.2 to 5.0
V
DIR, Clk.h 0 to VCCA
Input voltage
Enable
VIN
0 to 5.0
V
VI/OA 0 to VCCA (Note 2)
Bus I/O voltage
VI/OB 0 to VCCB O/P(Note 2)
V
IOUTA ±6 (Note 3)
Output current
IOUTB ±6 (Note 4)
mA
Operating temperature Topr −30 to 85 °C
Input rise and fall time dt/dv 0 to 10 (Note 5) ns/V
Note 1: The operating range is required to ensure the normal operation of the device. Unused inputs and bus inputs
must be tied to either VCC or GND. Please connect both bus inputs and the bus outputs with VCC or GND
when the I/O of the bus terminal changes by the function. In this case, please note that the output is not
short-circuited.
Note 2: High or low state
Note 3: VCCA = 1.65 to 1.95 V
Note 4: VCCB = 2.8 to 3.0 V, VCCB is supplied from the built-in LDO.
Note 5: VCCA = 1.65 V, VCCB = 2.8 V
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Electrical Characteristics
DC Characteristics (1.65 V ≤ VCCA ≤ 1.95 V, 2.8 V ≤ VCCB ≤ 3.0 V)
Ta = −30 to 85°C
Characteristics Symbol Test Condition VCCA (V) VCCB (V)
Min Max
Unit
VIHA DIR, An (Note 1) 1.65 to 1.95 2.8 to 3.0 VCCA
×0.65 ⎯
H-level input voltage
VIHB Bn (Note 1) 1.65 to 1.95 2.8 to 3.0 2.0 ⎯
V
VILA DIR, An (Note 1) 1.65 to 1.95 2.8 to 3.0 ⎯ VCCA
×0.35
L-level input voltage
VILB Bn (Note 1) 1.65 to 1.95 2.8 to 3.0 ⎯ 0.8
V
IOHA = −100μA 1.65 to 1.95 2.8 to 3.0 VCCA
− 0.2 ⎯
VOHA
IOHA = −6 mA 1.65 2.8 to 3.0 1.15 ⎯
IOHB = −100 μA 1.65 to 1.95 2.8 to 3.0 VCCB
− 0.2 ⎯
H-level output voltage
VOHB
VIN = VIH or VIL
IOHB = −6 mA 1.65 to 1.95 2.8 2.2 ⎯
V
IOLA = 100 μA 1.65 to 1.95 2.8 to 3.0 ⎯ 0.2
VOLA
IOLA = 6 mA 1.65 2.8 to 3.0 ⎯ 0.3
IOLB = 100 μA 1.65 to 1.95 2.8 to 3.0 ⎯ 0.2
L-level output voltage
VOLB
VIN = VIH or VIL
IOLB = 6 mA 1.65 to 1.95 2.8 ⎯ 0.4
V
IIA
VINA = VCCA or GND
DIR = HIGH
VCD = VWP = VCCA
1.65 to 1.95 2.8 to 3.0 ⎯ ±5.0
Input leakage current
IIB
VCMD-B, DAT0, DAT1, DAT2 = VCCA
VDAT3 = GND
DIR = LOW
VCD = VWP = VCCA
1.65 to 1.95 2.8 to 3.0 ⎯ ±5.0
μA
Quiescent supply current ICCA
VINA = VCCA or GND
DIR = HIGH
VCD = VWP = VCCA
1.65 to 1.95 2.8 to 3.0 ⎯ 20 μA
Note 1: An is a host side signal. Bn is a card side signal.
Note: VCCB is supplied from the built-in LDO.
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AC Characteristics (Ta = −30 to 85°C, Input: tr = tf = 2.0 ns)
VCCA = 1.8 ± 0.15 V, VCCB = 2.9 ± 0.1 V
Characteristics Symbol Test Condition Min Typ. Max Unit
Propagation delay time
(Bn → An)
tpLH
tpHL
Figure 1, Figure 2 1.0 ⎯ 8.5 ns
Propagation delay time
(An → Bn)
tpLH
tpHL
Figure 1, Figure 2 1.0 ⎯ 8.5 ns
Propagation delay time
(Clk.h → Clk-f)
tpLH
tpHL
Figure 1, Figure 2 1.0 ⎯ 14 ns
Output Transition Time
(An)
tTLH
tTHL
Figure 1, Figure 2 ⎯ 1.5 ⎯ ns
Output Transition Time
(Bn)
tTLH
tTHL
Figure 1, Figure 2 ⎯ 1.5 ⎯ ns
Output to output skew
tosLH
tosHL
(Note 1) ⎯ ⎯ 0.5 ns
Note 1: Parameter guaranteed by design. (tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)
Note: An is a host side signal. Bn is a card side signal.
VCCB is supplied from the built-in LDO.
Dynamic Switching Characteristics (Ta = 25°C, Input: tr = tf = 2.0 ns, CL = 15 pF)
Characteristics Symbol Test Condition VCCA (V) VCCB (V) Typ. Unit
A → B 1.8 2.9 0.35
Quiet output maximum
dynamic VOL B → A
VOLP VIH = VCC, VIL = 0 V
(Note 2) 1.8 2.9 0.25
V
A → B 1.8 2.9 −0.35
Quiet output minimum
dynamic VOL B → A
VOLV
VIH = VCC, VIL = 0 V
(Note 2) 1.8 2.9 −0.25
V
A → B 1.8 2.9 3.25
Quiet output maximum
dynamic VOH B → A
VOHP
VIH = VCC, VIL = 0 V
(Note 2) 1.8 2.9 2.05
V
A → B 1.8 2.9 2.55
Quiet output minimum
dynamic VOH B → A
VOHV
VIH = VCC, VIL = 0 V
(Note 2) 1.8 2.9 1.55
V
Note 2: Parameter guaranteed by design.
Note: An is a host side signal. Bn is a card side signal.
Capacitive Characteristics (Ta = 25°C)
Characteristics Symbol Test Circuit VCCA (V) VCCB (V) Typ. Unit
A → B (DIR = “H”) 1.8 2.9 24
CPDA
B → A (DIR = “L”) 1.8 2.9 22
A → B (DIR = “H”) 1.8 2.9 76
Power dissipation capacitance
(Note 3) CPDB
B → A (DIR = “L”) 1.8 2.9 28
pF
Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr) = CPD･VCC･fIN + ICC/6 (per bit)
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Regulator Section
Electrical Characteristics (unless otherwise specified, VIN = VOUT + 1 V, IOUT = 1 mA,
CIN = 0.1 μF, COUT = 2.2 μF, Tj = 25°C)
Characteristics Symbol Test Condition Min Typ. Max Unit
Input voltage VIN ⎯ 3.2 ⎯ 5.0 V
Output voltage VCCB O/P
2.8 2.9 3.0 V
Line regulation Reg･line VOUT + 0.5 V ≤ VIN ≤ 5.0 V,
IOUT = 1 mA ⎯ 3 15 mV
Load regulation Reg･load 1 mA ≤ IOUT ≤ 200 mA ⎯ ⎯ 150 mV
IB1 IOUT = 0 mA ⎯ 40 80
Quiescent current
IB2 I
OUT = 100 mA ⎯ 45 85
μA
Stand-by current IB (OFF) V
CT = 0 V ⎯ 0.1 1.0 μA
Output noise voltage VNO
VIN = VOUT + 1 V, IOUT = 10 mA,
10 Hz ≤ f ≤ 100 kHz,
, Ta = 25°C
⎯ 140 ⎯ μVrms
Temperature coefficient TCVO −40°C ≤ Topr ≤ 85°C ⎯ 100 ⎯ ppm/°C
Ripple rejection R.R.
VIN = VOUT + 1 V, IOUT = 10 mA,
f = 1 kHz, VRipple = 500 mVp-p,
Ta = 25°C
⎯ 40 ⎯ dB
Control voltage (ON) VCT (ON) ⎯ 1.5 ⎯ V
IN V
Control voltage (OFF) VCT (OFF) ⎯ 0 ⎯ 0.25 V
Control current (ON) ICT (ON) V
CT = 1.5 V ⎯ ⎯ 0.1 μA
Control current (OFF) ICT (OFF) V
CT = 0 V ⎯ ⎯ 0.1 μA
Peak output current Ioutpeak 200 ⎯ ⎯ mA
EMI Filter Response (Typical Performance)
-60
-50
-40
-30
-20
-10
0
0.1 1 10
Frequency [GHz]
Attenuation [dB]
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90%
10%
Output
(Bn, An)
Input
(An, Bn)
VOL
VOH
VIH
VM
tpLH tpHL
tr 2.0 ns tf 2.0 ns
VM
GND
90%
10%
tTLH tTHL
AC Test Circuit
Figure 1
AC Waveform
Figure 2 tpLH, tpHL, tTLH, tTHL
VCC (output)
Symbol
2.9 ± 0.1 V 1.8 ± 0.18 V
RL 2 kΩ 2 kΩ
CL 15 pF 15 pF
VCC
Symbol
2.9 ± 0.1 V 1.8 ± 0.18 V
VIH V
CC V
CC
VM V
CC/2 VCC/2
Out
p
ut Measure
RL
CL
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Package Dimensions
Weight: 0.006 g (typ.)
The resin used in this
p
roduct includes no flame retardants.
Unit: mm
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must
also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,
the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA
Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are
solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the
appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any
information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other
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LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
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