1
FEATURES
DESCRIPTION
TPS2014600mA
TPS20151 A
TPS2041B500mA
TPS2051B500mA
TPS2045A 250mA
TPS2049100mA
TPS2055A 250mA
TPS20611 A
TPS20651 A
TPS20681.5 A
TPS20691.5 A
TPS201xA 0.2 A -2 A
TPS202x0.2 A -2 A
TPS203x0.2 A -2 A
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007www.ti.com
POWER-DISTRIBUTION SWITCHES
•33-m Ω(5-V Input) High-Side MOSFET Switch•Short-Circuit and Thermal Protection•Operating Range . . . 2.7 V to 5.5 V•Logic-Level Enable Input•Typical Rise Time. . . 6.1 ms•Undervoltage Lockout•Maximum Standby Supply Current. . . 10 μA•No Drain-Source Back-Gate Diode•Available in 8-pin SOIC and 14-Pin TSSOPPackages
•Ambient Temperature Range, – 40 °C to 85 °C•2-kV Human-Body-Model, 200-VMachine-Model ESD Protection
The TPS201xA family of power distribution switches is intended for applications where heavy capacitive loadsand short circuits are likely to be encountered. These devices are 50-m ΩN-channel MOSFET high-side powerswitches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive isprovided by an internal charge pump designed to control the power-switch rise times and fall times to minimizecurrent surges during switching. The charge pump requires no external components and allows operation fromsupplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS201xA limits the outputcurrent to a safe level by switching into a constant-current mode. When continuous heavy overloads and shortcircuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermalprotection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic oncethe device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage ispresent.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
DESCRIPTION (CONTINUED)
TPS201xA FUNCTIONAL BLOCK DIAGRAM
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The TPS201xA devices differ only in short-circuit current threshold. The TPS2010A limits at 0.3-A load, theTPS2011 at 0.9-A load, the TPS2012A at 1.5-A load, and the TPS2013A at 2.2-A load (see Available Options).The TPS201xA is available in an 8-pin small-outline integrated-circuit (SOIC) package and in a 14-pin thin-shrinksmall-outline package (TSSOP) and operates over a junction temperature range of -40 °C to 125 °C.)
AVAILABLE OPTIONS
RECOMMENDED PACKAGED DEVICES
(1)TYPICAL SHORT-CIRCUITMAXIMUM CONTINUOUS
SMALL OUTLINE TSSOPT
A
ENABLE CURRENT LIMIT AT 25 °CLOAD CURRENT
(D)
(2)
(PWP)
(3)(A)(A)
0.2 0.3 TPS2010AD TPS2010APWPR0.6 0.9 TPS2011AD TPS2011APWPR– 40 °C to 85 °C Active low
1 1.5 TPS2012AD TPS2012APWPR1.5 2.2 TPS2013AD TPS2013APWPR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR)(3) The PWP package is only available left-end taped-and-reeled.
TERMINAL FUNCTIONS
TERMINAL
NO. I/O DESCRIPTIONNAME
D PWP
EN 4 7 I Enable input. Logic low turns on power switch.GND 1 1 I GroundIN 2, 3 2 – 6 I Input voltageOUT 5 – 8 8 – 14 O Power-switch output
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DETAILED DESCRIPTION
POWER SWITCH
CHARGE PUMP
DRIVER
ENABLE ( EN)
CURRENT SENSE
THERMAL SENSE
UNDERVOLTAGE LOCKOUT
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 m Ω(V
I(IN)
= 5V).Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT whendisabled.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requiresvery little supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.
The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce thesupply current to less than 10 μA when a logic high is present on EN . A logic zero input on EN restores bias tothe drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOSlogic levels.
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET intoits saturation region, which switches the output into a constant current mode and holds the current constant whilevarying the voltage on the load.
An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately140 °C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20 °C, theswitch turns back on. The switch continues to cycle off and on until the fault is removed.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a controlsignal turns off the power switch.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
I(IN)
Input voltage range
(2)
– 0.3 to 6 VV
O(OUT)
Output voltage range
(2)
– 0.3 to V
I(IN)
+ 0.3 VV
I(EN)
Input voltage range – 0.3 to 6 VI
O(OUT)
Continuous output current Internally LimitedContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range – 40 to 125 °CT
stg
Storage temperature range – 65 to 150 °CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °CHuman body model 2 kVESD Electrostatic discharge protection
Machine model 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
D 725 mW 5.8 mW/ °C 464 mW 377 mWPWP 700 mW 5.6 mW/ °C 448 mW 364 mW
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
I(IN)
2.7 5.5Input voltage VV
IH
0 5.5TPS2010A 0 0.2TPS2011A 0 0.6I
O
Continuous output current ATPS2012A 0 1TPS2013A 0 1.5T
J
Operating virtual junction temperature – 40 125 °C
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ELECTRICAL CHARACTERISTICS
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= rated current, EN = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
POWER SWITCH
V
I(IN)
= 5 V, T
J
= 25 °C, I
O
= 1.5 A 33 36V
I(IN)
= 5 V, T
J
= 85 °C, I
O
= 1.5 A 38 46V
I(IN)
= 5 V, T
J
= 125 °C, I
O
= 1.5 A 44 50TPS2013A m ΩV
I(IN)
= 3.3 V, T
J
= 25 °C, I
O
= 1.5 A 37 41V
I(IN)
= 3.3 V, T
J
= 85 °C, I
O
= 1.5 A 43 52V
I(IN)
= 3.3 V, T
J
= 125 °C, I
O
= 1.5 A 51 61Static drain-source on-stater
DS(on)
resistance
V
I(IN)
= 5 V, T
J
= 25 °C, I
O
= 0.18 A 30 34V
I(IN)
= 5 V, T
J
= 85 °C, I
O
= 0.18 A 35 41V
I(IN)
= 5 V, T
J
= 125 °C, I
O
= 0.18 A 39 47TPS2010A m ΩV
I(IN)
= 3.3 V, T
J
= 25 °C, I
O
= 0.18 A 33 37V
I(IN)
= 3.3 V, T
J
= 85 °C, I
O
= 0.18 A 39 46V
I(IN)
= 3.3 V, T
J
= 125 °C, I
O
= 0.18 A 44 56V
I(IN)
= 5.5 V, T
J
= 25 °C, C
L
= 1 μF, R
L
= 10 Ω6.1t
r
Rise time, output msV
I(IN)
= 2.7 V, T
J
= 25 °C, C
L
= 1 μF, R
L
= 10 Ω8.6V
I(IN)
= 5.5 V, T
J
= 25 °C, C
L
= 1 μF, R
L
= 10 Ω3.4t
f
Rise time, output msV
I(IN)
= 2.7 V, T
J
= 25 °C, C
L
= 1 μF, R
L
= 10 Ω3
ENABLE INPUT ( EN)
V
IH
High-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2 V4.5 V ≤V
I(IN)
≤5.5 V 0.8V
IL
Low-level input voltage V2.7 V ≤V
I(IN)
≤4.5 V 0.5I
I
Input current EN = 0 V or EN = V
I(IN)
– 0.5 0.5 μAt
on
Turnon time C
L
= 100 μF, R
L
= 10 Ω20 mst
off
Turnoff time C
L
= 100 μF, R
L
= 10 Ω40 ms
CURRENT LIMIT
TPS2010A 0.22 0.3 0.4T
J
= 25 °C, V
I
= 5.5 V,
TPS2011A 0.66 0.9 1.1I
OS
Short-circuit output current OUT connected to GND, ATPS2012A 1.1 1.5 1.8Device enable into short circuit
TPS2013A 1.65 2.2 2.7
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
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ELECTRICAL CHARACTERISTICS (Continued)
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= rated current, EN = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
SUPPLY CURRENT
T
J
= 25 °C 0.3 1Supply current, low-level output No Load on OUT EN = V
I(IN)
μA– 40 °C≤T
J
≤125 °C 10T
J
= 25 °C 58 75Supply current, high-level output No Load on OUT EN = 0 V μA– 40 °C≤T
J
≤125 °C 75 100Leakage current OUT connected to ground EN = V
I(IN)
– 40 °C≤T
J
≤125 °C 10 μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage 2 2.5 VHysteresis T
J
= 25 °C 100 mV
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
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PARAMETER MEASUREMENT INFORMATION
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 1. Test Circuit and Voltage Waveforms
Table 1. Timing Diagrams
FIGURE
Turnon Delay and Rise Time 2Turnoff Delay and Fall Time 3Turnon Delay and Rise TIME with 1- μF Load 4Turnoff Delay and Rise TIME with 1- μF Load 5Device Enabled into Short 6TPS2010A, TPS2011A, TPS2012A, and TPS2013A, Ramped Load on Enabled Device 7, 8, 9, 10TPS2013A, Inrush Current 117.9- ΩLoad Connected to an Enabled TPS2010A Device 123.7- ΩLoad Connected to an Enabled TPS2010A Device 133.7- ΩLoad Connected to an Enabled TPS2011A Device 142.6- ΩLoad Connected to an Enabled TPS2011A Device 152.6- ΩLoad Connected to an Enabled TPS2012A Device 161.2- ΩLoad Connected to an Enabled TPS2012A Device 171.2- ΩLoad Connected to an Enabled TPS2013A Device 180.9- ΩLoad Connected to an Enabled TPS2013A Device 19
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time
Figure 4. Turnon Delay and Rise Time With 1- μF Load Figure 5. Turnoff Delay and Fall Time With 1- μF Load
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 6. Device Enabled Into Short Figure 7. TPS2010A, Ramped Load on Enabled Device
Figure 8. TPS2011A, Ramped Load on Enabled Device Figure 9. TPS2012A, Ramped Load on Enabled Device
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 10. TPS2013A, Ramped Load on Enabled Device Figure 11. TPS2013A, Inrush Current
Figure 12. 7.9- ΩLoad Connected to an Enabled Figure 13. 3.7- ΩLoad Connected to an EnabledTPS2010A Device TPS2010A Device
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 14. 3.7- ΩLoad Connected to an Enabled Figure 15. 2.6- ΩLoad Connected to an EnabledTPS2011A Device TPS2011A Device
Figure 16. 2.6- ΩLoad Connected to an Enabled Figure 17. 1.2- ΩLoad Connected to an EnabledTPS2012A Device TPS2012A Device
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 18. 1.2- ΩLoad Connected to an Enabled TPS2013A Device
Figure 19. 0.9- ΩLoad Connected to an Enabled TPS2013A Device
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TYPICAL CHARACTERISTICS
Table of Graphs
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
FIGURE
t
d(on)
Turnon delay time vs Output voltage 20t
d(off)
Turnoff delay time vs Input voltage 21t
r
Rise time vs Load current 22t
f
Fall time vs Load current 23Supply current (enabled) vs Junction temperature 24Supply current (disabled) vs Junction temperature 25Supply current (enabled) vs Input voltage 26Supply current (disabled) vs Input voltage 27I
OS
Short-circuit current limit vs Input voltage 28vs Junction temperature 29r
DS(on)
Static drain-source on-state resistance vs Input voltage 30vs Junction temperature 31vs Input voltage 32vs Junction temperature 33Undervoltage lockout Input voltage vs Temperature 34
TURNON DELAY TIME TURNOFF DELAY TIMEvs vsOUTPUT VOLTAGE INPUT VOLTAGE
Figure 20. Figure 21.
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
RISE TIME FALL TIMEvs vsLOAD CURRENT LOAD CURRENT
Figure 22. Figure 23.
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 24. Figure 25.
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
SUPPLY CURRENT (ENABLED) SUPPLY CURRENT (DISABLED)vs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 26. Figure 27.
SHORT-CIRCUIT CURRENT LIMIT SHORT-CIRCUIT CURRENT LIMITvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 28. Figure 29.
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SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCEvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 30. Figure 31.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCEvs vsINPUT VOLTAGE JUNCTION TEMPERATURE
Figure 32. Figure 33.
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TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
UNDERVOLTAGE LOCKOUT
Figure 34.
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APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
OVERCURRENT
POWER DISSIPATION AND JUNCTION TEMPERATURE
PD+rDS(on) I2
(1)
TJ+PD RqJA )TA
(2)
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Figure 35. Typical Application
A 0.01- μF to 0.1- μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output and input pins is recommended when the output load isheavy. This precaution reduces power supply transients that may cause ringing on the input. Additionally,bypassing the output with a 0.01- μF to 0.1- μF ceramic capacitor improves the immunity of the device toshort-circuit transients.
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase theseries resistance of the current path. When an overcurrent condition is detected, the device maintains a constantoutput current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is presentlong enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before V
I(IN)
has been applied (see Figure 6 ). The TPS201xA senses the short andimmediately switches into a constant-current output.
In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive loadoccurs, very high currents may flow for a short time before the current-limit circuit can react (seeFigure 12 –Figure 19 ). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the deviceswitches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded (see Figures Figure 7 7–Figure 10 ). The TPS201xA is capable of delivering current up to thecurrent-limit threshold without damaging the device. Once the threshold has been reached, the device switchesinto its constant-current mode.
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to passlarge currents. The thermal resistance of these packages are high compared to those of power packages; it isgood design practice to check power dissipation and junction temperature. The first step is to find r
DS(on)
at theinput voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature ofinterest and read r
DS(on)
from SLVS1892074Figure 30 –Figure 33 . Next, calculate the power dissipation using:
Finally, calculate the junction temperature:
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THERMAL PROTECTION
UNDERVOLTAGE LOCKOUT (UVLO)
GENERIC HOT-PLUG APPLICATIONS (see Figure 36 )
TPS2010A, TPS2011ATPS2012A, TPS2013A
SLVS189C – DECEMBER 1998 – REVISED SEPTEMBER 2007
Where:
T
A
= Ambient Temperature °CR
θJA
= Thermal resistance SOIC = 172 °C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get an acceptable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The faults force the TPS201xA into constant current mode, which causes the voltageacross the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal tothe input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protectioncircuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sensecircuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continuesto cycle in this manner until the load fault or input power is removed.
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the inputvoltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design ofhot-insertion systems where it is not possible to turn off the power switch before input power is removed. TheUVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if theswitch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMIand voltage overshoots.
In many applications it may be necessary to remove modules or p-c boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Because of the controlled rise times and fall times of the TPS201xA series, these devices canbe used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature ofthe TPS201xA also ensures the switch will be off after the card has been removed, and the switch will be offduring the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertionof the card or module.
Figure 36. Typical Hot-Plug Implementation
By placing the TPS201xA between the V
CC
input and the rest of the circuitry, the input power will reach thisdevice first after insertion. The typical rise time of the switch is approximately 9 ms, providing a slow voltageramp at the output of the device. This implementation controls system surge currents and provides ahot-plugging mechanism for any device.
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PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2010AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2010ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2010ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2010ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2011AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2011ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2011ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2011ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2011APWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2011APWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2012AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2012ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2012ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2012ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2013AD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2013ADG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2013ADR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 30-Jul-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2013ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2013APWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2013APWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2013APWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2013APWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2010ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2011ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2012ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2013ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2013APWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2010ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2011ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2012ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2013ADR SOIC D 8 2500 340.5 338.1 20.6
TPS2013APWPR HTSSOP PWP 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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