DATASHEET
BUFFER/CLOCK DRIVER ICSLV810
IDT™ / ICS™
BUFFER/CLOCK DRIVER 1
ICSLV810 REV H 051310
Description
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout
buffer. This device is specifically designed for data
communications clock management. The large fanout from
a single input line reduces loading on the input clock. The
TTL level outputs reduce noise levels on the part. Typical
applications are clock and signal distribution.
Features
•Packaged in 20-pin QSOP/SSOP
•Split 1:10 fanout Buffer
•Maximum skew between outputs of different packages
0.75 ns
•Max propagation delay of 3.8 ns
•Operating voltage of 1.5 V to 2.5 V on Bank A
•Operating voltage of 1.5 V to 2.5 V on Banks B and C
•Advanced, low power, CMOS process
•Industrial temperature range -40° C to +85° C
•3.3 V tolerant input when VDDA=2.5 V
•Pb (lead) free packaging
Block Diagram
CLK 1
CLK 2
CLK 3
CLK 4
CLK 5
CLK 6
CLK 7
CLK 8
CLK 9
CLK 10
VDDA
VDDB
CLKIN
VDDC
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 2
ICSLV810 REV H 051310
Pin Assignment
Pin Descriptions
20 pin (150mil) SSOP
CLKIN
GND
CLK 1
VDDA
CLK 2
GND
CLK 3
CLK 4
VDDA
GND
GND
GND
VDDB
VDDC
CLK 5
CLK 6
CLK 7
CLK 8
CLK 9
CLK 10
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 CLKIN Input Clock input.
2 GND Power Connect to ground.
3 CLK1 Output Clock output.
4 VDDA Power Connect to +1.5 - +2.5 V.
5 CLK2 Output Clock output.
6 GND Power Connect to ground.
7 CLK3 Output Clock output.
8 VDDA Power Connect to +1.5 - +2.5 V.
9 CLK4 Output Clock output.
10 GND Power Connect to ground.
11 CLK5 Output Clock output.
12 CLK6 Output Clock output.
13 GND Power Connect to ground.
14 CLK7 Output Clock output.
15 VDDC Power Connect to +1.5 - 2.5 V.
16 CLK8 Output Clock output.
17 GND Power Connect to ground.
18 CLK9 Output Clock output.
19 CLK10 Output Clock output.
20 VDDB Power Connect to +1.5 - 2.5 V.
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 3
ICSLV810 REV H 051310
External Components
The ICSLV810 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitors
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pins
as possible. No vias should be used between the
decoupling capacitors and VDD pins. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI the 33Ω series termination resistor, if
needed, should be placed close to the clock output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICSLV810. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
Item Rating
Supply Voltage, VDD MAX 7 V
All Inputs and Outputs -0.5 V to VDDA + 1.2 V
Ambient Operating Temperature -40 to +85°C
Storage Temperature -65 to +150°C
Junction Temperature 125°C
Soldering Temperature 260°C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature -40 +85 °C
Power Supply Voltage (measured with respect to GND), VDDA 1.425 2.625 V
Power Supply Voltage (measured with respect to GND), VDDB 1.425 2.625 V
Power Supply Voltage (measured with respect to GND), VDDC 1.425 2.625 V
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
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ICSLV810 REV H 051310
DC Electrical Characteristics—CLKIN and Bank A
VDDA = 2.5 V, Ambient Temperature -40° C to +85° C
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics—Bank B
VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDDA 1.425 2.625 V
Quiescent Power Supply
Current
IDDA No Load
F = 40 MHz 15 mA
Short Circuit Current IOS CLK 1 - 5 ±80 mA
Input High Voltage,
CLKIN VIH
Guaranteed
Logic Level
High
1.6 V
Input Low Voltage,
CLKIN
VIL Guaranteed
Logic Level Low
0.8 V
Output High Voltage VOH VIN = VIH or
VIL
IOH = -7 mA 1.8 V
Output Low Voltage VOL VIN = VIH or
VIL
IOL =12 mA 0.4 V
Input High Current IIH VDD = max VIN = 2.4 V 1 µA
Input Low Current IIL VDD = max VIN = 0.5 V -1 µA
Input High Current IIVDD = max VIN = VDD
(max)
20 µA
Input Capacitance CIN VIN = 0V, Note1 5 6.0 pF
Output Capacitance COUT VOUT = 0V,
Note1
5.5 8.0 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDDB 1.425 2.625 V
Quiescent Power
Supply Current
IDDB VDDB = 2.5 V
No Load
F = 40 MHz
7mA
VDDB = 1.5 V
No Load
F = 40 MHz
3mA
Short Circuit
Current
IOS VDDB = 1.5 V CLK8-10 ±35 mA
VDDB = 2.5 V CLK8-10 ±80 mA
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 5
ICSLV810 REV H 051310
Note1: This parameter is not tested, guaranteed by design.
DC Electrical Characteristics—Bank C
VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Output High Voltage VOH VDDB = 1.5 V
VIN = VIH or VIL
IOH = -7 mA 1.1 V
VDDB = 2.5 V
VIN = VIH or VIL
IOH = -7 mA 1.8 V
Output Low Voltage VOL VDDB = 1.5 V
VIN = VIH or VIL
IOL =12 mA 0.42 V
VDDB = 2.5 V
VIN = VIH or VIL
IOL =12 mA 0.4 V
Input High Current IIH VDDB = max 1 µA
Input Low Current IIL VDDB = max -1 µA
Input High Current IIVDDB = max,
VIN = VDD (max)
20 µA
Input Capacitance CIN VIN = 0V, Note1 5 6.0 pF
Output Capacitance COUT VOUT = 0V,
Note 1
5.5 8.0 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDDC 1.425 2.625 V
Quiescent Power
Supply Current
IDDC VDDC = 2.5 V
No Load
F = 40 MHz
3mA
VDDC = 1.5 V
No Load
F = 40 MHz
2mA
Short Circuit Current IOS VDDC = 1.5 V CLK6-7 ±35 mA
VDDC = 2.5 V CLK6-7 ±80 mA
Output High Voltage VOH VDDC = 1.5 V
VIN = VIH or VIL
IOH = -7 mA 1.1 V
VDDC = 2.5 V
VIN = VIH or VIL
IOH = -7 mA 1.8 V
Output Low Voltage VOL VDDC = 1.5 V
VIN = VIH or VIL
IOL =12 mA 0.42 V
VDDC = 2.5 V
VIN = VIH or VIL
IOL =12 mA 0.4 V
Input High Current IIH VDDC = max 1 µA
Input Low Current IIL VDDC = max -1 µA
Parameter Symbol Conditions Min. Typ. Max. Units
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 6
ICSLV810 REV H 051310
Note1: This parameter is not tested, guaranteed by design.
AC Electrical Characteristics—Bank A
VDDA = 2.5 V, Ambient Temperature -40° C to +85° C
Input High Current IIVDDC = max,
VIN = VDD (max)
20 µA
Input Capacitance CIN VIN = 0V, Note1 5 6.0 pF
Output Capacitance COUT VOUT = 0V,
Note 1
5.5 8.0 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0) CL = 3 pF,
RL = 500Ω
Figure 3
-200 200 ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P) CL = 3 pF,
RL = 500Ω
Figure 4
-200 200 ps
Propagation Delay tpLH / tpHL CL = 3 pF,
RL = 500Ω
Figure 2
1.5 2.6 3.5 ns
Part to Part Skew tSK(t) CL = 3 pF,
RL = 500Ω
Figure 5
-650 650 ps
Output Rise Time
20% to 80%
tr(o) CL = 3 pF,
RL = 500Ω
0.8 ns
Output Fall Time
80% to 20%
tf(o) CL = 3 pF,
RL = 500Ω
0.8 ns
Additive Jitter tJAll Outputs 50 ps
Duty Cycle
Measured at VDD/2
DC CL = 3 pF,
RL = 500Ω
45 55 %
Duty Cycle, VDDA=1.8V DC 40 50 60 %
Output Frequency Range 1 133 MHz
Parameter Symbol Conditions Min. Typ. Max. Units
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 7
ICSLV810 REV H 051310
AC Electrical Characteristics—Bank B
VDDB = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter Symbol Conditions Min. Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0)CL = 3 pF, RL = 500Ω
Figure 3
-200 200 ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P) CL = 3 pF, RL = 500Ω
Figure 4
-200 200 ps
Propagation Delay tpLH / tpHL CL = 3 pF, RL = 500Ω,
VDDB = 1.5 V
Figure 2
5.5 ns
CL = 3 pF, RL = 500Ω,
VDDB = 2.5 V
Figure 2
1.5 2.6 3.5 ns
Part to Part Skew CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
Figure 5
-1 1 ns
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
Figure 5
-650 650 ps
Output Rise Time
20% to 80%
tr(o) CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
1.0 ns
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
0.8 ns
Output Fall Time
80% to 20%
tf(o) CL = 3 pF, RL = 500Ω
VDDB = 1.5 V
1.0 ns
CL = 3 pF, RL = 500Ω
VDDB = 2.5 V
0.8 ns
Additive Jitter tJAll Outputs,
VDDB = 1.5 V
34 ps
All Outputs,
VDDB = 2.5 V
50 ps
Duty Cycle
Measured at VDD/2
DC CL = 3 pF,
RL = 500Ω
45 55 %
Duty Cycle, VDDB = 1.8V DC 40 50 60 %
Output Frequency Range 1 133 MHz
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 8
ICSLV810 REV H 051310
AC Electrical Characteristics—Bank C
VDDC = 2.5 V, Ambient Temperature -40° C to +85° C, unless otherwise noted
Parameter Symbol Conditions Min. Typ. Max. Units
Output Skew: skew between
outputs of same package
tSK(0)CL = 3 pF, RL = 500Ω
Figure 3
-200 200 ps
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P) CL = 3 pF, RL = 500Ω
Figure 4
-200 200 ps
Propagation Delay tpLH / tpHL CL = 3 pF, RL = 500Ω,
VDDC = 1.5 V
Figure 2
5.5 ns
CL = 3 pF, RL = 500Ω,
VDDC = 2.5 V
Figure 2
1.5 2.6 3.5 ns
Part to Part Skew CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
Figure 5
-1 1 ns
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
Figure 5
-650 650 ps
Output Rise Time
20% to 80%
tr(o) CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
1.0 ns
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
0.8 ns
Output Fall Time
80% to 20%
tf(o) CL = 3 pF, RL = 500Ω
VDDC = 1.5 V
1.0 ns
CL = 3 pF, RL = 500Ω
VDDC = 2.5 V
0.8 ns
Additive Jitter tJAll Outputs,
VDDC = 1.5 V
34 ps
All Outputs,
VDDC = 2.5 V
50 ps
Duty Cycle
Measured at VDD/2
DC CL = 3 pF,
RL = 500Ω
45 55 %
Duty Cycle, VDDC=1.8V DC 40 50 60 %
Output Frequency Range 1 133 MHz
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 9
ICSLV810 REV H 051310
Thermal Characteristics for 20QSOP
Thermal Characteristics for 20SOIC
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air 135 °C/W
θJA 1 m/s air flow 93 °C/W
θJA 3 m/s air flow 78 °C/W
Thermal Resistance Junction to Case θJC 60 °C/W
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
θJA Still air 83 °C/W
θJA 1 m/s air flow 71 °C/W
θJA 3 m/s air flow 58 °C/W
Thermal Resistance Junction to Case θJC 46 °C/W
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
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ICSLV810 REV H 051310
tPLH
Input
Output
From Output
Under Test
CL=3pF 500 ohm
VOH
VOL
VIH
VIL
tPHL
VOH
VOL
VOH
VOL
Input
Output 1
Output 2
tSK tSK
tPLH1 tPHL1
tPLH2 tPHL2
Figure 2. Propagation Delay
( tSK(O)=|tPLH2-tPHL2| or |tPLH1-tPHL1| )
Figure 3. Output Skew
Figure 1. Load Circuit
Figure 4. Pulse Skew ( tSK(p)=|tpLH – tpH| )
VOH
VOL
Input
Output 1
tPLH1 tPHL1
VOH
VOH
Input
Package
1 Output
Package
2 Output
tSK tSK
tPLH1 tPHL1
tPLH2 tPHL2
( tSK(O)=|tPLH2-tPHL2| or |tPLH1-tPHL1| )
Figure 5. Part-to-Part Skew
VOL
VOL
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
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ICSLV810 REV H 051310
Package Outline and Package Dimensions (20-pin QSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
INDEX
AREA
1 2
20
D
E1 E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
.10 (.004) C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A 1.351.75.053.069
A1 0.10 0.25 .0040 .010
A2 -- 1.50 -- .059
b 0.20 0.30 0.008 0.012
C 0.180.25.007.010
D 8.558.75.337.344
E 5.806.20.228.244
E1 3.80 4.00 .150 .157
e 0.635 Basic 0.025 Basic
L 0.401.27.016.050
α0°8°0°8°
ICSLV810
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IDT™ / ICS™
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ICSLV810 REV H 051310
Package Outline and Package Dimensions (20-pin SSOP, 209 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility
for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to
change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
Part / Order Number Marking Shipping Packaging Package Temperature
LV810RILF LV810RILF Tubes 20-pin QSOP -40 to +85° C
LV810RILFT LV810RILF Tape and Reel 20-pin QSOP -40 to +85° C
LV810FILF LV810FILF Tubes 20-pin SSOP -40 to +85° C
LV810FILFT LV810FILF Tape and Reel 20-pin SSOP -40 to +85° C
INDEX
AREA
1 2
20
D
E1 E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
.10 (.004) C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A — 2.00 — .079
A1 0.05 — .002 —
A2 1.65 1.85 .065 .073
b 0.22 0.38 0.009 0.015
c 0.09 0.25 .0035 .010
D 6.907.50.271.295
E 7.408.20.291.323
E1 5.00 5.60 .197 .220
e 0.65 Basic 0.0256 Basic
L 0.550.95.022.037
α0°8°0°8°
ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
IDT™ / ICS™
BUFFER/CLOCK DRIVER 13
ICSLV810 REV H 051310
Revision History
Rev. Originator Date Description of Change
A P.Griffith 03/25/05 New device/datasheet.
B P.Griffith 05/02/05 Released from Preliminary to final; changed Short Circuit Current parameter in 2.5 V DC
Char table to ±80 mA; changed Short Circuit Current parameter in 1.5 V DC Char table to
±35 mA
C P.Griffith 05/12/05 Added bullet in “Features” for operating voltage of 2.5 V on Bank A and specified that
operating voltages of 1.5 and 2.5 V are on Banks B and C; changed block diagram input
and pin 1 from IN to CLKIN; removed +1.5 V spec from pin 4 and pin 8 descriptions; added
“VDDA + 1.2 V” to “All Inputs and Outputs” section of Absolute Maximum Ratings; added
min and max values for Banks A, B, and C “Power Supply Voltage” in Recommended
Operating Conditions; expanded DC Electrical Char tables in to include a separate table
for Banks A, B, and C; expanded AC Electrical Char tables in to include a separate table
for Banks A, B, and C;
D P.Griffith 06/21/05 Added 209 mil 20-pin SSOP package and ordering info.
E K. Beckmeyer 07/27/05 Specified operating voltage on Bank A from 1.5V to 2.5V; Added figures 4 and 5 on page
10 to explain Pulse Skew and Part-to-Part Skew; Changed Output Frequency Max
Specification to 133MHz in AC Electrical Char tables for Banks A, B, and C; Added Duty
Cycle Spec for VDD = 1.5V in AC Electrical Char tables for Banks A, B, C; Changed CLK
conditions in DC Electrical Char tables on Banks B and C; removed SOIC package.
F K. Beckmeyer 10/13/05 Added “LF” packaging and ordering info to both “R” and”F” packages.
G 12/17/09 Added EOL note for non-gren parts.
H 05/13/10 Removed EOL note and non-green orderables.
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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ICSLV810
BUFFER/CLOCK DRIVER FAN OUT BUFFER
