HARRIS SEMICOND SECTOR iG] HARRIS CMOS 8-Bit Addressable Latch High-Voltage Types (20-Volt Rating) @ CD4099B &-bit addressable tatch Is a serial-input, parallel-output storage regis- ter that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs AO, Al, A2}) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; write oisaste |, |2-a0 OATA 3 ar Features: 5 LE ge Serial datainput = Active parallel output fa t Bes @ Storage register capability Master clear az} ea 12 3s Can function as demultiplexer RESET we LS? Standardized, symmetrical output characteristics Vss6 32.5 gaara @ 100% tested for quiescent current at 20 V Maximum input current of 1 uA at 18 V CD4099B Types (full package-temperature range), 100 nA at 18 V and 25C WUE D MM 4302271 0037550 S BMHAS T#6-07-t/ rt however, all 8 outputs can be continuously . Functional Diagram read independent of WRITE DISABLE and Noise margin (full package-temperature address inputs. range) = 1 Vat Vpp =5 V, 2 Vat Vpp = 10 V, 2.5 Vat Vpp = 15 V A master RESET input is available, which 4 5-V, 10-V, and 15-V parametric ratings Applications: = Multi-line decoders = A/D converters Meets all requirements of JEDEC Tentative Standard No. 138, Standard Specifications for Description of B Series CMOS Devices resets all bits to alogic O evel when RESET and WRITE DISABLE are at a high evel. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-0f-8 demultiplexer; the bit that is ad- MAXIMUM RATINGS, Absolute-Maximum Values: RD w Gressed has an active output which follows | OC SUPPLY-VOLTAGE RANGE, pp) = s the data input, while all unaddressed bits Voltages referanced to Vg Terminal) 0.0... .c cece sasesecccesenesneseseescassuce +. 70.5V to +20V 2 9g are held toa logic 0 level. OC INPUT COTA RANGE, ALL INPUTS 2... eee eee cceceeeeescunseteeseuene + -0.5V to Von +0.5V s 5 The CD40998 types are supplied in 16-lead POWER Dissiparion Poh pacrne (Pp): aa Treteererecernceees TOMA i <4 hermetic ceramic dual-in-line packages (D For Ta = -55C 10 #50006 ooo eee cc eeeccseecccseueeces seeseacase be eedeetenaeeees s00mW ES and F suffixes), 16-lead plastic dual-in-line For Ta = +100C to #1250. ce eec cease se cees Darate Linearity at 12mW/C to 200mW 8= Packages (E suffix), and in chip form (H OEVICE DISSIPATION PER OUTPUT TRANSISTOR sutfix). FOR Ta = FULL PACKAGE-TEMPERATURE RANGE (All Package TYPES) civ eees eee ees beveeaee 100mW OPERATING-TEMPERATURE RANGE (Ta) Veweeenevereeese ss S59 lo $1259G STORAGE TEMPERATURE RANGE (Tgig).-.. sss sssessseseeceeeteseeseesccecs -659C to #150C LEAD TEMPERATURE (DURING SOLDERING): At distance 1/16 + 1/32 inch (1.59 + 0.79mm) from case for 10s max .. peeeeee $2659C | a a Rl 6 5 | 35 > Bl @avousrun= TOP VIEW szes-24az6 TERMINAL ASSIGNMENT 9: RITE O > > ' aa wi a OFSABLE wo az + z RESET ESE Of>ofDeo-s R . ADONESS Yoo" 3 o0 oaTa , . *au. inpurs ane PROTECTED ay NETWORK ORAIN-TO-SOURCE VOLTAGE [vps)V . a cris ersiery vas 92CM-2767h1 Fig. 2 Typical output tow (sink) ; currat characteristics. Fig. 1 Logic diagram of CD40998 and detail of I of 8 latches. 3-231HARRIS SEMICOND SECTOR CD4099B Types RECOMMENDED OPERATING CONDITIONS at Ty = 25 C (Unless otherwise specified) For maximum reliability, neminal operating conditions should be selected so that operation is always within the following ranges. CHARACTERISTIC SEE | Vpo LIMITS UNITS FIG. 15* (v) MIN. MAX. Supply Voltage Range: {At Ta = Full Package 3 18 Vv Temperature Range) Minimum Pulse Width, tw 5 200 - Data G) 10 100 - 15 80 5 400 = ns Address 10 200 - 15 125 - 5 150 - Reset @) 10 76 - 15 50 - Setup Time, tg 5 100 - Data to WRITE DISABLE () 10 50 - 15 35 - ns Hoid Time, ty 5 150 = Data to WRITE DISABLE G) 10 75 - ns 15 50 - * Circled numbers refer to times indicated on master timing diagram. Note: Jn addition to the above characteristics, a WRITE DISABLE ON time (the time that WRITE DISABLE is at a high level) must be observed during an address change for the tota! time that the external address lines AO, Al, and A2 are settling to a stable level, to prevent a wrong cell from being addressed (sea Fig. 3}. Tt cu4047 4) 557 04520 ato, In <1g) oF 4 D4099 START CONVERSION To OISPLAY MSB * 4 C0401 Rak P MYCOMP nczI0SLD-2R LAODER Kxetwoak ! AHALOG 1" Fig. A/D converter 2cu-276ur 3-232 U4E D u302271 O03755% 7 MBHAS 7T- 76-07 UL - _ MODE SELECTION wo] p | ADDRESSED | UNADDRESSED LATCH LATCH - 0 | O| Follows Data: | Holds: Previous State . 0 | 1] Follows Data. | Reset to.0" (Active High 8-Channel: Demiulti-- plexer) 1 6 Holds Previous State 1_| 1] Reset-to Oo | Reset to 0 WD = WRITE DISABLE. ' R=RESET Ao Al Az wo. Q2CS-27676 Fig. 3 Definition of WRITE DISABLE ON time: ORAIN-T0-SOURCE VOLTAGE : - 92085 -24sigay Fig. 4. Minimum output low {sink} current Characteristics: ORAIN-TO-SOURCE VOLTAGE Vpgi=v = S Stesanens | Fig. = Typical output high (source) - - current chardteristics. - :HARRIS SEMICOND SECTOR STATIC ELECTRICAL CHARACTERISTICS YUE D CD4099B Types 4y302271 O03755e 4 ER HAS CONDITIONS LIMITS AT INDICATED TEMPERATURES (C) CHARACTER. ISTIC 75 UNITS Vo | Vin [Yop - (Vv) (v) | (vp | -55 | 40 +85 +125 | Min. | Typ. | Max. Quiescent Device - 0,5 5 5 5 150 150 - 0.04 5 Current, - 0,10] 10 | 10 10 300 | 300 | 0.04 | 10 uA 100 Max. - 015} 15 | 20 | 20 | 600 | 600 | | 0.04 | 20 - 0,20] 20 { 100 | too [3aco | 3000! | o0s8 | 100 Output Low o4 [os {56 | 064/061 | 042 | 0.26} 051 1 = (Sink) Current 05 |010/ 10] 16 | 15 Ww 09 | 13 2.6 - fou Min. 15 [015] 15 | 42 [4 | 28 | 241394) 68 |< Output High 46 | 05 | 5 | -064|~0.61|-0.42[-o36/-051[ 1 | mA (Source) 25 os | 5 | -2 |~18 | -1.3 ]-1.15f-1.6 | -3.2 - Current, 95 [o10{ 10 |-16/-15 |-11 |-09}-19} 6 | 10H Min. 13.5 |0,15{ 15 |-42 | -4 [-28 |[-24/-34 [-6e8 | Output Voltage: - 0,5 5 0.05 ~ Q 0.05 Low-Level, [o10] 10 0.05 0 | 0.05 Vot Max. = 0.15] 15 0.05 = 0 [oo] , Output Voltage - 05 5 4.95 4,95 - High-Level, = 0,10] 10 9.95 9.95 | 10 = VOH Min. [015] 15 14.95 14.95 | 15 input Low 0.5, 4.5 ~ 5 1.5 _ - 15 Voltage. 1,9 _ 10 _ _ 3 y / . Mex Te igs) TPs = aly Input High 05,45] - 5 3.5 3.5 - - Voltage, 1.9 { 10 7 = = VIH Ming Tre igs - | 15 11 ufo fe re current - for8} 18] 01] s01 7 2 | 21 | Jere-S] sor] pa b_4 -10 (0:102-0.254) 94-192 (2.388-2.591) 920N- 38095 CD4099BH DIMENSIONS AND PAD LAYOUT Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-9 inch), 3-233 T V6-O90-U ORAIN-TO-SOURCE VOLTASE (psinv ~ . f LT 7 Mtewcasnad - Fig.7 ~ Minimum output high: (source) 7 oR, 7 > current characteristics. LOAD CAPACITAKCE icclsaF 92eg-22ary HIGH VOLTAGE !Cs Fig. 8 = Typical propagation delay tim (data to Qn) vs. load capacitance: COMMERCIAL CMOS Cy Oo LOAD CAPACITANCE (CL)F dres-2esry Fig. 9 Typical transition time vs. load capacitance. . AMBIENT wesc {dels pf Sep, G O % a 5 Sy m2 ADDRESS CYCLE p . S2c8-27640 Fig.10 Typical dynamic power dissipation vs. address cycle time...HAS HARRIS SEMICOND SECTOR WOE D 4y302274 0037553 0 CD4099B Types a. a 7~Y6-00-!/ DYNAMIC ELECTRICAL CHARACTERISTICS at Ty = 25C, C) = 50 pF, . Yoo ; Input t,, t = 20ns, Ry = 200 KQ. Yoo . t . : inputs [- a : o Pe Soe Vss : : LIMITS _. = . CONDITIONS . Ls So CHARACTERISTIC SEE | Vop ALL PACKAGE TYPES | Units rn FIG.15*| (Vv) TYP. MAX. . - Propagation Delay: tpi yy. 5 200 400 - tru. | G@) [0 | 7s 180 - Data to Output, 15 50 100 Ow ss : ig. ~ Quiescent device current WRITE DISABLE 5 | 200 400 Fig. 11 testalreun et to Output, put tein. | (2) [10 80 160 ns vo PHL 15 60 120 / 5 175 350 inputs, | |gutputs Vv - Reset to Output, @ 10 80 160 a = Teg (PHL 15 68 130 +4 pe EO: jo a7 = Address to Output, 5 225 450 wore: OTE: | torn | @) [10 | 100 200 Veg TEST ANY coustnariog (PHL 15 75 160 _ 8732 TAMIL Transition Time, ty. 5 100 200 Fig. 12 = Input voltage test circurt. {Any Outpud = tT EW 10 50 too ns a 15 40 80 wuss | 7 . - Yoo NOTE Minimum Pulse 5 100 200 = ; MEASURE WniPuTS SEQUENTIALLY, Width, ty @ [10 50 100 ns Ss J #6 bore et tub Veg Data 15 40 80 LL _| eurs To eitnen 5 200 400 t Yon RNss~ azts~-27agz Address 10 100 200 ns Fig, 13 ~ Input current test circuit, - 15 65 125 - - ao ad oor 5 75 50 a al ait! go2 Be A2 oo3 Reset 10 40 75 ns wo p04 15 25 50 OATAIH 005 Minimum Setup 5 50 100 , pa Time, tg @ 10 25 50 ns poe Data to WRITE DISABLE 15 20 35 Minimum Hold 5 75 150 Time, ty @ [10 40 75 ns sO 8g 008 Data to WRITE DISABLE 15 25 50 Az G2 yy OOH wo cole . DATA bold Input Capacitance, Cypy Any Input 5 75 pF % 176 co4069 c04099 cota - oo1s *Ciccted numbers refer to times indicated on master timing diagram. dois 9208-27675 Bee ee Fig, 14 1 of 16 decoder/dmultiplexer. ac ae az 4 . : : Va cOsGi6 whut - 040988 soeaume fC DATA Ao > 2 a y are w } 3 z 7 1 . rr a 2 abe ee @ ope y YO 290 > hy on F 2 . oO . >? o faery hy so wo = os E s g @ s2cs- 27677 WO: - Loe Fi, - Fig. 16 ~ Multiple slection decading 4 x 4 7g. 15 Master timing diagram. crosspoint switch. - 3-234