REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
OP77
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Next Generation OP07
Ultralow Offset Voltage Operational Amplifier
PIN CONNECTIONS
Epoxy Mini-Dip (P-Suffix)
8-Pin Hermetic DIP
8
7
6
5
1
2
3
4
NC = NO CONNECT
V
OS
TRIM
–IN
+IN
V
OS
TRIM
V+
OUT
NCV–
OP07
TO-99
(J-Suffix)
V+
OUT
NC
4V– (CASE)
VOS TRIM
VOS TRIM 1
–IN 2
+IN 3
OP07
NC = NO CONNECT
FEATURES
Outstanding Gain Linearity
Ultrahigh Gain 5000 V/mV Min
Low VOS Over Temperature 60 ␮V Max
Excellent TCVos 0.3 ␮V/ⴗC Max
High PSRR 3 ␮V/V Max
Low Power Consumption 60 mW Max
Fits OP07, 725,108A/308A, 741 Sockets
Available in Die Form
(OPTIONAL
NULL)
Q27
7
V+
NOTE:
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY.
NON-
INVERTING
INPUT
INVERTING
INPUT
3
2
R3
R4
R2A
R1A
Q5 Q7
Q21
Q22 Q23
Q24
Q3
Q1
Q6 Q8 Q4
Q2
18
R2B
R1B
Q26
Q25
C1
C2
C3
Q11 Q12
Q14
Q13
R5
Q10
Q17 Q16
Q15
R6 R8
Q18
Q20
R10
R9
R7
Q19
Q9
OUTPUT
6
V–4
GENERAL DESCRIPTION
The OP77 significantly advances the state-of-the-art in precision
op amps. The OP77’s outstanding gain of 10,000,000 or more
is maintained over the full 10 V output range. This exceptional
gain-linearity eliminates incorrectable system nonlinearities
common in previous monolithic op amps, and provides superior
performance in high closed-loop gain applications. Low initial
V
OS
drift and rapid stabilization time, combined with only 50
mW power consumption, are significant improvements over
previous designs. These characteristics, plus the exceptional
TCV
OS
of 0.3 mV/∞C maximum and the low V
OS
of 25 mV maxi-
mum, eliminates the need for V
OS
adjustment and increases
system accuracy over temperature.
PSRR of 3 mV/V (110 dB) and CMRR of 1.0 mV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding char-
acteristics makes the OP77 ideally suited for high-resolution
instrumentation and other tight error budget systems.
REV. C
–2–
OP77–SPECIFICATIONS
OP77A
Parameter Symbol Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE V
OS
10 25 mV
LONG-TERM INPUT OFFSET
VOLTAGE STABILITY
1
DV
OS
/Time 0.2 mV/Mo
INPUT OFFSET CURRENT I
OS
0.3 nA
INPUT BIAS CURRENT I
B
–0.2 1.2 2.0 nA
INPUT NOISE VOLTAGE
2
e
np-p
0.1 Hz to 10 Hz 0.35 0.6 mV p-p
INPUT NOISE VOLTAGE DENSITY
2
e
n
f
O
= 10 Hz 10.3 18.0 nV/÷Hz
f
O
= 100 Hz 10.0 13.0
f
O
= 1000 Hz 9.6 11.0
INPUT NOISE CURRENT
2
i
np-p
0.1 Hz to10 Hz 14 30 pA p-p
INPUT NOISE CURRENT DENSITY
2
i
n
f
O
= 10 Hz 0.32 0.80 pA/÷Hz
f
O
= 100 Hz 0.14 0.23
f
O
= 1000 Hz 0.12 0.17
INPUT RESISTANCE
Differential Mode
3
R
IN
26 45 MV
Common Mode R
INCM
200 GV
INPUT VOLTAGE RANGE IVR ±13 ±14 V
COMMON-MODE
REJECTION RATIO CMRR V
CM
= ±13 V 0.1 1.0 mV/V
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 0.7 3 mV/V
LARGE-SIGNAL
VOLTAGE GAIN A
VO
R
L
≥ 2 kW ≥ VO = ±10V 5000 12000 V/mV
OUTPUT VOLTAGE SWING V
O
R
L
≥ 10 kW±13.5 ±14.0 V
R
L
≥ 2 kW±12.5 ±13.0
R
L
≥ 1 kW±12.0 ±12.5
SLEW RATE
2
SR RL ≥ 2 kW0.1 0.3 V/ms
CLOSED-LOOP BANDWIDTH
2
BW A
VCL
= +1 0.4 0.6 MHz
OPEN-LOOP OUTPUT RESISTANCE R
O
60 W
POWER CONSUMPTION P
d
V
S
= ±15 V, No Load 50 60 mW
V
S
= ±3 V, No Load 3.5 4.5
OFFSET ADJUSTMENT RANGE R
P
= 20 kW±3mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V
OS
vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V
OS
during the first 30 operating days are typically 2.5 mV.
2
Sample tested.
3
Guaranteed by design.
ELECTRICAL SPECIFICATIONS
(@ Vs = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.)
REV. C –3–
OP77
SPECIFICATIONS
OP77A
Parameter Symbol Conditions Min Typ Max Unit
INPUT OFFSET VOLTAGE V
OS
25 60 mV
AVERAGE INPUT OFFSET
VOLTAGE DRIFT
1
TCV
OS
0.1 0.3 mV/∞C
INPUT OFFSET CURRENT I
OS
0.5 2.2 nA
AVERAGE INPUT OFFSET
CURRENT DRIFT
2
TCI
OS
1.5 25 pA/∞C
INPUT BIAS CURRENT I
B
–0.2 2.4 4 nA
AVERAGE INPUT BIAS
CURRENT DRIFT
2
TCI
B
8 25pA/∞C
INPUT VOLTAGE RANGE IVR ±13 ±13.5 0.6 V
COMMON-MODE
REJECTION RATIO CMRR V
CM
= ±13 V 0.1 1.0 mV/V
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 1 3 mV/V
LARGE-SIGNAL
VOLTAGE GAIN A
VO
R
L
≥ 2 kW ≥ V
O
= ±10 V 2000 6000 V/mV
OUTPUT VOLTAGE SWING V
O
R
L
≥ 10 kW±12 ±13.0 V
POWER CONSUMPTION P
d
V
S
= ±15 V, No Load 60 75 mW
NOTES
1
OP77A: TCV
CS
is 100% tested.
2
Guaranteed by design.
ELECTRICAL SPECIFICATIONS
(@ Vs = ⴞ15 V, –55ⴗC £ TA £ 125ⴗC, unless otherwise noted.)
REV. C
–4–
OP77–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE VOS 10 25 20 60 mV
LONG-TERM
STABILITY
1
V
OS
/Time 0.3 0.4 mV/Mo
INPUT OFFSET CURRENT I
OS
0.3 1.5 0.3 2.8 nA
INPUT BIAS CURRENT I
B
–0.2 1.2 2.0 –0.2 1.2 2.8 nA
INPUT NOISE VOLTAGE
2
e
np-p
0.1 Hz to 10 Hz 0.35 0.6 0.38 0.65 mV
p-p
INPUT NOISE
VOLTAGE DENSITY e
n
f
O
= 10 Hz 10.3 18.0 10.5 20.0 nV/÷Hz
f
O
= 100 Hz
2
10.0 13.0 10.2 13.5
f
O
= 1000 Hz 9.6 11.0 9.8 11.5
INPUT NOISE CURRENT
2
i
np-p
0.1 Hz to 10 Hz 14 30 15 35 pA
p-p
INPUT NOISE
CURRENT DENSITY i
n
f
O
= 10 Hz 0.32 0.80 0.35 0.90 pA÷Hz
f
O
= 100 Hz
2
0.14 0.23 0.15 0.27
f
O
= 1000 Hz 0.12 0.17 0.13 0.18
INPUT RESISTANCE
Differential Mode
3
R
IN
26 45 18.5 45 MW
Common Mode R
INCM
200 200 GW
INPUT RESISTANCE
Common Mode R
INCM
200 200 GW
INPUT VOLTAGE RANGE IVR ⫾13 ⫾14 ⫾13 ⫾14 V
COMMON-MODE
REJECTION RATIO CMRR V
CM
= ⫾13 V 0.1 1.0 0.1 1.6 mV/V
POWER SUPPLY
REJECTION RATIO PSRR V
S
= 3 V to 18 V 0.7 3.0 0.7 3.0 mV/V
LARGE-SIGNAL
VOLTAGE GAIN A
VO
R
L
≥ 2 k⍀5000 12000 2000 6000 V/mV
OUTPUT VOLTAGE
SWING V
O
R
L
≥ 10 k⍀⫾13.5 ⫾14.0 ⫾13.5 ⫾14.0 V
R
L
≥ 2 k⍀⫾12.5 ⫾13.0 ⫾12.5 ⫾13.0
R
L
≥ 1 k⍀⫾12.0 ⫾12.5 ⫾12.0 ⫾12.5
SLEW RATE
2
SR R
L
≥ 2 k⍀0.1 0.3 0.1 0.3 V/ms
CLOSED-LOOP
BANDWIDTH
2
BW A
VCL
1 0.4 0.6 0.4 0.6 MHz
OPEN-LOOP OUTPUT
RESISTANCE R
O
60 60 W
POWER CONSUMPTION Pd V
S
= ⫾15 V, No Load 50 60 50 60
V
S
= ⫾3 V, No Load 3.5 4.5 3.5 4.5 mW
OFFSET ADJUSTMENT
RANGE Rp = 20 kn ⫾3⫾3mV
NOTES
1
Long-Term Input Offset Voltage Stability refers to the averaged trend line of V
OS
vs. Time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in V
OS
during the first 30 operating days are typically 2.5 mV.
2
Sample tested.
3
Guaranteed by design.
(@ Vs = ⴞ15 V, TA = 125ⴗC, unless otherwise noted.)
REV. C –5–
OP77
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
OP77E OP77F
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE V J. Z Packages 10 45 20 100 mV
10 55 20 100
AVERAGE INPUT OFFSET TVC
OS
J. Z Packages 0.1 0.3 0.2 0.6 mV/∞C
VOLTAGE DRIFT
1
0 3 0.6 0.4 1.0
INPUT OFFSET CURRENT I
OS
0.5 2.2 0.5 4.5 nA
AVERAGE INPUT OFFSET
CURRENT DRIFT
2
TCI
OS
1.5 4.0 1.5 85 pA/⬚C
INPUT BIAS CURRENT I
B
E, F -0.2 2.4 4.0 -0.2 2.4 6.0 nA
AVERAGE INPUT BIAS
CURRENT DRIFT
2
TCI
B
840 1560pA/∞C
INPUT VOLTAGE RANGE IVR ⫾13.0 ⫾13.5 ⫾13.0 ⫾13.5 V
COMMON-MODE
REJECTION RATIO CMRR V
CM
= ⫾13 V 0.1 1.0 0.1 3.0 pVlV
POWER SUPPLY
REJECTION RATIO PSRR V
S
= ⫾3 V to ⫾18 V 1.0 3.0 1.0 5.0 mV/V
LARGE-SIGNAL
VOLTAGE GAIN A
VO
R
L
≥ 2 kW2000 6000 1000 4000 V/mV
V
O
= ⫾10 V
OUTPUT VOLTAGE SWING V
O
R
L
≥ 2 kW⫾12 ⫾13.0 ⫾12 ⫾13.0 V
POWER CONSUMPTION P
d
V
S
= ⫾15 V, No Load 60 75 60 75 mW
NOTES
1
OP77E: TCV
OS
is 100% tested on J and Z packages.
2
Guaranteed by end-point limits.
(@ Vs = ⴞ15 V, –25ⴗC £ TA £ +85ⴗC for OP77E/FJ and OP77E/FZ, unless otherwise noted.)
REV. C
–6–
OP77–SPECIFICATIONS
OP77N
Parameter Symbol Conditions Limit Unit
INPUT OFFSET VOLTAGE V
OS
40 mV Max
INPUT OFFSET CURRENT I
OS
2.0 nA Max
INPUT BIAS CURRENT I
B
±2nA Max
INPUT RESISTANCE
Differential Mode R
IN
26 MW Min
INPUT VOLTAGE RANGE IVR ±13 V Min
COMMON-MODE REJECTION RATIO CMRR V
CM
= ±13 V 1 mV/V Max
POWER SUPPLY REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 3 mV/VMax
OUTPUT VOLTAGE SWING V
O
R
L
= 10 kW±13.5 V Min
R
L
= 2 kW±12.5
R
L
= 1 kW±12.0
LARGE-SIGNAL VOLTAGE GAIN A
VO
R
L
= 2 kW2000 V/mV Min
V
O
= ±10 V
DIFFERENTIAL INPUT VOLTAGE ±30 V Max
POWER CONSUMPTION P
d
V
OUT
= 0 V 60 mW Max
NOTES
1
Guaranteed by design.
2
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
WAFER TEST LIMITS
(@ Vs = ⴞ15 V, TA = 25ⴗC, for OP77N devices, unless otherwise noted.)
TYPICAL ELECTRICAL CHARACTERISTICS
(@ Vs = ⴞ15 V, TA = 25ⴗC, unless otherwise noted.)
OP77N
Parameter Symbol Conditions Limit Unit
AVERAGE INPUT OFFSET VOLTAGE DRIFT TCV
OS
R
S
= 50 W0.1 mV/OC
NULLED INPUT OFFSET VOLTAGE DRIFT TCV
OSn
R
S
= 50 W, R
P
= 20 kW0.1 mV/∞C
AVERAGE INPUT OFFSET CURRENT DRIFT TCI
OS
0.5 pA/∞C
SLEW RATE SR R
L
≥ 2 kW0.3 V/ms
BANDWIDTH BW A
VCL
+ 1 0.6 MHz
REV. C
OP77
–7–
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . .Indefinite
Storage Temperature Range
J and Z Packages . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP77A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP77E, OPP77F (J, Z) . . . . . . . . . . . . . . . . –25∞C to +85∞C
Junction Temperature (T
j
) . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 60 sec.) . . . . . . . . . . . . . 300∞C
NOTES
1
Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
Package Type ␪
jAⴱ
␪
jC
Unit
TO-99 (J) 150 18 ∞C/W
8-Lead Hermetic DIP (Z) 148 16 ∞C/W
NOTE
ⴱ
␪
jA
is specified for worst-case mounting conditions, i.e., ␪
jA
is specified for
device in socket for TO, CERDIP, P-DIP, and PLCC packages; ␪
jA
is specified
for device soldered to printed circuit board for SO package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP77 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
BONDING DIAGRAM
DIE SIZE 0.093
ⴛ
0.057 inch, 5301 sq. mm
(2.36
ⴛ
1.45 mm, 3.42 sq. mm)
1. BALANCE
2. INVERTING INPUT
3. NONINVERTING INPUT
4. V-
6. OUTPUT
7. V+
8. BALANCE
ORDERING GUIDE
Package Options Operating
CERDIP
*
Temperature
TO-99 8-Lead Range
OP77AZ MIL
OP77EJ OP77EZ IND
OP77FJ OP77FZ IND
ⴱ
Not for new designs; obsolete April 2002.
For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD Part Number ADI Equivalent
5962-87738012A OP77BRCMDA
5962-8773802GA OP77AJMDA
5962-8773802PA OP77AZMDA
REV. C
OP77
–8–
–Typical Performance Characteristics
OUTPUT VOLTAGE – V
INPUT VOLTAGE – ␮V
(NULLED TO 0␮ @VOUT = 0V)
–2 10
–1
0
1
2
50–5–10
VS = ⴞ15V
TA = 25ⴗC
RL = 10k⍀
TPC 1. Gain Linearity (Input
Voltage vs. Output Voltage)
TEMPERATURE – ⴗC
CHANGE IN OFFSET VOLTAGE – ␮V
–30–55
J, Z PACKAGES
+0.3␮V/ⴗC
–20
–10
0
10
20
30
–35 –15 5 25456585105125
MEAN
–0.3␮V/ⴗC
S.D.
TPC 4. Untrimmed Offset
Voltage vs. Temperature
FREQUENCY – Hz
CLOSED-LOOP GAIN – dB
–2010
V
S
= ⴞ15V
T
A
= 25ⴗC
0
20
40
60
80
100
100 1k 10k 10k 10M1M
TPC 7. Closed-Loop Response for
Various Gain Configurations
TEMPERATURE – ⴗC
OPEN-LOOP GAIN – V/␮V
0
–55
V
S
= ⴞ15V
–35 –15 525456585105125
5
10
15
20
25
TPC 2. Open-Loop Gain vs.
Temperature
TIME AFTER POWER SUPPLY TURN-ON – MINUTES
CHANGE IN INPUT OFFSET VOLTAGE – ␮V
–4 0
–3
–2
–1
0
1
2
3
4
0.5 1 1.5 2 2.5 3 3.5
V
S
= ⴞ15V
T
A
= 25ⴗC
TPC 5. Warm-Up Drift
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
0
0.01
V
S
= ⴞ15V
T
A
= 25ⴗC
0.1 1 10 100 1k 10k 100k 1M
20
40
60
80
100
120
140
160
180
135
90
45
0
TPC 8. Open-Loop Gain/Phase
Response
POWER SUPPLY VOLTAGE – V
OPEN-LOOP GAIN – V/␮V
00ⴞ5ⴞ10 ⴞ15 ⴞ20
4
8
12
16
TA = 25ⴗC
RL = 2k⍀
TPC 3. Open-Loop Gain vs.
Power Supply Voltage
MIN
TIME – SEC
ABSOLUTE CHANGE IN INPUT OFFSET
VOLTAGE – ␮V
00
VS = ⴞ15V
5
10
15
20
25
30
10 20 30 40 50 60 70
DEVICE IMMERSED IN
70ⴗC OIL BATH (20 UNITS)
MAX
AVE
TPC 6. Offset Voltage Change
Due to Thermal Shock
FREQUENCY – Hz
CMMR –dB
80 1
90
100
110
120
130
140
150
10 100 1k 10k 100k
TA = 25ⴗC
TPC 9. CMRR vs. Frequency
REV. C –9–
OP77
FREQUENCY – Hz
PSRR – dB
600.1
90
100
110
120
130
1.0 10 100 1k 10k
TA = 25ⴗC
80
70
TPC 10. PSRR vs. Frequency
FREQUENCY – Hz
RMS NOISE – mV
0.1
100 1k 10k 100k
1.0
10 VS = ⴞ15V
TA = 25ⴗC
TPC 13. Input Wideband Noise vs.
Bandwidth (0.1 Hz to Frequency
Indicated)
T
A
= 25ⴗC
TOTAL SUPPLY VOLTAGE, V+ TO V – V
010203040
POWER CONSUMPTION – mW
0
10
100
TPC 16. Power Consumption vs.
Power Supply
TEMPERATURE – ⴗC
INPUT BIAS CURRENT – nA
0–50
V
S
= ⴞ15V
050100
1
2
3
4
TPC 11. Input Bias Current
vs. Temperature
FREQUENCY – Hz
11
VS = ⴞ15V
TA = 25ⴗC
INPUT NOISE VOLTAGE – nV/ Hz
10 100 1k
10
100
1000
RS = 0
EXCLUDED
RS1 = RS2 = 200kV
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
TPC 14. Total Input Noise
Voltage vs. Frequency
LOAD RESISTANCE TO GROUND – ⍀
MAXIUM OUTPUT – VOLTS
0
100 1k 10k
5
10
15
20
NEGATIVE SWING
POSITIVE SWING
V
S
= ⴞ15V
T
A
= 25ⴗC
V
IN
= ⴞ10mV
TPC 17. Maximum Output Voltage
vs. Load Resistance
INPUT OFFSET CURRENT – nA
0–50
V
S
= ⴞ15V
050100
0.5
1.0
1.5
2.0
TEMPERATURE – ⴗC
TPC 12. Input Offset Current
vs. Temperature
FREQUENCY – Hz
PEAK-TO-PEAK AMPLITUDE – V
01k
4
8
12
16
20
24
28
32
10k 100k 1M
V
S
= ⴞ15V
T
A
= 25ⴗC
TPC 15. Maximum Output Swing
vs. Frequency
TIME FROM OUTPUT BEING SHORTED –
MINUTES
OUTPUT SHORT-CIRCUIT CURRENT – mA
15 04
123
20
25
30
35
40
V
S
= ⴞ15V
T
A
= 25ⴗC
TPC 18. Output Short-Circuit
Current vs. Time
REV. C
OP77
–10–
50⍀
200k⍀
V
O
V
OS
4000
=
V
O
OP77
Figure 1. Typical Offset Voltage Test Circuit
100⍀
2.5M⍀
VO
INPUT REFERRED NOISE 25,000
=
2
3
7
4
63.3k⍀
4.7␮F
10Hz FILTER)(
V+
V–
OUTPUT
100⍀
OP77
Figure 2. Typical Low-Frequency Noise Test Circuit
20k⍀
2
3
7
4
6
V–
OUTPUT
INPUT
V+
+
–18
OP77
Figure 3. Optional Offset Nulling Circuit
2
3
7
46
100k⍀
+18V
10⍀
10␮F
0.1␮F
10⍀
OP77
0.1␮F
10k⍀10k⍀
10␮F–18V 1 PER BOARD
+
+
*
*
*
Figure 4. Burn-In Circuit
RL
1M⍀
VX
10⍀
VIN = 10V
100k⍀
10k⍀
–10V +10V
0V
VX
VY
AVO 650V/mV
RL = 2k⍀
~
TYPICAL
PRECISION OP AMP
NOTES
1. GAIN NOT CONSTANT. CAUSES NONLINEAR ERRORS.
2. AVO SPEC IS ONLY PART OF THE SOLUTION.
3. CHECK THE OP AMP PERFORMANCE, ESPECIALLY AT TEMPERATURES.
Figure 5. Open-Loop Gain Linearity
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. This causes errors in high closed-
loop gain circuits. Since this is so difficult for manufacturers to
test, users should make their own evaluation. This simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
–10V +10V
0V VX
VY
AVO 650V/mV
RL = 2k⍀
~
Figure 6. Output Gain Linearity Trace
This is the output gain linearity trace for the new OP77. The
output trace is virtually horizontal at all points, assuring extremely
high gain accuracy. The average open-loop gain is truly impres-
sive—approximately 10,000,000.
REV. C
OP77
–11–
APPLICATIONS INFORMATION
7
2
34
6
R2
1M⍀
+15V
0.1␮F
–15V
R4
R3
R1
1k⍀
1M⍀
0.1␮F
1k⍀OP77E
Figure 7. Precision High-Gain Differential Amplifier
The high gain, gain linearity, CMRR, and low TCVos of the
OP77 make it possible to obtain performance not previously
available in single-stage very high-gain amplifier applications.
For best CMR,
R
R1
2
must equal
R
R3
4
. In this example,
with a 10 mV differential signal, the maximum errors are as listed
in Table I.
Table I. Maximum Errors
TYPE AMOUNT
COMMON-MODE VOLTAGE 0.01%/V
GAIN LINEARITY, WORST CASE 0.02%
TCVOS 0.003%/∞C
TCI OS 0.008%/∞C
2
3
6
RF
INPUT OP77
CLOAD
+15V
–15V
100⍀
RS
OUTPUT
10pF
0.1␮F
0.1␮F
4
7
Figure 8. Isolating Large Capacitive Loads
This circuit reduces maximum slew-rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output imped-
ance is reduced to insignificance by the high open-loop gain
of the OP77.
Bilateral Current Source
2
3
6
R2
990⍀
R4
R3
R1
10⍀
OP77
100k⍀
1k⍀
100k⍀R5
V
IN
I
OUT
< 15mA
Figure 9. Basic Current Source
2
3
6
R2
R4
R3
R1
OP77
R5
V
IN
I
OUT
< 100mA
+15V
–15V
2N2907
2N2222
I
OUT
= V
IN
R3
R1 – R5
( )
GIVEN R3 = R4 ⴙ R5, R1 = R2
Figure 10. 100 mA Current Source
These current sources will supply both positive and negative
current into a grounded load.
Note that
ZRR
R
RR
RR
R
O
=
+
Ê
Ë
Áˆ
¯
˜
+
54
21
54
23
1
and that for Z
O
to be infinite,
REV. C
OP77
–12–
RR
R
54
2
+
must =
R
R3
1
Precision Current Sinks
OP77
V
IN
V+
200⍀
R1
R
L
1⍀
1W
IRF520
I
O
=
FULL SCALE OF 1V,
1A/V
I
O
V
IN
R1
V
IN
> OV
I
O
=
Figure 11. Positive Current Sink
OP77
V
IN
V–
200⍀
R1
R
L
IRF520
I
O
=V
IN
R1
I
O
V
IN
> OV
Figure 12. Positive Current Source
These simple high-current sinks require the load to float between
the power supply and the sink.
In these circuits, OP77’s high gain, high CMRR, and low TCV
OS
ensure high accuracy.
OP77
R1
1.8k⍀
2mA
D1
1N4579A
6.4V ⴞ5%
ⴞ5ppm/ⴗC
15V
2
3
4
6
7
R2
R3
3.6k⍀
6.4k⍀
EO = 10V
AVCL 1.6
Figure 13. High Stability Voltage Reference
This simple bootstrapped voltage reference provides a precise 10 V
virtually independent of changes in power supply voltage, ambi-
ent temperature and output loading. Correct Zener operating
current of exactly 2 mA is maintained by R1, a selected 5 ppm/∞C
resistor, connected to the regulated output. Accuracy is prima-
rily determined by three factors: the 5 ppm/∞C temperature
coefficient of D1, 1 ppm/∞C ratio tracking of R2 and R3, and
operational amplifier V
OS
errors.
VOs errors, amplified by 1.6 (AVCL), appear at the output and
can be significant with most monolithic amplifiers. For example,
an ordinary amplifier with TCV
OS
of 5 mV/∞C contributes 0.8 ppm/
∞C of output error while the OP77, with TCV
OS
of 0.3 mV/∞C,
contributes but 0.05 ppm/∞C of output error, thus effectively
eliminating TCV
OS
as an error consideration.
The high gain and low TCV
OS
assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
OP77E
OP77E
VIN
+15V
2
3
6
7
–15V
0.1␮F
C1
30pF D1
1N4148
D2
2N4393
R3
2k⍀
1k⍀
VOUT
0 < VOUT < 10V
4
2
3
6
7
4
0.1␮F
0.1␮F
0.1␮F
+15V
–15V
1k⍀
Figure 14. Precision Absolute Value Amplifier
The high gain and low TCV
OS
assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always appears as a common-mode signal to the op amps. The OP77E
CMRR of 1 ␮V/V assures errors of less than 2 ppm.
REV. C
OP77
–13–
REF-01
V
O
OP77
15V
10␮F
+2
6
4
0.1␮F
V
OUT
REF-01
V
O
REF-01
V
O
100⍀
100⍀
100⍀
44
22
66
Figure 15. Low Noise Precision Reference
OP77
V
IN
1k⍀
AD820
15V
26
4
0.1␮F1N4148
2N930
C
H
RESET
V
OUT
–15V
–15V
15V
2
4
6
1k⍀
1k⍀
0.1␮F
0.1␮F
0.1␮F
3
3
7
7
Figure 16. Precision Positive Peak Detector
This circuit relies upon OP77’s low TCV
OS
and noise combined
with very high CMRR to provide precision buffering of the
averaged REF01 voltage outputs.
C
H
must be of polystyrene, Teflon*, or polyethylene to minimize
dielectric absorption and leakage. The droop rate is determined
by the size of C
H
and the bias current of the AD820.
*Teflon is a registered trademark of the Dupont Company
REV. C
OP77
–14–
+15V
7
–15V
4
0.1␮F
0.1␮F
OP77
VIN
1k⍀
2
6
2k⍀
CC
RF
D1
100k⍀
VOUT
VTH 1N4148
3
RS
R1
Figure 17. Precision Threshold Detector/Amplifier
When V
IN
< V
TH
, amplifier output swings negative, reverse
biasing diode D1. V
OUT
= V
TH
if R
L
= • when V
IN
> V
TH
, the
loop closes,
VVVV R
R
OUT TH IN TH F
S
=+
()
+
Ê
Ë
Áˆ
¯
˜
–1
C
C
is selected to smooth the response of the loop.
OP77
REF-02
V
IN
GND
TEMP
TRIM
VORA
50k⍀
1.5k⍀
2
6
5
4
3Rb1
Rbp
RC
VOUT
–15V
+15V0.1␮F
0.1␮F
Figure 18. Precision Temperature Sensor
Table II. Resistor Values
TCV
OUT
SLOPE (S) 10 mV/∞C100 mV/∞C10 mV/∞F
TEMPERATURE –55∞C to –55∞C to –67∞F to
RANGE +125∞C+125∞C+257∞C
OUTPUT VOLTAGE –0.55 V to –5.5 V to –0.67 V to
RANGE +1.25 V +12.5V +2.57V
ZERO-SCALE 0 V @ 0∞C0 V @ 0∞C0 V @ 0⬚F
R
a
(±1% Resistor) 9.09 kW15 kW7.5 kW
R
b1
(±1% Resistor) 1.5 kW1.82 kW1.21 kW
R
bp
(Potentiometer) 200 W500 W200 W
R
c
(±1% Resistor) 5.11 kW84.5 kW8.25 kW
REV. C
OP77
–15–
OUTLINE DIMENSIONS
8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
14
85
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.40)
MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Metal Can [TO-99]
(H-08)
Dimensions shown in inches and (millimeters)
0.2500 (6.35) MIN
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFERENCE PLANE
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.0400 (1.02) MAX
BASE & SEATING PLANE
0.0340 (0.86)
0.0280 (0.71)
0.0450 (1.14)
0.0270 (0.69)
0.1600 (4.06)
0.1400 (3.56)
0.1000 (2.54) BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
45 BSC
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
–16–
C00320–0–10/02(C)
PRINTED IN U.S.A.
Revision History
Location Page
10/02—Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/02—Data Sheet changed from REV. A to REV. B.
Remove 8-Lead SO PIN CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Remove OP77G column from WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Remove OP77G column from TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6