8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs DRAM MODULE MT9LD(T)872(F)X, MT18LD(T)1672(F)(D)X, MT36LD(T)3272(C)(F)X For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html FEATURES * JEDEC-standard ECC pinout in a 168-pin, dual inline memory module (DIMM) * 64MB (8 Meg x 72), 128MB (16 Meg x 72), and 256MB (32 Meg x 72) * High-performance CMOS silicon-gate process * Single +3.3V 0.3V power supply * All inputs, outputs, and clocks are LVTTL-compatible * All inputs are buffered except RAS# * 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms * Extended Data-Out (EDO) PAGE MODE access cycle OPTIONS PIN ASSIGNMENT PIN SYMBOL PIN 1 VSS 43 2 DQ0 44 3 DQ1 45 4 DQ2 46 5 DQ3 47 6 VDD 48 7 DQ4 49 8 DQ5 50 9 DQ6 51 10 DQ7 52 11 DQ8 53 12 VSS 54 13 DQ9 55 14 DQ10 56 15 DQ11 57 16 DQ12 58 17 DQ13 59 18 VDD 60 19 DQ14 61 20 DQ15 62 21 DQ16 63 22 DQ17 64 23 VSS 65 24 NC 66 25 NC 67 26 VDD 68 27 WE0# 69 28 CAS0# 70 29 RFU 71 30 RAS0# 72 31 OE0# 73 32 VSS 74 33 A0 75 34 A2 76 35 A4 77 36 A6 78 37 A8 79 38 A10 80 39 A12 81 40 VDD 82 41 RFU 83 42 RFU 84 *256MB version only MARKING * Components SOJ TSOP D DT * Package 168-pin DIMM (gold) G * Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows Blank F * Module Height Low profile, 1.65" (256MB only) Low profile, 1.25" (128MB only) C D * Timing 50ns access 60ns access -5 -6 * Access Cycle EDO PAGE MODE X KEY TIMING PARAMETERS SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 30ns 35ns tCAC tCAS 18ns 20ns 8ns 10ns Front View (128MB) 168-PIN DIMM SYMBOL VSS OE2# RAS2# CAS4# RFU WE2# VDD NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VDD DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID0 VDD PIN SYMBOL PIN SYMBOL 85 VSS 127 VSS 86 DQ36 128 RFU 87 DQ37 129 NC/RAS3#* 88 DQ38 130 NC/CAS5#* 89 DQ39 131 RFU 90 VDD 132 PDE# 91 DQ40 133 VDD 92 DQ41 134 NC 93 DQ42 135 NC 94 DQ43 136 DQ54 95 DQ44 137 DQ55 96 VSS 138 VSS 97 DQ45 139 DQ56 98 DQ46 140 DQ57 99 DQ47 141 DQ58 100 DQ48 142 DQ59 101 DQ49 143 VDD 102 VDD 144 DQ60 103 DQ50 145 RFU 104 DQ51 146 RFU 105 DQ52 147 RFU 106 DQ53 148 RFU 107 VSS 149 DQ61 108 NC 150 DQ62 109 NC 151 DQ63 110 VDD 152 VSS 111 RFU 153 DQ64 112 NC/CAS1#* 154 DQ65 113 RFU 155 DQ66 114 NC/RAS1#* 156 DQ67 115 RFU 157 VDD 116 VSS 158 DQ68 117 A1 159 DQ69 118 A3 160 DQ70 119 A5 161 DQ71 120 A7 162 VSS 121 A9 163 PD2 122 A11 164 PD4 123 NC (A13) 165 PD6 124 VDD 166 PD8 125 RFU 167 ID1 126 B0 168 VDD NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs PART NUMBERS PART NUMBER MT9LD872G-x X MT9LDT872G-x X MT9LD872FG-x X MT9LDT872FG-x X MT18LD1672G-x X MT18LDT1672G-x X MT18LD1672FG-x X MT18LDT1672FG-x X MT18LDT1672FDG-x X MT36LD3272G-x X MT36LDT3272G-x X MT36LD3272FG-x X MT36LDT3272FG-x X MT36LD3272CG-x X MT36LD3272CFG-x X x = speed EDO PAGE MODE CONFIGURATION 8 Meg x 72 ECC 8 Meg x 72 ECC 8 Meg x 72 ECC 8 Meg x 72 ECC 16 Meg x 72 ECC 16 Meg x 72 ECC 16 Meg x 72 ECC 16 Meg x 72 ECC 16 Meg x 72 ECC 32 Meg x 72 ECC 32 Meg x 72 ECC 32 Meg x 72 ECC 32 Meg x 72 ECC 32 Meg x 72 ECC 32 Meg x 72 ECC EDO PAGE MODE is an accelerated FAST-PAGEMODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipeline READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR'd, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also tristate the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the MT4LC16M4H9 DRAM data sheet for additional information on EDO functionality.) REFRESH ADDRESSING 4K 4K 8K 8K 4K 4K 8K 8K 8K 4K 4K 8K 8K 4K 8K GENERAL DESCRIPTION The Micron(R) MT9LD(T)872(F)X, MT18LD(T)1672(F)X, and MT36LD(T)3272(F)X are randomly accessed 64MB, 128MB, and 256MB memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the address bits. First, the row address is latched by the RAS# signal, then the column address by CAS#. Two copies of address 0 (A0 and B0) are defined to allow maximum performance for 4-byte applications which interleave between two 4-byte banks. A0 is common to the DRAMs used for DQ0-DQ35, while B0 is common to the DRAMs used for DQ36-DQ71. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. EARLY WRITE occurs when WE# goes LOW prior to CAS# going LOW, and the output pins remain open (High-Z) until the next CAS# cycle. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all 4,096 combinations of RAS# addresses (A0-A11) are executed at least every 64ms, regardless of sequence. However, with the RAS#-ONLY REFRESH method some compatibility issues may become apparent (128MB and 256MB versions only). For example, both 4K and 8K refresh options require 4,096 CBR REFRESH cycles, yet require a different number of RAS#-ONLY REFRESH cycles (4K = 4,096 and 8K = 8,192). JEDEC strongly recommends the use of CBR REFRESH for these devices. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT9LD(T)872(F)X (64MB) DQ0-DQ7 A0 DQ0-DQ7 A0 D WE0# DQ8-DQ15 DQ0-DQ7 A0 WE# D D RAS0# CAS0# D DQ0-DQ7 A0 WE# WE# DQ24-DQ31 DQ0-DQ7 A0 WE# U2 U1 U0 OE0# DQ16-DQ23 DQ32-DQ39 A0 DQ0-DQ7 WE# U3 U4 OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 A11 A12-A1 D A1 DQ40-DQ47 B0 A0 D WE2# DQ48-DQ55 DQ0-DQ7 A0 WE# D D RAS2# CAS4# D DQ0-DQ7 A0 WE# U5 OE2# DQ56-DQ63 DQ0-DQ7 WE# DQ64-DQ71 A0 U7 U6 DQ0-DQ7 WE# U8 OE# OE# OE# OE# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 PRESENCE DETECT GENERATOR E# PD1-PD8 U0-U8 = MT4LC8M8C2DJ EDO PAGE MODE, SOJ, 4K REFRESH U0-U8 = MT4LC8M8C2TG EDO PAGE MODE, TSOP, 4K REFRESH PDE# U0-U8 = MT4LC8M8P4DJ EDO PAGE MODE, SOJ, 8K REFRESH VDD U0-U8, BUFFERS VSS U0-U8, BUFFERS U0-U8 = MT4LC8M8P4TG EDO PAGE MODE, TSOP, 8K REFRESH NOTE: 1. All inputs with the exception of RAS# are redriven. 2. D = line buffers. 3. Reference designators in this diagram do not necessarily match the actual module. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT18LD(T)1672(F)X (128MB) A0 D WE0# D DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# WE# WE# WE# WE# U0 OE0# D RAS0# CAS0# D U1 U3 U2 U4 U5 U6 U7 U8 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ64-DQ67 DQ68-DQ71 A11 A12-A1 D A1 B0 A0 D WE2# DQ0-DQ3 WE# D DQ0-DQ3 A0 WE# U9 OE2# D RAS2# CAS4# D A0 DQ0-DQ3 WE# U10 A0 DQ0-DQ3 A0 WE# DQ0-DQ3 WE# U12 U11 A0 DQ0-DQ3 WE# U13 A0 DQ0-DQ3 WE# U14 DQ0-DQ3 A0 DQ0-DQ3 A0 WE# WE# U15 U16 U17 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 PRESENCEDETECT PD1-PD8 GENERATOR U0-U17 = MT4LC16M4H9DJ EDO PAGE MODE, SOJ, 4K REFRESH U0-U17 = MT4LC16M4H9TG EDO PAGE MODE, TSOP, 4K REFRESH E# PDE# U0-U17 = MT4LC16M4G3DJ EDO PAGE MODE, SOJ, 8K REFRESH VDD U0-U17, BUFFERS VSS U0-U17, BUFFERS U0-U17 = MT4LC16M4G3TG EDO PAGE MODE, TSOP, 8K REFRESH NOTE: 1. All inputs with the exception of RAS# are redriven. 2. D = line buffers. 3. Reference designators in this diagram do not necessarily match the actual module. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT36LD(T)3272(C)(F)X (256MB) A0 D WE0# D DQ0-DQ3 DQ4-DQ7 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# D RAS0# CAS0# D DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# WE# WE# U1 U0 OE0# DQ8-DQ11 U3 U2 U4 U5 U6 U7 U8 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 11 11 11 11 11 11 11 11 11 A11 A11-A1 D A1 B0 DQ36-DQ39 A0 D WE2# DQ40-DQ43 DQ0-DQ3 A0 WE# D DQ0-DQ3 WE# D RAS2# CAS4# D DQ64-DQ67 DQ68-DQ71 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# U12 U11 U13 U14 U15 U16 U17 OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 11 11 11 11 11 11 11 11 11 DQ4-DQ7 DQ0-DQ3 A0 DQ0-DQ3 WE# DQ8-DQ11 A0 DQ0-DQ3 WE# U19 DQ12-DQ15 A0 DQ0-DQ3 WE# DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# U21 U20 U22 U23 U24 U25 OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 11 11 11 11 11 11 11 11 11 DQ36-DQ39 DQ40-DQ43 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ64-DQ67 DQ68-DQ71 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 A0 DQ0-DQ3 WE# WE# WE# WE# WE# DQ0-DQ3 A0 DQ0-DQ3 WE# U27 DQ44-DQ47 A0 DQ0-DQ3 WE# U28 A0 DQ0-DQ3 WE# U30 U29 U31 U32 U33 OE# U26 OE# WE# D DQ60-DQ63 OE# A0 CAS5# DQ56-DQ59 OE# U18 RAS3# DQ0-DQ3 WE# U10 WE# D A0 DQ52-DQ55 OE# A0 CAS1# DQ0-DQ3 DQ48-DQ51 OE# DQ0-DQ3 RAS1# A0 WE# U9 OE2# DQ44-DQ47 U34 U35 OE# OE# OE# OE# OE# OE# OE# OE# OE# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# RAS# CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 CAS# A1-A11 11 11 11 11 11 11 11 11 11 PRESENCEDETECT GENERATOR PD1-PD8 U0-U35 = MT4LC16M4T8DJ EDO PAGE MODE, SOJ, 4K REFRESH U0-U35 = MT4LC16M4T8TG EDO PAGE MODE, TSOP, 4K REFRESH E# U0-U35 = MT4LC16M4A7DJ EDO PAGE MODE, SOJ, 8K REFRESH PDE# VDD U0-U35, BUFFERS VSS U0-U35, BUFFERS U0-U35 = MT4LC16M4A7TG EDO PAGE MODE, TSOP, 8K REFRESH NOTE: 1. All inputs with the exception of RAS# are redriven. 2. D = line buffers. 3. Reference designators in this diagram do not necessarily match the actual module. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS 30, 45, 114, 129 SYMBOL RAS0#-RAS3# TYPE Input 28, 46, 112, 130 CAS0#, CAS1#, Buffered Input CAS4#, CAS5# DESCRIPTION Row-Address Strobe: RAS# is used to clock in the rowaddress bits. Two RAS# inputs allow for one x72 bank or two x36 banks. Column-Address Strobe: CAS# is used to clock in the column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Write Enable: WE# is the READ/WRITE control for the DQ pins. WE0# controls DQ0-DQ35. WE2# controls DQ36DQ71. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. Output Enable: OE# is the input/output control for the DQ pins. OE0# controls DQ0-DQ35. OE2# controls DQ36DQ71. These signals may be driven, allowing LATE WRITE cycles. Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. A0 is common to the DRAMs used for DQ0-DQ35, while B0 is common to the DRAMs used for DQ36-DQ71. Data I/Os: For WRITE cycles, DQ0-DQ71 act as inputs to the addressed DRAM location. For READ access cycles, DQ0-DQ71 act as outputs for the addressed DRAM location. 27, 48 WE0#, WE2# Buffered Input 31, 44 OE0#, OE2# Buffered Input 33-39, 117-122, 126 A0-A12, B0 Buffered Input 2-5, 7-11, 13-17, 19-22, 52-53, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-106, 136-137, 139-142, 144, 149-151, 153-156, 158-161 79-82, 163-166 DQ0-DQ71 Input/ Output PD1-PD8 Buffered Output 29, 41-42, 47, 61-64, 111, 113, 115, 125, 128, 131, 145-148 6, 18, 26, 40, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 68, 78, 85, 96, 107, 116, 127, 138, 152, 162 83, 167 RFU - VDD Supply Power Supply: +3.3V 0.3V. VSS Supply Ground. ID0, ID1 Output 132 PDE# Input ID Bits: ID0 = DIMM type. ID1 = Refresh Mode. These pins will be either left floating (NC) or they will be grounded (VSS). Presence Detect-Enable: PDE# is the READ control for the buffered presence-detect pins. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 Presence-Detect: These pins are read by the host system and tell the system the DIMM's personality. They will be either no connect (1), or they will be driven to VOL (0). Reserved for Future Use: These pins should be left unconnected. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs PRESENCE-DETECT TRUTH TABLE CHARACTERISTICS PRESENCE-DETECT PIN (PDx) Module Density Module Organization Row/Column Addresses 1 2 3 4 0MB No module installed X 1 1 1 1 8MB 8MB 1 Meg x 64/72 1 Meg x 64/72 10/9 10/10 1 0 1 0 0 1 0 0 16MB 16MB 2 Meg x 64/72 2 Meg x 64/72 10/10 11/10 1 1 0 0 1 0 0 1 32MB 32MB 4 Meg x 64/72 4 Meg x 64/72 11/10 12*/11* 0 1 1 1 0 0 1 1 * 64MB 8 Meg x 64/72 12/11 1 0 1 1 128MB 16 Meg x 64/72 16 Meg x 64/72 12/11 12/13/11/12 0 1 1 1 1 1 1 1 32 Meg x 64/72 12/13/11/12 1 0 0 0 * 128MB * 256MB Operating Mode Access Timing ID0 ID1 6 7 80ns 1 0 70ns 0 1 60ns 1 1 0 0 Fast Page Mode 0 EDO Page Mode 1 50ns Refresh Control Data Width, Parity 5 Standard Vss Self NC 8 x64, No Parity Vss 1 x72, Parity NC 1 x72, ECC Vss 0 x80, ECC NC 0 NOTE: VSS = Ground; VOL = 0; NC = 1. * This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect setting. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Pin Relative to VSS ......... -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ....................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0C to +70C Storage Temperature (plastic) ............ -55C to +125C Power Dissipation ................................................. 18W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Note: 1) (VDD = +3.3V 0.3V) PARAMETER/CONDITION SYMBOL SIZE MIN MAX SUPPLY VOLTAGE VDD ALL 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH ALL 2 VDD + 0.3 V 2 INPUT LOW VOLTAGE: Logic 0; All inputs VIL ALL -0.5 0.8 V 2 I I1 ALL -2 2 A RAS0#-RAS3# I I2 64MB 128MB 256MB -9 -18 -18 9 18 18 A DQ0-DQ71 IOZ 64MB 128MB 256MB -5 -5 -10 5 5 10 A VOH ALL 2.4 - V VOL ALL - 0.4 V INPUT LEAKAGE CURRENT: CAS0#, CAS1#, CAS4#, Any input 0V VIN VDD + 0.3V CAS5#, A0-A12, B0, (All other pins not under test = 0V) WE0#, WE2#, OE0#, OE2#, PDE# OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V VOUT VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) UNITS NOTES NOTE: 1. All voltages referenced to VSS. 2. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1-3) (VDD = +3.3V 0.3V) PARAMETER/CONDITION MAX SYMBOL REFRESH SIZE STANDBY CURRENT: TTL (RAS# = CAS# = VIH) IDD1 STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) IDD2 OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) -5 -6 All 64MB 128MB 256MB 66 75 99 66 75 99 mA All 64MB 128MB 256MB 4.5 9 18 4.5 9 18 mA 4K 64MB 1,575 128MB 3,060 256MB 3,135 1,485 2,880 2,955 8K 64MB 1,215 128MB 2,340 256MB 2,415 1,125 2,160 2,235 All 64MB 1,395 128MB 2,700 256MB 2,775 1,125 2,160 2,235 4K 64MB 1,575 128MB 3,060 256MB 3,135 1,485 2,880 2,955 8K 64MB 1,215 128MB 2,340 256MB 2,415 1,125 2,160 2,235 4K 64MB 1,485 128MB 2,880 256MB 2,955 1,395 2,700 2,778 64MB 1,485 128MB 2,880 256MB 2,955 1,395 2,700 2,778 IDD3 OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) IDD4 REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) IDD5 REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) IDD6 8K UNITS NOTES mA 4, 5 mA 4, 5 mA 4, 6 mA 4, 7 NOTE: 1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 3. An initial pause of 100s is required after power-up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 5. Column address changed once each cycle. 6. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the 4K version and 8,192 rows for the 8K version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms. 7. Enables on-chip refresh and address counters. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs CAPACITANCE MAX PARAMETER SYMBOL 64MB 128MB 256MB UNITS Input Capacitance: A0-A12, B0, WE0#, WE2#, OE0#, OE2# CI1 9 Input Capacitance: CAS0#, CAS1#, CAS4#, CAS5#, PDE# CI 2 9 Input Capacitance: RAS0#-RAS3# CI 3 39 Input/Output Capacitance: DQ0-DQ71 CIO 12 Output Capacitance: PD1-PD8 CO 10 9 9 pF 9 9 pF 67 67 pF 12 22 pF 10 10 pF NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 31; notes appear on next page and page 13) (VDD = +3.3V 0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# going HIGH during WRITE Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time PDE# to valid presence-detect data PDE# inactive to presence-detects inactive EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 -5 -6 SYMBOL tAA tACH MIN MAX 30 MIN 12 15 tAR 36 2 5 44 43 2 5 51 MAX 35 UNITS ns ns NOTES 10 11 12 10 12, 13 10, 14 10 tOEH 6 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tOEHC tORD 5 5 4 2 0 10 5 5 2 0 ns ns ns ns ns tPC 20 tASC tASR tAWD tCAC 18 tCAH 13 8 6 2 3 8 tCAS tCHR tCLZ tCOH tCP tCPA 10,000 20 15 10 8 2 3 10 33 tCRP 10 36 7 30 8 13 -2 0 tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEP tOES tOFF tPD 12 12 17 40 10 43 7 37 10 15 -2 0 2 49 tPRWC tRAC 7 7 50 50 84 9 tRAH tRAS tRASP tRC tRCD 11 20 10 2 58 50 tRAD 15 15 25 10 tPDOFF 10,000 10,000 125,000 60 10 8 60 60 104 12 10,000 125,000 ns ns ns ns ns ns ns ns ns ns ns 11, 16 12, 18 15 10 10 11 12, 16 12, 13 10, 17 11, 17 18 11 19, 20 21 21 12 22 23, 24 11 24, 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 1-8; notes appear below and on next page) (VDD = +3.3V 0.3V) AC CHARACTERISTICS PARAMETER READ command hold time (referenced to CAS#) READ command setup time Refresh period RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WE# to outputs in High-Z WRITE command pulse width WE# pulse width to disable outputs WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRCH tRCS tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 2 2 -6 MAX MIN 2 2 64 30 5 0 18 121 69 18 2 13 36 2 50 64 40 5 0 20 145 81 20 2 15 43 2 17 5 10 6 10 MAX 50 20 5 10 8 12 UNITS ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 27 28 27 10 10 26 10 10 11 16 10 10 12 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. An initial pause of 100s is required after power-up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 2ns for -5 and 2.5ns for -6. 4. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 5. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6. If CAS# and RAS# = VIH, data output is High-Z. 7. If CAS# = VIL, data output may contain data from the last valid READ cycle. 8. Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 9. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not possible. 10. A +5ns timing skew from the DRAM to the module resulted from the addition of line drivers. 11. A -2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 12. A +2ns timing skew from the DRAM to the module resulted from the addition of line drivers. 13. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, t AWD and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14. Requires that tAA and tRAC are not violated. 15. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16. Enables on-chip refresh and address counters. 17. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 18. The 3ns minimum is a parameter guaranteed by design. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs NOTES: (continued) 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 20. A +2ns (MIN) and a +5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers. 21. tPDOFF (MAX) is determined by the pullup resistor value. Care must be taken to ensure adequate recovery time prior to reading valid up-level on subsequent DIMM position. 22. Requires that tAA and tCAC are not violated. 23. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 24. A -2ns (MIN) and a -5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers. 25. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 26. Column address changed once each cycle. 27. Either tRCH or tRRH must be satisfied for a READ cycle. 28. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the 4K version and 8,192 rows for the 8K version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs READ CYCLE tRC tRP tRAS RAS# V IH V IL tCSH tRSH tCRP CAS# tCAS tAR tASC tCAH tRRH V IH V IL tRAD tRAH tASR ADDR tRCD V IH V IL tACH ROW ROW COLUMN tRCH tRCS WE# V IH V IL tAA tRAC NOTE 1 tOFF tCAC tCLZ DQ V OH V OL OPEN OE# OPEN VALID DATA tOE tOD V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA -6 MAX MIN UNITS SYMBOL 35 tOFF tACH 12 15 ns ns tAR 36 2 5 43 2 5 ns ns ns tRAD ns ns tRC ns ns ns tRCH tRRH 15 ns ns 15 ns tASC tASR 30 -5 MAX tCAC 18 tCAH 13 tCAS 8 2 10 tCLZ tCRP tCSH tOD 36 0 tOE 20 15 10,000 12 12 10 2 10 43 0 10,000 MAX MIN MAX UNITS 2 17 50 2 20 60 ns ns 10,000 ns ns ns tRAC tRAH tRAS tRCD tRCS tRP tRSH -6 MIN 7 7 50 10,000 10 8 60 84 9 104 12 ns ns 2 2 30 2 2 40 ns ns ns 0 18 0 20 ns ns NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EARLY WRITE CYCLE tRC tRAS RAS# tRP V IH V IL tCSH tRSH tCRP CAS# tRCD tCAS V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH tACH ROW COLUMN tCWL tRWL tWCR tWCH tWCS tWP WE# V IH V IL tDS V DQ V IOH IOL OE# tDH VALID DATA V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD MIN 12 -5 -6 MAX MIN 15 MAX SYMBOL UNITS ns tRAH 36 2 43 2 ns ns tRAS 5 13 8 5 15 10 ns ns ns tRCD 10,000 10,000 tRC tRP tRSH 10 36 10 43 ns ns tRWL 8 13 10 15 ns ns tWCR -2 7 -2 10 ns ns tWP 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 tWCH tWCS 15 MIN 7 50 84 -6 MAX MIN MAX UNITS 10,000 8 60 104 10,000 ns ns ns 9 30 12 40 ns ns 18 18 13 20 20 15 ns ns ns 36 2 43 2 ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE READ CYCLE tRASP RAS# V IH V IL tCSH tCRP CAS# tRP tRCD tPC tCP tCAS tCAS tRSH tCAS tCP tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL ROW tACH tACH tACH tASC tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRCS WE# tRCH V IH V IL tAA tRAC tAA tCPA tCAC tCAC DQ V OH V OL VALID DATA OPEN tOFF tOEHC VALID DATA tOE OE# tCAC tCLZ tCOH tCLZ VALID DATA OPEN tOE tOD tOES V IH V IL tRRH tAA tCPA tOD tOES tOEP DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR MIN tCAS tCLZ tCOH tCP MAX 35 SYMBOL UNITS ns tOEHC 15 43 ns ns tOEP 2 5 2 5 tOFF 20 ns ns ns tRAD 10,000 ns ns ns ns ns tRASP ns ns tRCS ns ns tRRH 15 15 ns 18 13 8 10,000 2 3 8 tCPA 15 10 2 3 10 33 tCRP 10 tCSH 36 0 tOD MIN 12 36 tCAC tCAH -5 -6 MAX 30 tOE 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 40 10 12 12 43 0 tOES MIN 5 5 4 2 20 tPC tRAC tRAH tRCD tRCH tRP tRSH 16 -6 MAX MIN 17 2 25 50 7 7 50 9 MAX 10 5 5 ns ns ns 20 ns ns 60 ns ns ns 125,000 ns ns 10 8 125,000 60 12 UNITS 2 2 30 2 2 40 ns ns ns 0 18 0 20 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE EARLY WRITE CYCLE tRP tRASP RAS# V IH V IL tCSH tCRP CAS# tRCD tPC tCP tCAS tCAS tRSH tCAS tCP V IH V IL tAR tACH tRAD tASR ADDR V IH V IL tRAH tACH tASC ROW tCAH tACH tCAH tASC COLUMN tASC COLUMN tCWL tWCH tWCS tWCS tCAH COLUMN tCWL tWCH tWP WE# ROW tCWL tWCH tWCS tWP tWP V IH V IL tWCR tDS V DQ V IOH IOL OE# tCP tRWL tDH tDS VALID DATA tDH tDS VALID DATA tDH VALID DATA V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH MIN 12 -6 MAX MIN 15 -5 MAX UNITS ns SYMBOL tPC MIN 20 -6 MAX MIN 25 tAR 36 43 ns tRAD 7 10 tASC 2 5 13 8 2 5 15 10 ns ns ns ns tRAH 7 50 9 30 8 60 12 40 tASR tCAH tCAS tCP 10,000 10,000 tRASP tRCD tRP 8 10 10 10 ns ns tRSH 43 10 15 ns ns ns tWCH tDH 36 8 13 tDS -2 -2 ns tWP tCRP tCSH tCWL 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 tRWL tWCR tWCS 17 125,000 MAX UNITS ns ns 125,000 ns ns ns ns 18 18 20 20 ns ns 13 36 2 15 43 2 ns ns ns 5 5 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS RAS# t RP V IH V IL t CSH t RSH t CRP CAS# t RCD V IH V IL t AR t RAD t ASR ADDR t CAS V IH V IL t ASC t CAH t ACH t RAH ROW COLUMN t RCS WE# ROW t RWD t CWL t CWD t RWL t AWD t WP V IH V IL t AA t RAC t CAC t DS t CLZ V DQ V IOH IOL VALID D OUT OPEN t OE OE# t DH VALID D IN t OD OPEN t OEH V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tAWD MIN 2 5 44 2 5 51 ns ns ns tRAC 20 ns ns tRAS 10,000 ns ns ns tRCS 18 8 2 10 tCWL tDH tDS tOD tOE 13 tCWD SYMBOL UNITS ns ns ns tCAS tCSH MAX 35 15 43 tCAH tCRP MIN 12 36 tCAC tCLZ -5 -6 MAX 30 15 10,000 10 2 10 tOEH MAX UNITS 0 12 12 0 15 15 ns ns ns 60 ns ns 6 7 50 9 tRSH 43 37 ns ns tRWC 8 13 -2 10 15 -2 ns ns ns tRWL tRWD tWP 8 50 tRAH tRP 18 MIN 7 36 30 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 MAX tRAD tRCD -6 MIN 10 10,000 8 60 12 10,000 ns ns ns 2 30 2 40 ns ns 18 121 69 20 145 81 ns ns ns 18 5 20 5 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP RAS# V IH V IL tCSH tCRP CAS# tPRWC NOTE 1 tPC tRCD tCAS tCP tCAS tRSH tCP tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR tRP V IH V IL tASC ROW tCAH tASC COLUMN tCAH tASC COLUMN tCAH COLUMN ROW tRWD tRCS WE# tCWL tWP tAWD tCWD tAA tAA tDH tCAC tCLZ V IOH V IOL tAA tDH tCPA tDS tCAC tCLZ VALID D OUT OPEN tDH tCPA tDS tDS tCAC tCLZ VALID DIN VALID D OUT tOD VALID D IN VALID D OUT tOD tOE OE# tWP tAWD tCWD V IH V IL tRAC DQ tRWL tCWL tCWL tWP tAWD tCWD tOE VALID D IN OPEN tOD tOEH tOE V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR tASC tASR tAWD tCAS tCLZ tCP tCSH tCWD tCWL tDH tDS -5 MAX UNITS 35 SYMBOL tOD 36 2 43 2 ns ns ns 5 44 5 51 ns ns tPC ns ns ns tRAC ns ns tRASP tRCS 18 13 8 10,000 2 8 tCPA tCRP MIN 30 tCAC tCAH -6 MAX 20 15 10 10,000 2 10 33 40 MIN 0 tOE -6 MAX 12 MIN 0 12 tOEH tPRWC tRAD tRAH tRCD 10 36 10 43 ns ns ns 30 8 37 10 ns ns tRWD 13 -2 15 -2 ns ns tWP tRP tRSH tRWL 6 20 49 UNITS ns 15 ns 60 ns ns ns ns 8 25 58 50 7 7 50 9 2 MAX 15 10 8 125,000 60 12 2 ns ns 125,000 ns ns ns 30 18 40 20 ns ns 69 18 81 20 ns ns 5 5 ns NOTE: 1. tPC is for LATE WRITE cycles only. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RP t RASP RAS# V IH V IL t CSH tPC tCRP CAS# t RCD tRSH tPC t CP t CAS t CP t CAS t CP t CAS V IH V IL tAR tRAD tASR ADDR V IH V IL t ACH tRAH tASC tCAH t ASC COLUMN (A) ROW t CAH COLUMN (B) V IH V IL ROW tWCS tWCH tAA tAA tCPA tRAC tCAC tCAC tCOH DQ V IOH V IOL t CAH COLUMN (N) tRCH tRCS WE# tASC OPEN t DS VALID DATA (B) VALID DATA (A) t DH t WHZ VALID DATA IN tOE OE# V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA -6 MAX MIN UNITS SYMBOL 35 tOE tACH 12 15 ns ns tAR 36 2 5 43 2 5 ns ns ns tRAC 20 ns ns tRASP 10,000 ns ns ns tRCH tRSH tASC tASR 30 -5 MAX tCAC 18 tCAH 13 tCAS 8 3 8 tCOH tCP tCPA 15 10,000 10 3 10 33 tCRP 10 10 ns ns tCSH tDH 36 13 43 15 ns ns tDS -2 -2 ns 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 40 -6 MAX MIN 12 tPC 20 7 tRAH 7 50 9 MAX UNITS 15 ns ns 60 ns ns 25 50 tRAD tRCD 10 125,000 8 60 12 125,000 ns ns ns 2 2 2 2 ns ns tWCH 30 18 13 40 20 15 ns ns ns tWCS 2 tRCS tRP tWHZ 20 MIN 2 17 20 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs EDO READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tRCD tCRP CAS# tCAS tCP V IH V IL tAR tRAD tRAH tASR ADDR V IH V IL tASC ROW tCAH tASC COLUMN COLUMN tRCS WE# tRCH tWPZ tRCS V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL tWHZ OPEN OPEN VALID DATA tOE OE# tCLZ tOD V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR MIN 36 2 5 tCAC 13 tCAS 8 2 8 tCP tCRP tCSH MIN 10 36 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 -5 MAX 35 43 2 5 18 tCAH tCLZ -6 MAX 30 20 15 10,000 10 2 10 10 43 10,000 UNITS ns SYMBOL tOD ns ns ns tOE ns ns tRAH ns ns ns tRCH ns ns tWPZ MAX MIN MAX 0 12 0 15 ns 15 60 ns ns 12 50 tRAC tRAD tRCD tRCS UNITS 7 7 9 10 8 12 ns ns ns 2 2 2 2 ns ns tWHZ 21 -6 MIN 17 10 20 10 ns ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs RAS#-ONLY REFRESH CYCLE tRC tRAS RAS# tRP V IH V IL tRPC tCRP CAS# V IH V IL tASR ADDR tRAH V IH V IL ROW ROW V DQ V OH OL WE# OPEN V IH V IL CBR REFRESH CYCLE (Addresses, OE# = DON'T CARE) tRP RAS# tRAS tRP NOTE 1 tRAS V IH V IL tRPC tCP CAS# V IH V IL DQ V OH V OL tCSR tCSR tCHR OPEN tWRP WE# tRPC tCHR tWRH tWRP tWRH V IH V IL DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR MIN -6 MAX MIN -5 MAX UNITS SYMBOL 5 6 8 5 8 10 ns ns ns tRAS 10 7 ns ns tRPC tCSR 10 7 tRAH 7 8 ns tCHR tCP tCRP 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 tRC tRP 22 -6 MIN MAX MIN MAX UNITS 50 84 10,000 60 104 10,000 ns ns tWRH 30 5 6 40 5 8 ns ns ns tWRP 10 12 ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW) tRC tRAS RAS# tRAS V IH V IL tCRP CAS# tRP tRSH tRCD tCHR V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC ROW tCAH COLUMN tAA tRAC tOFF tCAC tCLZ V DQ V IOH IOL OPEN VALID DATA OPEN DON'T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL MIN tAA tAR -6 MAX MIN 30 tASC 36 2 43 2 tASR 5 5 tCAC tCAH tCHR tCLZ tCRP tOD 18 13 6 2 10 0 tOE -5 MAX UNITS 35 ns ns ns tOFF ns ns tRAD ns ns ns tRAS ns ns tRP 15 15 ns 20 15 8 2 12 12 10 0 SYMBOL tORD MAX MIN MAX UNITS 2 0 17 2 0 20 60 ns ns ns 10,000 ns ns ns tRAC tRAH tRC tRCD tRSH -6 MIN 50 7 7 50 10,000 10 8 60 84 9 104 12 ns ns 30 18 40 20 ns ns NOTE: A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM (64MB SOJ) FRONT VIEW .200 (5.08) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.255 (31.88) 1.245 (31.62) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .054 (1.37) .046 (1.17) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) 168-PIN DIMM 64MB TSOP FRONT VIEW .125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.355 (34.42) 1.345 (34.16) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM (128MB SOJ) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX .079 (2.00) R (2X) 1.105 (28.07) 1.095 (27.81) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .054 (1.37) .046 (1.17) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) 168-PIN DIMM (128MB TSOP) FRONT VIEW .125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) 2.005 (50.93) 1.995 (50.67) .079 (2.00) R (2X) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM (128MB TSOP) .157 (4.00) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.255 (31.88) 1.245 (31.62) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM (256MB SOJ) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX 2.005 (50.93) 1.995 (50.67) .079 (2.00) R (2X) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .054 (1.37) .046 (1.17) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP .050 (1.27) TYP PIN 1 (PIN 85 ON BACKSIDE) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) 168-PIN DIMM (256MB TSOP) FRONT VIEW .157 (4.00) MAX 5.256 (133.50) 5.244 (133.20) 2.005 (50.93) 1.995 (50.67) .079 (2.00) R (2X) .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc. 8, 16, 32 MEG x 72 BUFFERED DRAM DIMMs 168-PIN DIMM (256MB SOJ) FRONT VIEW .350 (8.89) MAX 6.955 (176.66) 6.945 (176.40) 1.655 (42.04) 1.645 (41.78) .079 (2.00) R (2X) .870 (22.10) MIN .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.700 (43.18) .128 (3.25) (2X) .118 (3.00) .039 (1.00)R (2X) .039 (1.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8, 16, 32 Meg x 72 Buffered DRAM DIMMs DM77_2.p65 - Rev. 3/00 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2000, Micron Technology, Inc.