DATASHEET MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR Description Features The MK74CG117A is a monolithic CMOS high-speed, low-skew clock driver that includes an on-chip PLL. Ideal for communications and other systems that require a large number of high-speed clocks, the unique combination of PLL and 16 low-skew outputs can eliminate oscillators and low-skew buffers from systems. * 48-pin SSOP (300 mil) package * On-chip PLL generates output clocks up to 90 MHz from a simple crystal or clock input * 16 low-skew outputs * Output skew less than 350 ps on rising edges * Ability to configure as The device has a number of built-in multipliers, making it possible to run from one inexpensive, low-frequency crystal, and produce high-frequency clock outputs. Another selection allows the chip to run as a divider, dividing the input clock by two (or 4 using the mode select). - 16 clocks at full-frequency - 12 at full and 4 at half-frequency - 8 at full and 8 at half-frequency The device also has a buffered reference output, allowing multiple devices to be easily driven from one clock source. * Tri-state mode for Output Enable function * 3.3 V 5% supply voltage Block Diagram VDD 9 S2:0 M1:0 Crystal or X1/ICLK clock input 3 Clock Synthesis and Mode Select Circuitry 2 Clock 1 Clock 2 Clock 16 Crystal Ocsillator REF X2 The crystal requires external capacitors for accurate tuning of the clock IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR 10 GND 1 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Pin Assignment VDD 1 48 S0 X1/ICLK 2 47 CLK16 X2 3 46 VDD NC 4 45 VDD NC 5 44 NC GND 6 43 CLK15 GND 7 42 CLK14 S2 8 41 GND REF 9 40 GND S1 10 39 M1 GND 11 38 CLK13 GND 12 37 CLK12 CLK1 13 36 VDD CLK2 14 35 VDD VDD 15 34 M0 VDD 16 33 CLK11 CLK3 17 32 CLK10 CLK4 18 31 CLK9 GND 19 30 VDD GND 20 29 NC NC 21 28 GND CLK5 22 27 GND CLK6 23 26 CLK8 VDD 24 25 CLK7 48-pin (300 mil) SSOP IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR 2 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Pin Descriptions Pin Number Pin Name Pin Type 1, 15, 16, 24, 30, 35, 36, 45, 46 VDD Power 2 X1/ICLK XI Connect to a crystal input or clock. 3 X2 XO Connect to a crystal or leave unconnected for clock input. 4, 5, 21, 29, 44 NC -- No connect. Nothing is connected to these pins. 6, 7, 11, 12, 19, 20, 27, 28, 40, 41 GND Power Connect to ground. 8, 10, 48 S2, S1, S0 Input Multiplier select pins. See table 2. 9 REF Output Crystal oscillator buffered reference clock output. 13, 14, 17, 18 CLK1 - 4 Output Clock 1-4. Can be either full or half-speed per Table 1. 22, 23, 25, 26, 31, 32, 33, 37 CLK5 - 12 Output Clock outputs 5-12. At full (1x) speed unless tri-stated per Table 1. 34, 39 M0, M1 Input Mode Select pins. Selects tri-state or speed of outputs per Table 1. 38, 42, 43, 47 CLK13 - 16 Output Clock 13-16. Can be either full or half-speed per Table 1. External Components Pin Description Connect to VDD. 3) An optimum layout is one with all components on the same side of the board, thus minimizing vias through other signal layers. Other signal traces should be routed away from the MK74CG117A device. This includes signal traces located underneath the device, or on layers adjacent to the ground plane layer used by the device. The MK74CG117A requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.1F must be connected between each VDD and GND. Connect the capacitor as close to these pins as possible. For optimum device performance, mount the decoupling capacitor on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant crystal. The oscillator has internal caps that provide the proper load for a crystal with CL = 18 pF. The value of these capacitors is given by the following equation: PCB Layout Recommendations Crystal caps (pF) = (CL - 18) x 2 For optimum device performance and lowest output phase noise, observe the following guidelines: 1) Mount the 0.01F decoupling capacitor on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to the VDD pin and the PCB trace to the ground via should be kept as short as possible. 2) To minimize EMI, place the 33 series-termination resistor (if needed) close to the clock output. IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR 3 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Power Dissipation, Termination, and Operating Frequency Table 2. Multiplier Selections (Input and CLK Frequencies in MHz) As with all clock drivers, the power dissipated by the MK74CG117A is affected by the external loading on the output pins. This consists of the capacitance of the load that is being driven, as well as the PC board trace itself. Since this capacitance must be charged and discharged with each cycle of the output clock, as the frequency goes up, so does the power required. Operating below the specified maximum output clock frequency shown in Table 2 will keep the MK74CG117A power dissipation within acceptable limits. External series termination resistors must be used in series with each output. These resistors serve two purposes: The first is to match the source impedance to the line (PC board trace) that is being driven. This will minimize reflections that cause non-linear transitions on the output clock waveform. The output impedance of the MK74CG117A is approximately 20; assuming a 50 line, then a 33 resistor should be used at each output as shown in Figure 1. Mode at CLK(1x) at CLK/2(0.5x) 0 0 All outputs, including REF, tri-stated Z Z 0 1 12 @ 1x, 4 @ 0.5x CLK1-12 CLK13-16 Input Multiplier CLK Out Comments 0 0 0 33-50 0.5 16.5-25 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 20-50 16-40 10-45 8-36 8-27 8-22.5 8-18 1 1.25 2 2.5 3.333 4 5 20-50 20-50 20-90 20-90 26.7-90 32-90 40-90 Divider only; no PLL PLL PLL PLL PLL PLL PLL PLL Figure 1. External Termination MK74CG117 Output Table 1. Tri-state and Mode Select M1 M0 S2 S1 S0 33 ohm To load Max Output Freq. As speeds rise, the limiting factor in device operation becomes the power generated by having a large number of drivers in one package. Using the external termination resistors reduces the power dissipated within the device, allowing output frequencies up to 100 MHz. 83.3 MHz 0.8 1 0 8 @ 1x, 8 @ 0.5x CLK5-12 CLK1-4, 13-16 83.3 MHz 1.25 1 1 16 outputs @ 1x CLK1-16 None 90 MHz Note that the maximum operating frequency of the MK74CG117A is determined by the Mode selected from Table 1 and the Multiplier selected from Table 2. For output frequencies above 83.3 MHz, all 16 outputs must be at the same frequency (M1=M0=1). When operating with a combination of 1X and 0.5X outputs, the output frequency cannot exceed 83.3 MHz. IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR 4 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK74CG117A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device, at these or any other conditions, above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD (referenced to GND) 7V All Inputs and Outputs (referenced to GND) 0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70C Storage Temperature -65 to +150C Junction Temperature 125C Soldering Temperature 260C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 C +3.14 3.47 V Min. Typ. Max. Units 3.14 3.3 3.47 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Symbol Conditions Operating Voltage VDD Supply Current (at 50 MHz) IDD No load Input High Voltage, ICLK VIH pin 2 Input Low Voltage, ICLK VIL pin 2 Output High Voltage VOH IOH = -8 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.0 V Output Low Voltage, 3.3 V VOL IOL = 12 mA Short Circuit Current Input Capacitance VDD-1 VDD/2 V 1 0.4 S0, S1, FRSEL pins IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR mA VDD/2 Each output CIN 63 5 V V 35 mA 7 pF MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70 C, CL = 15 pF Parameter Symbol Conditions Min. Input Clock Frequency See table 2 Input Crystal Frequency Except when S2=S1=1 Output Clock Frequency (see tables 1, 2) M1=M0=1 Output Clock Duty Cycle At VDD/2 Output Clock Rising Edge Skew Typ. 8 Max. Units 20 MHz 90 MHz 50 55 % VDD=3.3 V, Note 2 200 350 ps Absolute Clock Period Jitter, except REF VDD=3.3 V 300 ps Absolute Clock Period Jitter, REF VDD=3.3 V 500 ps 45 Output Clock Rise Time tR 0.8 to 2.0 V, Note 1 1.5 2 ns Output Clock Fall Time tF 2.0 V to 0.8 V, Note 1 1.5 2 ns 100 MHz output clock 240 pF 83.3 MHz output clock 320 pF Maximum Load per Total of 16 Outputs, with 33 termination, Note 3 Note 1: Based upon characterization data with a 33 series termination resistor and 15 pF capacitor to ground. Note 2: Between any two outputs with equal loading. Note 3: Additional load may be driven with the addition of an external heat sink. Contact ICS for details. Thermal Characteristics for 48-pin SSOP Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR Conditions Min. Typ. Max. Units JA Still air 80 C/W JA 1 m/s air flow 67 C/W JA 3 m/s air flow 54 C/W 45 C/W JC 6 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Package Outline and Package Dimensions (48-pin SSOP, 300 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 48 Millimeters Symbol E1 INDEX AREA A A1 b c D E E1 e h L E 1 2 D Min Inches Max Min 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 0 8 Max .095 .110 .008 .016 .008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 0 8 A A2 A1 c - Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature MK74CG117AF MK74CG117AFT MK74CG117A MK74CG117A Tubes Tape and Reel 48-pin SSOP 48-pin SSOP 0 to +70 C 0 to +70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDTTM / ICSTM 16 OUTPUT LOW SKEW CLOCK GENERATOR 7 MK74CG117A REV F 082704 MK74CG117A 16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 <product line email> <product line phone> Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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