© Semiconductor Components Industries, LLC, 2012
July, 2012 − Rev. 10
1Publication Order Number:
MC74LCX16373/D
MC74LCX16373
Low-Voltage CMOS 16-Bit
Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX16373 is a high performance, non−inverting 16−bit
transparent latch operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16−bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX16373 inputs to be safely driven from 5.0 V devices.
The MC74LCX16373 contains 16 D−type latches with 3−state
5.0 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state outputs are controlled by the Output
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When
OE is HIGH, the standard outputs are in the high impedance state, but
this does not interfere with new data entering into the latches.
Features
•Designed for 2.3 to 3.6 V VCC Operation
•5.4 ns Maximum tpd
•5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
•Supports Live Insertion and Withdrawal
•IOFF Specification Guarantees High Impedance When VCC = 0 V
•LVTTL Compatible
•LVCMOS Compatible
•24 mA Balanced Output Sink and Source Capability
•Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
•Latchup Performance Exceeds 500 mA
•ESD Performance:
♦Human Body Model >2000 V
♦Machine Model >200 V
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAM
TSSOP−48
DT SUFFIX
CASE 1201
1
48
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
1
48
LCX16373G
AWLYYWW
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
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2
481 LE1OE1
472 D0O0
463 D1O1
454 GNDGND
445 D2O2
436 D3O3
427 VCC
VCC
418 D4O4
409 D5O5
3910 GND
GND
3811 D6O6
3712 D7O7
3613 D8O8
3514 D9O9
3415 GNDGND
3316 D10O10
3217 D11O11
3118 VCC
VCC
3019 D12O12
2920 D13O13
2821 GNDGND
2722 D14O14
2623 D15
O15
2524 LE2OE2
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
LE1
OE1
O8
D8
O9
D9
O10
D10
O11
D11
O12
D12
O13
D13
O14
D14
O15
D15
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
LE2
OE2
1
48
24
25
2
47
3
46
5
44
6
43
8
41
9
40
11
38
12
37
13
36
14
35
16
33
17
32
19
30
20
29
22
27
23
26
Figure 1. Pinout: 48−Lead
(Top View)
Figure 2. Logic Diagram
Table 1. PIN NAMES
Pins Function
OEn Output Enable Inputs
LEn Latch Enable Inputs
D0−D15 Inputs
O0−O15 Outputs
TRUTH TABLE
Inputs Outputs Inputs Outputs
LE1 OE1 D0:7 O0:7 LE2 OE2 D8:15 O8:15
X H X Z X H X Z
H L L L H L L L
H L H H H L H H
L L X O0 L L X O0
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs
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ORDERING INFORMATION
Device Package Shipping†
MC74LCX16373DTG TSSOP−48
(Pb−Free)
39 Units / Rail
M74LCX16373DTR2G TSSOP−48
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Symbol Parameter Value Condition Units
VCC DC Supply Voltage −0.5 to +7.0 V
VIDC Input Voltage −0.5 ≤ VI ≤ +7.0 V
VODC Output Voltage −0.5 ≤ VO ≤ +7.0 Output in 3−State V
−0.5 ≤ VO ≤ VCC + 0.5 Output in HIGH or LOW State. (Note 1) V
IIK DC Input Diode Current −50 VI < GND mA
IOK DC Output Diode Current −50 VO < GND mA
+50 VO > VCC mA
IODC Output Source/Sink Current ±50 mA
ICC DC Supply Current Per Supply Pin ±100 mA
IGND DC Ground Current Per Ground Pin ±100 mA
TSTG Storage Temperature Range −65 to +150 °C
MSL Moisture Sensitivity Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Units
VCC Supply Voltage
Operating
Data Retention Only
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
VIInput Voltage 0 5.5 V
VOOutput Voltage
(HIGH or LOW State)
(3−State)
0
0
VCC
5.5
V
IOH HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
−24
−12
−8
mA
IOL LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+24
+12
+8
mA
TAOperating Free−Air Temperature −55 +125 °C
Dt/DVInput Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V
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DC ELECTRICAL CHARACTERISTICS
Symbol Characteristic Condition
TA = −55°C to +125°C
Units
Min Max
VIH HIGH Level Input Voltage (Note 2) 2.3 V ≤ VCC ≤ 2.7 V 1.7 V
2.7 V ≤ VCC ≤ 3.6 V 2.0
VIL LOW Level Input Voltage (Note 2) 2.3 V ≤ VCC ≤ 2.7 V 0.7 V
2.7 V ≤ VCC ≤ 3.6 V 0.8
VOH HIGH Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mAVCC −0.2 V
VCC = 2.3 V; IOH = −8 mA 1.8
VCC = 2.7 V; IOH = −12 mA 2.2
VCC = 3.0 V; IOH = −18 mA 2.4
VCC = 3.0 V; IOH = −24 mA 2.2
VOL LOW Level Output Voltage 2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA0.2 V
VCC = 2.3 V; IOL = 8 mA 0.6
VCC = 2.7 V; IOL = 12 mA 0.4
VCC = 3.0 V; IOL = 16 mA 0.4
VCC = 3.0 V; IOL = 24 mA 0.55
IOZ 3−State Output Current VCC = 3.6 V, VIN = VIH or VIL,
VOUT = 0 to 3.6 V
±5mA
IOFF Power Off Leakage Current VCC = 0, VIN = 3.6 V or VOUT = 3.6 V 10 mA
IIN Input Leakage Current VCC = 0 to 3.6 V, VIN = 3.6 V or GND ±5mA
ICC Quiescent Supply Current VCC = 3.6 V, VIN = 3.6 V or VOUT = 3.6 V 20 mA
DICC Increase in ICC per Input 2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V 500 mA
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W)
Symbol Parameter Waveform
TA = −55°C to +125°C
Units
VCC = 3.3 V ± 0.3 V
CL = 50 pF
VCC = 2.7 V
CL = 50 pF
VCC = 2.5 V ± 0.2 V
CL = 30 pF
Min Max Min Max Min Max
tPLH
tPHL
Propagation Delay
Dn to On
1 1.5
1.5
5.4
5.4
1.5
1.5
5.9
5.9
1.5
1.5
6.5
6.5
ns
tPLH
tPHL
Propagation Delay
LE to On
3 1.5
1.5
5.5
5.5
1.5
1.5
6.4
6.4
1.5
1.5
6.6
6.6
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2 1.5
1.5
6.1
6.1
1.5
1.5
6.5
6.5
1.5
1.5
7.9
7.9
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2 1.5
1.5
6.0
6.0
1.5
1.5
6.3
6.3
1.5
1.5
7.2
7.2
ns
tsSetup Time, HIGH or LOW Dn to
LE
3 2.5 2.5 3.0 ns
thHold Time, HIGH or LOW Dn to LE 3 1.5 1.5 2.0 ns
twLE Pulse Width, HIGH 3 3.0 3.0 3.5 ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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DYNAMIC SWITCHING CHARACTERISTICS
Symbol Characteristic Condition
TA = +25°C
Units
Min Typ Max
VOLP Dynamic LOW Peak Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV Dynamic LOW Valley Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol Parameter Condition Typical Units
CIN Input Capacitance VCC = 3.3 V, VI = 0 V or VCC 7 pF
COUT Output Capacitance VCC = 3.3 V, VI = 0 V or VCC 8 pF
CPD Power Dissipation Capacitance 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 20 pF
Figure 3. AC Waveforms
WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
VCC
0 V
Dn
LEn
Vmi
On
VCC
0 V
VOH
VOL
tPLH, tPHL
tw
Vmo
Vmo
Vmo
th
ts
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
0 V
OEn
On
tPZH tPHZ
tPZL tPLZ
On
Vmo
Vmo
Vmi
VOH
VHZ
VOL
VCC
VLZ
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
0 V
VOH
VOL
Dn
On
tPLH
tPHL
VmiVmi
Vmo Vmo
Table 2. AC WAVEFORMS
Symbol
VCC
3.3 V ± 0.3 V 2.7 V 2.5 V ± 0.2 V
Vmi 1.5 V 1.5 V VCC / 2
Vmo 1.5 V 1.5 V VCC / 2
VHZ VOL + 0.3 V VOL + 0.3 V VOL + 0.15 V
VLZ VOH − 0.3 V VOH − 0.3 V VOH − 015 V
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OPEN
PULSE
GENERATOR
RT
DUT
VCC
RL
R1
CL
6 V or VCC × 2
GND
Figure 4. Test Circuit
Table 3. TEST CIRCUIT
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V
6 V at VCC = 2.5 ± 0.2 V
Open Collector/Drain tPLH and tPHL 6 V
tPZH, tPHZ GND
CL= 50 pF at VCC = 3.3 ± 0.3 V or equivalent (includes jig and probe capacitance)
CL= 30 pF at VCC = 2.5 ± 0.2 V or equivalent (includes jig and probe capacitance)
RL= R1 = 500 W or equivalent
RT= ZOUT of pulse generator (typically 50 W)
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PACKAGE DIMENSIONS
TSSOP−48
DT SUFFIX
CASE 1201−01
ISSUE B
ÇÇÇ
ÇÇÇ
S
U
M
0.12 (0.005) V S
T
S
U
M
0.254 (0.010) T
−V−
B
A
L
K
−U−
48X REF
PIN 1
IDENT.
124
2548
0.076 (0.003)
SEATING
D
−T−
PLANE
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A12.40 12.60 0.488 0.496
B6.00 6.20 0.236 0.244
C−−− 1.10 −−− 0.043
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.50 BSC 0.0197 BSC
H0.37 −−− 0.015 −−−
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.17 0.27 0.007 0.011
K1 0.17 0.23 0.007 0.009
L7.95 8.25 0.313 0.325
M0 8 0 8
__ __
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
ÉÉÉ
ÉÉÉ
C
GH
−W−
DETAIL E
J
K1
K
J1
SECTION N−N
M
0.25 (0.010)
F
DETAIL E
N
N
8.45
48X
0.32
0.50
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
RECOMMENDED
48X
1.00
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